SiC superjunction structure with gradient-varying buffer layer and its fabrication method

Abstract

This invention discloses a SiC superjunction structure with a gradient-varying buffer layer and its fabrication method, comprising: the SiC superjunction structure including several spaced P-pillar regions and N-pillar regions, with a PN junction interface formed between the P-pillar regions and the N-pillar regions, and a buffer layer structure formed at the PN junction interface; the buffer layer structure including a group of P-pillar buffer layers and a group of N-pillar buffer layers, the P-pillar buffer layer group being adjacent to the P-pillar regions and the N-pillar buffer layer group, and the N-pillar buffer layer group being adjacent to the N-pillar regions and the P-pillar buffer layer group; wherein the P-pillar buffer layer group and the N-pillar buffer layer group each include at least one corresponding buffer layer. This invention improves the SiC superjunction device, giving it better load bias resistance, reliability, and high breakdown voltage characteristics.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a SiC superjunction structure with a gradient-varying buffer layer and its fabrication method. Background Technology

[0002] SiC power devices can reduce converter losses, increase power density, lower heat dissipation requirements, and reduce system size and complexity, significantly improving system performance. Their high temperature, high pressure, and low loss characteristics make SiC power devices suitable for power supplies, rail transportation, motor control, electric vehicles, aerospace, and other systems. SiC power devices have inherent advantages over other types of switching devices in low-to-medium power applications. As a novel structural device, SiC superjunction devices, by incorporating P- and N-pillar structures within the traditional pressure-bearing layer, transform the electric field within the depletion layer from a triangular shape to a rectangular shape when the device operates under reverse bias. This effectively balances the relationship between the characteristic on-resistance and breakdown voltage of the power device, breaking the theoretical limit of one-dimensional unipolar materials.

[0003] However, the most common SiC superjunction structure is a continuous P and N columnar structure. Since the P and N column regions inside the SiC pressure-bearing layer are abruptly doped, if the difference in doping concentration between the P and N column regions is too large, a serious charge imbalance problem will occur. The charge imbalance will cause a decrease in the device's pressure-bearing capacity, thereby affecting the device's reliability. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a SiC superjunction structure with a gradient-varying buffer layer and its fabrication method.

[0005] In a first aspect, embodiments of the present invention provide a method for fabricating a SiC superjunction structure with a gradient-varying buffer layer structure. The SiC superjunction structure includes a plurality of spaced P-pillar regions and N-pillar regions, with a PN junction interface formed between the P-pillar regions and the N-pillar regions, and a buffer layer structure formed at the PN junction interface. The buffer layer structure includes a group of P-pillar buffer layers and a group of N-pillar buffer layers, with the P-pillar buffer layer group adjacent to the P-pillar regions and the N-pillar buffer layer group, and the N-pillar buffer layer group adjacent to the N-pillar regions and the P-pillar buffer layer group. The P-pillar buffer layer group and the N-pillar buffer layer group each include at least one corresponding buffer layer.

[0006] In one embodiment of the present invention, the width of the P-pillar region and the N-pillar region is 1 μm to 10 μm.

[0007] In one embodiment of the present invention, from the N-column region to the P-column region, the N-type ion concentration decreases sequentially, while the P-type ion concentration increases sequentially, exhibiting a step-like nonlinear distribution.

[0008] In one embodiment of the present invention, the P-pillar buffer layer group and the N-pillar buffer layer group each include a corresponding buffer layer, and the width of the corresponding buffer layer is less than 1 μm.

[0009] In one embodiment of the present invention, the P-pillar buffer layer group and the N-pillar buffer layer group each include a plurality of corresponding buffer layers;

[0010] From the N-pillar region to the P-pillar region, the widths of multiple corresponding buffer layers in the N-pillar buffer layer group decrease sequentially, while the widths of multiple corresponding buffer layers in the P-pillar buffer layer group increase sequentially.

[0011] In one embodiment of the present invention, from the N-pillar region to the P-pillar region, the width of the buffer layer adjacent to the N-pillar region in the N-pillar buffer layer group is less than 1 μm, and the width of other buffer layers in the N-pillar buffer layer group is half the width of the previous buffer layer.

[0012] In one embodiment of the present invention, from the N-pillar region to the P-pillar region, the width of the buffer layer adjacent to the P-pillar region in the P-pillar buffer layer group is less than 1 μm, and the width of other buffer layers in the P-pillar buffer layer group is twice the width of the previous buffer layer.

[0013] In one embodiment of the present invention, from the N-column region to the P-column region, the N-type ion concentration decreases sequentially, while the P-type ion concentration increases sequentially, exhibiting a stepwise linear distribution.

[0014] In one embodiment of the present invention, the P-pillar buffer layer group and the N-pillar buffer layer group each include a corresponding buffer layer, and the width of the corresponding buffer layer is less than 2μm.

[0015] Secondly, embodiments of the present invention provide a method for fabricating a SiC superjunction structure with a gradient-varying buffer layer structure, characterized in that it includes:

[0016] Growth of N-type SiC epitaxial layer;

[0017] A stepped or ladder-shaped mask is etched on the N-type SiC epitaxial layer; wherein, one end face of the N-type SiC epitaxial layer is not covered by the mask;

[0018] P-ion implantation is performed on the stepped mask or the stepped mask and the N-type SiC epitaxial layer to form a first P-pillar region, a first N-pillar region, a first P-pillar buffer layer group and a first N-pillar buffer layer group; wherein the P-pillar buffer layer group and the N-pillar buffer layer group each include at least one corresponding buffer layer.

[0019] The epitaxial growth, etching mask, and ion implantation processes described above are repeated on the first P-pillar region, the first N-pillar region, the first P-pillar buffer layer group, and the first N-pillar buffer layer group to form a SiC superjunction structure with a gradient-varying buffer layer structure.

[0020] The beneficial effects of this invention are:

[0021] This invention proposes a SiC superjunction structure with a gradient-varying buffer layer. Addressing the inherent problems of traditional SiC superjunction devices, this invention introduces a novel SiC superjunction structure. Specifically, a buffer layer is added at the junction interface between P-pillar region 1 and N-pillar region 2 in the SiC superjunction, thus gradually smoothing the alternating doping concentration gradient between them. This leads to three performance improvements: First, the buffer layer avoids charge imbalance-induced charge biasing issues, improving the charge bias resistance of the SiC superjunction device. Second, the buffer layer significantly improves the internal electric field distribution, preventing spikes and enhancing device reliability. Third, the buffer layer reduces the bulk electric field, increasing the device's breakdown voltage. Therefore, the SiC superjunction device proposed in this invention exhibits better charge bias resistance, reliability, and high breakdown voltage, making it more suitable for low-to-medium power applications such as power supplies, rail transportation, motor control, electric vehicles, and aerospace systems.

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a SiC superjunction structure with a gradient-varying buffer layer structure provided in an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of a SiC superjunction structure with a double-layer gradient variation buffer layer provided in an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of a SiC superjunction structure with four gradient-varying buffer layers provided in an embodiment of the present invention;

[0026] Figure 4 This is a schematic flowchart of a method for fabricating a SiC superjunction structure with a gradient-varying buffer layer structure provided in an embodiment of the present invention;

[0027] Figure 5 (a)~ Figure 5 (g) is a schematic diagram of the fabrication process of a SiC superjunction structure with a gradient-changing buffer layer structure provided in an embodiment of the present invention;

[0028] Figure 6 This is a schematic flowchart of another method for fabricating a SiC superjunction structure with a gradient-varying buffer layer structure provided in an embodiment of the present invention;

[0029] Figure 7 (a)~ Figure 7 (g) is a schematic diagram of the fabrication process of another SiC superjunction structure with a gradient change buffer layer structure provided in the embodiment of the present invention.

[0030] Explanation of reference numerals in the attached figures:

[0031] 1-P column area; 2-N column area; 3-P column buffer layer group; 4-N column buffer layer group; 301-P column buffer layer; 302-P column buffer layer; 401-N column buffer layer; 402-N column buffer layer. Detailed Implementation

[0032] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0033] Currently, the focus of consideration for SiC superjunction devices is primarily on their application in power devices, rather than addressing the inherent drawbacks of SiC superjunctions themselves. For example, when the SiC superjunction structure is a continuous P- and N-pillar structure with abrupt doping changes in the P- and N-pillar regions, a significant difference in doping concentration between the two regions can lead to severe charge imbalance, causing a decrease in the device's voltage withstand capability due to charge polarization. To address these issues and improve the charge polarization resistance of SiC superjunction devices, please refer to [link to relevant documentation / reference]. Figure 1 This invention provides a SiC superjunction structure with a gradient-varying buffer layer structure. The SiC superjunction structure includes several spaced-apart P-pillar regions 1 and N-pillar regions 2, with a PN junction interface formed between the P-pillar regions 1 and N-pillar regions 2. A buffer layer structure is formed at the PN junction interface. The buffer layer structure includes a P-pillar buffer layer group 3 and an N-pillar buffer layer group 4. The P-pillar buffer layer group 3 is adjacent to the P-pillar regions 1 and the N-pillar buffer layer group 4, and the N-pillar buffer layer group 4 is adjacent to the N-pillar regions 2 and the P-pillar buffer layer group 3. Each of the P-pillar buffer layer group 3 and the N-pillar buffer layer group 4 includes at least one corresponding buffer layer. Figure 2 As shown, P-pillar buffer layer group 3 and N-pillar buffer layer group 4 each include a corresponding buffer layer; as Figure 3 As shown, the P-pillar buffer layer group 3 and the N-pillar buffer layer group 4 each include two corresponding buffer layers.

[0034] As can be seen, by adding a buffer layer at the junction interface of the traditional P-pillar region 1 and N-pillar region 2, the alternating doping concentration gradient of the P-pillar region 1 and N-pillar region 2 is slowed down, avoiding the problem of charge imbalance, thereby reducing the decrease in the load-bearing capacity of SiC superjunction devices caused by charge bias, and thus improving the load bias resistance characteristics of SiC superjunction devices.

[0035] Preferably, the width of P-pillar region 1 and N-pillar region 2 is 1μm to 10μm.

[0036] This invention provides an optional scheme in which the concentration of N-type ions decreases sequentially from N-column region 2 to P-column region 1, while the concentration of P-type ions increases sequentially, exhibiting a step-like non-linear distribution. That is, the ion concentration in N-column region 2 is greater than that in N-column buffer layer group 4, and the ion concentration in P-column region 1 is greater than that in P-column buffer layer group 3; the ion distribution in N-column region 2, P-column region 1, N-column buffer layer group 4, and P-column buffer layer group 3 is uniform, exhibiting a step-like non-linear distribution between them.

[0037] For cases with a stepped nonlinear distribution, this invention provides an optional solution where the P-pillar buffer layer group 3 and the N-pillar buffer layer group 4 each include a corresponding buffer layer, preferably with a width of less than 1 μm for each buffer layer. That is, please refer to [further details omitted]. Figure 2 The P-pillar buffer layer group 3 includes a P-pillar buffer layer 301, preferably with a width of less than 1 μm; the N-pillar buffer layer group 4 includes an N-pillar buffer layer 401, preferably with a width of less than 1 μm.

[0038] For cases with a stepped, non-linear distribution, another alternative solution provided by this invention is that the P-pillar buffer layer group 3 and the N-pillar buffer layer group 4 each include multiple corresponding buffer layers; from the N-pillar region 2 to the P-pillar region 1, the widths of the multiple corresponding buffer layers in the N-pillar buffer layer group 4 decrease sequentially, while the widths of the multiple corresponding buffer layers in the P-pillar buffer layer group 3 increase sequentially. That is, please refer again... Figure 3 The P-pillar buffer layer group 3 includes a P-pillar buffer layer 301 and a P--pillar buffer layer 302. The P-pillar buffer layer 301 is adjacent to the P-pillar region 1, and the width of the P-pillar buffer layer 301 is wider than that of the P--pillar buffer layer 302. The N-pillar buffer layer group 4 includes an N-pillar buffer layer 401 and an N--pillar buffer layer 402. The N-pillar buffer layer 401 is adjacent to the N-pillar region 2, and the width of the N-pillar buffer layer 401 is wider than that of the N--pillar buffer layer 402. The widths of the P-pillar buffer layer 301 and the N-pillar buffer layer 401 may be the same or different.

[0039] Preferably, from N-pillar region 2 to P-pillar region 1, the width of the buffer layer adjacent to N-pillar region 2 in the N-pillar buffer layer group 4 is less than 1 μm, and the width of other buffer layers in the corresponding N-pillar buffer layer group 4 is half the width of the previous buffer layer. That is, the width of N-pillar buffer layer 401 is less than 1 μm, and the width of N-pillar buffer layer 402 is less than 0.5 μm.

[0040] Preferably, from N-pillar region 2 to P-pillar region 1, the width of the buffer layer adjacent to P-pillar region 1 in the P-pillar buffer layer group 3 is less than 1 μm, and the width of other buffer layers in the P-pillar buffer layer group 3 is twice the width of the previous buffer layer. That is, the width of P-pillar buffer layer 301 is less than 1 μm, and the width of P-pillar buffer layer 302 is less than 0.5 μm.

[0041] This invention provides another alternative scheme, in which the concentration of N-type ions decreases sequentially from N-column region 2 to P-column region 1, while the concentration of P-type ions increases sequentially, exhibiting a stepwise linear distribution. That is, the ion concentration in N-column region 2 is greater than the ion concentration in N-column buffer layer group 4, and the ion concentration in P-column region 1 is greater than the ion concentration in P-column buffer layer group 3; the ion distribution within N-column region 2, P-column region 1, N-column buffer layer group 4, and P-column buffer layer group 3 is non-uniform, exhibiting a stepwise linear distribution.

[0042] For cases with a stepped linear distribution, this invention provides an optional solution where the P-pillar buffer layer group 3 and the N-pillar buffer layer group 4 each include a corresponding buffer layer, preferably with a width of less than 2 μm for each buffer layer. That is, please refer to [further details omitted]. Figure 2 The P-pillar buffer layer group 3 includes a P-pillar buffer layer 301, preferably with a width of less than 2 μm; the N-pillar buffer layer group 4 includes an N-pillar buffer layer 401, preferably with a width of less than 2 μm.

[0043] It is evident that regardless of whether the ion concentration in the SiC superjunction exhibits a step-like nonlinear distribution or a step-like linear distribution, the abrupt doping changes in P-pillar region 1 and N-pillar region 2 are avoided. Introducing a buffer layer structure at the junction interface of P-pillar region 1 and N-pillar region 2 softens the alternating doping concentration gradient between them. The step-like linear distribution makes the alternating doping concentration gradient between P-pillar region 1 and N-pillar region 2 even smoother, which better ensures the charge distribution balance and achieves better charge-bias resistance characteristics of SiC superjunction devices.

[0044] In summary, this invention provides a SiC superjunction structure with a gradient-varying buffer layer. Addressing the inherent problems of traditional SiC superjunction devices, a novel SiC superjunction structure is proposed. Specifically, a buffer layer is added at the junction interface between P-pillar region 1 and N-pillar region 2 in the SiC superjunction, thus gradually smoothing the alternating doping concentration gradient between them. This leads to three performance improvements: First, the buffer layer avoids charge imbalance-induced charge biasing issues, improving the charge bias resistance of the SiC superjunction device. Second, the buffer layer significantly improves the internal electric field distribution, preventing spikes and enhancing device reliability. Third, the buffer layer reduces the bulk electric field, increasing the device's breakdown voltage. Therefore, the SiC superjunction device proposed in this invention exhibits better charge bias resistance, reliability, and high breakdown voltage, making it more suitable for low-to-medium power applications such as power supplies, rail transportation, motor control, electric vehicles, and aerospace systems.

[0045] Secondly, embodiments of the present invention provide a method for fabricating a SiC superjunction structure with a gradient-varying buffer layer structure. Please refer to [link to relevant documentation]. Figure 4 ,include:

[0046] Growth of N-type SiC epitaxial layer;

[0047] A stepped or ladder-shaped mask is formed by etching on an N-type SiC epitaxial layer; however, one end face of the N-type SiC epitaxial layer is not covered by the mask.

[0048] P-ion implantation is performed on a stepped or ladder-shaped mask and an N-type SiC epitaxial layer to form a first P-pillar region 1, a first N-pillar region 2, a first P-pillar buffer layer group 3, and a first N-pillar buffer layer group 4; wherein, the P-pillar buffer layer group 3 and the N-pillar buffer layer group 4 each include at least one corresponding buffer layer.

[0049] The epitaxial growth, etching mask, and ion implantation processes described above are repeated on the first P-pillar region 1, the first N-pillar region 2, the first P-pillar buffer layer group 3, and the first N-pillar buffer layer group 4 to form a SiC superjunction structure with a gradient-varying buffer layer structure.

[0050] This invention employs metal-organic chemical vapor deposition (MOCVD) to grow materials such as... Figure 5 The N-type SiC epitaxial layer shown in (a) can be used, or an existing N-type SiC epitaxial layer structure can be used without fabrication.

[0051] In this embodiment of the invention, a mask is formed on an N-type SiC epitaxial layer using photoresist, and the photoresist is dry-etched using an inductively coupled plasma (ICP) process to create a stepped mask. Here, taking the addition of a single-layer buffer structure at the junction interface between P-pillar region 1 and N-pillar region 2 in a SiC superjunction structure as an example, i.e., adding a P-pillar buffer layer 301 and an N-pillar buffer layer 401 between P-pillar region 1 and N-pillar region 2, the corresponding stepped shape is formed as follows: the lower the mask thickness of N-pillar region 2, N-pillar buffer layer 401, P-pillar buffer layer 301, and P-pillar region 1, the less mask is required to form P-pillar region 1. Figure 5 As shown in (b).

[0052] Since the epitaxial layer is an N-type SiC epitaxial layer, this embodiment of the invention utilizes an ion implantation process to perform P-ion implantation on the N-type SiC epitaxial layer coated with a stepped mask. The stepped mask affects the P-ion implantation of the N-type SiC epitaxial layer, resulting in the formation of... Figure 5 (c) shows the first part P-pillar region 1, the first part N-pillar region 2, the first part P-pillar buffer layer, and the first part N-pillar buffer layer.

[0053] Immediately afterwards, such as Figure 5 As shown in (d), an N-type SiC epitaxial layer continues to grow on the first P-pillar region 1, the first N-pillar region 2, the first P-pillar buffer layer, and the first N-pillar buffer layer; Figure 5 (e) shows the continued coating of a stepped mask on the N-type SiC epitaxial layer; as shown in Figure 1. Figure 5 (f) P-ion implantation is performed on the N-type SiC epitaxial layer coated with a stepped mask; the epitaxial growth, mask etching, and ion implantation process described above is repeated to form the final layer as shown in the image. Figure 5 (g) The desired SiC superjunction structure having a gradient-varying buffer layer structure.

[0054] For the SiC superjunction structure with multi-layer buffer structure, the fabrication process is similar, except that the step-shaped mask has more steps, so that the buffer structure formed between P-pillar region 1 and N-pillar region 2 includes P-pillar buffer layer 301, P-pillar buffer layer 302, N-pillar buffer layer 401, and N-pillar buffer layer 402, which will not be described in detail here.

[0055] This invention provides another method for fabricating a SiC superjunction structure with a gradient-varying buffer layer. Please refer to [link to relevant documentation]. Figure 6 ,include:

[0056] Growth of N-type SiC epitaxial layer;

[0057] A stepped or ladder-shaped mask is formed by etching on an N-type SiC epitaxial layer; however, one end face of the N-type SiC epitaxial layer is not covered by the mask.

[0058] P-ion implantation is performed on a stepped or ladder-shaped mask and an N-type SiC epitaxial layer to form a first P-pillar region 1, a first N-pillar region 2, a first P-pillar buffer layer group 3, and a first N-pillar buffer layer group 4; wherein, the P-pillar buffer layer group 3 and the N-pillar buffer layer group 4 each include at least one corresponding buffer layer.

[0059] The epitaxial growth, etching mask, and ion implantation processes described above are repeated on the first P-pillar region 1, the first N-pillar region 2, the first P-pillar buffer layer group 3, and the first N-pillar buffer layer group 4 to form a SiC superjunction structure with a gradient-varying buffer layer structure.

[0060] visible, Figure 6 and Figure 4 The implementation is basically the same, the difference lies in the shape of the mask. Figure 4 The resulting mask has a stepped shape. Figure 6 The resulting mask has a stepped shape. Similarly, taking the addition of P-pillar buffer layer 301 and N-pillar buffer layer 401 between P-pillar region 1 and N-pillar region 2 as an example, the corresponding structures in the fabrication process are 7(a) to 7(g), which are similar to the implementation processes of 5(a) to 5(g), and will not be described in detail here.

[0061] In summary, the fabrication method for a SiC superjunction structure with a gradient buffer layer proposed in this invention addresses the problems inherent in traditional SiC superjunction device structures. It proposes a novel SiC superjunction structure and a corresponding fabrication process. The fabrication process utilizes stepped or ladder-shaped masks. For the same ion implantation energy and dose, different mask thicknesses can result in different P-pillar concentrations. A single ion implantation process can form a SiC superjunction structure with a gradient buffer layer, simplifying the process implementation. Furthermore, by adding a buffer layer structure at the junction interface of P-pillar region 1 and N-pillar region 2 in the SiC superjunction, the alternating doping concentration gradient between P-pillar region 1 and N-pillar region 2 is softened, resulting in three improvements in device performance: First, the addition of the buffer layer structure avoids the charge imbalance problem caused by charge bias, improving the charge bias resistance of the SiC superjunction device; second, the addition of the buffer layer structure can significantly improve the distribution of the internal electric field, avoiding the occurrence of peak electric fields and improving the reliability of the device; third, the addition of the buffer layer structure can reduce the bulk electric field, improving the breakdown voltage of the device. Therefore, the SiC superjunction device prepared by the method of this invention has better charge bias resistance, reliability, and high breakdown voltage characteristics, and can be better applied to low-to-medium power demand scenarios, such as power supplies, rail transit, motor control, electric vehicles, and aerospace systems.

[0062] As the method embodiments are basically similar to the device embodiments, the description is relatively simple, and relevant parts can be found in the description of the device embodiments.

[0063] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0064] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0065] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A SiC superjunction structure with a gradient-varying buffer layer, the SiC superjunction structure comprising a plurality of spaced-apart P-pillar regions and N-pillar regions, wherein a PN junction interface is formed between the P-pillar regions and the N-pillar regions, characterized in that, The PN junction interface has a buffer layer structure; the buffer layer structure includes a P-pillar buffer layer group and an N-pillar buffer layer group, the P-pillar buffer layer group being adjacent to the P-pillar region and the N-pillar buffer layer group, and the N-pillar buffer layer group being adjacent to the N-pillar region and the P-pillar buffer layer group; wherein, the P-pillar buffer layer group and the N-pillar buffer layer group each include at least one corresponding buffer layer; wherein... From the N-column region to the P-column region, the concentration of N-type ions decreases sequentially, while the concentration of P-type ions increases sequentially, exhibiting a step-like nonlinear distribution. The P-pillar buffer layer group and the N-pillar buffer layer group each include a corresponding buffer layer, and the width of the corresponding buffer layer is less than 1 μm. Alternatively, the P-pillar buffer layer group and the N-pillar buffer layer group each include multiple corresponding buffer layers; from the N-pillar region to the P-pillar region, the widths of the multiple corresponding buffer layers in the N-pillar buffer layer group decrease sequentially, and the widths of the multiple corresponding buffer layers in the P-pillar buffer layer group increase sequentially.

2. The SiC superjunction structure with a gradient-varying buffer layer structure according to claim 1, characterized in that, The width of the P-pillar region and the N-pillar region is 1μm to 10μm.

3. The SiC superjunction structure with a gradient-varying buffer layer structure according to claim 1, characterized in that, From the N-pillar region to the P-pillar region, the width of the buffer layer adjacent to the N-pillar region in the N-pillar buffer layer group is less than 1 μm, and the width of other buffer layers in the N-pillar buffer layer group is half the width of the previous buffer layer.

4. The SiC superjunction structure with a gradient-varying buffer layer structure according to claim 1, characterized in that, From the N-pillar region to the P-pillar region, the width of the buffer layer adjacent to the P-pillar region in the P-pillar buffer layer group is less than 1 μm, and the width of other buffer layers in the P-pillar buffer layer group is twice the width of the previous buffer layer.

5. A method for fabricating a SiC superjunction structure with a gradient-varying buffer layer, characterized in that, The fabrication method is used to fabricate the SiC superjunction structure with a gradient-changing buffer layer structure as described in any one of claims 1 to 4; the corresponding fabrication method includes: Growth of N-type SiC epitaxial layer; A stepped or ladder-shaped mask is etched on the N-type SiC epitaxial layer; wherein, one end face of the N-type SiC epitaxial layer is not covered by the mask; P-ion implantation is performed on the stepped mask or the stepped mask and the N-type SiC epitaxial layer to form a first P-pillar region, a first N-pillar region, a first P-pillar buffer layer group and a first N-pillar buffer layer group; wherein the P-pillar buffer layer group and the N-pillar buffer layer group each include at least one corresponding buffer layer. The epitaxial growth, etching mask, and ion implantation processes described above are repeated on the first P-pillar region, the first N-pillar region, the first P-pillar buffer layer group, and the first N-pillar buffer layer group to form a SiC superjunction structure with a gradient-varying buffer layer structure.

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