Chips and methods for manufacturing chips

Abstract

This invention provides a wafer and a method for manufacturing the wafer. The wafer includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doped regions and a plurality of second doped regions. The first and second doped regions are located on a first surface of the semiconductor substrate. The second doped regions are in contact with the first doped regions. The first and second doped regions are arranged alternately. Each of the first and second doped regions contains a plurality of N-type dopants. The doping concentration of the N-type dopants in each of the first doped regions is not greater than the doping concentration of the N-type dopants in each of the second doped regions.

Description

Technical Field

[0001] This invention relates to a wafer and a method for manufacturing the same. Background Technology

[0002] Generally, communication devices require chips for processing high-frequency electromagnetic waves, such as radio frequency (RF) chips. RF chips are core components of many communication devices, and many manufacturers are currently dedicated to their research and development to obtain RF chips with better functionality and lower cost. Common RF chips are manufactured using semiconductor processes. Various components are placed in and on a semiconductor substrate to obtain the RF chip. However, if the conductivity of the semiconductor substrate is too high, it can negatively affect the signals generated or received by the RF chip. Summary of the Invention

[0003] The present invention provides a wafer that can improve the problem of elements in the epitaxial layer diffusing into the semiconductor substrate and causing insufficient semiconductor resistance.

[0004] This invention provides a method for manufacturing a wafer that can improve the problem of elements in the epitaxial layer diffusing into the semiconductor substrate and causing insufficient semiconductor resistance.

[0005] At least one embodiment of the present invention provides a wafer including a semiconductor substrate. The semiconductor substrate includes a plurality of first doped regions and a plurality of second doped regions. The first doped regions and the second doped regions are located on a first surface of the semiconductor substrate. The second doped regions are in contact with the first doped regions. The first doped regions and the second doped regions are arranged alternately. Each of the first doped regions and the second doped regions contains a plurality of N-type dopants. The doping concentration of the N-type dopants in each first doped region is not greater than the doping concentration of the N-type dopants in each second doped region.

[0006] At least one embodiment of the present invention provides a method for manufacturing a wafer, comprising: providing a semiconductor substrate; performing a first ion implantation process on a first surface of the semiconductor substrate to form an N-type lightly doped region in the semiconductor substrate; forming a barrier layer on the first surface of the semiconductor substrate, the barrier layer having a plurality of openings exposing the N-type lightly doped region; using the barrier layer as a mask, performing a second ion implantation process on the N-type lightly doped region of the semiconductor substrate to form a plurality of first N-type doped regions and a plurality of second N-type doped regions that are in contact with each other, wherein the first N-type doped regions and the second N-type doped regions are arranged alternately, wherein both the first N-type doped regions and the second N-type doped regions contain a plurality of N-type dopants, and the doping concentration of the N-type dopants in each first N-type doped region is not greater than the doping concentration of the N-type dopants in each second N-type doped region.

[0007] At least one embodiment of the present invention provides a method for manufacturing a wafer, comprising: providing a semiconductor substrate; forming a barrier layer on a first surface of the semiconductor substrate, the barrier layer having a plurality of openings exposing the first surface; forming an N-type doped material layer on the barrier layer and in the openings; heating the N-type doped material layer to diffuse a plurality of N-type dopants in the N-type doped material layer into the semiconductor substrate, wherein: a portion of the N-type dopants diffuse from the N-type doped material layer through the barrier layer into the semiconductor substrate to define a plurality of first N-type doped regions; and another portion of the N-type dopants diffuse directly from the N-type doped material layer into the semiconductor substrate to define a plurality of second N-type doped regions, wherein the first N-type doped regions and the second N-type doped regions are arranged alternately, wherein both the first N-type doped regions and the second N-type doped regions contain a plurality of N-type dopants, and the doping concentration of the N-type dopants in each first N-type doped region is not greater than the doping concentration of the N-type dopants in each second N-type doped region. Attached Figure Description

[0008] Figures 1A to 1F This is a cross-sectional schematic diagram of a wafer manufacturing method according to an embodiment of the present invention;

[0009] Figure 2 yes Figure 1F The equivalent circuit diagram of the chip;

[0010] Figure 3 This is a cross-sectional schematic diagram of a wafer manufacturing method according to an embodiment of the present invention;

[0011] Figure 4 yes Figure 3 The equivalent circuit diagram of the chip;

[0012] Figures 5A to 5C This is a cross-sectional schematic diagram of a wafer manufacturing method according to an embodiment of the present invention;

[0013] Figure 6 This is a top view schematic diagram of a chip according to an embodiment of the present invention;

[0014] Figure 7 This is a top view schematic diagram of a chip according to an embodiment of the present invention;

[0015] Figure 8 This is a top view schematic diagram of a chip according to an embodiment of the present invention;

[0016] Figures 9A to 9B This is a cross-sectional schematic diagram of a wafer manufacturing method according to an embodiment of the present invention;

[0017] Figures 10A to 10B This is a cross-sectional schematic diagram of a wafer manufacturing method according to an embodiment of the present invention.

[0018] Explanation of reference numerals in the attached figures

[0019] 100, 500, 600: Semiconductor substrates;

[0020] 110: Lightly doped region;

[0021] 110', 512, 514, 516, 611, 612, 613, 614, 615: First N-type doped region;

[0022] 110", 110a, 512', 514', 516', 611', 612', 613', 614', 615': First doped region;

[0023] 120, 522, 524, 526, 621, 622, 624, 624, 625, 626: Second N-type doped region;

[0024] 120', 522', 524', 526', 621', 622', 624', 624', 625', 626': Second doped region;

[0025] 130: Epitaxial layer;

[0026] 200: N-type doped material layer;

[0027] D1, D2, D1', D2': Depth;

[0028] HD: Horizontal direction;

[0029] i: Intrinsic semiconductor region;

[0030] M: Barrier layer;

[0031] OP: Opening;

[0032] P1: First ion implantation process;

[0033] P2: Second ion implantation process;

[0034] P3: Doping process;

[0035] PN1, PN2: Diodes;

[0036] S1: First page. Detailed Implementation

[0037] Figures 1A to 1F This is a cross-sectional schematic diagram of a wafer manufacturing method according to an embodiment of the present invention.

[0038] Please refer to Figure 1AA semiconductor substrate 100 is provided. The semiconductor substrate 100 is, for example, a silicon substrate or other semiconductor substrate suitable for epitaxial processes. In some embodiments, the first surface S1 of the semiconductor substrate 100 is a flat surface that has been ground and polished, thereby improving the yield of subsequent processes.

[0039] In some embodiments, the semiconductor substrate 100 may be formed by a floating zone melting method, a Czochralski method, or other suitable processes. The resistivity of the semiconductor substrate 100 before performing the ion doping process is 1500 Ωcm to 10000 Ωcm.

[0040] Please refer to Figure 1B A first ion implantation process P1 is performed on the first surface S1 of the semiconductor substrate 100 to form an N-type lightly doped region 110 in the semiconductor substrate 100. In some embodiments, the first ion implantation process P1 is performed to form an N-type lightly doped region 110 with a depth D1 of 0.1 μm to 5 μm on the first surface S1. In some embodiments, the N-type dopant used in the first ion implantation process P1 includes phosphorus, arsenic, antimony, or other suitable elements. In some embodiments, the doping concentration of the N-type lightly doped region 110 is 10. 13 cm -3 Up to 10 17 cm -3 .

[0041] In this embodiment, the N-type lightly doped region 110 is formed over the entire surface of the first surface S1 of the semiconductor substrate 100, but the invention is not limited thereto. In other embodiments, the N-type lightly doped region 110 is formed only in a localized area of ​​the first surface S1 of the semiconductor substrate 100. In other words, in other embodiments, a masking layer is formed on the first surface S1 before performing the first ion implantation process P1, so that the N-type lightly doped region 110 is not formed over the entire surface of the first surface S1.

[0042] In this embodiment, N-type dopant is used to dope the semiconductor substrate 100 with N-type dopant to form a lightly doped N-type region 110, but the present invention is not limited thereto. In other embodiments, thermal diffusion or other suitable methods are used to form the lightly doped N-type region 110.

[0043] Please refer to Figure 1C A barrier layer M is formed on the first surface S1 of the semiconductor substrate 100, and the barrier layer M has a plurality of openings OP that expose the lightly doped N-type regions 110. The openings OP are staggered with the solid portion of the barrier layer M.

[0044] In some embodiments, the method of forming the barrier layer M includes a photolithography process, and the material of the barrier layer M includes cured photoresist, but the present invention is not limited thereto.

[0045] The shape of the opening OP projected vertically onto the first surface S1 can be adjusted as needed. For example, the shape of the opening OP projected vertically onto the first surface S1 can be a triangle, a quadrilateral, or other geometric shapes.

[0046] In this embodiment, the barrier layer M includes multiple openings OP of the same size and shape, but the invention is not limited thereto. In some embodiments, the barrier layer M includes multiple openings OP of different sizes and shapes.

[0047] Please refer to Figure 1D Using the barrier layer M as a mask, a second ion implantation process P2 is performed on the N-type lightly doped region 110 of the semiconductor substrate 100 to form multiple first N-type doped regions 110' and multiple second N-type doped regions 120 that are in contact with each other. The first N-type doped regions 110' overlap the barrier layer M, while the second N-type doped regions 120 are located below the opening OP. The first N-type doped regions 110' and the second N-type doped regions 120 are arranged alternately.

[0048] Both the first N-type doped region 110' and the second N-type doped region 120 contain a plurality of N-type dopants. In some embodiments, the N-type dopants used in the second ion implantation process P2 include phosphorus, arsenic, antimony, or other suitable elements. In some embodiments, the N-type dopants used in the first ion implantation process P1 are the same as those used in the second ion implantation process P2. In some embodiments, both the first N-type doped region 110' and the second N-type doped region 120 are N-type semiconductors.

[0049] The doping concentration of N-type dopant in each first N-type doped region 110' is not greater than the doping concentration of N-type dopant in each second N-type doped region 120. In some embodiments, the doping concentration of the first N-type doped region 110' is 10. 13 cm -3 Up to 10 17 cm -3 The preferred value is 10. 13 cm -3 Up to 10 15 cm -3 10 is better 13 cm -3 Up to 10 14 cm -3 In some embodiments, the doping concentration of the second N-type doped region 120 is 10. 16 cm -3 Up to 10 21 cm -3 The preferred value is 10. 16 cm -3 Up to 10 19 cm -3 10 is better16 cm -3 Up to 10 18 cm -3 .

[0050] In some embodiments, the depth D2 of the second N-type doped region 120 is less than 10 μm, less than 2 μm, or less than 1 μm, and the depth D1 of the first N-type doped region 110' is 1% to 50%, 1% to 25%, or 1% to 10% of the depth D2 of the deepest second N-type doped region 120.

[0051] In this embodiment, the semiconductor substrate 100 includes a plurality of first N-type doped regions 110' of the same depth and a plurality of second N-type doped regions 120 of the same depth, but the present invention is not limited thereto. In other embodiments, the semiconductor substrate 100 includes a plurality of first N-type doped regions 110' of different depths and a plurality of second N-type doped regions 120 of different depths.

[0052] exist Figure 1D In the present invention, the cross-sectional shape of the second N-type doped region 120 is rectangular, but the present invention is not limited thereto.

[0053] Please refer to Figure 1E and Figure 1F The barrier layer M is removed. An epitaxial layer 130 is formed on the first N-type doped region 110' and the second N-type doped region 120, and the first N-type doped region 110' and the second N-type doped region 120 are subjected to a doping process P3. In this embodiment, the material of the epitaxial layer 130 includes gallium nitride, aluminum nitride, or other III-V group nitride materials or other suitable materials.

[0054] The doping process P3 includes diffusing some elements (e.g., aluminum or gallium) in the epitaxial layer 130 into the first N-type doped region 110' and the second N-type doped region 120, thereby forming the first doped region 110" and the second doped region 120' respectively.

[0055] The first doped region 110” and the second doped region 120’ are located on the first surface S1 of the semiconductor substrate 110, and the second doped region 120’ contacts the first doped region 110”. The first doped region 110” and the second doped region 120’ are arranged alternately. Specifically, in the cross-sectional schematic diagram of the structure (e.g. Figure 1F As shown), the side of each first doped region 110” is adjacent to the second doped region 120’; in the top view of the structure (as shown) Figure 6 As shown), the edge of the top surface of each first doped region 110” is adjacent to the second doped region 120’.

[0056] In this embodiment, both the first doped region 110” and the second doped region 120’ contain a plurality of N-type dopants. The aforementioned N-type dopants are formed in the first doping process P1 and the second doping process P2.

[0057] In this embodiment, doping process P3 provides P-type dopants to the first doped region 110” and the second doped region 120’, and the epitaxial layer 130 contains the same elements as the P-type dopants. In this embodiment, the doping concentration of N-type dopants in each of the first doped regions 110” is not greater than the doping concentration of N-type dopants in each of the second doped regions 120’. In some embodiments, the concentration of N-type dopants in the first doped region 110” is substantially equal to the concentration of N-type dopants in the first N-type doped region 110’, and the concentration of N-type dopants in the second doped region 120’ is substantially equal to the concentration of N-type dopants in the second N-type doped region 120’.

[0058] Since the concentration of N-type dopants in the first N-type doped region 110' is not greater than the concentration of N-type dopants in the second N-type doped region 120', doping process P3 converts the first N-type doped region 110' into a P-type semiconductor, but doping process P3 does not convert the second N-type doped region 120' into a P-type semiconductor. In the first doped region 110', the concentration of P-type dopants is greater than the concentration of N-type dopants, and the first doped region 110' is a P-type semiconductor. In the second doped region 120', the concentration of N-type dopants is greater than the concentration of P-type dopants, and the second doped region 120' is an N-type semiconductor.

[0059] The depth D1' of each first doped region 110" (P-type semiconductor) is not greater than the depth D2' of the adjacent second doped region 120" (N-type semiconductor). In this embodiment, the N-type dopants in the first N-type doped region 110" suppress the P-type dopants provided by the doping process P3 from penetrating into the semiconductor substrate 100, thereby preventing the depth D1' of the first doped region 110" from being greater than the depth D2' of the second doped region 120" and reducing the probability of the two first doped regions 110" contacting each other. In addition, since the N-type dopants in the first N-type doped region 110' suppress the P-type dopants provided by the doping process P3 from penetrating into the semiconductor substrate 100, the depth D2' of the second doped region 120" does not need to be too thick to block the adjacent first doped region 110". Therefore, the energy used by the first ion implantation process P1 and the energy used by the second ion implantation process P2 can be reduced, thereby reducing the problem of damage to the first surface S1 of the semiconductor substrate 100 by the first ion implantation process P1 and the second ion implantation process P2.

[0060] In some embodiments, the semiconductor substrate 100 further includes an intrinsic semiconductor region i. The intrinsic semiconductor region i is located at the bottom of the first doped region 110” and the second doped region 120’. In some embodiments, the depth D1’ is less than the depth D2’, and in the horizontal direction HD, the second doped region 120’ contacts the first doped region 110” and the intrinsic semiconductor region i, wherein the horizontal direction HD is parallel to the first surface S1.

[0061] exist Figure 1F In the present invention, the cross-sectional shape of the first doped region 110” and the second doped region 120’ is presented as a rectangle, but the present invention is not limited thereto.

[0062] In this embodiment, since the first doped region 110” and the second doped region 120’ are alternately arranged in the semiconductor substrate 100, the semiconductor substrate 100 has alternating forward-oriented diodes PN1 and reverse-oriented diodes PN2, as shown below. Figure 2 As shown.

[0063] Alternating arrangement of forward-biased diodes PN1 and reverse-biased diodes PN2 can restrict the movement of electrons, thereby improving the quality and stability of the component.

[0064] Please refer to Figure 1F and Figure 2 In the horizontal direction HD, the second doped region 120' contacts the first doped region 110" and the intrinsic semiconductor region i. Therefore, the forward diode PN1 and the reverse diode PN2 are connected in parallel to the resistor R, which is formed by the intrinsic semiconductor region i.

[0065] Based on the above, this embodiment can reduce the energy used in the first ion implantation process P1 and the second ion implantation process P2, thereby improving the problem of damage to the first surface S1 of the semiconductor substrate 100 by the first ion implantation process P1 and the second ion implantation process P2. Furthermore, the alternating arrangement of the first doped region 110” and the second doped region 120’ can restrict electron movement, thereby improving the quality and stability of the device. In general semiconductor processes, before forming an epitaxial layer on a semiconductor substrate, the entire surface or a portion of the semiconductor substrate is usually lightly doped or heavily doped once, thereby preventing elements in the subsequently formed epitaxial layer from diffusing into the semiconductor substrate and causing leakage. Unlike general semiconductor processes, in the embodiments of this invention, the first N-type doped region 110’ and the second N-type doped region 120’ with different doping levels are arranged alternately (e.g., ...). Figure 1FAs shown, the first N-type doped region 110' and the second N-type doped region 120 can selectively use a doping concentration lower than that of light and heavy doping, so that a structure that can restrict the movement of electrons can be obtained in the future (alternating arrangement of the first doped region 110" and the second doped region 120'), thereby reducing the damage to the surface of the semiconductor substrate caused by the doping process.

[0066] Figure 3 This is a cross-sectional schematic diagram of a wafer manufacturing method according to an embodiment of the present invention.

[0067] It must be stated here that, Figure 3 The embodiments follow Figures 1A to 1F The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0068] Figure 3 Implementation examples and Figure 1F The difference between the embodiments is: Figure 1F The depth D1' of the first doped region 110' is smaller than the depth D2' of the second doped region 120', while Figure 3 The depth D1' of the first doped region 110a is equal to the depth D2' of the second doped region 120'.

[0069] Please refer to Figure 3 In this embodiment, in the horizontal direction HD, the second doped region 120' contacts the first doped region 110a, and the second doped region 120' does not contact the intrinsic semiconductor region i.

[0070] In this embodiment, since the first doped region 110a and the second doped region 120' are alternately arranged in the semiconductor substrate 100, and the semiconductor substrate 100 has alternating forward-oriented diodes PN1 and reverse-oriented diodes PN2, as shown... Figure 4 As shown.

[0071] Alternating arrangement of forward-biased diodes PN1 and reverse-biased diodes PN2 can restrict the movement of electrons, thereby improving the quality and stability of the component.

[0072] Based on the above, this embodiment can reduce the energy required for the first ion implantation process and the second ion implantation process, thereby improving the problem of damage to the first surface S1 of the semiconductor substrate 100 by the first and second ion implantation processes. Furthermore, the alternating arrangement of the first doped region 110a and the second doped region 120' can restrict electron movement, thereby improving the quality and stability of the device.

[0073] Figures 5A to 5C This is a cross-sectional schematic diagram of a wafer manufacturing method according to an embodiment of the present invention.

[0074] It must be stated here that, Figures 5A to 5C The embodiments follow Figures 1A to 1F The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0075] Please refer to Figure 5A A semiconductor substrate 100 is provided. The semiconductor substrate 100 is, for example, a silicon substrate or other semiconductor substrate suitable for epitaxial processes. In some embodiments, the first surface S1 of the semiconductor substrate 100 is a flat surface that has been ground and polished, thereby improving the yield of subsequent processes.

[0076] A barrier layer M is formed on the first surface S1 of the semiconductor substrate 100, and the barrier layer M has a plurality of openings OP that expose the first surface S1.

[0077] Please refer to Figure 5B An N-type doped material layer 200 is formed on the barrier layer M and in the opening OP.

[0078] The N-type doped material layer 200 is heated, causing a plurality of N-type dopants in the N-type doped material layer 200 to diffuse into the semiconductor substrate 100. In some embodiments, the N-type dopants are, for example, phosphorus, arsenic, antimony, or other suitable elements.

[0079] Some N-type dopants diffuse from the N-type doped material layer 200 through the barrier layer M into the semiconductor substrate 100 to define a plurality of first N-type doped regions 110', and another portion of N-type dopants diffuse directly from the N-type doped material layer 200 into the semiconductor substrate 100 to define a plurality of second N-type doped regions 120.

[0080] Multiple first N-type doped regions 110' and multiple second N-type doped regions 120 are in contact with each other. The first N-type doped regions 110' overlap the barrier layer M, while the second N-type doped regions 120 are located below the opening OP. The first N-type doped regions 110' and the second N-type doped regions 120 are arranged alternately.

[0081] Both the first N-type doped region 110' and the second N-type doped region 120 contain multiple N-type dopants. Both the first N-type doped region 110' and the second N-type doped region 120 are N-type semiconductors.

[0082] Because the barrier layer M reduces the diffusion of N-type dopants into the semiconductor substrate 100, the doping concentration of N-type dopants in each first N-type doped region 110' is no greater than the doping concentration of N-type dopants in each second N-type doped region 120. In some embodiments, the doping concentration of the first N-type doped region 110' is 10. 13 cm -3 Up to 10 17 cm -3 The preferred value is 10. 13 cm -3 Up to 10 15 cm -3 10 is better 13 cm -3 Up to 10 14 cm -3 In some embodiments, the doping concentration of the second N-type doped region 120 is 10. 16 cm -3 Up to 10 21 cm -3 The preferred value is 10. 16 cm -3 Up to 10 19 cm -3 10 is better 16 cm -3 Up to 10 18 cm -3 .

[0083] In some embodiments, the depth D2 of the second N-type doped region 120 is less than 5 μm, less than 2 μm, or less than 1 μm, and the depth D1 of the first N-type doped region 110' is 1% to 50%, 1% to 25%, or 1% to 10% of the depth D2 of the deepest second N-type doped region 120.

[0084] In this embodiment, the semiconductor substrate 100 includes a plurality of first N-type doped regions 110' of the same depth and a plurality of second N-type doped regions 120 of the same depth, but the present invention is not limited thereto. In other embodiments, the semiconductor substrate 100 includes a plurality of first N-type doped regions 110' of different depths and a plurality of second N-type doped regions 120 of different depths.

[0085] Please refer to Figure 5C Remove the barrier layer M and the N-type doped material layer 200. After removing the barrier layer M and the N-type doped material layer 200, the following can be performed: Figure 1F The process shown forms the first doped region 110” and the second doped region 120’. Please refer to the relevant information. Figure 1F and corresponding Figure 1F The explanation will not be repeated here.

[0086] Based on the above, the alternating first doped regions (drawn on...) Figure 1F ) and the second doped region (drawn on Figure 1F It can restrict the movement of electrons, thereby improving the quality and stability of the component.

[0087] Figure 6 This is a top view schematic diagram of a chip according to an embodiment of the present invention, wherein... Figure 6 The epitaxial layer is omitted from the drawing.

[0088] Figure 6 The chip manufacturing method can be referenced. Figures 1A to 1F Implementation examples or Figures 5A to 5C Examples of implementations.

[0089] Please refer to Figure 6 In this embodiment, the alternating first doped region 110” and second doped region 120’ are both rectangular.

[0090] Figure 7 This is a top view schematic diagram of a chip according to an embodiment of the present invention, wherein... Figure 7 The epitaxial layer is omitted from the drawing.

[0091] Figure 7 The chip manufacturing method can be referenced. Figures 1A to 1F Implementation examples or Figures 5A to 5C Examples of implementations.

[0092] Please refer to Figure 7 In this embodiment, the alternating first doped region 110” and second doped region 120’ are both trapezoidal.

[0093] Figure 8 This is a top view schematic diagram of a chip according to an embodiment of the present invention, wherein... Figure 8 The epitaxial layer is omitted from the drawing.

[0094] Figure 8 The chip manufacturing method can be referenced. Figures 1A to 1F Implementation examples or Figures 5A to 5C Examples of implementations.

[0095] Please refer to Figure 8 In this embodiment, the alternating first doped region 110” and second doped region 120’ are both triangular.

[0096] Figures 9A to 9B This is a cross-sectional schematic diagram of a wafer manufacturing method according to an embodiment of the present invention.

[0097] Please refer to Figure 9AA plurality of first N-type doped regions 512, 514, and 516 and a plurality of second N-type doped regions 522, 524, and 526 are formed in a semiconductor substrate 500. In this embodiment, the first N-type doped regions 512, 514, and 516 are all of the same depth, but this invention is not limited thereto. In this embodiment, the second N-type doped regions 522, 524, and 526 are all of the same depth, but this invention is not limited thereto.

[0098] The first N-type doped regions 512, 514, and 516 and the second N-type doped regions 522, 524, and 526 are arranged alternately. Each of the first N-type doped regions 512, 514, and 516 and the second N-type doped regions 522, 524, and 526 contains multiple N-type dopants, and the doping concentration of the N-type dopants in each of the first N-type doped regions 512, 514, and 516 is not greater than the doping concentration of the N-type dopants in each of the second N-type doped regions 522, 524, and 526.

[0099] In some embodiments, the method for forming the first N-type doped regions 512, 514, 516 and the second N-type doped regions 522, 524, 526 includes ion implantation, high-temperature diffusion doping or other similar methods.

[0100] In some embodiments, the depths of the first N-type doped regions 512, 514, and 516 are different from each other, and the depths of the second N-type doped regions 522, 524, and 526 are also different from each other. The depths of the second N-type doped regions 522, 524, and 526 are greater than the depths of the adjacent first N-type doped regions 512, 514, and 516.

[0101] In some embodiments, the first N-type doped regions 512, 514, and 516 have different doping concentrations. For example, the doping concentration of the first N-type doped region 512 is greater than that of the first N-type doped region 514, and the doping concentration of the first N-type doped region 514 is greater than that of the first N-type doped region 516, but this invention is not limited thereto. In some embodiments, the second N-type doped regions 522, 524, and 526 have different doping concentrations. For example, the doping concentration of the second N-type doped region 522 is greater than that of the second N-type doped region 524, and the doping concentration of the second N-type doped region 524 is greater than that of the second N-type doped region 526, but this invention is not limited thereto.

[0102] In some embodiments, the difference in doping concentration between the first N-type doped regions 512, 514, and 516 is no greater than 10%, and the difference in doping concentration between the second N-type doped regions 522, 524, and 526 is no greater than 10%.

[0103] Please refer to Figure 9B An epitaxial layer 130 is formed on the first N-type doped regions 512, 514, 516 and the second N-type doped regions 522, 524, 526, and a doping process P3 is performed on the first N-type doped regions 512, 514, 516 and the second N-type doped regions 522, 524, 526. Some elements (P-type dopants) in the epitaxial layer 130 diffuse into the first N-type doped regions 512, 514, 516 and the second N-type doped regions 522, 524, 526 to form the first doped regions 512', 514', 516' and the second doped regions 522', 524', 526', respectively. In this embodiment, the first doped regions 512', 514', 516' are P-type semiconductors, and the second doped regions 522', 524', 526' are N-type semiconductors.

[0104] In some embodiments, at different locations on the first surface S1 of the semiconductor substrate 500, the doping process P3 may be non-uniform due to uneven process temperature, uneven thickness of the epitaxial layer 130, or other factors. By making the depths of the first N-type doped regions 512, 514, and 516 different, the depth of the P-type semiconductor (first doped regions 512', 514', and 516') can be better controlled.

[0105] In some embodiments, P-type dopants in the epitaxial layer 130 diffuse into the semiconductor substrate 500 due to heat. In some embodiments, the surface of the semiconductor substrate 500 may have uneven heat distribution, for example, the temperature of the portion of the semiconductor substrate 500 closer to the heat source is higher than the temperature of the portion farther from the heat source. Therefore, P-type dopants will diffuse to different degrees in different regions of the semiconductor substrate 500. Based on this, a first N-type doped region 512 with a higher doping concentration is provided in the portion where more P-type dopants are expected to diffuse (i.e., the portion closer to the heat source), while a first N-type doped region 516 with a lower doping concentration is provided in the portion where less P-type dopants are expected to diffuse (i.e., the portion farther from the heat source). This allows for better control of the depth and conductivity of the subsequently formed P-type semiconductor (first doped regions 512', 514', 516'), further improving the stability of the device. Similarly, a second N-type doped region 522 with a higher doping concentration is provided in the region where more P-type dopant diffusion is expected (i.e., the region closer to the heat source), while a second N-type doped region 526 with a lower doping concentration is provided in the region where less P-type dopant diffusion is expected (i.e., the region farther from the heat source). This allows the subsequently formed N-type semiconductor (second doped regions 522', 524', 526') to match the P-type semiconductor (first doped regions 512', 514', 516'). Through this design, the doping concentration can be reduced in the region where less P-type dopant diffusion is expected, thereby reducing damage to the surface of the semiconductor substrate 500 caused by the doping process. However, it should be noted that the position of the semiconductor substrate 500 near the heat source may change due to different heating tools or different arrangements of the semiconductor substrate 500. Therefore, the present invention does not particularly limit the arrangement and order of the first N-type doped regions 512, 514, 516 and the second N-type doped regions 522, 524, 526. The arrangement and order of the first N-type doped regions 512, 514, 516 and the second N-type doped regions 522, 524, 526 can be adjusted according to actual needs.

[0106] Based on the above, the alternating arrangement of the first doped regions 512', 514', 516' and the second doped regions 522', 524', 526' can restrict the movement of electrons, thereby improving the quality and stability of the device.

[0107] Figures 10A to 10B This is a cross-sectional schematic diagram of a wafer manufacturing method according to an embodiment of the present invention.

[0108] It must be stated here that, Figures 10A to 10B The embodiments follow Figures 9A to 9BThe component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0109] Figures 10A to 10B Implementation examples and Figures 9A to 9B The difference in the embodiments is that: Figures 9A to 9B In the embodiments, the depths of the first doped regions 512', 514', 516' and the second doped regions 522', 524', 526' gradually decrease from the edge of the semiconductor substrate 500 to the middle of the semiconductor substrate 500; in Figures 10A to 10B In the embodiments, the depths of the first doped regions 611', 612', 613', 614', 615' and the second doped regions 621', 622', 623', 624', 625', 626' gradually decrease from one side of the semiconductor substrate 600 to the other side of the semiconductor substrate 600.

[0110] Please refer to Figure 10A A plurality of first N-type doped regions 611, 612, 613, 614, 615 and a plurality of second N-type doped regions 621, 622, 623, 624, 625, 626 are formed in a semiconductor substrate 600.

[0111] The first N-type doped regions 611, 612, 613, 614, and 615 and the second N-type doped regions 621, 622, 623, 624, 625, and 626 are arranged alternately. The first N-type doped regions 611, 612, 613, 614, and 615 and the second N-type doped regions 621, 622, 623, 624, 625, and 626 each contain multiple N-type dopants, and the doping concentration of the N-type dopants in each of the first N-type doped regions 611, 612, 613, 614, and 615 is not greater than the doping concentration of the N-type dopants in each of the second N-type doped regions 621, 622, 623, 624, 625, and 626.

[0112] In some embodiments, the methods for forming the first N-type doped regions 611, 612, 613, 614, 615 and the second N-type doped regions 621, 622, 623, 624, 625, 626 include ion implantation, high-temperature diffusion doping or other similar methods.

[0113] In some embodiments, the first N-type doped regions 611, 612, 613, 614, and 615 include different doping concentrations. For example, the doping concentrations of the first N-type doped regions 611, 612, 613, 614, and 615 decrease sequentially, but the invention is not limited thereto. In some embodiments, the second N-type doped regions 621, 622, 623, 624, 625, and 626 include different doping concentrations. For example, the doping concentrations of the second N-type doped regions 621, 622, 623, 624, 625, and 626 decrease sequentially, but the invention is not limited thereto.

[0114] In some embodiments, the difference in doping concentration between the first N-type doped regions 611, 612, 613, 614, and 615 is no greater than 10%, and the difference in doping concentration between the second N-type doped regions 621, 622, 623, 624, 625, and 626 is no greater than 10%.

[0115] Please refer to Figure 10B An epitaxial layer 130 is formed on the first N-type doped regions 611, 612, 613, 614, 615 and the second N-type doped regions 621, 622, 623, 624, 625, 626, and a doping process P3 is performed on the first N-type doped regions 611, 612, 613, 614, 615 and the second N-type doped regions 621, 622, 623, 624, 625, 626. A portion of the elements (P-type dopants) in the epitaxial layer 130 diffuse into the first N-type doped regions 611, 612, 613, 614, 615 and the second N-type doped regions 621, 622, 623, 624, 625, 626, to form the first doped regions 611', 612', 613', 614', 615' and the second doped regions 621', 622', 623', 624', 625', 626', respectively. In this embodiment, the first doped regions 611', 612', 613', 614', 615' are P-type semiconductors, and the second doped regions 621', 622', 623', 624', 625', 626' are N-type semiconductors.

[0116] In some embodiments, at different locations on the first surface S1 of the semiconductor substrate 600, the doping process P3 may be non-uniform due to uneven process temperature, uneven thickness of the epitaxial layer 130, or other factors. By making the depths of the first N-type doped regions 611, 612, 613, 614, and 615 different, the depth of the P-type semiconductor (first doped regions 611', 612', 613', 614', and 615') can be better controlled.

[0117] Based on the above, the alternating arrangement of the first doped regions 611', 612', 613', 614', 615' and the second doped regions 621', 622', 623', 624', 625', 626' can restrict the movement of electrons, thereby improving the quality and stability of the device.

Claims

1. A chip, comprising: Semiconductor substrate, including: Multiple first doped regions are located on the first surface of the semiconductor substrate; A plurality of second doped regions are located on the first surface of the semiconductor substrate and in contact with the first doped region, wherein the first doped region and the second doped region are arranged alternately, wherein both the first doped region and the second doped region contain a plurality of N-type dopants, and the doping concentration of the N-type dopants in each of the first doped regions is less than the doping concentration of the N-type dopants in each of the second doped regions; and An epitaxial layer is located on the first doped region and the second doped region, wherein the first doped region and the second doped region further contain a plurality of p-type dopants, and the epitaxial layer contains the same elements as the p-type dopants, wherein: In the first doped region, the concentration of the P-type dopant is greater than the concentration of the N-type dopant, and the first doped region is a P-type semiconductor; and In the second doped region, the concentration of the N-type dopant is greater than the concentration of the P-type dopant, and the second doped region is an N-type semiconductor.

2. The wafer of claim 1, wherein the depth of each of the first doped regions is not greater than the depth of the adjacent second doped region.

3. The wafer according to claim 1, wherein the semiconductor substrate further comprises: The intrinsic semiconductor region is located at the bottom of the first doped region and the second doped region, wherein the second doped region contacts the first doped region and the intrinsic semiconductor region in a horizontal direction, wherein the horizontal direction is parallel to the first surface.

4. The wafer according to claim 1, wherein the first doped region comprises different doping concentrations, and the second doped region comprises different doping concentrations.

5. The wafer according to claim 4, wherein the difference in doping concentration between the first doped regions is no greater than 10%, and the difference in doping concentration between the second doped regions is no greater than 10%.

6. A method for manufacturing a wafer, comprising: Provide semiconductor substrates; A first ion implantation process is performed on the first surface of the semiconductor substrate to form an N-type lightly doped region in the semiconductor substrate; A barrier layer is formed on the first surface of the semiconductor substrate, and the barrier layer has a plurality of openings that expose the lightly doped N-type region; Using the barrier layer as a mask, a second ion implantation process is performed on the lightly doped N-type region of the semiconductor substrate to form a plurality of first N-type doped regions and a plurality of second N-type doped regions that are in contact with each other. The first N-type doped regions and the second N-type doped regions are arranged alternately. Each of the first N-type doped regions and the second N-type doped regions contains a plurality of N-type dopants, and the doping concentration of the N-type dopants in each of the first N-type doped regions is less than the doping concentration of the N-type dopants in each of the second N-type doped regions. Remove the barrier layer; as well as An epitaxial layer is formed on the first N-type doped region and the second N-type doped region, wherein some elements in the epitaxial layer diffuse into the first N-type doped region and the second N-type doped region, and at least a portion of the first N-type doped region is converted into a plurality of P-type semiconductors.

7. The wafer manufacturing method according to claim 6, wherein the depth of the P-type semiconductor is not greater than the depth of the second N-type doped region.

8. A method for manufacturing a wafer, comprising: Provide semiconductor substrates; A barrier layer is formed on a first surface of the semiconductor substrate, and the barrier layer has a plurality of openings exposing the first surface; An N-type doped material layer is formed on the barrier layer and in the opening; The N-type doped material layer is heated, causing multiple N-type dopant atoms in the N-type doped material layer to diffuse into the semiconductor substrate, wherein: Some of the N-type dopants diffuse from the N-type doped material layer through the barrier layer into the semiconductor substrate, thereby defining a plurality of first N-type doped regions; and Another portion of the N-type dopants diffuse directly from the N-type doped material layer into the semiconductor substrate to define a plurality of second N-type doped regions, wherein the first N-type doped regions and the second N-type doped regions are arranged alternately, wherein both the first N-type doped regions and the second N-type doped regions contain a plurality of N-type dopants, and the doping concentration of the N-type dopants in each of the first N-type doped regions is less than the doping concentration of the N-type dopants in each of the second N-type doped regions; Remove the barrier layer and the N-type doped material layer; and An epitaxial layer is formed on the first N-type doped region and the second N-type doped region, wherein some elements in the epitaxial layer diffuse into the first N-type doped region and the second N-type doped region, and at least a portion of the first N-type doped region is converted into a plurality of P-type semiconductors.

9. The wafer manufacturing method according to claim 8, wherein the depth of the P-type semiconductor is not greater than the depth of the second N-type doped region.

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