Electrostatic discharge protection circuit
By designing control circuits and filters in the ESD protection circuit, and using transistors of different sizes to handle different types of sudden currents, the problem of supply voltage jitter was solved, and stable current discharge and signal transmission were achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2021-06-28
- Publication Date
- 2026-08-04
AI Technical Summary
Traditional ESD protection circuits cause excessive supply voltage fluctuations when faced with sudden currents of varying speeds and energies. In particular, when a small but fast-moving sudden current passes through a large-size transistor, the supply voltage fluctuation problem is caused by the parasitic inductance effect.
An ESD protection circuit was designed, which includes a control circuit, a filter, and multiple transistors. The control signal is generated by detecting the supply voltage level. Different types of sudden currents are handled by transistors and filters of different sizes. This avoids the large transistors from conducting due to the low energy and high speed of the current, thus achieving effective current discharge.
It effectively protects the internal circuitry, prevents supply voltage fluctuations, ensures stable signal transmission, and adapts to different types of sudden current surges.
Smart Images
Figure CN115603295B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to electrostatic discharge (ESD) protection circuits. Background Technology
[0002] In traditional ESD protection circuits, to effectively dissipate large electrostatic discharge currents, the ESD clamping transistor is typically designed to be very large, thus protecting the internal circuitry. However, if the ESD protection circuit encounters a small but fast-moving burst current, the large clamping transistor design can cause excessive voltage fluctuations due to the excessive discharge energy, coupled with the inductance effect of the chip package. This can prevent the internal circuitry from transmitting healthy signals. Summary of the Invention
[0003] Therefore, one of the objectives of this invention is to propose an ESD protection circuit that can have different discharge paths for sudden currents of different speeds and energies, so as to solve the problem of excessive supply voltage fluctuations in the prior art.
[0004] In one embodiment of the present invention, an ESD protection circuit is disclosed, comprising a control circuit, a first transistor, a filter, and a second transistor. The control circuit is used to detect the level of a supply voltage to generate a control signal; the first transistor is coupled between the supply voltage and a ground voltage and is used to determine whether to conduct based on the control signal to serve as a path for the supply voltage to discharge current to the ground voltage; the filter is used to filter the control signal to generate a filtered control signal; and the second transistor is coupled between the supply voltage and the ground voltage and is used to determine whether to conduct based on the first filtered control signal to serve as a path for the supply voltage to discharge current to the ground voltage. Attached Figure Description
[0005] Figure 1 This is a schematic diagram of an ESD protection circuit according to an embodiment of the present invention.
[0006] Figure 2 It describes burst currents with lower energy but higher speed and burst currents with higher energy but lower speed.
[0007] Figure 3 This is a schematic diagram of a control circuit according to an embodiment of the present invention.
[0008] Figure 4 This is a schematic diagram of an ESD protection circuit according to another embodiment of the present invention. Detailed Implementation
[0009] Figure 1 This is a schematic diagram of an ESD protection circuit 100 according to an embodiment of the present invention. Figure 1 As shown, the ESD protection circuit 100 includes a contact N1, a control circuit 110, a filter 120, and two transistors M1 and M2. The filter 120 includes a resistor R1 and a capacitor R1. In this embodiment, the ESD protection circuit 100 is installed on a chip, such as an Ethernet chip or any other chip that requires electrostatic discharge protection. The contact N1 is the signal access point of the chip, and the chip's supply voltage VDDX is generated by an external supply voltage VDD.
[0010] In this embodiment, since the internal supply voltage VDDX is generated by the external supply voltage VDD, and the external windings of the chip have parasitic inductance (in... Figure 1 (represented by "L" in the original text). Therefore, if a sudden current flows into the chip through contact N1 and triggers the electrostatic discharge protection mechanism, the supply voltage VDDX will fluctuate due to the effect of the parasitic inductance L. Furthermore, since sudden currents can have different speeds and energies depending on their source, for example… Figure 2 The diagram shows a low-energy but high-speed burst current depicted by dashed lines, while a high-energy but slow-speed burst current depicted by solid lines. For electrostatic discharge (ESD) protection, considering the high-energy burst current, a larger transistor is required to quickly discharge it; however, if a low-energy but high-speed burst current is discharged through a larger transistor, the supply voltage VDDX will fluctuate significantly due to the parasitic inductance L. Therefore, to solve this problem… Figure 1 The ESD protection circuit 100 shown is designed with two current discharge paths to discharge the two different types of sudden currents mentioned above, so as to effectively solve the jitter problem of the supply voltage VDDX.
[0011] Specifically, refer to Figure 1 The control circuit 110 detects the level of the supply voltage VDDX to determine if a sudden current flows into the chip, thereby generating a control signal Vc. The drain of transistor M1 is connected to the supply voltage VDDX, the source is connected to ground, and the gate receives the control signal Vc. Based on the control signal Vc, it determines whether to turn on the transistor to discharge the sudden current and lower the level of the supply voltage VDDX. Filter 120 is a low-pass filter used to filter the control signal Vc to generate a filtered control signal Vc'. The drain of transistor M2 is connected to the supply voltage VDDX, the source is connected to ground, and the gate receives the filtered control signal Vc'. Based on the filtered control signal Vc', it determines whether to turn on the transistor to discharge the sudden current and lower the level of the supply voltage VDDX.
[0012] In this embodiment, transistor M1 is used to dissipate low-energy but high-speed burst currents. Therefore, to avoid excessive current in transistor M1 causing fluctuations in the supply voltage VDDX, transistor M1 has a smaller size, meaning it has a smaller maximum current. Transistor M2, on the other hand, is used to dissipate high-energy but slow-speed burst currents. Therefore, to effectively dissipate large burst currents, transistor M2 has a larger size, meaning it has a larger maximum current. Furthermore, due to the design of filter 120, transistor M2 will not conduct when a low-energy but high-speed burst current occurs, thus preventing fluctuations in the supply voltage VDDX caused by transistor M2 conducting with such a burst.
[0013] In one embodiment, filter 120 has an adjustable cutoff frequency for adjustment during the testing phase to ensure that transistor M2 does not conduct due to low-energy, high-speed burst currents. For example, capacitor C1 can be a variable capacitor to be adjusted to an appropriate capacitance value.
[0014] Figure 3 This is a schematic diagram of a control circuit 110 according to an embodiment of the present invention. Figure 3 As shown, the control circuit 110 includes a resistor R2, a capacitor C2, and an inverter 310, wherein the inverter 310 includes a P-type transistor M3 and an N-type transistor M4. One end of the resistor R2 is connected to the supply voltage VDDX, and the other end is connected to terminal N2; one end of the capacitor C2 is connected to terminal N2, and the other end is connected to ground; the source of the P-type transistor M3 is connected to VDDX, which is the supply voltage for the inverter 110, the drain is connected to the output terminal to generate a control signal Vc, and the gate is connected to terminal N2; the source of the N-type transistor M4 is connected to ground, the drain is connected to the output terminal to generate a control signal Vc, and the gate is connected to terminal N2. Figure 3 In this architecture, when the supply voltage VDDX rises due to a sudden current flowing into the chip, the source voltage level of the P-type transistor M3 connected to the supply voltage VDDX increases. Furthermore, the voltage V1 at terminal N1 has a slower response speed due to resistor R2 and capacitor C2 (i.e., voltage V1 does not immediately rise due to the increase in the supply voltage VDDX). Therefore, the P-type transistor M3 immediately turns on, resulting in a high voltage level for the control signal Vc, thus enabling the chip. Figure 1 The transistor M1 is shown.
[0015] It should be noted that, Figure 3The circuit architecture shown is merely an example and not a limitation of the invention. As long as the control circuit 110 can effectively generate a control signal Vc to turn on the transistor M1 when the supply voltage VDDX level rises, for example, when the supply voltage VDDX is higher than a threshold value, the control circuit 110 can have different circuit designs.
[0016] As mentioned above, by designing transistors M1 and M2 to dissipate different types of burst current, the internal circuitry can be effectively protected while avoiding the jitter problem of the supply voltage VDDX.
[0017] exist Figure 1 The illustrated embodiment uses two transistors M1 and M2 for illustration; however, the invention can also be applied to cases with multiple transistors (i.e., multiple current venting paths). Specifically, Figure 4 This is a schematic diagram of an ESD protection circuit 400 according to another embodiment of the present invention. Figure 4 As shown, the ESD protection circuit 400 includes a contact N1, a control circuit 410, two filters 420 and 430, and three transistors M1, M2, and M3. Filter 420 includes a resistor R3 and a capacitor R3, and filter 430 includes a resistor R4 and a capacitor R4. In this embodiment, the ESD protection circuit 400 is installed on a chip, such as an Ethernet chip or any other chip requiring electrostatic discharge protection. Contact N1 is the signal access point of the chip, and the chip's supply voltage VDDX is generated by an external supply voltage VDD.
[0018] refer to Figure 4The control circuit 410 detects the level of the supply voltage VDDX to determine if a sudden current flows into the chip, thereby generating a control signal Vc. The drain of transistor M1 is connected to the supply voltage VDDX, the source is connected to ground, and the gate receives the control signal Vc. Based on the control signal Vc, it determines whether to turn on the transistor to discharge the sudden current and lower the level of the supply voltage VDDX. Filter 420 is a low-pass filter used to filter the control signal Vc to generate a filtered control signal Vc'. The drain of transistor M2 is connected to the supply voltage VDDX, the source is connected to ground, and the gate receives the filtered control signal Vc'. Based on the filtered control signal Vc', it determines whether to turn on the transistor to discharge the sudden current and lower the level of the supply voltage VDDX. Filter 430 is also a low-pass filter, used to filter the filtered control signal Vc' to generate the filtered control signal Vc'. The drain of transistor M3 is connected to the supply voltage VDDX, the source is connected to the ground voltage, and the gate is used to receive the filtered control signal Vc'. Based on the filtered control signal Vc', it determines whether to conduct in order to discharge the burst current and reduce the level of the supply voltage VDDX.
[0019] In this embodiment, transistor M1 is smaller than transistor M2, meaning the maximum current of transistor M1 is less than the maximum current of transistor M2; and transistor M2 is smaller than transistor M3, meaning the maximum current of transistor M2 is less than the maximum current of transistor M3. In other words, transistor M1 is primarily used to dissipate low-energy but high-speed burst currents, transistor M2 is primarily used to dissipate medium-energy but medium-speed burst currents, and transistor M3 is primarily used to dissipate high-energy but slow-speed burst currents. Furthermore, due to the design of filter 420, transistors M2 and M3 will not conduct when a low-energy but high-speed burst current occurs, thus avoiding the problem of supply voltage VDDX jitter caused by transistors M2 and M3 conducting due to low-energy but high-speed burst currents.
[0020] In one embodiment, filters 420 and 430 have adjustable cutoff frequencies for adjustment during the testing phase to ensure that transistors M2 and M3 do not conduct due to low-energy, high-speed burst currents. For example, capacitors C1 and C2 can be variable capacitors to be adjusted to appropriate capacitance values.
[0021] In one embodiment, the control circuit 410 may employ Figure 3 The circuit architecture shown is used for implementation, but the present invention is not limited thereto. As long as the control circuit 410 can effectively generate a control signal Vc to turn on the transistor M1 when the supply voltage VDDX level rises, it can have different circuit designs.
[0022] In summary, the ESD protection circuit of this invention uses two or more transistors to discharge different types of burst currents, and a filter is designed to prevent larger transistors from conducting due to low-energy, high-speed burst currents. This effectively protects the internal circuits while avoiding the jitter problem of the supply voltage VDDX.
[0023] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the protection scope of the present invention.
[0024] Explanation of reference numerals in the attached figures:
[0025] 100, 400: ESD protection circuit
[0026] 110, 410: Control circuit
[0027] 120, 420, 430: Filters
[0028] 310: Inverter
[0029] C1, C2, C3, C4: Capacitors
[0030] L: Parasitic inductance
[0031] M1, M2, M3, M4: Transistors
[0032] N1, N2: Contact
[0033] R1, R2, R3, R4: Resistors
[0034] V1: Voltage
[0035] Vc: Control signal
[0036] Vc', Vc”: Filtered control signal
[0037] VDD: External supply voltage
[0038] VDDX: Supply voltage
Claims
1. An electrostatic discharge protection circuit, comprising: The control circuit is used to detect the level of the supply voltage to generate a control signal; A first transistor, coupled between the supply voltage and the ground voltage, is used to determine whether to conduct according to the control signal to serve as a path for the supply voltage to discharge current to the ground voltage; A first filter is used to filter the control signal to generate a first filtered control signal; as well as The second transistor, coupled between the supply voltage and the ground voltage, is used to determine whether to conduct based on the first filtered control signal to serve as a path for the supply voltage to discharge current to the ground voltage.
2. The electrostatic discharge protection circuit as claimed in claim 1, wherein the size of the second transistor is larger than the size of the first transistor.
3. The electrostatic discharge protection circuit as described in claim 1, wherein the maximum current of the second transistor is greater than the maximum current of the first transistor.
4. The electrostatic discharge protection circuit as described in claim 1, wherein the first filter is a low-pass filter with an adjustable cutoff frequency.
5. The electrostatic discharge protection circuit as described in claim 1, further comprising: A second filter is used to filter the first filtered control signal to generate a second filtered control signal; and A third transistor, coupled between the supply voltage and the ground voltage, is used to determine whether to turn on as a path for the supply voltage to discharge current to the ground voltage, based on the second filtered control signal.
6. The electrostatic discharge protection circuit of claim 5, wherein the size of the second transistor is larger than the size of the first transistor, and the size of the third transistor is larger than the size of the second transistor.
7. The electrostatic discharge protection circuit as claimed in claim 5, wherein the maximum current of the second transistor is greater than the maximum current of the first transistor, and the maximum current of the third transistor is greater than the maximum current of the second transistor.
8. The electrostatic discharge protection circuit as described in claim 5, wherein the first filter and the second filter are both low-pass filters with adjustable cutoff frequencies.
9. The electrostatic discharge protection circuit of claim 1, wherein the detection circuit detects whether the level of the supply voltage is higher than a threshold value to generate the control signal; wherein if the level of the supply voltage is higher than the threshold value, the detection circuit generates the control signal to enable the first transistor.
10. The electrostatic discharge protection circuit of claim 9, wherein the detection circuit comprises: A resistor is coupled between the supply voltage and one terminal. A capacitor is coupled between the terminal and the ground voltage; An inverter, wherein the inverter is powered by the supply voltage, the terminal is used as the input terminal of the inverter, and the output terminal of the inverter is used to generate the control signal.