Auxiliary circuit for electronic devices

Abstract

The application discloses an auxiliary circuit and an electronic device. The auxiliary circuit is connected with a voltage conversion circuit, and the voltage conversion circuit comprises at least one power switch tube. The at least one power switch tube is controlled by a pulse width modulation signal to realize voltage conversion. The auxiliary circuit comprises a voltage acquisition branch, a voltage comparison branch and a control branch. The voltage acquisition branch is connected with an output end of the voltage conversion circuit, and the voltage acquisition branch acquires an output voltage of the output end of the voltage conversion circuit. The voltage comparison branch is connected with the voltage acquisition branch, and the voltage comparison branch outputs an activation signal when the output voltage is less than a first preset voltage or greater than a second preset voltage. The control branch is connected with the voltage comparison branch and the voltage conversion circuit, and the control branch outputs an adjustment signal to adjust the pulse width modulation signal when the activation signal is received. In this way, the power switch tube can be adjusted more quickly when the load changes, so as to reduce the risk that the load is abnormally or damaged.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, mainly to the field of voltage conversion technology, and in particular to an auxiliary circuit and electronic device. Background Technology

[0002] Voltage conversion circuits are widely used in various electronic products because they can perform voltage matching between circuit modules in different voltage domains. They are used to boost or buck the input voltage to provide power.

[0003] Currently, voltage conversion circuits typically use pulse width modulation (PWM) signals to control power switching transistors to achieve voltage boost or buck conversion. Furthermore, when the load connected to the voltage conversion circuit suddenly changes, the duty cycle of the PWM signal needs to be adjusted based on the comparison between the output voltage and the target voltage to regulate the output voltage of the voltage conversion circuit.

[0004] However, changing the duty cycle of the PWM signal has a slow response time, which may cause the output voltage of the voltage conversion circuit to deviate from the target voltage, or even damage the load. Summary of the Invention

[0005] This application aims to provide a method that can adjust power switching transistors more quickly when the load changes, thereby reducing the risk of load malfunction or damage.

[0006] To achieve the above objectives, in a first aspect, this application provides an auxiliary circuit for connection to a voltage conversion circuit, the voltage conversion circuit including at least one power switch, the at least one power switch being controlled by a corresponding pulse width modulation signal to achieve voltage conversion, the auxiliary circuit including:

[0007] A voltage acquisition branch is connected to the output terminal of the voltage conversion circuit, and the voltage acquisition branch is used to acquire the output voltage of the output terminal of the voltage conversion circuit.

[0008] A voltage comparison branch is connected to the voltage acquisition branch. The voltage comparison branch is used to output an activation signal when the output voltage is less than a first preset voltage or greater than a second preset voltage.

[0009] A control branch is connected to the voltage comparison branch and the voltage conversion circuit respectively. The control branch is used to output an adjustment signal to adjust the pulse width modulation signal when the activation signal is received.

[0010] In one alternative embodiment, the at least one power switch includes a first power switch that is controlled to be turned on or off by a first pulse width modulation signal, wherein the on-time of the first power switch is positively correlated with the output voltage.

[0011] The voltage comparison branch is also used to output a first activation signal when the output voltage is less than a first preset voltage.

[0012] The control branch is also used to output a first adjustment signal to adjust the first pulse width modulation signal when the first activation signal is received, so as to increase the conduction time of the first power switch in at least one cycle.

[0013] In one alternative embodiment, the at least one power switch includes a second power switch controlled to be turned on or off by a second pulse width modulation signal, wherein the on-time of the second power switch is negatively correlated with the output voltage.

[0014] The voltage comparison branch is also used to output a second activation signal when the output voltage is greater than the second preset voltage;

[0015] The control branch is also used to output a second adjustment signal to adjust the second pulse width modulation signal when the second activation signal is received, so as to increase the conduction time of the second power switch in at least one cycle.

[0016] In an alternative embodiment, the control branch is further configured to: time a first duration after outputting the adjustment signal;

[0017] During the first time period, the control branch stops outputting the adjustment signal.

[0018] In one alternative embodiment, the voltage acquisition branch includes a first resistor and a second resistor connected in series;

[0019] The first resistor and the second resistor are used to divide the output voltage and output a first voltage to the voltage comparison branch;

[0020] The voltage comparison branch is also used to output the activation signal when the first voltage is less than the third preset voltage or greater than the fourth preset voltage;

[0021] Specifically, when the output voltage is less than the first preset voltage, the first voltage is less than the third preset voltage; when the output voltage is greater than the second preset voltage, the first voltage is greater than the fourth preset voltage.

[0022] In one alternative embodiment, the non-series connection terminal of the first resistor is connected to the output terminal of the voltage conversion circuit, the connection terminal between the first resistor and the second resistor is connected to the voltage comparison branch, and the non-series connection point of the second resistor is connected to the terminal.

[0023] In one alternative embodiment, the voltage comparison branch includes a first comparator and a second comparator;

[0024] The first comparator is used to acquire the output voltage and to output a first activation signal when the output voltage is greater than the first preset voltage;

[0025] The second comparator is used to acquire the output voltage and to output a second activation signal when the output voltage is less than the second preset voltage.

[0026] In one alternative embodiment, the first input terminal of the first comparator and the first input terminal of the second comparator are both connected to the voltage acquisition branch, the second input terminal of the first comparator receives the first preset voltage, the second input terminal of the second comparator receives the second preset voltage, and the output terminals of the first comparator and the second comparator are both connected to the control branch.

[0027] In one alternative embodiment, the control branch includes a signal latching sub-branch, a signal output sub-branch, and a signal suppression sub-branch;

[0028] The signal suppression sub-branch is connected to the signal latching sub-branch. The signal suppression sub-branch is used to maintain the output suppression signal to the signal latching sub-branch for a first time period after receiving the activation signal.

[0029] The signal latching sub-branch is also connected to the voltage comparison sub-branch and the signal output sub-branch respectively. The signal latching sub-branch is used to latch the activation signal when the suppression signal is not received, and transmit the latched signal to the signal output sub-branch and the signal suppression sub-branch respectively.

[0030] The signal output sub-branch is used to output the adjustment signal based on the activation signal.

[0031] In one alternative embodiment, the signal latch sub-branch includes a first NOR gate and a first D flip-flop;

[0032] The first NOR gate is connected between the voltage comparison branch and the first D flip-flop. The first NOR gate is used to output a first level signal based on the activation signal when the suppression signal is not received, and to output a second level signal when the suppression signal is received.

[0033] The first D flip-flop is also connected to the signal output sub-branch and the signal suppression sub-branch respectively. The first D flip-flop is used to transmit the first level signal or the second level signal to the signal output sub-branch and the signal suppression sub-branch respectively.

[0034] In one alternative embodiment, the first input terminal of the first NOR gate is connected to the output terminal of the voltage comparison branch, the second input terminal of the first NOR gate is connected to the output terminal of the signal suppression sub-branch, the output terminal of the first NOR gate is connected to the first input terminal of the first D flip-flop, and the output terminal of the first D flip-flop is connected to both the signal output sub-branch and the signal suppression sub-branch.

[0035] In one alternative embodiment, the signal output sub-branch includes a first delay module, a first NAND gate, a first NOT gate, a second NAND gate, and a first switching transistor connected in sequence, wherein the first switching transistor is also connected to the voltage conversion circuit.

[0036] The first delay module is used to control the duration of the activation signal;

[0037] The combination of the first NAND gate, the first NOT gate, the second NAND gate, and the first switch is used to output the adjustment signal based on the activation signal during the duration of the duration.

[0038] In one alternative embodiment, the first input terminal of the first NAND gate is connected to the first delay module, the second input terminal of the first NAND gate is connected to the output terminal of the signal latch sub-branch, the input terminal of the first NOT gate is connected to the output terminal of the first NAND gate, the output terminal of the first NOT gate is connected to the first input terminal of the second NAND gate, the output terminal of the second NAND gate is connected to the first terminal of the first switching transistor, the second terminal of the first switching transistor is connected to the first power supply, and the third terminal of the first switching transistor is connected to the voltage conversion circuit.

[0039] In one alternative embodiment, the signal suppression sub-branch includes a third NAND gate, a second D flip-flop, and a second delay module connected in sequence.

[0040] The combination of the third NAND gate and the second D flip-flop is used to output the suppression signal when the activation signal is received;

[0041] The second delay module is used to control the duration of the suppression signal.

[0042] In one alternative embodiment, the first and second input terminals of the third NAND gate are both connected to the signal latch sub-branch, the first input terminal of the second D flip-flop is connected to the output terminal of the third NAND gate, and the output terminal of the second D flip-flop is connected to the second delay module.

[0043] Secondly, this application provides an electronic device. The electronic device includes a voltage conversion circuit and the auxiliary circuit described above.

[0044] The beneficial effects of this application are as follows: The auxiliary circuit provided in this application is used to connect with a voltage conversion circuit, which includes at least one power switch. The at least one power switch is controlled by a corresponding pulse width modulation signal to achieve voltage conversion. The auxiliary circuit includes a voltage acquisition branch, a voltage comparison branch, and a control branch. The voltage acquisition branch is connected to the output terminal of the voltage conversion circuit and is used to acquire the output voltage of the voltage conversion circuit. The voltage comparison branch is connected to the voltage acquisition branch and is used to output an activation signal when the output voltage is less than a first preset voltage or greater than a second preset voltage. The control branch is connected to both the voltage comparison branch and the voltage conversion circuit, and is used to output an adjustment signal to adjust the pulse width modulation signal when the activation signal is received. Therefore, this auxiliary circuit can promptly output an adjustment signal to directly act on the pulse width modulation signal controlling the power switch when the output voltage of the voltage conversion circuit changes, i.e., when the load changes, thereby adjusting the power switch more quickly and reducing the risk of load abnormalities or damage. Attached Figure Description

[0045] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0046] Figure 1 This is a schematic diagram of the voltage conversion circuit in related technologies;

[0047] Figure 2 This is a schematic diagram of the auxiliary circuit provided in an embodiment of this application;

[0048] Figure 3 This is a schematic diagram of the structure of an auxiliary circuit provided in another embodiment of this application;

[0049] Figure 4 This is a schematic diagram of the circuit structure connecting the auxiliary circuit and the voltage conversion circuit provided in the embodiments of this application;

[0050] Figure 5 Provided for the embodiments of this application Figure 4A schematic diagram of each signal in the circuit structure shown;

[0051] Figure 6 Provided for another embodiment of this application Figure 4 A schematic diagram of each signal in the circuit structure shown;

[0052] Figure 7 This is a schematic diagram of the auxiliary circuit provided in another embodiment of the present application;

[0053] Figure 8 This is a schematic diagram of the circuit structure of the control branch provided in an embodiment of this application. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0055] Voltage conversion circuits are widely used in various electronic products because they can perform voltage matching between circuit modules in different voltage domains. They are used to boost or buck the input voltage to provide power.

[0056] Currently, voltage conversion circuits typically use pulse width modulation (PWM) signals to control power switching transistors to achieve voltage boost or buck conversion. Furthermore, when the load connected to the voltage conversion circuit suddenly changes, the duty cycle of the PWM signal needs to be adjusted based on the comparison between the output voltage and the target voltage to regulate the output voltage of the voltage conversion circuit.

[0057] However, changing the duty cycle of the PWM signal results in a slow response time, which may cause the output voltage of the voltage conversion circuit to deviate from the target voltage, and may even damage the load. The following explanation uses a common control mode (i.e., voltage mode) in voltage conversion circuits as an example.

[0058] While voltage-mode voltage conversion is simpler in circuit design and uses only a single control loop, it responds more slowly to load changes. The load is driven by this voltage conversion circuit, and load changes are dynamic occurrences driven by the load's current demand. Furthermore, if the load changes suddenly, the response of the voltage-mode circuit is even slower, potentially causing the output voltage to temporarily deviate from its target voltage, which could further lead to abnormal load operation or even damage to the load.

[0059] In related technologies, improving response speed is often achieved by adding feedforward compensation or optimizing the circuit to obtain higher bandwidth. Adding feedforward compensation involves adding a capacitor between the output node and the feedback node of the voltage conversion circuit. The feedback node is the voltage sensing node, and the added capacitor provides a "fast" signal path from the output node to the feedback node. Therefore, when the voltage at the output node changes, it can be sensed and reflected at the feedback node more quickly, allowing the control loop of the voltage conversion circuit to react and adjust accordingly. Optimizing the circuit to obtain higher bandwidth involves adjusting the compensation component values ​​in the voltage conversion circuit to give it higher bandwidth. However, in practical applications, both of these methods sometimes still fail to achieve the expected speed in response to load changes.

[0060] Please refer to Figure 1 , Figure 1 The image exemplifies one structure of a voltage conversion circuit 200 in the related art. For example... Figure 1 As shown, the voltage conversion circuit 200 includes a ramp generator 202, an error amplifier 204, a comparator 206, a logic controller 208, a first power switch Q202, a second power switch Q204, a resistor R202, an inductor L202, and a capacitor C202.

[0061] In this circuit, the clock signal CLK202 is processed by the ramp generator 202 to generate a ramp signal, which is then passed through resistor R202 and input to one input of comparator 206. Simultaneously, the difference between the feedback signal FB and the reference voltage VF1 is amplified by the error amplifier 204 and input to the other input of comparator 206. Comparator 206 outputs a corresponding signal to logic controller 208 based on the magnitude relationship of the voltages input to its two inputs. Logic controller 208 then outputs two corresponding pulse-width modulation (PWM) signals based on the received signals to control the first power switch Q202 and the second power switch Q204, respectively. The first PWM signal controls the first power switch Q202, and the second PWM signal controls the second power switch Q204. The first and second PWM signals are complementary signals.

[0062] In this embodiment, Ton is defined as the duration during which the first power switch Q202 is turned on (i.e., the first pulse width modulation signal is at a high level) within one cycle T, which is the duration during which voltage V202 supplies power to the load through output terminal VO1 within one cycle T. One cycle T includes both high and low levels. During the high-level period of one cycle T, the first power switch Q202 is turned on, the second power switch Q204 is turned off, voltage V202 charges inductor L202, and the current flowing through inductor L202 increases. During the low-level period of one cycle T, the first power switch Q202 is turned off, the second power switch Q204 is turned on, the charge stored in inductor L202 is discharged and supplies power to the load through output terminal VO1, and the current flowing through inductor L202 decreases. This process cycles until charge and discharge reach equilibrium. It can be seen that the conduction time of the first power switch Q202 is positively correlated with the output voltage at the output terminal VO1, that is, the output voltage increases as the first power switch Q202 increases and decreases as the first power switch Q202 decreases; the conduction time of the second power switch Q204 is negatively correlated with the output voltage at the output terminal VO1, that is, the output voltage decreases as the second power switch Q204 increases and increases as the second power switch Q204 decreases.

[0063] In this embodiment, when the load connected to the output terminal VO1 changes, this change causes a change in the difference between the feedback signal FB and the reference voltage VF1. Subsequently, the signal output from the error amplifier 204 to the comparator 206 changes, causing a change in the signal output from the comparator 206 to the logic controller 208. At this point, the logic controller 208 adjusts the first pulse width modulation signal and the second pulse width modulation signal according to the received signal to adjust the output voltage. For example, if a change in load causes a momentary increase in the output voltage, the logic controller 208, after receiving the signal output from the comparator 206, adjusts the duty cycle of the first pulse width modulation signal to decrease and adjusts the duty cycle of the second pulse width modulation signal to increase, thereby reducing the output voltage.

[0064] However, the response speed of the above process is slow, and the output voltage may deviate from the target voltage because there is not enough time to adjust the output voltage. This may cause abnormalities in the load connected to the output terminal VO1, or even damage the load.

[0065] Based on this, this application provides an auxiliary circuit that can promptly output an adjustment signal to directly act on the pulse width modulation signal controlling the power switch when the output voltage of the voltage conversion circuit changes (i.e., the load changes), thereby adjusting the power switch more quickly. This reduces the risk of load malfunction or damage.

[0066] Please refer to Figure 2 , Figure 2 A schematic diagram of the auxiliary circuit provided in an embodiment of this application. (See attached diagram.) Figure 2 As shown, the auxiliary circuit 100 is used to connect to the voltage conversion circuit 200. The voltage conversion circuit 200 includes at least one power switch, which is controlled by a corresponding pulse width modulation signal to achieve voltage conversion. In some embodiments, the specific circuit structure of the voltage conversion circuit 200 is as follows: Figure 1 As shown, the voltage conversion circuit 200 includes a first power switch Q202 and a second power switch Q204.

[0067] The auxiliary circuit 100 includes a voltage acquisition branch 10, a voltage comparison branch 20, and a control branch 30. The voltage acquisition branch 10 is connected to the output terminal of the voltage conversion circuit 200. The voltage comparison branch 20 is connected to the voltage acquisition branch 10. The control branch 30 is connected to both the voltage comparison branch 20 and the voltage conversion circuit 200.

[0068] Specifically, voltage acquisition branch 10 is used to acquire the output voltage at the output terminal of voltage conversion circuit 200. Voltage comparison branch 20 is used to output an activation signal when the output voltage is less than a first preset voltage or greater than a second preset voltage. Control branch 30 is used to output an adjustment signal to adjust the pulse width modulation signal controlling at least one power switch when the activation signal is received.

[0069] The first preset voltage and the second preset voltage can be set according to the actual application, and this application embodiment does not impose specific limitations on them. Furthermore, the first preset voltage and the second preset voltage can be the same or different.

[0070] In this embodiment, when the load changes and causes the output voltage to increase, the voltage comparison branch 20 determines that the output voltage is greater than a second preset voltage, and outputs an activation signal to the control branch 30. Subsequently, the control branch 30 can output an adjustment signal to adjust the pulse width modulation signal controlling at least one power switch, thereby extending the on-time of the power switch used to reduce the output voltage, thus quickly adjusting the output voltage.

[0071] For example, in some embodiments, at least one power switch in the voltage conversion circuit 200 includes, for example, Figure 1The second power switch Q204 is shown. The second power switch Q204 is controlled to be turned on or off by a second pulse width modulation signal. Furthermore, the on-time of the second power switch Q204 is negatively correlated with the output voltage of the voltage conversion circuit 200. The activation signal output by the voltage comparison branch 20 includes a second activation signal. The adjustment signal output by the control branch 30 includes a second adjustment signal. When the load changes, causing the output voltage to increase, the voltage comparison branch 20 determines that the output voltage is greater than a second preset voltage, and outputs the second activation signal to the control branch 30. Subsequently, the control branch 30 can output the second adjustment signal to adjust the second pulse width modulation signal, thereby increasing the on-time of the second power switch Q204 within at least one cycle. Since the on-time of the second power switch Q204 is negatively correlated with the output voltage of the voltage conversion circuit 200, the output voltage of the voltage conversion circuit 200 can be reduced, thus achieving rapid adjustment of the output voltage.

[0072] Conversely, when the load changes and the output voltage decreases, control branch 30 controls to extend the conduction time of the power switch that increases the output voltage.

[0073] For example, in some other embodiments, at least one power switch in the voltage conversion circuit 200 includes, for example, Figure 1 The first power switch Q202 is shown. The first power switch Q202 is controlled to be turned on or off by a first pulse width modulation signal. Furthermore, the on-time of the first power switch Q202 is positively correlated with the output voltage of the voltage conversion circuit 200. The activation signal output by the voltage comparison branch 20 also includes a first activation signal. The adjustment signal output by the control branch 30 includes a first adjustment signal. When the load changes, causing the output voltage to decrease, the voltage comparison branch 20 determines that the output voltage is less than a first preset voltage, and outputs the first activation signal to the control branch 30. Subsequently, the control branch 30 can output the first adjustment signal to adjust the first pulse width modulation signal, thereby increasing the on-time of the first power switch Q202 within at least one cycle. Since the on-time of the first power switch Q202 is positively correlated with the output voltage of the voltage conversion circuit 200, the output voltage of the voltage conversion circuit 200 can be increased, thus achieving rapid adjustment of the output voltage.

[0074] In summary, this system enables faster adjustment of the corresponding power switching transistors when the load changes, causing the output voltage to increase or decrease. This reduces the risk of abnormalities or damage to the load connected to the output of the voltage conversion circuit 200.

[0075] In one implementation, the control branch 30 is also used to: time a first duration after outputting the adjustment signal, and stop outputting the adjustment signal within the first duration.

[0076] Specifically, if control branch 30 continuously outputs an adjustment signal, it is equivalent to directly taking over the control of the logic controller in voltage conversion circuit 200, which may even cause oscillation, leading to abnormalities in both voltage conversion circuit 200 and the load. Therefore, after each time control branch 30 outputs an adjustment signal, it simultaneously starts timing for a first duration. During this first duration, even if control branch 30 receives an activation signal again, it will not output an adjustment signal again to maintain the stable operation of voltage conversion circuit 200.

[0077] In one embodiment, such as Figure 3 As shown, the voltage acquisition branch 10 includes a first resistor R1 and a second resistor R2 connected in series. Specifically, the non-series connection terminal of the first resistor R1 is connected to the output terminal of the voltage conversion circuit 200. The connection terminal between the first resistor R1 and the second resistor R2 is connected to the voltage comparison branch 20. The non-series connection terminal of the second resistor R2 is grounded.

[0078] The first resistor R1 and the second resistor R2 are used to divide the output voltage and output a first voltage to the voltage comparison branch 20. The voltage comparison branch 20 is also used to output an activation signal when the first voltage is less than a third preset voltage or greater than a fourth preset voltage. Specifically, when the output voltage is less than the first preset voltage, the first voltage is less than the third preset voltage; when the output voltage is greater than the second preset voltage, the first voltage is greater than the fourth preset voltage.

[0079] Figure 3 The diagram also shows one structure of the voltage comparison branch 20. For example... Figure 3 As shown, the voltage comparison branch 20 includes a first comparator 21 and a second comparator 22. The first input terminals of both the first comparator 21 and the second comparator 22 are connected to the voltage acquisition branch 10 (the connection point between the first resistor R1 and the second resistor R2). The second input terminal of the first comparator 21 receives a first preset voltage VREF1; the second input terminal of the second comparator 22 receives a second preset voltage VREF2; and the output terminals of both the first comparator 21 and the second comparator 22 are connected to the control branch 30.

[0080] In this embodiment, the first comparator 21 is used to acquire the output voltage of the voltage conversion branch 200 and to output a first activation signal when the output voltage is less than a first preset voltage VREF1; the second comparator 22 is used to acquire the output voltage of the voltage conversion branch 200 and to output a second activation signal when the output voltage is greater than a second preset voltage VREF2.

[0081] Please refer to Figure 4 , Figure 4 The example shown in the middle Figure 3 The auxiliary circuit 100 shown is Figure 1 The voltage conversion circuit 200 shown is connected in one of the following structures.

[0082] like Figure 4 As shown, the output terminal of control branch 30 is connected to the second terminal of resistor R202 at node P1. The adjustment signal output by control branch 30 acts on the ramp signal input to comparator 206, thereby indirectly affecting the first pulse width modulation signal and the second pulse width modulation signal output by logic controller 208.

[0083] Please refer to the above as well. Figure 4 and Figure 5 , Figure 5 This is a schematic diagram of the signals in the auxiliary circuit and voltage conversion circuit shown in an embodiment of this application. Figure 5 As shown, curve L1 is a schematic diagram of the clock signal CLK202 input to the ramp generator 202; curve L2 is a schematic diagram of the first adjustment signal output by the control branch 30; curve L3 is a schematic diagram of the signal on node P1; curve L4 is a schematic diagram of the first pulse width modulation signal controlling the first power switch Q202; curve L5 is a schematic diagram of the second pulse width modulation signal controlling the second power switch Q204; curve L6 is a schematic diagram of the output voltage output by the voltage conversion branch 100; and curve L7 is a schematic diagram of the first duration.

[0084] Specifically, assuming the output voltage is in a normal state before time t1. At time t1, as shown by curve L6, the output voltage is forcibly reduced to below a first preset voltage to simulate a load change. Then, at time t2, as shown by curve L2, control branch 30 outputs a first adjustment signal acting on a ramp signal at node P1. The duration of the first adjustment signal can be set according to the actual application; this embodiment does not impose specific limitations on this. Subsequently, the ramp signal at node P1 increases and remains until time t3. During the period from time t2 to t3, the first pulse width modulation signal remains high, and the second pulse width modulation signal remains low, meaning the first power switch Q202 remains on, and the second power switch Q204 remains off. At time t3, control branch 30 stops outputting the first adjustment signal, and the ramp signal returns to its normal state. In the above process, when the output voltage decreases, the on-time of the first power switch Q202 is increased within one cycle, which correspondingly reduces the on-time of the second power switch Q204. The increased on-time is the duration from time t2 to time t3.

[0085] Simultaneously, timing begins at time t2, and the duration of this timing is the first duration. As shown by curve L7, the duration between times t2 and t4 is the first duration. During this first duration, control branch 30 does not output the first adjustment signal. However, if the output voltage is still lower than the first preset voltage after the first duration ends, control branch 30 outputs the first adjustment signal again at time t5, acting on node P1 to keep the first pulse width modulation signal high again, thus extending the conduction time of the first power switch Q202 for another cycle. At time t7, the output voltage is forced to return to normal. In this case, even if the first duration ends at time t8, control branch 30 will not output the first adjustment signal again. Understandably, if the output voltage is again less than the first preset voltage, the conduction time of the first power switch Q202 can be increased by referring to the above process. For example, if the output voltage is forced to be less than the first preset voltage again after time t9, the control branch 30 will output the first adjustment signal at time t10 to increase the conduction time of the first power switch Q202.

[0086] Please refer to the above as well. Figure 4 and Figure 6 , Figure 6 This is a schematic diagram of the signals in the auxiliary circuit and voltage conversion circuit shown in another embodiment of this application. Figure 6 As shown, curve L1 is a schematic diagram of the clock signal CLK202 input to the ramp generator 202; curve L8 is a schematic diagram of the second adjustment signal output by the control branch 30; curve L9 is a schematic diagram of the signal on node P1; curve L10 is a schematic diagram of the first pulse width modulation signal controlling the first power switch Q202; curve L11 is a schematic diagram of the second pulse width modulation signal controlling the second power switch Q204; curve L12 is a schematic diagram of the output voltage output by the voltage conversion branch 100; and curve L13 is a schematic diagram of the first duration.

[0087] Specifically, assuming the output voltage is in a normal state before time t12. At time t12, as shown by curve L12, the output voltage is forcibly increased to a level greater than the second preset voltage to simulate a load change. Then, at time t13, as shown by curve L8, control branch 30 outputs a second adjustment signal acting on the ramp signal at node P1. The duration of the second adjustment signal can be set according to the actual application; this embodiment does not impose specific limitations on this. Subsequently, the ramp signal at node P1 decreases and remains until time t14. During the period from time t13 to time t14, the first pulse width modulation signal remains at a low level, and the second pulse width modulation signal remains at a high level; that is, the first power switch Q202 remains off, and the second power switch Q204 remains on. At time t14, control branch 30 stops outputting the second adjustment signal, and the ramp signal returns to its normal state. In the above process, when the output voltage increases, the on-time of the second power switch Q204 is increased within one cycle, which correspondingly reduces the on-time of the first power switch Q202. The increased on-time is the duration from time t13 to time t14.

[0088] Simultaneously, timing begins at time t13, with the timing duration being the first duration. As shown by curve L13, the duration between times t14 and t15 is the first duration. During this first duration, control branch 30 does not output the second adjustment signal. However, if the output voltage is still higher than the second preset voltage after the first duration ends, control branch 30 outputs the second adjustment signal again at time t16, acting on node P1 to keep the second pulse width modulation signal high again, thus extending the conduction time of the second power switch Q204 for another cycle. At time t18, the output voltage is forced back to normal. In this case, even if the first duration ends at time t19, control branch 30 will not output the second adjustment signal again. Understandably, if the output voltage is greater than the second preset voltage again, the conduction time of the second power switch Q204 can be increased by referring to the above process. For example, if the output voltage is forced to be greater than the second preset voltage again after time t20, the control branch 30 will output the second adjustment signal at time t21 to increase the conduction time of the second power switch Q204.

[0089] Through the above process, the output voltage is adjusted promptly when the load changes. Furthermore, by directly applying the adjustment signal to the ramp signal to adjust the corresponding pulse width modulation signal, a fast response speed is achieved. In addition, the adjustment signal output by the auxiliary circuit 100 only affects the dynamic behavior of the logic controller 208 and does not reduce the control accuracy of the voltage conversion circuit 200.

[0090] It should be noted that in this embodiment, the adjustment signal output by control branch 30 is applied to node P1, indirectly changing the pulse width modulation signal output by logic controller 208. In other embodiments, the adjustment signal output by control branch 30 can also be applied to other locations in the voltage conversion circuit 200, as long as it can correspondingly adjust the pulse width modulation signal output by logic controller 208. This application does not impose specific limitations on this. For example, the adjustment signal output by control branch 30 can be directly applied to the pulse width modulation signal output by logic controller 208.

[0091] Please refer to Figure 7 , Figure 7 The diagram shows a structural schematic of an auxiliary circuit 100 provided in another embodiment of this application. Figure 7 As shown, the control branch 30 includes a signal latch sub-branch 31, a signal output sub-branch 32, and a signal suppression sub-branch 33. The signal suppression sub-branch 33 is connected to the signal latch sub-branch 31. The signal latch sub-branch 31 is also connected to the voltage comparison branch 20 and the signal output sub-branch 32, respectively.

[0092] Specifically, the signal suppression sub-branch 31, upon receiving an activation signal, maintains the output suppression signal to the signal latch sub-branch 31 for a certain period of time. The signal latch sub-branch 31, when no suppression signal is received, latches the activation signal and transmits the latched signal to both the signal output sub-branch 32 and the signal suppression sub-branch 33. The signal output sub-branch 32 outputs an adjustment signal based on the activation signal.

[0093] In this embodiment, when the load changes, the output voltage changes, and the voltage comparison branch 20 outputs an activation signal to the signal latch sub-branch 31. The signal latch sub-branch 31 then latches the activation signal and sends it to the signal output sub-branch 32 and the signal suppression sub-branch 33, respectively. On one hand, after receiving the activation signal, the signal suppression sub-branch 33 maintains an output suppression signal to the signal latch sub-branch 31 for a first duration, so that the signal latch sub-branch 31 does not output the activation signal during the first duration. On the other hand, after receiving the activation signal, the signal output sub-branch 32 outputs a corresponding adjustment signal based on the activation signal to adjust the first pulse width modulation signal and the second pulse width modulation signal.

[0094] Please refer to Figure 8 , Figure 8 The diagram illustrates one structure of the control branch 30.

[0095] In one embodiment, such as Figure 8As shown, the signal latching sub-branch 31 includes a first NOR gate a1 and a first D flip-flop b1. The first NOR gate a1 is connected between the voltage comparison branch 20 and the first D flip-flop b1. The first D flip-flop b1 is also connected to the signal output sub-branch 32 and the signal suppression sub-branch 33, respectively.

[0096] Specifically, the first input terminal of the first NOR gate a1 is connected to the output terminal of the voltage comparison branch 20 (i.e., the output terminal of the first comparator 21). The second input terminal of the first NOR gate a1 (i.e., the end of the first NOR gate not connected to the first comparator 21) is connected to the output terminal (not shown) of the signal suppression sub-branch 33 and is used to input the suppression signal output by the signal suppression sub-branch 33. The output terminal of the first NOR gate a1 is connected to the first input terminal of the first D flip-flop b1. The output terminal of the first D flip-flop b1 is connected to both the signal output sub-branch 32 and the signal suppression sub-branch 33.

[0097] In this embodiment, the first NOR gate a1 is used to output a first-level signal based on the activation signal when no suppression signal is received, and to output a second-level signal when a suppression signal is received. For example, when the output voltage of the voltage conversion circuit 200 is less than the first preset voltage, causing the first comparator 21 to output a low-level signal, if the signal suppression sub-branch 33 has not yet output a suppression signal (assuming it is a high-level signal), then both inputs of the first NOR gate a1 are low-level signals, and the first NOR gate a1 outputs a high-level signal (i.e., the first-level signal); if the signal suppression sub-branch 33 has already output a suppression signal, then the two inputs of the first NOR gate a1 are low-level signals and high-level signals respectively, and the first NOR gate a1 outputs a low-level signal (i.e., the second-level signal). The first D flip-flop b1 is used to transmit the first-level signal or the second-level signal to the signal output sub-branch 32 and the signal suppression sub-branch 33 respectively.

[0098] It should be noted that the above only shows a portion of the circuitry of the signal latch sub-branch 31 connected to the first comparator 21. Of course, the portion of the circuitry connected to the second comparator 22 can be configured in the same manner. For example... Figure 8 As shown, the signal latch sub-branch 31 includes a second NOR gate a2 and a third D flip-flop b2. The specific connection and application are similar to the circuit connected to the first comparator 21. It is within the scope of what those skilled in the art can easily understand, and will not be described in detail here.

[0099] In one embodiment, please continue to refer to Figure 8 The signal output sub-branch 32 includes a first delay module 321, a first NAND gate e1, a first NOT gate f1, a second NAND gate e2 and a first switch Q1 connected in sequence. The first switch Q1 is connected to the voltage conversion circuit 200 through interface S1.

[0100] In this circuit, the first input terminal of the first NAND gate e1 is connected to the first delay module 321. The second input terminal of the first NAND gate e1 is connected to the output terminal of the signal latch sub-branch 31. The input terminal of the first NOT gate f1 is connected to the output terminal of the first NAND gate e1. The output terminal of the first NOT gate f1 is connected to the first input terminal of the second NAND gate e2. The output terminal of the second NAND gate e2 is connected to the first terminal of the first switch Q1. The second terminal of the first switch Q1 is connected to the first power supply V1. The third terminal of the first switch Q1 is connected to the voltage conversion circuit 200 through interface S1.

[0101] Specifically, the first delay module 321 is used to control the duration of the activation signal. Corresponding to the above embodiment, the first delay module 321 is used to control the delay duration of the first level signal. The combination of the first NAND gate e1, the first NOT gate f1, the second NAND gate e2, and the first switch Q1 is used to output an adjustment signal based on the activation signal within the duration of the activation signal.

[0102] In this embodiment, the first delay module 321 includes four multiplexers: a first multiplexer C1, a second multiplexer C2, a third multiplexer C3, and a fourth multiplexer d1. The combination of the first multiplexer C1, the second multiplexer C2, and the third multiplexer C3 is used for delay, while the fourth multiplexer d1 determines how many multiplexers to select for delay, thus determining the delay duration. For example, the fourth multiplexer d1 can select the first multiplexer C1 and the second multiplexer C2 for delay, or it can select the first multiplexer C1, the second multiplexer C2, and the third multiplexer C3 for delay, etc. This embodiment uses a combination of three multiplexers for delay as an example; however, in other embodiments, more or fewer multiplexers can be selected to implement the delay function, and this application does not specifically limit this.

[0103] Subsequently, after the first D flip-flop outputs the first level signal (i.e., a high-level signal) corresponding to the activation signal, before the first delay module 321 has completed its delay duration, the fourth multiplexer d1 outputs a low-level signal. Then, the first NAND gate e1 outputs a high-level signal, the first NOT gate f1 outputs a low-level signal, and the second NAND gate e2 outputs a high-level signal. The first switch Q1 is turned on, outputting a high-level signal (i.e., the first adjustment signal) based on the first power supply V1, and acting on the pulse width modulation signal in the voltage conversion circuit 200 through interface S1, thereby extending the power switch (e.g., the one that increases the output voltage of the voltage conversion circuit 200) that increases the output voltage of the voltage conversion circuit 200. Figure 4The first power switch (Q202) in the circuit is turned on for a certain duration. Then, if the first delay module 321 has reached its delay duration, the fourth multiplexer d1 outputs a high-level signal. The first NAND gate e1 outputs a low-level signal, the first NOT gate f1 outputs a high-level signal, and the second NAND gate e2 outputs a low-level signal, causing the first switch Q1 to turn off and stop outputting the first adjustment signal.

[0104] Similarly, the signal output sub-branch 32 may also include circuitry similar to the circuitry described above. Specifically, the signal output sub-branch 32 further includes a third delay module 322, a fourth NAND gate e3, a second NOT gate f2, a fifth NAND gate e4, and a second switch Q2. The specific connection and application methods are similar to those of the circuitry connected to the first D flip-flop b1, and will not be elaborated further here as they are readily understood by those skilled in the art.

[0105] In one embodiment, please continue to refer to Figure 8 The signal suppression sub-branch includes a third NAND gate e5, a second D flip-flop, and a second delay module 331 connected in sequence.

[0106] Specifically, both the first and second inputs of the third NAND gate e5 are connected to the signal latch sub-branch 31. The first input of the third NAND gate e5 is connected to the output of the first D flip-flop b1, and the second input of the third NAND gate e5 is connected to the output of the third D flip-flop b2. The first input of the second D flip-flop b3 is connected to the output of the third NAND gate e5. The output of the second D flip-flop b3 is connected to the second delay module 331.

[0107] In this embodiment, the combination of the third NAND gate e5 and the second D flip-flop b3 is used to output a suppression signal when an activation signal is received. Specifically, in the above embodiment, the combination of the third NAND gate e5 and the second D flip-flop b3 is used to output a suppression signal when a first level signal output by the first D flip-flop b1 is received; or the combination of the third NAND gate e5 and the second D flip-flop b3 is used to output a suppression signal when a third level signal output by the second D flip-flop b2 is received. When the first comparator 21 outputs a first activation signal, the first D flip-flop b1 outputs a first level signal; when the second comparator 22 outputs a second activation signal, the second D flip-flop b2 outputs a third level signal.

[0108] The second delay module 331 is used to control the duration of the suppression signal, which corresponds to the first duration in the above embodiment. The second delay module 331 includes a fourth D flip-flop b4, a fifth D flip-flop b5, a sixth D flip-flop b6, a seventh D flip-flop b7, a fifth multiplexer d3, a sixth NAND gate e6, and a third NOT gate f3. The combination of the fourth D flip-flop b4, fifth D flip-flop b5, sixth D flip-flop b6, and seventh D flip-flop b7 is used for delay, while the combination of the fifth multiplexer d3, sixth NAND gate e6, and third NOT gate f3 is used to determine how many D flip-flops to select for delay, thereby determining the delay duration. For example, the combination of the fifth multiplexer d3, sixth NAND gate e6, and third NOT gate f3 can select only the fourth D flip-flop b4 to achieve the delay, or it can select the fourth D flip-flop b4, fifth D flip-flop b5, sixth D flip-flop b6, and seventh D flip-flop b7 to achieve the delay, etc. Meanwhile, this embodiment uses a combination of four D flip-flops for delay as an example. In other embodiments, more or fewer D flip-flops can be selected to implement the delay function. This application does not specifically limit this.

[0109] Furthermore, this embodiment may also include other functions, such as a reset function. For example, the signal latch sub-branch 31 further includes a seventh NAND gate e7 and a fourth NOT gate f4. The first input terminal of the fourth NAND gate e7 is used to input a reset signal, the output terminal of the fourth NAND gate e7 is connected to the input terminal of the fourth NOT gate f4, and the output terminal of the fourth NOT gate f4 is connected to the second input terminal of the first D flip-flop b1. If a reset signal is input to the fourth NAND gate e7, the fourth NOT gate f4 outputs a signal corresponding to the reset signal, which is then input to the first D flip-flop b1 to reset the first D flip-flop b1.

[0110] This application also provides an electronic device, which includes the auxiliary circuit 100 and voltage conversion circuit 200 in any embodiment of this application.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An auxiliary circuit, characterized in that, For connection to a voltage conversion circuit, the voltage conversion circuit includes a ramp generator, an error amplifier, a comparator, a logic controller, a first power switch, a second power switch, resistors, inductors, and capacitors. A clock signal is generated by the ramp generator to produce a ramp signal. This ramp signal is then input to one input of the comparator after passing through the resistor. The difference between the feedback signal and the reference voltage is amplified by the error amplifier and input to the other input of the comparator. The comparator outputs a signal to the logic controller based on the magnitude relationship of the voltages input to its two inputs. The logic controller outputs two corresponding pulse width modulation (PWM) signals to control the first and second power switches respectively, wherein the first PWM signal controls the first power switch, and the second PWM signal controls the second power switch. The first and second PWM signals are complementary signals. The auxiliary circuit includes: A voltage acquisition branch is connected to the output terminal of the voltage conversion circuit, and the voltage acquisition branch is used to acquire the output voltage of the output terminal of the voltage conversion circuit. A voltage comparison branch is connected to the voltage acquisition branch. The voltage comparison branch is used to output an activation signal when the output voltage is less than a first preset voltage or greater than a second preset voltage. The voltage comparison branch is also used to output a first activation signal when the output voltage is less than a first preset voltage; the voltage comparison branch is also used to output a second activation signal when the output voltage is greater than a second preset voltage; A control branch is connected to the voltage comparison branch, and the control branch is connected to the second terminal of the resistor and one input terminal of the comparator. The control branch is used to output an adjustment signal to act on the ramp signal input to the comparator when the activation signal is received, so as to indirectly act on the first pulse width modulation signal and the second pulse width modulation signal output by the logic controller. The control branch is further configured to: upon receiving the first activation signal, output a first adjustment signal to adjust the first pulse width modulation signal to increase the conduction duration of the first power switch within at least one cycle; and upon receiving the second activation signal, output a second adjustment signal to adjust the second pulse width modulation signal to increase the conduction duration of the second power switch within at least one cycle, wherein the conduction duration of the first power switch is positively correlated with the output voltage, and the conduction duration of the second power switch is negatively correlated with the output voltage.

2. The auxiliary circuit according to claim 1, characterized in that, The control branch is also used to: time a first duration after outputting the adjustment signal; During the first time period, the control branch stops outputting the adjustment signal.

3. The auxiliary circuit according to claim 1, characterized in that, The voltage acquisition branch includes a first resistor and a second resistor connected in series; The first resistor and the second resistor are used to divide the output voltage and output a first voltage to the voltage comparison branch; The voltage comparison branch is also used to output the activation signal when the first voltage is less than the third preset voltage or greater than the fourth preset voltage; Specifically, when the output voltage is less than the first preset voltage, the first voltage is less than the third preset voltage; when the output voltage is greater than the second preset voltage, the first voltage is greater than the fourth preset voltage.

4. The auxiliary circuit according to claim 3, characterized in that, The non-series connection terminal of the first resistor is connected to the output terminal of the voltage conversion circuit, the connection terminal between the first resistor and the second resistor is connected to the voltage comparison branch, and the non-series connection terminal of the second resistor is grounded.

5. The auxiliary circuit according to claim 1, characterized in that, The voltage comparison branch includes a first comparator and a second comparator; The first comparator is used to acquire the output voltage and to output a first activation signal when the output voltage is less than the first preset voltage; The second comparator is used to acquire the output voltage and to output a second activation signal when the output voltage is greater than the second preset voltage.

6. The auxiliary circuit according to claim 5, characterized in that, The first input terminal of the first comparator and the first input terminal of the second comparator are both connected to the voltage acquisition branch. The second input terminal of the first comparator receives the first preset voltage, and the second input terminal of the second comparator receives the second preset voltage. The output terminals of the first comparator and the second comparator are both connected to the control branch.

7. The auxiliary circuit according to claim 1, characterized in that, The control branch includes a signal latching sub-branch, a signal output sub-branch, and a signal suppression sub-branch; The signal suppression sub-branch is connected to the signal latching sub-branch. The signal suppression sub-branch is used to maintain the output suppression signal to the signal latching sub-branch for a first time period after receiving the activation signal. The signal latching sub-branch is also connected to the voltage comparison sub-branch and the signal output sub-branch respectively. The signal latching sub-branch is used to latch the activation signal when the suppression signal is not received, and transmit the latched signal to the signal output sub-branch and the signal suppression sub-branch respectively. The signal output sub-branch is used to output the adjustment signal based on the activation signal.

8. The auxiliary circuit according to claim 7, characterized in that, The signal latch sub-branch includes a first NOR gate and a first D flip-flop; The first NOR gate is connected between the voltage comparison branch and the first D flip-flop. The first NOR gate is used to output a first level signal based on the activation signal when the suppression signal is not received, and to output a second level signal when the suppression signal is received. The first D flip-flop is also connected to the signal output sub-branch and the signal suppression sub-branch respectively. The first D flip-flop is used to transmit the first level signal or the second level signal to the signal output sub-branch and the signal suppression sub-branch respectively.

9. The auxiliary circuit according to claim 8, characterized in that, The first input terminal of the first NOR gate is connected to the output terminal of the voltage comparison branch, the second input terminal of the first NOR gate is connected to the output terminal of the signal suppression sub-branch, the output terminal of the first NOR gate is connected to the first input terminal of the first D flip-flop, and the output terminal of the first D flip-flop is connected to the signal output sub-branch and the signal suppression sub-branch respectively.

10. The auxiliary circuit according to claim 7, characterized in that, The signal output sub-branch includes a first delay module, a first NAND gate, a first NOT gate, a second NAND gate, and a first switching transistor connected in sequence. The first switching transistor is also connected to the voltage conversion circuit. The first delay module is used to control the duration of the activation signal; The combination of the first NAND gate, the first NOT gate, the second NAND gate, and the first switch is used to output the adjustment signal based on the activation signal during the duration of the duration.

11. The auxiliary circuit according to claim 10, characterized in that, The first input terminal of the first NAND gate is connected to the first delay module, the second input terminal of the first NAND gate is connected to the output terminal of the signal latch sub-branch, the input terminal of the first NOT gate is connected to the output terminal of the first NAND gate, the output terminal of the first NOT gate is connected to the first input terminal of the second NAND gate, the output terminal of the second NAND gate is connected to the first terminal of the first switching transistor, the second terminal of the first switching transistor is connected to the first power supply, and the third terminal of the first switching transistor is connected to the voltage conversion circuit.

12. The auxiliary circuit according to claim 7, characterized in that, The signal suppression sub-branch includes a third NAND gate, a second D flip-flop, and a second delay module connected in sequence. The combination of the third NAND gate and the second D flip-flop is used to output the suppression signal when the activation signal is received; The second delay module is used to control the duration of the suppression signal.

13. The auxiliary circuit according to claim 12, characterized in that, The first and second input terminals of the third NAND gate are both connected to the signal latch sub-branch, the first input terminal of the second D flip-flop is connected to the output terminal of the third NAND gate, and the output terminal of the second D flip-flop is connected to the second delay module.

14. An electronic device, characterized in that, It includes a voltage conversion circuit and an auxiliary circuit as described in any one of claims 1-13.

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