A high-voltage-resistant interface circuit, an interface device and a CMOS chip

Abstract

The embodiment of the application discloses a high-voltage-resistant interface circuit, an interface device and a CMOS chip, the high-voltage-resistant interface circuit comprises an input-output interface, a signal input interface, a signal output interface, an enable signal interface, a first inverter, a second inverter, an NAND gate, an NOR gate, a switch unit, a first control unit, a second control unit, a first isolation transistor, a second isolation transistor, a pull-up driving transistor and a pull-down driving transistor; based on the high-voltage-resistant interface circuit, a chip can directly communicate signals with an external device, when signal voltage output by the external device is greater than power supply voltage signal voltage of the chip, the switch unit, the first control unit, the second control unit and each isolation transistor can effectively prevent signal of the external device from flowing back to the chip through the pull-up driving transistor or the pull-down driving transistor while ensuring normal communication of the chip.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a high-voltage resistant interface circuit, interface device, and CMOS chip. Background Technology

[0002] The voltage levels at the input / output interfaces of a chip often exceed its operating power supply voltage. For example, the operating power supply voltage at the input / output interfaces of a CMOS chip is generally no more than 3.3V, while the transistor-to-transistor logic (TTL) level is 5V. A typical CMOS chip interface circuit is as follows: Figure 1 As shown, if a 5V TTL level is connected to the input / output interface of the CMOS chip, while the internal operating power supply VDD of the CMOS chip is only 3.3V, the parasitic diode of the pull-up driver transistor MP1 will experience reverse current, which may burn out the chip in severe cases.

[0003] The existing solution requires adding an intermediate isolation device between the CMOS chip interface and the TTL level to prevent damage to the CMOS chip. This solution is costly and complex to operate when the CMOS chip needs to be connected to external devices. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a high-voltage resistant interface circuit, an interface device, and a CMOS chip, with the specific solution as follows: In a first aspect, embodiments of this application provide a high-voltage resistant interface circuit for providing an interface for a CMOS chip. The high-voltage resistant interface circuit includes: an input / output interface, a signal input interface, a signal output interface, an enable signal interface, a first inverter, a second inverter, a NAND gate, a NOR gate, a switching unit, a first control unit, a second control unit, a first isolation transistor, a second isolation transistor, a pull-up drive transistor, and a pull-down drive transistor. Both the signal input interface and the signal output interface are used to connect to the CMOS chip. The signal input interface is used to receive signals sent by the CMOS chip, and the signal output interface is used to input signals to the CMOS chip. The input and output interfaces are used to connect to external devices. The enable signal interface is connected to the first input terminal of the NAND gate through the first inverter. The enable signal interface is also connected to the first input terminal of the NOR gate. The second input terminal of the NAND gate and the second input terminal of the NOR gate are both connected to the signal input interface. The output of the NAND gate is connected to the control terminal of the pull-up driving transistor through the first control unit. The source terminal of the pull-up driving transistor is used to connect to the power supply voltage signal, and the drain terminal of the pull-up driving transistor is used to connect to the input / output interface. The output terminal of the NOR gate is connected to the control terminal of the pull-down driving transistor, the source terminal of the pull-down driving transistor is grounded, and the drain terminal of the pull-down driving transistor is connected to the input / output interface through the first isolation transistor. The input / output interface is connected to the signal output interface via a voltage divider resistor, a second isolation transistor, and a second inverter. One end of the second control unit is used to receive the power supply voltage signal, and the other end of the second control unit is connected to the substrate of the pull-up drive transistor. The second control unit is used to turn off when the voltage at the input / output interface is greater than or equal to a preset voltage threshold, and to turn on when the voltage at the input / output interface is less than the preset voltage threshold. One end of the switching unit is connected to the input / output interface through the voltage divider resistor, and the other end of the switching unit is connected to the substrate and control terminal of the pull-up drive transistor. The switching unit is used to turn on when the voltage at the input / output interface is greater than or equal to a preset voltage threshold, and to turn off when the voltage at the input / output interface is less than the preset voltage threshold.

[0005] According to a specific embodiment of the present application, the first control unit includes a first control transistor and a second control transistor, and the second control unit includes a third control transistor and a weak pull-down transistor group. The source terminal of the third control transistor is used to connect to the power supply voltage signal, and the drain terminal of the third control transistor is connected to the substrate terminal of the pull-up drive transistor through the first potential point. The output of the NAND gate is connected to the control terminal of the pull-up driving transistor through the first control transistor and the second control transistor, respectively. The control terminal of the first control transistor is connected to the control terminal of the third control transistor through the second potential point. The control terminal of the second control transistor is used to access the power supply voltage signal. The weak pull-down transistor group includes a predetermined number of N-type transistors connected in series, wherein the control terminal of each N-type transistor is connected to the drain terminal, and the voltage of the control terminal of each N-type transistor is obtained by voltage division of the second potential point.

[0006] According to a specific embodiment of the present application, the switching unit includes a first switching transistor, a second switching transistor, and a third switching transistor; The control terminals of the first switching transistor, the second switching transistor, and the third switching transistor are all used to connect to the power supply voltage signal; The source terminals of the first switching transistor, the second switching transistor, and the third switching transistor are all connected to the input / output interface through the voltage divider resistor; The drain terminal of the first switching transistor is connected to the substrate terminals of the first switching transistor, the second switching transistor, the third switching transistor, the first control transistor, the pull-up drive transistor, and the third control transistor respectively through the first potential point; The drain of the second switching transistor is connected to the control terminal of the third control transistor through the second potential point, and the drain of the third switching transistor is connected to the control terminal of the pull-up drive transistor. The first switching transistor, the second switching transistor, the third switching transistor, the first control transistor, the third control transistor, and the pull-up driving transistor are all P-type transistors, and the second control transistor, the first isolation transistor, the second isolation transistor, and the pull-down driving transistor are all N-type transistors.

[0007] According to a specific embodiment of this application, the source terminal of the first control transistor is connected to the output terminal of the NAND gate, and the drain terminal of the first control transistor is connected to the control terminal of the pull-up drive transistor. The source terminal of the second control transistor is connected to the output terminal of the NAND gate, and the drain terminal of the second control transistor is connected to the control terminal of the pull-up drive transistor.

[0008] According to a specific embodiment of this application, the drain of the pull-down driving transistor is connected to the source of the first isolation transistor, and the drain of the first isolation transistor is connected to the input / output interface. The source of the second isolation transistor is connected to the input / output interface through the voltage divider resistor, and the drain of the second isolation transistor is connected to the signal output interface through the second inverter.

[0009] According to a specific embodiment of this application, when the enable signal interface is used to access a power supply voltage signal, the input / output interface is in input mode; when the enable signal interface is used to access a ground signal, the input / output interface is in output mode. The input / output interface is used to output signals to the external device in the output mode, and the input / output interface is used to receive signals sent by the external device in the input mode.

[0010] According to a specific embodiment of the present application, when the enable signal interface is used to access a power supply voltage signal, the second isolation transistor is turned on; If the voltage value of the signal received by the input / output interface is greater than or equal to the preset voltage threshold, the first switching transistor, the second switching transistor, and the third switching transistor are turned on, and the first control transistor, the second control transistor, the third control transistor, the pull-up drive transistor, the pull-down drive transistor, and the first isolation transistor are all turned off. If the voltage value of the signal received by the input / output interface is less than the preset voltage threshold, the first switching transistor, the second switching transistor, and the third switching transistor are all turned off, the first control transistor and the third control transistor are all turned on, and the pull-up drive transistor, the pull-down drive transistor, the second control transistor, and the first isolation transistor are all turned off.

[0011] According to a specific embodiment of this application, when the enable signal interface is used to access the ground signal, the first switching transistor, the second switching transistor, and the third switching transistor are all turned off, and the third control transistor is turned on. If the signal input interface is used to receive a high-level signal, the first control transistor is turned off, the second control transistor is turned on, the pull-up drive transistor is turned on, the pull-down drive transistor is turned off, and the input / output interface is used to output a high-level signal. If the signal input interface is used to receive a low-level signal, the first control transistor is turned on, the second control transistor is turned off, the pull-up drive transistor is turned off, the pull-down drive transistor is turned on, and the input / output interface is used to output a low-level signal.

[0012] Secondly, embodiments of this application provide an interface device, which includes the high-voltage resistant interface circuit described in the first aspect and any embodiment of the first aspect.

[0013] Thirdly, embodiments of this application provide a CMOS chip, which includes the interface device described in the second aspect.

[0014] This application provides a high-voltage resistant interface circuit, interface device, and CMOS chip. Based on the high-voltage resistant interface circuit proposed in this invention, the CMOS chip can directly communicate with external devices. When the signal voltage output by the external device is greater than the power supply voltage of the CMOS chip, the switching unit, the first control unit, the second control unit, and each isolation transistor ensure normal communication of the CMOS chip while effectively preventing the signal from the external device from flowing back to the CMOS chip through the pull-up or pull-down transistors. This effectively improves the communication security of the CMOS chip. Furthermore, the high-voltage resistant interface circuit proposed in this embodiment can be implemented with a small number of transistors, making the connection scheme between the CMOS chip and external devices simpler and more convenient. Attached Figure Description

[0015] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope of protection of the present invention. In the various drawings, similar components are numbered similarly.

[0016] Figure 1 This illustration shows one of the circuit structure diagrams of a high-voltage resistant interface circuit provided in an embodiment of this application; Figure 2 The second schematic diagram of the circuit structure of a high-voltage resistant interface circuit provided in this application embodiment is shown.

[0017] Summary of attached image labels: Input / output interface - PAD; Signal input interface - IN; Signal output interface - OUT; Enable signal interface - OEN; First inverter - INV1; Second inverter - INV2; NAND gate - ND1; NOR gate - NR1; First switching transistor - MP2; Second switching transistor - MP4; Third switching transistor - MP5; First control transistor - MP6; Second control transistor - MN4; Third control transistor - MP3; First isolation transistor - MN1; Second isolation transistor - MN3; Pull-up drive transistor - MP1; Pull-down drive transistor - MN2; First potential point - FNW; Second potential point - INT. Detailed Implementation

[0018] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0019] The components of the embodiments of the invention described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0020] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of the invention, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.

[0021] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0022] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the invention pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of the invention.

[0023] refer to Figure 1 This is a schematic diagram of a high-voltage resistant interface circuit provided in an embodiment of this application. The high-voltage resistant interface circuit provided in this embodiment is used to provide an interface for a CMOS chip, such as... Figure 1 As shown, the high-voltage interface circuit includes: input / output interface PAD, signal input interface IN, signal output interface OUT, enable signal interface OEN, first inverter INV1, second inverter INV2, NAND gate ND1, NOR gate NR1, switching unit, first control unit, second control unit, first isolation transistor MN1, second isolation transistor MN3, pull-up drive transistor MP1, and pull-down drive transistor MN2; Both the signal input interface IN and the signal output interface OUT are used to connect to the CMOS chip. The signal input interface IN is used to receive signals sent by the CMOS chip, and the signal output interface OUT is used to input signals to the CMOS chip. The input / output interface PAD is used to connect to external devices. When the input / output interface PAD is used as an input interface, the signal output interface OUT is used to output signals to the CMOS chip. When the input / output interface PAD is used as an output interface, the signal input interface IN is used to receive signals sent by the CMOS chip. The enable signal interface OEN is connected to the first input terminal of the NAND gate ND1 through the first inverter INV1. The enable signal interface OEN is also connected to the first input terminal of the NOR gate NR1. The second input terminals of the NAND gate ND1 and the NOR gate NR1 are both connected to the signal input interface IN. The output of the NAND gate ND1 is connected to the control terminal of the pull-up drive transistor MP1 through the first control unit. The source terminal of the pull-up drive transistor MP1 is used to connect to the power supply voltage signal, and the drain terminal of the pull-up drive transistor MP1 is used to connect to the input / output interface PAD. The output terminal of the NOR gate NR1 is connected to the control terminal of the pull-down driving transistor MN2. The source terminal of the pull-down driving transistor MN2 is grounded, and the drain terminal of the pull-down driving transistor MN2 is connected to the input / output interface PAD through the first isolation transistor MN1. The input / output interface PAD is connected to the signal output interface OUT through a voltage divider resistor, a second isolation transistor MN3, and a second inverter INV2. One end of the second control unit is used to connect to the power supply voltage signal VDD, and the other end of the second control unit is connected to the substrate of the pull-up drive transistor MP1. The second control unit is used to turn off when the voltage at the input / output interface PAD is greater than or equal to a preset voltage threshold, and to turn on when the voltage at the input / output interface PAD is less than the preset voltage threshold. One end of the switching unit is connected to the input / output interface PAD through the voltage divider resistor, and the other end of the switching unit is connected to the substrate and control terminal of the pull-up drive transistor MP1. The switching unit is used to turn on when the voltage at the input / output interface PAD is greater than or equal to a preset voltage threshold, and to turn off when the voltage at the input / output interface PAD is less than the preset voltage threshold.

[0024] Specifically, the CMOS chip is a complementary metal-oxide-semiconductor (CMOS) chip. In specific application scenarios, the CMOS chip is a read-write RAM chip used to store hardware configuration information and user-defined settings parameters in the computer system.

[0025] The high-voltage interface circuit provided in this embodiment can provide a connection design scheme for the CMOS chip to communicate with other devices in the computer system. That is, the CMOS chip can realize information communication with external devices through the signal input interface IN and the signal output interface OUT.

[0026] The external device can be any device in the computer system that needs to communicate with the CMOS chip, or it can be a device outside the computer system that needs to communicate with the CMOS chip. This embodiment does not limit this.

[0027] The external device communicates with the CMOS chip via the input / output interface PAD.

[0028] In addition, before the CMOS chip communicates with external devices, it can send an enable signal to the enable signal interface OEN according to the transmit or receive function to be executed, so as to determine whether the chip is sending a signal to the external device or receiving a signal from the external device, that is, to determine whether the input / output interface PAD is used as an input interface or as an output interface.

[0029] Specifically, when the enable signal interface OEN is used to connect to a power supply voltage signal, the input / output interface PAD is in input mode; when the enable signal interface OEN is used to connect to a ground signal, the input / output interface PAD is in output mode. The input / output interface PAD is used in the output mode to receive signals sent by the chip through the input interface IN and to output signals to the external device through the input / output interface PAD. In the input mode, the input / output interface PAD is used to receive signals sent by the chip through the input / output interface PAD and to output signals to the external device through the output interface OUT.

[0030] In a specific embodiment, when an external device needs to send a signal to the CMOS chip, it sends a power voltage signal to the enable signal interface OEN. At this time, the input / output interface PAD serves as an input interface, and the signal sent by the external device is transmitted to the CMOS chip through the input / output interface PAD and the signal output interface OUT.

[0031] When an external device needs to obtain a signal from the CMOS chip, it sends a ground signal to the enable signal interface OEN. At this time, the input / output interface PAD acts as an output interface, and the signal from the CMOS chip is transmitted to the external device through the signal input interface IN and the input / output interface PAD.

[0032] The switching unit can be a switching device that switches on and off according to the change in the voltage of the input / output interface PAD. Specifically, when the voltage of the input / output interface PAD is greater than a preset voltage threshold, the switching unit is turned on so that the voltage of the substrate and control terminal of the pull-up driving transistor MP1 is synchronized with the voltage at the input / output interface PAD.

[0033] When the voltage of the input / output interface PAD is less than the preset voltage threshold, the switching unit is turned off. At this time, the voltage of the control terminal of the pull-up drive transistor MP1 is determined by the on / off state of the first control unit, and the voltage of the substrate terminal of the pull-up drive transistor MP1 is determined by the on / off state of the second control unit.

[0034] When the voltage of the input / output interface PAD is greater than or equal to a preset voltage threshold, the input / output interface PAD is in input mode, and the voltage value of the signal sent by the connected external device is greater than the voltage value of the power supply voltage signal of the CMOS chip. The switching unit can synchronize the voltage at the input / output interface PAD to the control terminal and the substrate terminal of the second control unit so that the second control unit remains off.

[0035] When the voltage of the input / output interface PAD is less than a preset voltage threshold, the input / output interface PAD can be in either input or output mode. The control terminal of the second control unit is grounded, and the second control unit is turned on, guiding the power supply voltage signal from the source end to the substrate of the pull-up drive transistor through the first potential point FNW. The first control unit controls the switching on and off of the pull-up drive transistor based on the output signal of the NAND gate.

[0036] In one specific embodiment, the first control unit includes a first control transistor MP6 and a second control transistor MN4, and the second control unit includes a third control transistor MP3 and a weak pull-down transistor group. The source terminal of the third control transistor MP3 is used to connect to the power supply voltage signal VDD, and the drain terminal of the third control transistor MP3 is connected to the substrate terminal of the pull-up drive transistor MP1 through the first potential point FNW; the control terminal of the third control transistor MP3 is grounded through the weak pull-down transistor group. The output of the NAND gate ND1 is connected to the control terminal of the pull-up drive transistor MP1 through the first control transistor MP6 and the second control transistor MN4, respectively. The control terminal of the first control transistor MP6 is connected to the control terminal of the third control transistor MP3 through the second potential point INT. The control terminal of the second control transistor MN4 is used to connect to the power supply voltage signal VDD. The switching unit includes a first switching transistor MP2, a second switching transistor MP4, and a third switching transistor MP5; The control terminals of the first switching transistor MP2, the second switching transistor MP4, and the third switching transistor MP5 are all used to connect to the power supply voltage signal VDD; The source terminals of the first switching transistor MP2, the second switching transistor MP4, and the third switching transistor MP5 are all connected to the input / output interface PAD through the voltage divider resistor; The drain of the first switching transistor MP2 is connected to the substrates of the first switching transistor MP2, the second switching transistor MP4, the third switching transistor MP5, the first control transistor MP6, the pull-up drive transistor MP1, and the third control transistor MP3 respectively through the first potential point FNW. The drain of the second switching transistor MP4 is connected to the control terminal of the third control transistor MP3 through the second potential point INT, and the drain of the third switching transistor MP5 is connected to the control terminal of the pull-up drive transistor MP1. The first inverter INV1 is used to invert the enable signal received by the enable signal interface OEN. When the enable signal interface OEN is connected to a power supply voltage signal, the first inverter INV1 outputs a ground signal. When the enable signal interface OEN is connected to a ground signal, the first inverter INV1 outputs the power supply voltage signal.

[0037] The first input terminal of the NAND gate ND1 is connected to the output terminal of the first inverter INV1, the second input terminal of the NAND gate ND1 is connected to the signal input interface IN, and the output terminal of the NAND gate ND1 is connected to the source terminal of the first control transistor MP6 and the source terminal of the second control transistor MN4. The gate of the first control transistor MP6 is connected to the second potential point INT, and the gate of the second control transistor MN4 is connected to the power supply voltage signal.

[0038] The first input terminal of the NOR gate NR1 is directly connected to the enable signal interface OEN, the second input terminal of the NOR gate NR1 is connected to the signal input interface IN, and the output terminal of the NOR gate NR1 is connected to the gate of the pull-down driving transistor MN2. The source of the pull-down driving transistor MN2 is grounded, and the drain terminal of the pull-down driving transistor MN2 is connected to the input / output interface PAD through the first isolation transistor MN1. When the pull-down driving transistor MN2 is turned on, it pulls down the voltage signal at the input / output interface PAD.

[0039] The second inverter INV2 is used to invert the external device signal received by the input / output interface PAD, so as to transmit the external device signal to the signal output interface OUT. Specifically, the voltage at the input terminal of the second inverter INV2 should not be higher than the power supply voltage signal.

[0040] When the input / output interface PAD is used as an input interface, the voltage divider resistor is used to carry the voltage of the input signal at the input / output interface PAD. In this embodiment, the voltage divider resistor can be a single resistor, or it can be composed of multiple resistors connected in series or parallel. This embodiment limits the type of voltage divider resistor. The resistance value of the voltage divider resistor can be adaptively set according to the voltage of the external device signal connected to the input / output interface PAD in the actual application scenario.

[0041] According to a specific embodiment of this application, the high-voltage interface circuit further includes a weak pull-down transistor group, which includes a predetermined number of N-type transistors connected in series. The control terminal of each N-type transistor is connected to its drain terminal, and the voltage of the control terminal of each N-type transistor is obtained by voltage division of the second potential point. The source terminal of the first-stage N-type transistor of the weak pull-down transistor group is grounded, and the drain terminal of the predetermined number of N-type transistors of the weak pull-down transistor group is connected to the second potential point INT.

[0042] For example, such as Figure 2 As shown, the weak pull-down transistor group includes four N-type transistors connected in series, namely MN5, MN6, MN7 and MN8, wherein the control terminal voltage of MN5 is equal to the voltage of the second potential point, the control terminal voltage of MN6 is equal to 3 / 4 of the voltage of the second potential point, the control terminal voltage of MN7 is equal to 1 / 2 of the voltage of the second potential point, and the control terminal voltage of MN8 is equal to 1 / 4 of the voltage of the second potential point.

[0043] The weak pull-down transistor group is used to pull down the voltage at the second potential point INT when the first switching transistor MP2, the second switching transistor MP4, and the third switching transistor MP5 are all off, so that the third control transistor MP3 remains on.

[0044] When the second switching transistor MP4 is turned on, and the voltage at the second potential point INT is the same as the voltage at the input / output interface PAD, the pull-down effect of the weak pull-down transistor group on the voltage at the second potential point INT can be ignored, so that the third control transistor MP3 remains off.

[0045] Specifically, the number of the weak pull-down transistor groups can be adaptively set according to the highest voltage that the input / output interface PAD can be connected to in the actual application scenario. This embodiment does not make a specific limitation on this.

[0046] According to a specific embodiment of this application, the first switching transistor MP2, the second switching transistor MP4, the third switching transistor MP5, the first control transistor MP6, the third control transistor MP3, and the pull-up driving transistor MP1 are all P-type transistors, and the second control transistor MN4, the first isolation transistor MN1, the second isolation transistor MN3, and the pull-down driving transistor MN2 are all N-type transistors.

[0047] Specifically, the transistors in this embodiment can also be configured using different types of transistors. When each transistor is replaced with a different type of transistor, the connection of each transistor needs to be further changed to ensure that the signal flow conforms to the principle of the high-voltage interface circuit design in this embodiment. This embodiment does not limit the circuit after replacement.

[0048] According to a specific embodiment of this application, the source terminal of the first control transistor MP6 is connected to the output terminal of the NAND gate ND1, and the drain terminal of the first control transistor MP6 is connected to the control terminal of the pull-up drive transistor MP1. The source terminal of the second control transistor MN4 is connected to the output terminal of the NAND gate ND1, and the drain terminal of the second control transistor MN4 is connected to the control terminal of the pull-up drive transistor MP1.

[0049] Specifically, such as Figure 2 As shown, the on / off state of the first control transistor MP6 and the second control transistor MN4 both determine the on / off state of the pull-up drive transistor MP1.

[0050] The on / off state of the first control transistor MP6 and the second control transistor MN4 is determined by the signals at the first potential point FNW and the second potential point INT.

[0051] Specifically, when the potential of the second potential point INT is high and the potential of the first potential point FNW is also high, the first control transistor MP6 and the second control transistor MN4 remain off. When the potential of the second potential point INT is low and the potential of the first potential point FNW is high, both the first control transistor MP6 and the second control transistor MN4 remain on.

[0052] According to a specific embodiment of this application, the drain of the pull-down driving transistor MN2 is connected to the source of the first isolation transistor MN1, and the drain of the first isolation transistor MN1 is connected to the input / output interface PAD. The source of the second isolation transistor MN3 is connected to the input / output interface PAD through the voltage divider resistor, and the drain of the second isolation transistor MN3 is connected to the signal output interface OUT through the second inverter INV2.

[0053] Specifically, when the voltage at the input / output interface PAD is greater than the power supply voltage signal, the first isolation transistor MN1 is used to ensure that the voltage at the pull-down drive transistor MN2 does not exceed the power supply voltage signal.

[0054] When the voltage at the input / output interface PAD is greater than the power supply voltage signal, the second isolation transistor MN3 is used to ensure that the voltage at the input terminal of the second inverter INV2 will not be higher than the power supply voltage signal.

[0055] For example, when the voltage at the input / output interface PAD is 3.8V and the power supply voltage signal is 3.3V, the first isolation transistor MN1 is used to ensure that the voltage at the pull-down drive transistor MN2 will not exceed 3.3V, and the second isolation transistor MN3 is used to ensure that the voltage at the input terminal of the second inverter INV2 will not exceed 3.3V.

[0056] According to a specific embodiment of this application, when the enable signal interface OEN is used to access the power supply voltage signal, the second isolation transistor MN3 is turned on. If the voltage value of the signal received by the input / output interface PAD is greater than a preset voltage threshold, the first switching transistor MP2, the second switching transistor MP4 and the third switching transistor MP5 are turned on, and the first control transistor MP6, the second control transistor MN4, the third control transistor MP3, the pull-up drive transistor MP1, the pull-down drive transistor MN2 and the first isolation transistor MN1 are all turned off. If the voltage value of the signal received by the input / output interface PAD is less than a preset voltage threshold, the first switching transistor MP2, the second switching transistor MP4, and the third switching transistor MP5 are all turned off, the first control transistor MP6, the second control transistor MN4, and the third control transistor MP3 are all turned on, and the pull-up drive transistor MP1, the pull-down drive transistor MN2, and the first isolation transistor MN1 are all turned off.

[0057] Specifically, when the enable signal interface OEN is connected to a power supply voltage signal, the input / output interface PAD in this embodiment is in input mode. The voltage value of the external device signal received at the input / output interface PAD includes two cases: a case greater than a preset voltage threshold and a case less than a preset voltage threshold.

[0058] The preset voltage threshold is determined based on the power supply voltage signal of the CMOS chip. For example, when the power supply voltage signal is 3.3V, the preset voltage threshold can be set to 3.8V. This embodiment does not limit the specific value of the preset voltage threshold and can be adaptively set according to the actual application scenario.

[0059] Assuming the voltage of the external device signal input at the input / output interface PAD is higher than a preset voltage threshold, i.e., higher than 3.8V, the first switching transistor MP2 is turned on, causing the voltage at the first potential point FNW to be pulled up to the same voltage as the external device signal input at the input / output interface PAD. At this time, the voltage at the substrate of MP1-MP6 is also pulled up to the same voltage as the external device signal input at the input / output interface PAD.

[0060] When the second switching transistor MP4 is turned on, the voltage output from the second potential point INT is pulled up to the same voltage as the external device signal connected to the input / output interface PAD. At this time, the effect of the weak pull-down transistor group is ignored, and the third control transistor MP3 is turned off, preventing the external device signal from flowing back to the power supply through the third control transistor MP3.

[0061] When the third switching transistor MP5 is turned on, the voltage at the control terminal of the pull-up driving transistor MP1 is pulled up to the same voltage as the external device signal connected to the input / output interface PAD. At this time, the pull-up driving transistor MP1 is turned off, preventing the external device signal from flowing back to the power supply through the pull-up driving transistor MP1.

[0062] The signal input to the enable signal interface OEN is the power supply voltage signal, and the signal output from the second inverter INV2 is the ground signal. Since the signal input interface IN is not working, both the first and second input terminals of the NAND gate ND1 are connected to ground, and the NAND gate ND1 outputs the power supply voltage signal. At this time, both the first control transistor MP6 and the second control transistor MN4 are turned off.

[0063] The first input terminal of the NOR gate NR1 is connected to the power supply voltage signal, and the second input terminal of the NOR gate NR1 is connected to the ground signal. The NOR gate NR1 outputs a low signal. At this time, the pull-down drive transistor MN2 is turned off.

[0064] Therefore, when the voltage value of the external device signal input at the input / output interface PAD is higher than the preset voltage threshold, i.e., higher than 3.8V, the external device signal can be normally transmitted to the CMOS chip through the voltage divider resistor, the second isolation transistor MN3, the second inverter INV2, and the signal output interface OUT.

[0065] Furthermore, when the external device signal exceeds a preset voltage threshold, the first isolation transistor MN1 isolates the input / output interface PAD from the pull-down drive transistor MN2, ensuring that the drain voltage of the pull-down drive transistor MN2 does not exceed the power supply voltage signal. The second isolation transistor MN3 isolates the input / output interface PAD from the second inverter INV2, ensuring that the input voltage of the second inverter INV2 does not exceed the power supply voltage signal.

[0066] It should be noted that when the voltage value of the external device signal connected to the input / output interface PAD is equal to the preset voltage threshold, the specific implementation process of the high voltage resistant interface circuit in this embodiment refers to the above-mentioned case where the voltage is greater than the preset voltage threshold, and will not be repeated here.

[0067] Assuming the voltage value of the external device signal input at the input / output interface PAD is lower than a preset voltage threshold, i.e., lower than 3.8V, then the first switching transistor MP2, the second switching transistor MP4, and the third switching transistor MP5 are all turned off. The voltage at the second potential point INT is pulled down to ground by the weak pull-down transistor group. At this time, the third control transistor MP3 is turned on, and the voltage at the first potential point FNW is pulled up to the same voltage as the power supply voltage signal.

[0068] The voltage at the substrate of each of MP1-MP6 is pulled up to be the same as the voltage of the power supply voltage signal.

[0069] The NAND gate ND1 outputs a power supply voltage signal. The control terminal of the first control transistor MP6 is connected to the ground signal, and the first control transistor MP6 is turned on. The voltage at the control terminal of the pull-up drive transistor MP1 is the same as the voltage of the power supply voltage signal, and the pull-up drive transistor MP1 is turned off.

[0070] When the NOR gate NR1 outputs a low signal, the pull-down drive transistor MN2 remains off.

[0071] Therefore, when the voltage value of the external device signal input at the input / output interface PAD is lower than the preset voltage threshold, i.e., lower than 3.8V, the external device signal can still be transmitted normally to the CMOS chip through the voltage divider resistor, the second isolation transistor MN3, the second inverter INV2, and the signal output interface OUT.

[0072] According to a specific embodiment of the present application, when the enable signal interface OEN is used to access the ground signal, the first switching transistor MP2, the second switching transistor MP4, and the third switching transistor MP5 are all turned off, and the first control transistor MP6, the second control transistor MN4, and the third control transistor MP3 are all turned on. If the signal input interface IN is used to receive a high-level signal, the pull-up driving transistor MP1 is turned on, the pull-down driving transistor MN2 is turned off, and the input / output interface PAD is used to output a high-level signal. If the signal input interface IN is used to receive a low-level signal, the pull-up driving transistor MP1 is turned off, the pull-down driving transistor MN2 is turned on, and the input / output interface PAD is used to output a low-level signal.

[0073] Specifically, when the enable signal interface OEN is used to access the ground signal, the input / output interface PAD in this embodiment is in output mode, and the signal output by the input / output interface PAD is adaptively changed according to the signal received by the signal input interface IN.

[0074] When the input / output interface PAD is used to output a signal, the voltage at the input / output interface PAD will not be greater than the voltage of the power supply voltage signal. The first switching transistor MP2, the second switching transistor MP4, and the third switching transistor MP5 are all turned off. At this time, the voltage at the second potential point INT is pulled down to ground by the weak pull-down transistor group, the third control transistor MP3 is turned on, and the voltage at the first potential point FNW is pulled up to be the same as the voltage of the power supply voltage signal.

[0075] Both the first control transistor MP6 and the second control transistor MN4 are turned on.

[0076] When the signal received by the signal input interface IN is a high-level signal, i.e., a power supply voltage signal, the signals at both the first and second input terminals of the NAND gate ND1 are high-level signals, and the output signal of the NAND gate ND1 is a low-level signal. Similarly, the signal at the first input terminal of the NOR gate NR1 is a ground signal, the signal at the second input terminal is a high-level signal, and the output signal of the NOR gate NR1 is a low-level signal.

[0077] At this time, the pull-up driving transistor MP1 is turned on, the pull-down driving transistor MN2 is turned off, and the input / output interface PAD outputs a high-level signal.

[0078] When the signal received by the signal input interface IN is a low-level signal, i.e., a ground signal, the first input terminal of the NAND gate ND1 is a high-level signal, the second input terminal is a ground signal, and the NAND gate ND1 outputs a high-level signal. Similarly, when the first input terminal of the NOR gate NR1 is a ground signal, the second input terminal is a low-level signal, and the NOR gate NR1 outputs a high-level signal.

[0079] At this time, the pull-up drive transistor MP1 is turned off, the pull-down drive transistor MN2 is turned on, and the input / output interface PAD outputs a low-level signal.

[0080] The high-voltage resistant interface circuit proposed in this embodiment can normally transmit the signal received by the signal input interface IN to the input / output interface PAD when the enable signal is ground, so that external devices can obtain data from the CMOS chip.

[0081] In summary, this embodiment provides a high-voltage resistant interface circuit. By switching the first, second, and third switching transistors on and off, the potentials of the first potential point, the second potential point, and the gate of the pull-up drive transistor are controlled, respectively. When an input signal with a voltage greater than the power supply voltage signal is applied to the input / output interface PAD, this embodiment can synchronize the potential of the substrate of the pull-up drive transistor with that of the input / output interface PAD by turning on the first, second, and third switching transistors. This ensures that the high-voltage resistant interface circuit can operate normally while preventing voltage reverse current from damaging the pull-up drive transistor.

[0082] In addition, this embodiment also ensures the safety of the high-voltage interface circuit by setting the first isolation transistor and the second isolation transistor, so that when the voltage at the input / output interface PAD is high, the potential at the pull-down drive transistor and the signal output interface will not be damaged due to excessively high voltage.

[0083] The high-voltage interface circuit proposed in this embodiment eliminates the need for additional step-down devices between the CMOS chip and external devices, enabling direct communication between the CMOS chip and external devices, such as direct communication with a 5V TTL interface. This effectively improves the efficiency of the CMOS chip and reduces production costs.

[0084] In addition, this application provides an interface device, which includes the high-voltage resistant interface circuit in the aforementioned circuit embodiments.

[0085] Specifically, the interface device in this embodiment can be any communication connector equipped with the high-voltage interface circuit in the aforementioned circuit embodiment. This embodiment does not limit the type of interface device.

[0086] It should be noted that the interface device can also be directly disposed inside the CMOS chip, and this embodiment does not limit this.

[0087] This application also provides a CMOS chip, which includes the interface device described in the foregoing embodiments.

[0088] Specifically, in this embodiment, the CMOS chip communicates with an external device via the interface device, and the voltage of the signal output by the external device can be greater than the power supply voltage of the CMOS chip.

[0089] The specific implementation process of the interface device and CMOS chip mentioned in the above embodiments can be found in the specific implementation process of the above circuit embodiments, and will not be repeated here.

[0090] In addition, the functional modules or units in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0091] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-voltage resistant interface circuit, characterized in that, The high-voltage resistant interface circuit is used to provide an interface for CMOS chips and includes: an input / output interface, a signal input interface, a signal output interface, and an enable signal interface. Both the signal input interface and the signal output interface are used to connect to the CMOS chip, and the input / output interface is used to connect to external devices. The enable signal interface is connected to the first input terminal of the NOR gate and connected to the first input terminal of the NAND gate through the first inverter. The second input terminal of the NAND gate and the second input terminal of the NOR gate are both connected to the signal input interface. The output of the NAND gate is connected to the control terminal of the pull-up drive transistor through the first control unit. The source terminal of the pull-up drive transistor is used to connect to the power supply voltage signal, and the drain terminal is used to connect to the input / output interface. The output of the NOR gate is connected to the control terminal of the pull-down driving transistor. The source terminal of the pull-down driving transistor is grounded, and the drain terminal is connected to the input / output interface through the first isolation transistor. The input / output interface is connected to the signal output interface via a voltage divider resistor, a second isolation transistor, and a second inverter. One end of the second control unit is used to receive the power supply voltage signal, and the other end is connected to the substrate of the pull-up driving transistor. The second control unit is used to turn off when the voltage at the input / output interface is greater than or equal to a preset voltage threshold, and to turn on when the voltage at the input / output interface is less than the preset voltage threshold. One end of the switching unit is connected to the input / output interface through the voltage divider resistor, the other end of the switching unit is connected to the substrate of the pull-up driving transistor, and another end of the switching unit is connected to the control terminal of the pull-up driving transistor. The switching unit is used to turn on when the voltage at the input / output interface is greater than or equal to a preset voltage threshold, and to turn off when the voltage at the input / output interface is less than the preset voltage threshold. The first control unit includes a first control transistor and a second control transistor, and the second control unit includes a third control transistor and a group of weak pull-down transistors; The source terminal of the third control transistor is used to connect to the power supply voltage signal, and the drain terminal is connected to the substrate terminal of the pull-up drive transistor through the first potential point. The output of the NAND gate is connected to the control terminal of the pull-up driving transistor through the first control transistor and the second control transistor, respectively. The control terminal of the first control transistor is connected to the control terminal of the third control transistor through the second potential point. The control terminal of the second control transistor is used to access the power supply voltage signal. The weak pull-down transistor group includes a predetermined number of N-type transistors connected in series, wherein the control terminal of each N-type transistor is connected to the drain terminal, and the voltage of the control terminal of each N-type transistor is obtained by voltage division of the second potential point.

2. The high-voltage resistant interface circuit according to claim 1, characterized in that, The switching unit includes a first switching transistor, a second switching transistor, and a third switching transistor; The control terminals of the first switching transistor, the second switching transistor, and the third switching transistor are all used to connect to the power supply voltage signal; The source terminals of the first switching transistor, the second switching transistor, and the third switching transistor are all connected to the input / output interface through the voltage divider resistor; The drain terminal of the first switching transistor is connected to the substrate terminals of the first switching transistor, the second switching transistor, the third switching transistor, the first control transistor, the pull-up drive transistor, and the third control transistor respectively through the first potential point; The drain of the second switching transistor is connected to the control terminal of the third control transistor through the second potential point, and the drain of the third switching transistor is connected to the control terminal of the pull-up drive transistor. The first switching transistor, the second switching transistor, the third switching transistor, the first control transistor, the third control transistor, and the pull-up driving transistor are all P-type transistors, and the second control transistor, the first isolation transistor, the second isolation transistor, and the pull-down driving transistor are all N-type transistors.

3. The high-voltage resistant interface circuit according to claim 2, characterized in that, The source terminal of the first control transistor is connected to the output terminal of the NAND gate, and the drain terminal of the first control transistor is connected to the control terminal of the pull-up drive transistor. The source terminal of the second control transistor is connected to the output terminal of the NAND gate, and the drain terminal of the second control transistor is connected to the control terminal of the pull-up drive transistor.

4. The high-voltage resistant interface circuit according to claim 2, characterized in that, The drain of the pull-down driving transistor is connected to the source of the first isolation transistor, and the drain of the first isolation transistor is connected to the input / output interface. The source of the second isolation transistor is connected to the input / output interface through the voltage divider resistor, and the drain of the second isolation transistor is connected to the signal output interface through the second inverter.

5. The high-voltage resistant interface circuit according to claim 2, characterized in that, When the enable signal interface is used to connect to a power supply voltage signal, the input / output interface is in input mode; when the enable signal interface is used to connect to a ground signal, the input / output interface is in output mode. The input / output interface is used to output signals to the external device in the output mode, and the input / output interface is used to receive signals sent by the external device in the input mode.

6. The high-voltage resistant interface circuit according to claim 5, characterized in that, When the enable signal interface is used to access a power supply voltage signal, the second isolation transistor is turned on. If the voltage value of the signal received by the input / output interface is greater than or equal to the preset voltage threshold, the first switching transistor, the second switching transistor, and the third switching transistor are turned on, and the first control transistor, the second control transistor, the third control transistor, the pull-up drive transistor, the pull-down drive transistor, and the first isolation transistor are all turned off. If the voltage value of the signal received by the input / output interface is less than the preset voltage threshold, the first switching transistor, the second switching transistor, and the third switching transistor are all turned off, the first control transistor and the third control transistor are all turned on, and the pull-up drive transistor, the pull-down drive transistor, the second control transistor, and the first isolation transistor are all turned off.

7. The high-voltage resistant interface circuit according to claim 5, characterized in that, When the enable signal interface is used to access the ground signal, the first switching transistor, the second switching transistor, and the third switching transistor are all turned off, and the third control transistor is all turned on. If the signal input interface is used to receive a high-level signal, the first control transistor is turned off, the second control transistor is turned on, the pull-up drive transistor is turned on, the pull-down drive transistor is turned off, and the input / output interface is used to output a high-level signal. If the signal input interface is used to receive a low-level signal, the first control transistor is turned on, the second control transistor is turned off, the pull-up drive transistor is turned off, the pull-down drive transistor is turned on, and the input / output interface is used to output a low-level signal.

8. An interface device, characterized in that, The interface device includes the high-voltage resistant interface circuit as described in any one of claims 1-7.

9. A CMOS chip, characterized in that, The CMOS chip includes the interface device as described in claim 8.

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