Phased array channel correction method and array lock-in unit

Abstract

The application discloses a phased array channel correction method and an array phase-locked unit. A phase discriminator is used to perform first multiplication processing on a signal, a loop filter is used to perform filtering, a phase generator is used to perform function transformation, a multiplier is used to perform second multiplication processing, and the obtained signal is sent to the phase discriminator to constitute a phase-locked loop. Since the phase-locked loop can continuously process the signal until the loop stable condition is reached and the phase-locked loop is exited, a correction signal is output. The correction signal can indicate that the phases of the reference array element and the compensation array element have been aligned, and the phase difference between the array elements is solved. The phase difference between channels can also be regarded as part of the phase difference between the array elements, so the phase difference between the channels can also be corrected simultaneously.

Description

Technical Field

[0001] This invention relates to the field of phased array antenna design, and more specifically, to a phased array channel correction method and an array phase-locked unit. Background Technology

[0002] A phased array receiver can be considered an array antenna, comprising multiple phased array elements that work together to transmit information signals. Conventional phased array elements may include filters, mixers, and additional functional modules to provide reception capabilities. When a phased array receiver transmits millimeter waves, the signal attenuation during propagation is a significant problem. Therefore, researchers have devoted considerable time and effort to studying and improving phased array technology and systems. Phased array systems achieve electromagnetic wave superposition by controlling the phase of the signals transmitted by each antenna. Using multiple antennas in a phased array system increases the signal transmission power, and the superposition of signals with different phases concentrates the transmitted energy in one direction. Beam modulation based on the user's location ensures no interference between different users on the same frequency, greatly improving communication channel capacity.

[0003] In the prior art, since phased array systems require a large number of structurally identical transmitting arrays, the different bias states of amplifiers in different channels will cause the gain and phase shift of the channel output signal, resulting in the direction shift and directional gain attenuation of the array synthesized beam. This will result in a phase difference. When the effective radiation pattern emitted by the phased array antenna is enhanced in a certain direction and suppressed in other specific directions, it will also cause the phase of the antenna input signal used for transmission to shift, resulting in a phase difference between signals. Therefore, how to ensure the phase consistency in the array element antenna has become a problem that those skilled in the art must solve. Summary of the Invention

[0004] The purpose of this application is to overcome the shortcomings of existing technologies by providing a phased array channel correction method and an array phase-locked unit, which can solve the problem of phase inconsistency by performing phase compensation on each array element to be compensated.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] In a first aspect, this application proposes a phased array channel correction method applied to an array phase-locked system. The array phase-locked system includes a reference array element, at least one array element to be compensated, and at least one array phase-locked unit. Each array phase-locked unit includes a phase detector, a loop filter, a phase generator, and a multiplier. The phase detector, the loop filter, the phase generator, and the multiplier are connected end-to-end to form a loop. Each array phase-locked unit corresponds one-to-one with the array element to be compensated. The method includes:

[0007] The phase detector receives the reference signal sent by the reference array element and the first compensation signal sent by the multiplier, performs a first multiplication process to obtain a phase detection signal, and sends it to the loop filter. The first compensation signal is the initial signal of the multiplier.

[0008] The loop filter filters the phase detection signal to obtain a filtered signal, which is then sent to the phase generator.

[0009] The phase generator performs a function transformation on the filtered signal to obtain a generated signal, which is then sent to the multiplier.

[0010] The multiplier receives the signal to be compensated sent by the array element to be compensated, and performs a second multiplication process on the generated signal and the signal to be compensated to obtain a second compensated signal.

[0011] The multiplier sends the second compensation signal to the phase detector, causing the phase detector to perform the first multiplication process on the reference signal and the second compensation signal to form a phase-locked loop until the loop stability condition is met, at which point it exits the phase-locked loop and outputs a correction signal.

[0012] The array phase-locked system further includes an adder, and the method includes:

[0013] The adder sums the correction signals output by each of the multipliers to obtain the array element correction signals.

[0014] The phase detector includes a complex multiplier and a real multiplier. The phase detector receives a reference signal transmitted by the reference array element and a first compensation signal transmitted by the multiplier, performs a first multiplication process to obtain a phase detection signal, and sends it to the loop filter. The steps include:

[0015] The complex multiplier performs a complex multiplication operation on the reference signal and the first compensation signal to obtain a complex signal, which is then sent to the real multiplier.

[0016] The real number multiplier performs real number multiplication on the complex number signal to obtain a phase detection signal, which is then sent to the loop filter.

[0017] The phase generator includes an accumulator and a function processor. The step of the phase generator performing a function transformation on the filtered signal to obtain a generated signal and sending it to the multiplier includes:

[0018] The accumulator accumulates the filtered signal to obtain an accumulated signal and sends it to the function processor;

[0019] The function processor performs a function transformation on the accumulated signal to obtain the generated signal, which is then sent to the multiplier.

[0020] The signal to be compensated includes the phase difference between the reference array element and the array element to be compensated. The step of exiting the phase-locked loop and outputting the correction signal when the loop stability condition is reached includes:

[0021] When the accumulated signal is consistent with the phase difference estimate, the multiplier exits the phase-locked loop and outputs a correction signal. The phase difference estimate is obtained by using the least squares method on the phase difference.

[0022] Secondly, this application proposes an array phase-locked unit, which includes a phase detector, a loop filter, a phase generator, and a multiplier. The phase detector, the loop filter, the phase generator, and the multiplier are connected end-to-end to form a loop. The array phase-locked unit corresponds one-to-one with the array element to be compensated. The method includes:

[0023] The phase detector is used to receive the reference signal sent by the reference array element and the first compensation signal sent by the multiplier, perform a first multiplication process to obtain a phase detection signal, and send it to the loop filter. The first compensation signal is the initial signal of the multiplier.

[0024] The loop filter is used to filter the phase detection signal to obtain a filtered signal and send it to the phase generator.

[0025] The phase generator is used to perform a function transformation on the filtered signal to obtain a generated signal and send it to the multiplier;

[0026] The multiplier is used to receive the signal to be compensated sent by the array element to be compensated, and to perform a second multiplication process on the generated signal and the signal to be compensated to obtain a second compensation signal.

[0027] The multiplier is further configured to send the second compensation signal to the phase detector, so that the phase detector performs the first multiplication process on the reference signal and the second compensation signal to form a phase-locked loop until the loop stability condition is met, at which point it exits the phase-locked loop and outputs a correction signal.

[0028] Thirdly, this application also proposes a computer device comprising a processor and a memory, wherein the memory stores a computer program, which is loaded and executed by the processor to implement the phased array channel correction method as described in any of the first aspects.

[0029] Fourthly, this application also proposes a computer-readable storage medium storing a computer program that is loaded and executed by a processor to implement the phased array channel correction method as described in any of the first aspects.

[0030] The main solution of the present invention and its various further alternative solutions described above can be freely combined to form multiple solutions, all of which are solutions that can be adopted and are claimed by the present invention; furthermore, the (non-conflicting alternatives) can also be freely combined with each other and with other alternatives. Those skilled in the art, after understanding the solution of the present invention, will realize from the prior art and common general knowledge that there are many combinations, all of which are technical solutions to be protected by the present invention, and will not be exhaustively listed here.

[0031] The beneficial effects of this invention are as follows:

[0032] First, because a phase-locked loop is formed by using a phase detector, a loop filter, a phase generator, and a multiplier, the phase-locked loop can continuously process the signal until the loop stability condition is reached, at which point it exits the phase-locked loop and outputs a correction signal, which enables the phase alignment of the reference array element and the compensated array element.

[0033] Second, an adder is used to sum the correction signals output by each phase-locked array unit. The resulting array element correction signal can indicate that the phases of the array elements in the entire phased array antenna array are aligned.

[0034] Third, since there may be phase differences between the various channels of the signal acquired by the existing technology, this application can regard the phase difference between the channels as part of the phase difference between the reference array element and the compensated array element, without the need to additionally correct the phase difference between the channels, thus reducing costs. Attached Figure Description

[0035] Figure 1 A schematic diagram of an array phase-locked system proposed in an embodiment of this application is shown.

[0036] Figure 2 A schematic diagram of an array phase-locked unit proposed in an embodiment of this application is shown.

[0037] Figure 3 This paper illustrates a flowchart of a phased array channel correction method provided in an embodiment of this application.

[0038] Figure 4 A flowchart of step S100 in the phased array channel correction method is shown.

[0039] Figure 5 A schematic diagram showing the phase detector of an embodiment of this application obtaining a phase detection signal is shown.

[0040] Figure 6 A flowchart of step S300 in the phased array channel correction method is shown.

[0041] Icons: 10 - Phase-locked array system; 100 - Phase-locked array unit; 101 - Array element to be compensated; 102 - Reference array element; 110 - Phase detector; 120 - Loop filter; 130 - Phase generator; 140 - Multiplier; 141 - Complex multiplier; 142 - Real multiplier. Detailed Implementation

[0042] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0043] Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] In existing technologies, since phased array systems require a large number of structurally identical transmitting arrays, the different bias states of amplifiers in different channels will cause the output signal gain and phase shift of the channel, resulting in a shift in the direction of the array synthesized beam and a decrease in directional gain. This will lead to a phase difference. When the effective radiation pattern emitted by the phased array antenna is enhanced in a certain direction and suppressed in other specific directions, it will also cause a phase shift in the antenna input signal used for transmission, resulting in a signal phase difference. This phase difference will in turn lead to the inconsistency problem of array element channels.

[0045] To address the issue of channel inconsistency, existing technologies use phase-shift compensation control signals. However, obtaining these signals requires a dedicated reference signal channel. Channel inconsistencies are corrected by receiving signals of the same amplitude from the reference signal channel. But designing the reference signal channel is very complex, and correcting multiple channels is also quite difficult. Therefore, ensuring the consistency of each channel is a problem that those skilled in the art must solve.

[0046] Based on the above problems, this application proposes a phased array channel correction method, which can solve the problem of phase inconsistency by performing phase compensation on each array element to be compensated. The following is a detailed description.

[0047] Please refer to Figure 1 , Figure 1 A schematic diagram of an array phase-locked system 10 proposed in an embodiment of this application is shown.

[0048] The array phase-locked system 10 includes a reference array element 102, at least one array element to be compensated 101, and at least one array phase-locked unit 100. The reference array element 102, the array element to be compensated 101, and the array phase-locked unit 100 are connected in sequence. The reference array element 102 is an array element in the phased array antenna array. If the phased array antenna array is a uniform linear array, the reference array element 102 can be selected from the head or tail of the uniform linear array. If the phased array antenna array is a uniform planar array, the reference array element 102 can be selected from one of the four corners of the uniform planar array. In addition, the selection of the reference array element 102 can also be selected according to different actual needs. This application embodiment does not limit this in any way.

[0049] The element to be compensated 101 is one element in the phased array antenna array excluding the reference element 102. Each element to be compensated 101 has a one-to-one correspondence with an array phase-locked unit 100, that is, each array antenna of the element to be compensated 101 needs an array phase-locked unit 100.

[0050] The functions of each part of the array phase-locked unit 100, which implements the phased array channel correction method, are described below. For the specific structure of the array phase-locked unit 100, please refer to [reference needed]. Figure 2 , Figure 2 The diagram shows a structural schematic of an array phase-locked unit 100 proposed in an embodiment of this application. The array phase-locked unit 100 includes a phase detector 110, a loop filter 120, a phase generator 130, and a multiplier 140, wherein the phase detector 110, the loop filter 120, the phase generator 130, and the multiplier 140 are connected end to end to form a loop.

[0051] Phase detector 110 is a device capable of identifying the phase difference of input signals. It is a circuit that establishes a definite relationship between the output signal and the phase difference between the two input signals. It receives the reference signal transmitted by reference array element 102 and the first compensation signal transmitted by multiplier 140, performs a first multiplication process on the reference signal and the first compensation signal to obtain a phase detection signal, and sends the phase detection signal to loop filter 120. In this embodiment, phase detector 110 can be a digital phase detector or an analog phase detector; this embodiment does not impose any limitation on either.

[0052] The loop filter 120 is a linear low-pass filter designed according to the requirements of a second-order type II phase-locked loop to filter out high-frequency components and noise in the phase detection signal to obtain a filtered signal, and then sends the filtered signal to the phase generator 130.

[0053] The phase generator 130 is mainly composed of a delay accumulation structure, which is used to delay and accumulate the received filtered signal, and after function processing, obtain the generated signal and send the generated signal to the multiplier 140.

[0054] Multiplier 140 receives the generated signal and the signal to be compensated sent by the array element to be compensated 101, and performs a second multiplication process on the generated signal and the signal to be compensated to obtain a second compensation signal. The second compensation signal is then subjected to a first multiplication process to form a phase-locked loop. The loop will exit the phase-locked loop when the loop stability condition is reached, and a correction signal will be output.

[0055] exist Figure 1 and Figure 2 Based on this, the phased array channel correction method applied to the aforementioned phase-locked loop system 10 will be described in detail below. Please refer to... Figure 3 , Figure 3 This paper illustrates a flowchart of a phased array channel correction method provided in an embodiment of this application. This method is applied to radar and communication phased array antennas and includes the following steps:

[0056] S100: The phase detector receives the reference signal sent by the reference array element and the first compensation signal sent by the multiplier, performs the first multiplication process to obtain the phase detection signal, and sends it to the loop filter 120.

[0057] During the processing of array signals, an arbitrary element is pre-selected from the phased array antenna array as a reference element 102. This reference element 102 will send a reference signal r(t) = e to the phase detector 110. jωt +n r (t), where ω is the center angular frequency of the signal, j is the imaginary sign, t is the time period, and n r (t) is Gaussian white noise. The first compensation signal y(t) is the initial signal of multiplier 140. It is worth noting that both the reference signal and the first compensation signal are complex signals.

[0058] The first multiplication process involves performing complex multiplication on the reference signal and the first compensation signal, then performing real multiplication on the resulting signal to obtain the phase detection signal, and finally sending the phase detection signal to the loop filter 120.

[0059] In addition, the phase detector 110 includes a complex multiplier 141 and a real multiplier 142. For the specific operation process of complex multiplication, please refer to... Figure 4 , Figure 4 This diagram illustrates a flowchart of step S100 in a phased array channel correction method. Step S100 includes:

[0060] S110, the complex multiplier performs complex multiplication on the reference signal and the first compensation signal to obtain a complex signal, which is then sent to the real multiplier.

[0061] S120, the real number multiplier performs real number multiplication on the complex signal to obtain the phase detection signal, and sends it to the loop filter.

[0062] Since both the reference signal r(t) and the first compensation signal y(t) are complex numbers, they also have real and imaginary parts. The real part of the reference signal r(t) is represented by Re[r(t)], and the imaginary part by Im[r(t)]. Similarly, the real part of the first compensation signal y(t) is represented by Re[y(t)], and the imaginary part by Im[y(t)]. Please refer to [reference needed]. Figure 5 , Figure 5 A schematic diagram showing the phase detector 110 of an embodiment of this application obtaining a phase detection signal is shown.

[0063] The real and imaginary parts of the reference signal r(t) and the first compensation signal y(t) are respectively input into the complex multiplier 141. Real multiplication (complex multiplication) is performed on the two signals to obtain the real and imaginary parts of the complex signal d(t). This complex signal d(t) is then sent to the real multiplier 142. The real multiplier 142 multiplies the real part Re[d(t)] and the imaginary part Im[d(t)] of the complex signal d(t) to obtain the phase detection signal e(t), which is then sent to the loop filter 120. It is worth noting that the phase detection signal e(t) is a real signal.

[0064] S200 and the loop filter filter the phase detection signal to obtain a filtered signal, which is then sent to the phase generator.

[0065] The loop filter 120 in this embodiment can be designed using a closed-loop method for second-order phase-locked loop carrier frequency offset tracking. Its basic principle is to dynamically adjust the tracking carrier frequency through a feedback loop. When the feedback frequency is the same as the carrier frequency, the system loop tends to converge, thus achieving accurate carrier frequency tracking. Ideally, carrier tracking methods can estimate a large dynamic range of frequency offset, but their carrier tracking accuracy is poor, and the residual frequency offset after system stabilization is too large. The phase-locked loop-based carrier tracking method can effectively resist the influence of link noise on system frequency offset estimation and can adapt to dynamic changes in frequency offset.

[0066] The loop filter 120 filters the received phase detection signal to obtain a filtered signal, which is then sent to the phase generator 130. It is worth noting that the loop filter 120 converts the input voltage signal into a phase signal before performing low-pass filtering. This low-pass filtering process has no effect on the phase of the reference signal or the phase difference caused by the array element positions; it only filters out other phase signals and noise. Therefore, the loop filter 120 can also improve the signal-to-noise ratio.

[0067] Furthermore, the parameters of the loop filter 120 must satisfy the condition that the frequency response function of the loop filter has a low-pass characteristic. For example, the loop filter parameters can be C1 = 8B. L T S / 3, C2 = 32(B LT S ) 2 / 9, where B L For the equivalent noise bandwidth, T s For the sampling period, the loop filter 120 also includes a delay unit, which delays the signal by one period.

[0068] S300, the phase generator performs a function transformation on the filtered signal to obtain the generated signal, which is then sent to the multiplier.

[0069] After receiving the filtered signal, the phase generator 130 performs a function transformation on it. Since the phase generator 130 includes an accumulator and a function processor, please refer to [reference needed] for the specific calculation process of the function transformation. Figure 6 , Figure 6 This diagram illustrates a flowchart of step S300 in a phased array channel correction method. Step S300 includes:

[0070] S310, the accumulator accumulates the filtered signal to obtain the accumulated signal and sends it to the function processor.

[0071] S320, the function processor performs a function transformation on the accumulated signal to obtain a generated signal, which is then sent to the multiplier 140.

[0072] The accumulator's function is to perform a time-delay accumulation on the filtered signal. First, the filtered signal is delayed by an arbitrary period. Then, the delayed signal is accumulated with the filtered signal to obtain the accumulated signal. Accumulated signal After passing through the function processor via e jx The generated signal is obtained after processing by the function. The generated signal g(t) is then sent to multiplier 140.

[0073] S400: The multiplier receives the signal to be compensated sent by the array element to be compensated, and performs a second multiplication process on the generated signal and the signal to be compensated to obtain the second compensation signal.

[0074] When multiplier 140 receives the generated signal sent by phase generator 130, it can also receive the compensation signal sent by the compensation element 101. Where ω is the center angular frequency of the signal, j is the imaginary sign, t is the time period, and n i (t) represents Gaussian white noise. It is worth noting that the signal to be compensated, x... i n in (t) i (t) and n in the reference signal r(t) r Although both (t) are Gaussian white noise, they are independent and identically distributed. θ iThe phase difference caused by the spatial position difference and channel inconsistency of the i-th array element 101 to be compensated relative to the reference array element 102.

[0075] The second multiplication process involves generating the signal. and the signal to be compensated Multiplying them together yields the second compensation signal y(t) = g(t) * x i (t), and then send the second compensation signal to the phase detector 110.

[0076] S500: The multiplier sends the second compensation signal to the phase detector, which then performs a first multiplication on the reference signal and the second compensation signal to form a phase-locked loop. The loop continues until the stability condition is met, at which point the phase-locked loop exits and outputs a correction signal.

[0077] After multiplier 140 sends the second compensation signal to phase detector 110, phase detector 110 compares the second compensation signal y(t) with the reference signal r(t) sent by reference array element 102. jωt +n r (t) Continue the first multiplication process to obtain the phase detection signal, that is, replace the first compensation signal in step S100 with the second compensation signal, and continue to execute step S100. This forms a phase-locked loop of phase detector 110 → loop filter 120 → phase generator 130 → multiplier 140 → phase detector 110. This phase-locked loop can continuously process the signal until the loop stability condition is reached, at which point it exits the phase-locked loop and outputs the correction signal.

[0078] Optionally, the loop stability condition is the accumulated signal. When the phase difference estimate is consistent with the value, multiplier 140 exits the phase-locked loop and outputs a correction signal. At this point, the correction signal can achieve the effect of aligning the phase of the reference signal with the phase of the signal to be compensated.

[0079] Furthermore, the phase difference estimate can be obtained by using the least squares method to obtain the phase difference between the reference signal and the signal to be compensated, or it can be obtained by normalization processing. This application does not limit this in any way.

[0080] Optionally, the array phase-locked system 10 also includes an adder to sum the correction signals output by each multiplier 140 to obtain the array element correction signal.

[0081] Since the array elements in the phased array antenna array are divided into a reference array element 102 and several array elements 101 to be compensated, and the several array elements 101 to be compensated correspond to several array phase-locked units 100, and the correction signal output by each array phase-locked unit 100 can represent the phase alignment of the reference signal and the array element 101 to be compensated corresponding to that array phase-locked unit 100, if we want to represent the phase alignment of the array elements in the entire phased array antenna array, we need an adder to sum the correction signals output by each array phase-locked unit 100. Only the final array element correction signal can represent that the phase of the array elements in the entire phased array antenna array has been aligned.

[0082] Compared with the prior art, the embodiments of this application have the following beneficial effects:

[0083] First, since a phase-locked loop is formed by using a phase detector, a loop filter, a phase generator, and a multiplier, the phase-locked loop can continuously process the signal until the loop stability condition is reached, at which point it exits the phase-locked loop and outputs a correction signal, which enables the phases of the reference array element and the array element to be compensated to be aligned.

[0084] Second, an adder is used to sum the correction signals output by each phase-locked array unit. The resulting array element correction signal can indicate that the phases of the array elements in the entire phased array antenna array are aligned.

[0085] Third, since there may be phase differences between the various channels of the signal acquired by the existing technology, this application can regard the phase difference between the channels as part of the phase difference between the reference array element and the array element to be compensated, without the need for additional correction of the phase difference between the channels, thus reducing costs.

[0086] This preferred embodiment provides a computer device that can implement the steps of any embodiment of the phased array channel correction method provided in this application. Therefore, it can achieve the beneficial effects of the phased array channel correction method provided in this application. For details, please refer to the previous embodiments, which will not be repeated here.

[0087] Example 4

[0088] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor. Therefore, embodiments of the present invention provide a storage medium storing multiple instructions that can be loaded by a processor to execute the steps of any embodiment of the phased array channel correction method provided by the present invention.

[0089] The storage medium may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0090] Since the instructions stored in the storage medium can execute the steps in any phased array channel correction method embodiment provided by the present invention, the beneficial effects that any phased array channel correction method provided by the present invention can achieve can be realized, as detailed in the preceding embodiments, and will not be repeated here.

[0091] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A phased array channel correction method, characterized in that, The method is applied to an array phase-locked system, which includes a reference array element, at least one array element to be compensated, and at least one array phase-locked unit. Each array phase-locked unit includes a phase detector, a loop filter, a phase generator, and a multiplier. The phase detector, the loop filter, the phase generator, and the multiplier are connected end-to-end to form a loop. Each array phase-locked unit corresponds one-to-one with the array element to be compensated. The phase detector receives the reference signal sent by the reference array element and the first compensation signal sent by the multiplier, performs a first multiplication process to obtain a phase detection signal, and sends it to the loop filter. The first compensation signal is the initial signal of the multiplier. The loop filter filters the phase detection signal to obtain a filtered signal, which is then sent to the phase generator. The phase generator performs a function transformation on the filtered signal to obtain a generated signal, which is then sent to the multiplier. The multiplier receives the signal to be compensated sent by the array element to be compensated, and performs a second multiplication process on the generated signal and the signal to be compensated to obtain a second compensation signal; The multiplier sends the second compensation signal to the phase detector, so that the phase detector performs the first multiplication process on the reference signal and the second compensation signal to form a phase-locked loop until the loop stability condition is reached and the phase-locked loop is exited, and a correction signal is output. The phase generator includes an accumulator and a function processor. The step of the phase generator performing a function transformation on the filtered signal to obtain a generated signal and sending it to the multiplier includes: The accumulator accumulates the filtered signal to obtain an accumulated signal and sends it to the function processor; The function processor performs a function transformation on the accumulated signal to obtain the generated signal, which is then sent to the multiplier. There is a phase difference between the reference array element and the array element to be compensated. The loop stability condition is that the accumulated signal is consistent with the phase difference estimate, which is obtained from the phase difference.

2. The phased array channel correction method as described in claim 1, characterized in that, The array phase-locked system further includes an adder, and the method includes: The adder sums the correction signals output by each of the multipliers to obtain the array element correction signals.

3. The phased array channel correction method as described in claim 1, characterized in that, The phase detector includes a complex multiplier and a real multiplier. The phase detector receives a reference signal transmitted by the reference array element and a first compensation signal transmitted by the multiplier, performs a first multiplication process to obtain a phase detection signal, and sends it to the loop filter. The steps include: The complex multiplier performs a complex multiplication operation on the reference signal and the first compensation signal to obtain a complex signal, which is then sent to the real multiplier. The real number multiplier performs real number multiplication on the complex number signal to obtain a phase detection signal, which is then sent to the loop filter.

4. An array phase-locked unit, characterized in that, The array phase-locked unit includes a phase detector, a loop filter, a phase generator, and a multiplier. The phase detector, the loop filter, the phase generator, and the multiplier are connected end-to-end to form a loop. The array phase-locked unit corresponds one-to-one with the array element to be compensated. The unit includes: The phase detector is used to receive the reference signal sent by the reference array element and the first compensation signal sent by the multiplier, perform a first multiplication process to obtain a phase detection signal, and send it to the loop filter. The first compensation signal is the initial signal of the multiplier. The loop filter is used to filter the phase detection signal to obtain a filtered signal and send it to the phase generator. The phase generator is used to perform a function transformation on the filtered signal to obtain a generated signal and send it to the multiplier; The multiplier is used to receive the signal to be compensated sent by the array element to be compensated, and to perform a second multiplication process on the generated signal and the signal to be compensated to obtain a second compensation signal. The multiplier is also used to send the second compensation signal to the phase detector, so that the phase detector performs the first multiplication process on the reference signal and the second compensation signal to form a phase-locked loop until the loop stability condition is reached and the phase-locked loop is exited to output a correction signal. The phase generator includes an accumulator and a function processor. The step of the phase generator performing a function transformation on the filtered signal to obtain a generated signal and sending it to the multiplier includes: The accumulator accumulates the filtered signal to obtain an accumulated signal and sends it to the function processor; The function processor performs a function transformation on the accumulated signal to obtain the generated signal, which is then sent to the multiplier. There is a phase difference between the reference array element and the array element to be compensated. The loop stability condition is that the accumulated signal is consistent with the phase difference estimate, which is obtained from the phase difference.

5. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program, which is loaded and executed by the processor to implement the phased array channel correction method as described in any one of claims 1-3.

6. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which is loaded and executed by a processor to implement the phased array channel correction method as described in any one of claims 1-3.

Images