Nucleus cache coherency and target discovery

Abstract

A method and apparatus for transferring data from a first processor core to a second processor core is disclosed. The first processor core executes a hide instruction having a first operand associated with a data address of the data. Based on the data address or a second operand, the second processor core is determined to be a hide target of a hide message. The hide message is sent to the second processor core, thereby informing the second processor core of the data being written. In response to receiving the hide message, the second processor core can choose to store the data in its cache. The data can be included in the hide message or retrieved in response to a read request of the second processor core. The second processor core can be determined based at least in part on a prediction based on monitored data transactions.

Description

Background Technology

[0001] In a multi-core data processing system, data generated by a processing thread executing on a first processor core can be consumed by a processing thread executing on a second processor core. During operation, the generator core writes data to its local cache or shared memory. The next read operation by the second processor core for the newly written data results in a cache miss because the data has not yet been loaded into the second processor's local cache. Moving data into the consuming core's local cache causes processing delays or latency. Attached Figure Description

[0002] The accompanying drawings provide visual representations that will be used to more fully describe various representative embodiments and can be used by those skilled in the art to better understand the disclosed representative embodiments and their advantages. In these drawings, similar reference numerals denote corresponding or similar elements.

[0003] Figure 1 It is a simplified block diagram of a multi-core data processing system based on various representative implementation schemes.

[0004] Figure 2 It is a flowchart of a method for data transmission in a multi-core data processing system based on various representative implementation schemes.

[0005] Figure 3 It is an interactive diagram of exemplary verification and kernel hiding operations based on various representative implementation schemes.

[0006] Figure 4 This is an interactive diagram of another example of the verification and kernel hiding operation based on various representative implementation schemes.

[0007] Figure 5 Examples of Hidden Target Tables (STTs) based on various representative implementation schemes are shown.

[0008] Figure 6 Further examples of Hidden Target Tables (STTs) based on various representative implementation schemes are shown.

[0009] Figures 7 to 11 This is an interactive diagram illustrating methods for updating the hidden target table based on various representative implementation schemes.

[0010] Figure 12 It is a flowchart of a method for creating and updating a hidden target table by a home agent, based on various representative implementation schemes.

[0011] Figure 13 and Figure 14 It is an interactive diagram of exemplary verification and kernel hiding operations based on various representative implementation schemes.

[0012] Figure 15 This is an interactive diagram of an exemplary hidden target registration operation based on various representative implementation schemes.

[0013] Figure 16 It is an interactive diagram of exemplary verification and kernel hiding operations based on various representative implementation schemes. Detailed Implementation

[0014] The various apparatuses, devices, and methods described herein provide mechanisms for core-to-core cache hiding in multicore data processing systems.

[0015] While this disclosure can have many different embodiments, specific embodiments are shown in the accompanying drawings and will be described in detail herein. It should be understood that the embodiments shown and described herein should be considered as examples providing the principles of this disclosure, and are not intended to limit this disclosure to the specific embodiments shown and described. In the following description, similar reference numerals are used to describe the same, similar, or corresponding parts in several views of the drawings. For simplicity and clarity, reference numerals may be repeated in the drawings to indicate corresponding or similar elements.

[0016] In this document, relational terms such as first and second, top and bottom, etc., are used only to distinguish one entity or action from another entity or action, and do not necessarily require or imply any actual such relationship or order between such entities or actions. The terms “comprising,” “including,” “containing,” “having,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article of manufacture, or apparatus that comprises a list of elements includes at least the listed elements, and may also include other elements not expressly listed or inherent to such process, method, article of manufacture, or apparatus. An element preceded by “comprising…one” does not exclude the presence of additional identical elements in the process, method, article of manufacture, or apparatus that includes that element, unless further limited.

[0017] Throughout this document, the terms “an embodiment,” “certain embodiments,” “implementation,” “specific implementation,” “aspect,” or similar terms refer to a particular feature, structure, or characteristic described in connection with that embodiment, which is included in at least one embodiment of this disclosure. Therefore, the appearance of such phrases in various places throughout this specification does not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics can be combined in any suitable manner without limitation in one or more embodiments.

[0018] As used herein, the term "or" will be interpreted inclusively, meaning any one or any combination. Therefore, "A, B, or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B, and C." Exceptions to this definition will only occur if the combination of elements, functions, steps, or actions is inherently mutually exclusive in some way.

[0019] As used herein, when applied to a component, the term "configured to" indicates that the component can be designed or constructed to perform a specified function, or has the necessary structure to enable it to be reconfigured or adapted to perform that function.

[0020] Figure 1 This is a simplified block diagram of a multi-core data processing system 100 according to various representative embodiments. A first processor core 102 (also referred to as a transmitter core or generator core) includes at least one local cache 104 (which may be dedicated to that core or, for example, a core cluster), and a second processor core 106 includes at least one local cache 108. The second processor core 106 is also referred to as a receiver core or consumer core. Generally, the data processing system 100 may include any number of processor cores, some of which may be arranged in clusters and share lower-level caches. The processor cores are coupled via an interconnect structure 110 configured to pass messages between the processor cores and other devices coupled to the interconnect structure. Also coupled to the interconnect structure 110 is a home agent 112. Optionally, the home agent 112 may include a system-level cache 114. Shared memory 116 is coupled to the interconnect structure 110 via a memory controller 118. The processor cores access shared memory 116 by sending request messages to the home agent 112. The cached agent manages a set or range of memory addresses and acts as a consistency and serialization point for data, ensuring that copies of data stored in the cache are consistent and up-to-date. It will be apparent to those skilled in the art that any number of other components, such as I / O devices, network interfaces, additional memory, processing accelerators, etc., may be included in the data processing system. The system may be integrated into a single integrated module, a multi-chip module, or may include distributed components.

[0021] Embodiments of the present invention involve transferring data to a cache 108 of a second processor core 106 before the second processor core reads data written or generated by a transmitter processor core 102. When the second processor core executes an instruction to read data, the access time is significantly reduced if the data is already stored in the cache 108. Therefore, the disclosed mechanism provides an improvement to the operation of a data processing system. Data may include information in a cache line (e.g., 64 bytes) and may be identified by the high bits of a data address or some other identifier. Here, the term 'data address' refers to the address of a data element (e.g., a word or byte) and the identifier of the data block containing that address (such as the high bits of the element address). When the data block is larger than the width of the data channel in the interconnect structure, data may be transmitted over the data channel in two or more chips (flow control bits).

[0022] Data can be associated with data addresses. Data addresses can be physical addresses in, for example, backing up memory or storage devices, or addresses of input / output devices. The processor core can operate in a virtual address space that is mapped to the physical address space. Virtual addresses can be mapped to physical addresses via one or more intermediate addresses. To speed up processing, copies of the data can be stored in one or more caches within the data processing system. This type of data is said to be 'associated' with a data address. However, data can be modified or written by the processor core, and at a given time, the data stored at the associated address may not match.

[0023] Data generated by a processing thread executing on the first processor core 102 can be consumed by a processing thread executing on the second processor core 106. In previous multi-core data processing systems, the generator core wrote data to local cache 104, home agent 114, or shared memory 116. A read operation by the consuming core 106 on the newly written data would result in a cache miss. The data must then be moved to the consuming core's local cache, causing processing delays or latency.

[0024] As disclosed herein, the kernel-to-kernel hiding provides a mechanism for transferring data from the first processor core 102 to the local cache 108 of the second processor core 106 before the second processor core reads the data. This increases the probability of a cache hit when reading data.

[0025] Kernel hiding mitigates performance degradation caused by cache misses, for example, by consumer processes in generator-consumer communication patterns. In one implementation, when generator kernel 102 completes a write to a cache line, it executes a hiding instruction to initiate a transfer of the cache line to a dedicated cache 108 of the consumer kernel. When the transfer completes before the consumer kernel issues a request for the cache line, the consumer will hit its dedicated cache, thereby significantly reducing cache line access latency.

[0026] In some applications, the generator thread can know which kernel is running the consumer thread and identify that kernel as the target of the hiding operation. In one implementation, the target kernel for the hiding operation is specified by the generator processor kernel.

[0027] In other applications, determining the target kernel or propagating that information across multiple software layers can be difficult or costly for the generator thread. For example, it may be challenging to propagate information from a Message Passing Interface (MPI) library to a low-level communication library such as the Unified Communications X (UCX) library.

[0028] In another embodiment, prior data based on the processor core uses an automatically identified target core. In this embodiment, transactions from processor cores that allocate and free data in the cache are monitored by Hidden Target Table (STT) control circuitry 120, and these transactions can be used to update information in Hidden Target Table 122. Hidden Target Table 122 can be memory, such as a set-associative cache. The cache can be indexed by the physical or intermediate addresses of cache lines and can be fully or partially tagged. The Hidden Target Table stores multiple entries. Each entry stores the identifier of one or more hidden targets at a given address. Hidden Target Table control circuitry 120 and Hidden Target Table 122 can be implemented in a home agent or in one or more processor cores and are used to identify one or more processor cores as hidden target cores for data associated with a specified data address.

[0029] The home agent 112 may also include a snooping filter 124 that also monitors transactions from processor cores that allocate and free data in the cache. STT 122 can be implemented by adding an additional field identifying the predicted hidden target to the snooping filter's cache entry.

[0030] Therefore, according to embodiments of this disclosure, the data processing system 100 includes an interconnect structure 110 and a plurality of processor cores (102, 106) interconnected through the interconnect structure. At least one processor core is configured to write data associated with a first data address to a cache and execute a first hiding instruction for the first data address. A hiding target table control circuit 120 is configured to monitor transactions from processor cores that allocate and release data to and from the cache of the processor cores, and to create and update entries in the hiding target table 122. The hiding target table control circuit 120 is also configured to, in response to the first hiding instruction, predict that one or more processor cores will be hiding target cores for the data associated with the first data address, and send a hiding message to the hiding target cores, the hiding message informing the hiding target cores of the data associated with the first data address and generated by the first processor core. A second processor core among the one or more hiding target cores is configured to, in response to receiving the hiding message, store the data associated with the first data address in the cache of the second processor core.

[0031] like Figure 1 As shown, an implementation of the data processing system may further include a home agent 112 coupled to a processor core via an interconnect structure 110, the home agent providing a consistency and serialization point for the data processing system. In this implementation, the home agent includes hidden target table control circuitry 120. In an alternative implementation, the hidden target table control circuitry 120 may be implemented in one or more processor cores within the processor core.

[0032] The hiding instruction executed by the generator thread specifies the data address. This instruction may or may not specify an identifier for the intended target kernel. When the target is not explicitly stated in the instruction, the hiding target can be determined in various ways. For example, the receiver kernel may register itself as a hiding target with the home agent, or the home agent may predict the hiding target. In some implementations, this prediction is based on the home agent monitoring shared-to-unique translations, unique-to-share translations of the data address, and read operations on previously hidden data addresses.

[0033] A data transfer method is disclosed, wherein a first processor core (sending core) of a data processing system writes data associated with a first data address into a first cache. The writing may include, for example, generating data and associating it with the first data address in the cache, or modifying the data in the cache associated with the first address. In either case, the first processor core may claim ownership of the data associated with the first address, thereby invalidating copies of the data in other caches. For example, the first data address may be a virtual address or a physical address.

[0034] Figure 2This is a flowchart 200 of a method for data transmission in a multi-core data processing system, based on various representative implementation schemes. Figure 2 Following the start box 202, at box 204, the hiding operation begins, executed by the generator processor core with a hiding instruction. This hiding instruction has an input register or operand specifying the address of the data to be hidden, and optionally another input register or operand identifying one or more hiding targets. The cache line in the first processor core's cache that holds the data associated with that address is the object of the operation. This hiding instruction may be included in the instruction set architecture (ISA) of the data processing system. See again. Figure 2 When the hiding instruction includes an identifier of the hidden target (as depicted in the affirmative branch from decision box 206), at 208, a hiding message is sent to the identified hidden target (receiver or consumer processor core) via the interconnect structure. This hiding message identifies a data address and provides the hidden target with notification or indication that data associated with that address is available. The hiding message can be sent directly to the hidden target or via a home agent. When sent via a home agent, the home agent generates the hiding message and identifies the target from the target identifier within the message. If the hidden target chooses to accept the data (as depicted in the affirmative branch from decision box 210), then at box 212, the hidden target prefetches the data associated with that data address. Then, as indicated in box 214, the execution of the hiding instruction is completed. If the hidden target determines not to accept the data, as depicted in the negative branch from decision box 210, then execution is also completed.

[0035] When the hide instruction does not include an identifier for the hide target (as depicted in the negative branch from decision block 206), the hide target is predicted based on previous data transactions in the data processing system. At block 216, the Hidden Target Table (STT) is accessed based on the data address to identify one or more hide targets. In one embodiment, the STT is accessed by the generator processor core. In another embodiment, the generator processor core sends a hide request to the home agent via an interconnect structure, and the home agent accesses the STT. The hide request includes a first data address. As described above, the home agent acts as a consistency and serialization point for memory or other addressable elements of the data processing system, shared among processor cores. The home agent may include a snooping filter that records the presence and consistency status of data in various caches of the data processing system. By monitoring transactions from processor cores that allocate and free data in their caches, the entries in the snooping filter are updated. The home agent may also include a system-level or last-level cache. The ownership agent records which processor cores share copies of cache lines (e.g., this can be recorded as an existence vector) and which sharers (if any) are designated as having ownership of the cache lines.

[0036] If the entry for the data address exists in the hidden target table, and that entry identifies one or more second processor cores as targets, as depicted in the affirmative branch from decision box 218, the process continues to box 208, and a hidden message is sent to each of the target processor cores. The hidden message informs the target processor core that newly written data associated with the first data address is available. Alternatively, the target processor core may ignore the hidden message or prefetch the data associated with the first data address into the cache of the second processor core. This cache may be, for example, a local or dedicated cache of the second processor core, or a lower-level cache of the kernel cluster. A cache hit occurs when the second processor core executes instructions to read the data before it is evicted from the cache, and the time to read the data is reduced. A cache hit improves the performance of the data processing system by reducing the time spent performing read operations on the data. If the entry for the data address does not exist in the hidden target table, or if the existing entry does not identify any target, as depicted in the negative branch from decision box 218, the execution of the hidden instruction is completed, as indicated in box 214. However, as will be described in detail below, the hidden target table can be updated.

[0037] Figure 3This is an exemplary kernel hiding operation interaction diagram 300 according to various representative implementations. The diagram shows a timeline 302 for a transmitter or generator kernel S, a home agent timeline 304, and a receiver or consumer kernel R timeline 306, where time flows downwards. At 308, the transmitter kernel writes data associated with data address A to a cache line of the transmitter kernel. At 310, the transmitter kernel executes a hiding instruction for data address A, thereby designating kernel R as the hiding target. The hiding instruction may take the following form:

[0038] STASH data_address, target_id

[0039] The operand `data_address` can be a virtual address, an indicator of a virtual address range, or some other indicator of one or more data addresses. The operand `target_id` identifies one or more processor cores as cache targets. It can be, for example, a numeric identifier or a bit vector. In a bit vector, the bit positions correspond to the hidden targets.

[0040] Message 312 is sent to the home agent. In response, the home agent sends a hidden message 316 to the target kernel R. The hidden message 316 indicates that the data associated with data address A has been modified. Kernel R can choose to ignore the message or prefetch the data associated with data address A. When kernel R chooses to prefetch the data associated with data address A, it sends a read request 318 for that data to the home agent. In response, the home agent sends message 320 to the sender kernel, requesting that the data associated with data address A be sent to kernel R. The message from the home agent to the processor kernel can be referred to as a 'snooping' message. The sender kernel performs the hiding operation by forwarding the data associated with data address A to the receiver kernel (kernel R) in message 322. The forwarded data is stored in the local cache of kernel R. When the receiver kernel R performs a read operation at 324, the data is already in the local cache, so the read results in a cache hit and the data can be loaded with minimal latency. This improves the performance of the data processing system.

[0041] In another implementation, when the hiding instruction identifies the hiding target, the hiding message can be sent directly from the sender kernel to the receiver kernel. In this case, after forwarding the data to kernel R, it may be necessary to send an acknowledgment from the sender kernel to the home agent so that the home agent can monitor data consistency.

[0042] Figure 4This is an interactive diagram 400 illustrating another example of a kernel hiding operation based on various representative implementations. The diagram shows a timeline 402 for the transmitter or generator kernel S, a timeline 404 for the home agent, and a timeline 406 for the receiver or consumer kernel R, with time flowing downwards. At 408, the transmitter kernel writes data associated with data address A into the transmitter kernel's cache line. At 410, the transmitter kernel executes a hiding instruction for data address A, without specifying a hiding target. The hiding instruction may take the following form:

[0043] STASH data_address

[0044] The operand data_address can be, for example, a virtual address.

[0045] exist Figure 3 In this context, the owner agent directly determines the hidden target from message 312. However, in... Figure 4 In the hidden message 412, data address A is contained, but target identifier is not. In this implementation, the home agent determines one or more hidden targets based on the data address A indicated in the hidden message 412 by accessing a hidden target table at 414. If the table contains an entry for data address A and that entry identifies one or more hidden targets, a hidden message 416 for data address A is sent to the identified receiver kernel. This method is described in reference to... Figure 3 The continuation, where interactions 418-424 correspond to elements 318-324, describes a process where kernel R selects to prefetch data associated with data address A. It sends a read request 418 for that data to the home agent. In response, the home agent sends message 420 to the sender kernel, requesting that the data associated with data address A be sent to kernel R. The sender kernel performs the hiding operation by forwarding the data associated with data address A to the receiver kernel (kernel R) in message 422. This data is stored in kernel R's local cache. When the receiver kernel (kernel R) performs a read operation at 424, the data is already in its local cache, resulting in a cache hit and minimal data loading latency.

[0046] Reference Figure 3 In the method described, the identifier in the hidden message is used to determine the hidden target, while in the reference... Figure 4 The method described uses a hidden target table to determine the hidden targets. See below for reference. Figures 7 to 11 This section describes several exemplary mechanisms for generating and maintaining a table of hidden targets. Generally, the home agent generates and maintains hidden targets by monitoring data transfers and performing data consistency operations on data addresses.

[0047] therefore, Figure 3 and Figure 4 An example of a data transfer method in a data processing system is illustrated. According to this method, a first processor core writes data associated with a first data address into a first cache and sends a first hiding request to a home agent of the data processing system, the first hiding request including the first data address. The home agent or generator core determines a second processor core, at least in part, based on the first hiding request, to receive and send a hiding message to the second processor core. Upon receiving the hiding message, the second processor core may optionally prefetch the data associated with the first data address into its own cache. In one embodiment, the first hiding request includes an identifier of the second processor core. In another embodiment, the hiding target is determined by accessing a first entry in a hiding target table, the first entry being associated with the first data address.

[0048] Figure 5 Example 500 of a Hidden Target Table (STT) according to various representative implementations is shown. Each entry in Table 500 includes a data address 502 and an identifier 504 for one or more hidden targets. Initially, an entry may have a data address but no hidden target. The data address 502 may be a physical address or an intermediate address, such as a surface or dummy physical address. The data address may be, for example, an identifier of a cache line or page. More generally, memory can be logically divided into regions at a specified granularity (less than, greater than, or equal to a cache line), in which case the data address may be an identifier of the region. The data processing system may include multiple SSTs using different granularities.

[0049] Figure 6 Another example 600 of a Hidden Target Table (STT) according to various representative implementations is shown. Each entry in this table includes a base data address 602, an identifier 604 for one or more hidden targets, and a size 606. The base address and size together indicate a size address range (e.g., size cache line, size word, or size bytes), from base_address to base_address + size - 1. Thus, the first entry in STT 600 indicates the hidden targets for addresses A, A+1, A+2, and A+3, and is equivalent to... Figure 5 The first four entries in Table 500. In this example, the hidden targets are identified as bit vectors. For example, the identifier in the second entry of Table 600 is the bit vector 00001010, where the position of 1 indicates the hidden targets 2 and 4 at data address B.

[0050] The range of entries specified by the base data address 602 and size 606 can be restricted to not crossing specified memory boundaries. This enables the implementation of set-associative tables, where only one set needs to be searched for each table lookup operation.

[0051] STT can be located at the home agent or at each of the multiple processor cores. Alternatively, the hidden target information can be stored in the home agent's snoop filter cache. For each cache line, the snoop filter cache can include entries with data fields that record the sharer, owner, and consistency state of the multiple cache lines. Additional fields can be provided to record the hidden target of the cache line. This is efficient for applications where most cache lines have cache targets, but less efficient for applications where only a small fraction of cache lines have hidden targets.

[0052] Subsequently, various exemplary methods for creating and updating STTs are disclosed. These examples are described with reference to the home agent. However, equivalent methods can also be used to maintain STTs at the processor core.

[0053] Figure 7 This is an interaction diagram 700 illustrating methods for updating a hidden target table according to various representative implementations. According to this method, the receiver processor core sends a target registration message for a data address to the home agent. In response, the home agent generates an entry in the hidden target table, the first entry identifying the receiver processor core as the target of data associated with that data address. (See reference...) Figure 7 The diagram illustrates timeline 702 for the transmitter or generator kernel S, timeline 704 for the home agent, and timeline 706 for the receiver or consumer kernel R, with time flowing downwards. At 708, the receiver kernel R executes a registration instruction that instructs the hardware that the software running on the receiver kernel (the future target) expects to read data that will be hidden by another kernel. This data can be specified by a virtual address. For example, the registration instruction can take the following form:

[0054] STASH_TARGET virtual_address

[0055] The kernel executing this instruction is identified as a future hidden target containing a cache line corresponding to the physical address of that virtual address.

[0056] Alternatively, the STASH_TARGET instruction can specify a virtual address range, and this instruction takes the form of, for example, the following:

[0057] STASH_TARGET base_virtual_address, size

[0058] This instruction identifies all cache lines associated with the corresponding physical address as potential targets for a hidden operation aimed at the kernel executing the STASH_TARGET instruction.

[0059] Execution of the registration instruction causes message 710 to be sent from the receiver kernel R to the home agent. Note that the virtual address can be translated into an intermediate or physical address to be included in message 710.

[0060] In some applications, threads are pinned to the kernel. In others, the STASH_TARGET instruction may need to be executed or re-executed after a consumer thread migration to ensure that the reported target kernel is correct when performing the actual hiding operation. There are various opportunities to execute the STASH_TARGET instruction when initializing, reading, or recirculating data buffers, so it may not be necessary to actively execute the STASH_TARGET instruction immediately after each thread migration. Threads are typically executed by the kernel for a longer period than the program iterations that adapt to hiding. Therefore, a lack of active registration may result in only a small fraction of hiding opportunities being missed.

[0061] At 712, the home agent creates or updates an entry in the hidden target table for data address A, which indicates the receiver kernel R as a hidden target.

[0062] Similarly, since the snooping filter in the home agent records metadata associated with each cache line (including the consistency status of the cache line in each cache, which kernels have copies of the cache line, and which kernel (if any) owns the cache line), the metadata can be expanded to include hidden target fields (such as bit vectors) that store the hidden target of the cache line.

[0063] In an alternative implementation, the hidden target table described above can be used to record reported target kernel information. This hidden target table only needs to record data for cache lines to be hidden, which may be a small fraction of the total number of cache lines stored in the snoop filter cache. The hidden target table can be a set-associative cache, indexed by the physical addresses of the cache lines and fully or partially tagged, with each entry storing one or more hidden targets. A cache replacement strategy based on recent access can be used, ensuring that the least recently used entries in the table are eventually replaced, including those that have expired due to thread migration, etc. The only potential impact of incorrect hidden targets due to expired entries is the occurrence of the same cache misses that would have occurred if no hiding had been performed. The target will be corrected when the consumer thread re-executes a new STASH_TARGET instruction for that line.

[0064] As mentioned above, the hidden target table can specify address ranges. This reduces the number of entries required, for example, when hiding large messages or when the communication library works with a large buffer. When address ranges are specified, overlaps between address ranges can be detected, and older entries are updated and / or invalidated to prevent overlap.

[0065] Figure 8 This is an additional exemplary update interaction diagram 800 for hiding the target table according to various representative implementations. The diagram illustrates a timeline 802 for the transmitter or generator kernel S, a timeline 804 for the home agent, and a timeline 806 for the receiver or consumer kernel R, where time flows in a downward direction. In this implementation, the home agent updates the hidden target table when the consistency state of the data changes.

[0066] The kernel (sender) about to write to a cache line must request that the line be in a unique state, thus invalidating all copies of that line in other kernels' dedicated caches. This confirms the kernel's ownership of the cache line. The kernel that receives the invalidation message (the sharer of the line) is the previous reader or writer of the line, and therefore a potential target for hiding the line when the sender performs a hide operation on the newly created cache line. Typically, the time between writing to the cache line and hiding it is very short (usually less than a few thousand cycles), creating an opportunity for the kernel with the most recently invalidated copy of the cache line to identify as the target of subsequent hide operations.

[0067] See you again Figure 8 At 808, the transmitter kernel S initiates a write operation for data associated with data address A. In this case, it shares a cache line with other kernels, and therefore sends message 810 to the home agent, requesting ownership of the appropriate cache line for kernel S. In response, the home agent accesses its snooping filter and identifies the receiver kernel R as the sharer of the cache line. The home agent then sends an invalidation message 812 to the receiver kernel R to invalidate the cache line in the receiver kernel's cache.

[0068] Based on this transaction, it is clear that the sender kernel is the generator of the data associated with data address A, while the receiver kernel was at least previously the consumer (or generator) of that data. Based on this understanding, at 814, the home agent generates or updates an entry in the hidden target table, thereby indicating that the receiver kernel R is a potential hidden target of the data associated with data address A. This operation is completed by the receiver kernel R acknowledging the invalid message from the home agent in message 816, and the home agent forwarding this acknowledgment to the sender kernel S in message 818. The data in the sender kernel S's local cache is now in a uniquely consistent state, and the sender kernel S owns the cache line.

[0069] This method allows the hidden target table to be updated by the owner agent without the kernel needing to know the identity of the hidden target or hidden source. This is useful in situations where software has difficulty accessing the hidden target ID, such as in virtualized environments and when multiple library layers exist, such as the network stack.

[0070] This mechanism is effective, for example, when used with communication libraries that reuse buffers used for communication between the two kernels. In this case, the snooping filter will repeatedly look for the same shared-to-unique translation for a given address (cache line).

[0071] If there are more than two sharers when a request to make a target unique is received at the home agent, the home agent may insert multiple targets into the hidden target table.

[0072] like Figure 9 As shown, there is another opportunity to predict a hidden target when a dirty cache line (i.e., a cache line containing data that has been written to but not yet stored back into memory) is requested by another kernel and forwarded to that kernel. The requesting kernel is a potential hidden target for the hiding operation. When the home agent receives a forwarding acknowledgment from the sender, it can insert the hidden target into the hidden target table according to the cache coherence protocol.

[0073] Figure 9 This is an interactive diagram 900 illustrating alternative methods for updating the hidden target table according to various representative implementations. The diagram shows a timeline 902 for the transmitter or generator kernel S, a timeline 904 for the home agent, and a timeline 906 for the receiver or consumer kernel R, where time flows downwards. In this implementation, the home agent updates the hidden target table again when the data consistency state changes. However, in this case, the table is updated when the cache transitions from a unique, dirty state to a shared, dirty state.

[0074] See Figure 9At 908, the receiver kernel R requests data associated with data address A by sending request 910 to the home agent. The home agent accesses its snooping filter, identifies the sender kernel S as the owner of the cache line, and sends snooping request 912 to the sender kernel S. In response, the sender kernel S forwards the cache line to the receiver kernel R in message 914 and acknowledges the home agent's transaction in message 916. Based on this transaction and the understanding that the data is 'dirty' (i.e., modified), it is clear that the sender kernel S is the generator of the data associated with data address A, and the receiver kernel R is the consumer of that data. Therefore, at 918, the home agent creates an entry for data address A in the hidden target table, which identifies the receiver kernel R as the hidden target.

[0075] Figure 9 The method in this paper is effective only if the updated hide target table entry has not yet been removed from the hide target table when the sender writes to the cache line and executes the hide instruction. However, it should be recognized that not all forwarded cache lines will be the actual targets of future hide operations.

[0076] Figure 10 This is an interactive diagram 1000 for another exemplary update of the hidden target table according to various representative implementations. The diagram shows a timeline 1002 for the transmitter or generator kernel S, a timeline 1004 for the home agent, and a timeline 1006 for the receiver or consumer kernel R, with time flowing downwards. At 1008, when a hiding instruction is executed without a hidden target, a corresponding message 1010 is sent to the home agent. At 1012, the hidden target table is accessed, and it is determined that the receiver kernel R will be the hidden target. A hiding message 1014 is sent to the hidden target. In this example, the receiver kernel R chooses to reject the hiding message and sends message 1016, thereby acknowledging receipt of the hiding message and rejecting the data associated with data address A. At 1018, the home agent updates the hidden target table to remove the receiver kernel R as the hidden target for data address A.

[0077] Figure 11 This is an interactive diagram 1100 illustrating another method for updating the hidden target table according to various representative implementations. In the method shown, only entries for those cached lines already specified in the hiding instruction are inserted into the hidden target table. The diagram shows the timeline 1102 of the transmitter or generator kernel S, the timeline 1104 of the home agent, and the timeline 1106 of the receiver or consumer kernel R, where time flows downwards. At 1108, when the hiding instruction is executed without a hidden target, a corresponding message 1110 is sent to the home agent. Figure 11In the example shown, the cache line is in a unique, dirty state. That is, only the sender kernel has a valid copy of the data, but the data is dirty because it has not yet been written back to memory. At 1112, in response to the hidden message, the home agent generates an entry for data address A in the hidden target table (assuming such an entry does not yet exist). However, any new entry created at 1112 does not identify any hidden target.

[0078] Later, at 1114, the receiver kernel R initiates a read operation. Since the data is not in kernel R's local cache, a request for the data is sent to the home agent at 1116. The home agent sends a listening message at 1118 to the sender kernel S, and the sender kernel S forwards the requested data to the receiver kernel R in message 1120. Then, the sender kernel S acknowledges the home agent's transaction in message 1122. At 1124, the home agent updates the entry for data address A to indicate the receiver kernel R as the hidden target of data address A.

[0079] It will be apparent to those skilled in the art that other events can be used to identify the target of the hidden target table. Events include, for example, data being removed from the receiver's dedicated cache, a conversion from shared to unique, and the forwarding of dirty cache lines. The target can then be used for future hiding instructions.

[0080] The hidden targets in the hidden target table can be reset after executing a specified number of hiding instructions, allowing the system to relearn the hidden targets for the next iteration. Alternatively, this can be done using feedback from the receiver regarding whether the hiding was effective.

[0081] Since the capacity of the target table is limited, it can follow a recent access-based replacement strategy (such as Least Recently Used) for each entry. The software can consider the capacity of the target table to determine how many rows might be reasonable to hide without specifying a target.

[0082] Figure 12This is a flowchart 1200 of a method for creating and updating a hidden target table by a home agent, according to various representative implementations. At block 1202, the home agent receives a message from the processor core specifying a data address. If the home agent determines that there is currently no entry in the hidden target table associated with that data address, as depicted in the negative branch from decision block 1204, the process continues to decision block 1206. If the message received from the processor core is neither a hidden message nor a target registration message, as depicted in the negative branch from decision block 1206, the hidden target table is not updated, as indicated in block 1208. If the message from the processor core is a hidden message or a target registration message, as depicted in the positive branch from decision block 1206, at block 1210, a new entry for that data address is created in the hidden target table, and the process continues to decision block 1212. If an entry for that data address already exists in the table, the process also continues to decision block 1212, as depicted in the positive branch from decision block 1204.

[0083] If the received message is a request to read modified or dirty data from the generator kernel, or an explicit request to register the kernel as a hidden target, as depicted in the affirmative branch of decision box 1212, then at box 1214, the identifier of the kernel that sent the message to the home agent is inserted into the entry for the specified data address in the hidden target table.

[0084] If the received message is a request for ownership of a cache line from the generator kernel (i.e., a request to make the cache line unique), or a hiding request from the generator kernel, as depicted in the affirmative branch of decision box 1216, the ownership agent determines from the snooping filter which (if any) other kernels share the cache line, and at box 1218, inserts the identifiers of those kernels into the hidden target table entry for that data address. If the message is some other message, as depicted in the negative branch of decision box 1216, an update to the hidden target table is performed for the received message, as indicated in box 1220.

[0085] In this way, the home agent can create and update the hidden target table in response to messages received from the processor cores. When the sending core knows the target of the hiding operation, the target's identifier can be included in the hiding message. When the receiver of the hiding operation knows the source of the updated data, the receiver can register with the home agent. In other cases, the home agent determines the hiding target based on the interaction between the processor cores.

[0086] In one implementation, the home agent, in response to receiving a hide request for a data address from a first processor core, generates an entry for that data address in a hide target table. When data associated with that data address is stored in the caches of one or more second processor cores, in response to a request from the first processor core to make that data unique within its cache, invalidates data in other caches. The home agent updates the entry to identify that one or more second processor cores as the target of future hide requests for that data address.

[0087] This entry can also be created or updated when the home agent forwards a read request for data associated with that data address from the second processor core to the first processor core. An updated entry identifies the second processor core as the target of a hidden request for that data address.

[0088] More generally, the home agent updates the entry for the first data address in the hidden target table in response to a change in the consistency state of the data associated with the first data address in the cache of the first processor core from unique to shared or from shared to unique.

[0089] For example, the home agent may generate an entry for a data address in a hidden target table in response to a hidden message from a first processor core, and later update the entry in response to forwarding data associated with that data address to a second processor core to identify the second processor core as a hidden target for that data address.

[0090] Figure 13This is an interactive diagram 1300 illustrating the kernel hiding operation according to various representative implementations. The diagram shows a timeline 1302 for the transmitter or generator kernel S, a timeline 1304 for the first receiver kernel R1, and a timeline 1306 for the second receiver kernel R2, with time flowing downwards. At 1308, the transmitter kernel writes data associated with data address A into its cache line. At 1310, the transmitter kernel executes a hiding instruction for data address A, thereby designating kernels R1 and R2 as hiding targets. The transmitter kernel S sends a hiding message 1312 to receiver kernel R1 and a hiding message 1314 to receiver kernel R2. Alternatively, the hiding message can be broadcast to all other receiver kernels. The hiding message informs or prompts the receiver kernels that the data associated with address A is available at the transmitter kernel S. In the example shown, at 1316, receiver kernel R1 chooses to reject the data, while at 1318, receiver kernel R2 chooses to accept the data. Receiver kernel R2 requests the data in message 1320, and the data is returned from sender kernel S in forwarding message 1322. Subsequently, at 1324, receiver kernel R2 executes a read instruction for the data associated with address A. This instruction results in a cache hit because the data is already hidden in receiver kernel R2's local cache. In this implementation, a home agent is not required. Each kernel can monitor data transactions to track data consistency. Additionally, each kernel can maintain a hidden target table.

[0091] Figure 14 This is an additional interactive diagram 1400 of the kernel hiding operation according to various representative embodiments. The diagram shows a timeline 1402 for the transmitter or generator kernel S, a timeline 1404 for the first receiver kernel R1, and a timeline 1406 for the second receiver kernel R2, with time flowing downwards. At 1408, the transmitter kernel writes data associated with data address A into its cache line. At 1410, the transmitter kernel executes a hiding instruction for data address A, where there is no identifier for the hiding target. At 1412, the transmitter kernel accesses the hiding target table. If an entry for data address A exists in the hiding target table, a hiding message is sent to each hiding target identified in that entry. In the example shown, the entry identifies receiver kernel R1 as the unique target, and a hiding message 1414 is sent to receiver kernel R1. In this embodiment, the hiding message includes the data written at 1408. At 1416, receiver kernel R1 can choose to accept the data and store it in its local cache, or reject the data. Alternatively, the receiver kernel R1 may choose to reject data, in which case the response (such as an acknowledgment) may be specified by the protocol.

[0092] It will be obvious to those skilled in the art that Figure 13 Hidden messages can optionally contain data instead of notifications, and Figure 14 Hidden messages can optionally include notifications instead of data.

[0093] Figure 15 This is an interactive diagram 1500 illustrating an exemplary hidden target registration operation according to various representative implementations. The diagram shows timelines 1502, 1504, and 1506 for a first processor core, a second processor core, and a third processor core, with time flowing downwards. At 1508, kernel 3 executes a registration instruction to register as a hidden target for data address A with other kernels. The registration message is then broadcast to the other kernels in the processing system. In this example, registration message 1510 is sent to kernel 2 and registration message 1512 is sent to kernel 1. Upon receiving the message, the kernels record the data address in their respective hidden target tables—kernel 2 at 1514 and kernel 1 at 1516. The table entry for address A then identifies kernel 3 as a hidden target. In this way, a hidden table can be created at each kernel. Thus, data transaction processing between kernels can be monitored and used to predict which kernels will benefit from receiving data or hidden notifications.

[0094] As mentioned above, hidden messages can contain data or hidden notifications. Figure 16 An example is shown in the image.

[0095] Figure 16 This is an interactive diagram 1600, representing another example of a kernel hiding operation based on various representative implementations. The diagram shows a timeline 1602 for the transmitter or generator kernel S, a timeline 1604 for the home agent, and a timeline 1606 for the receiver or consumer kernel R, with time flowing downwards. At 1608, the transmitter kernel writes data associated with data address A into the transmitter kernel's cache line. At 1610, the transmitter kernel executes a hiding instruction for data address A, without specifying a hiding target. The hiding instruction may take the following form:

[0096] STASH data_address

[0097] The operand data_address can be a virtual address or some other indicator of a cache line (such as an address label), or a hidden instruction can identify one or more hidden targets.

[0098] exist Figure 16In the example shown, message 1612 contains data address A and the data associated with data address A, but not the target identifier. Therefore, at 1614, the data is stored in the home agent's system cache. Also at 1614, the home agent determines one or more hidden targets by accessing the hidden target table based on the data address A identified in hidden message 1612. If the table contains an entry for data address A and that entry identifies one or more hidden targets, a hidden message 1616 for data address A is sent to the identified receiver kernel. When kernel R chooses to prefetch the data associated with data address A, it sends a read request 1618 for that data to the home agent. In response, the home agent sends a request for data to the receiver kernel R in message 1620. This information is stored in kernel R's local cache. When the receiver kernel (kernel R) performs a read operation at 1622, the data is already in the local cache, so the read results in a cache hit and the data can be loaded with minimal latency.

[0099] Numerous details are set forth to provide an understanding of the embodiments described herein. These embodiments may be practiced without these details. In other instances, well-known methods, procedures, and components have not been described in detail to avoid obscuring the embodiments described. This disclosure should not be construed as limiting the scope to the embodiments described herein.

[0100] Those skilled in the art will recognize that this disclosure has been described with the aid of examples. This disclosure may be implemented using hardware component equivalents such as dedicated hardware and / or dedicated processors, which are equivalents of this disclosure as described and claimed. Similarly, dedicated processors and / or dedicated hardwired logic may be used to construct alternative equivalent embodiments of this disclosure.

[0101] Specialized or reconfigurable hardware components used to implement the disclosed mechanisms can be described, for example, by instructions in a hardware description language (HDL), such as VHDL, Verilog, or RTL (Register Transfer Language), or by a netlist of components and connectivity. Instructions can be at the functional or logical level, or a combination thereof. Instructions or netlists can be input into automated design or manufacturing processes (sometimes called high-level synthesis), which interpret the instructions and create digital hardware that implements the described functions or logic.

[0102] HDL instructions or netlists may be stored on non-transitory computer-readable media, such as electrically erasable programmable read-only memory (EEPROM); non-volatile memory (NVM); mass storage devices, such as hard disk drives, floppy disk drives, optical disk drives; and, without departing from this disclosure, optical storage elements, magnetic storage elements, magneto-optical storage elements, flash memory, magnetic core memory, and / or other equivalent storage technologies. Such alternative storage devices should be considered equivalents.

[0103] The various embodiments described herein are implemented using dedicated hardware, configurable hardware, or a programmable processor that executes programming instructions, which are broadly described in flowchart form and can be stored on any suitable electronic storage medium or transmitted via any suitable electronic communication medium. Combinations of these elements may be used. Those skilled in the art will understand that the above processes and mechanisms can be implemented in any number of variations without departing from this disclosure. For example, the order of certain operations performed may often be changed, additional operations may be added, or operations may be deleted without departing from this disclosure. Such variations are conceivable and are considered equivalent.

[0104] Various representative embodiments described in detail herein are given by way of example rather than limitation. Those skilled in the art will understand that various changes can be made to the form and details of the described embodiments to obtain equivalent embodiments that remain within the scope of the appended claims.

Claims

1. A data transmission method, the data transmission method comprising: The first processor core of the data processing system writes the data associated with the first data address into the first cache. The first processor core executes a hidden instruction, which has a virtual address corresponding to the first data address as a first operand. Based at least in part on the first data address or the second operand of the hidden instruction, it is determined that the second processor core of the data processing system will be the hidden target of the hidden message; Send the hidden message to the second processor core, the hidden message including the first data address; as well as In response to receiving the hidden message, the second processor core stores the data associated with the first data address in the cache of the second processor core. Wherein, the first cache is the cache of the first processor core, and the second processor core stores the data associated with the first data address in the cache of the second processor core, including: The second processor core requests the data associated with the first data address; and The first processor core forwards the data associated with the first data address to the second processor core.

2. The method according to claim 1, further comprising the first processor core determining that the second processor core will be the hidden target and sending the hidden message to the second processor core.

3. The method according to claim 1, wherein, The second operand of the hidden instruction includes the identifier of the second processor core.

4. The method according to claim 1, wherein, The hidden message includes the data associated with the first data address.

5. The method according to claim 1, wherein, The determination includes accessing a first entry in the hidden target table, the first entry being associated with the first data address.

6. The method of claim 5, further comprising, prior to the determination: The second processor core sends a target registration message for the first data address; and The first entry in the hidden target table is generated, and the first entry identifies the second processor core as the target of data associated with the first data address.

7. The method of claim 5, further comprising, prior to the determination: In response to receiving a previous hiding request for the first data address from the first processor core, the first entry for the first data address is generated in the hiding target table.

8. The method according to claim 5, further comprising: In response to a change in the consistency status of the data associated with the first data address in the cache of the first processor core from unique to shared or from shared to unique, the first entry in the hidden target table is updated.

9. The method of claim 5, further comprising, before the writing: In response to the first processor core's request for ownership of the data associated with the first data address, invalidate the data associated with the first data address stored in the cache of one or more third processor cores; and Update the first entry in the hidden target table to identify the one or more third processor cores as the hidden target of the first data address.

10. The method according to claim 1, further comprising: The first processor core sends a first hiding request to the home agent of the data processing system. The first hiding request includes the first data address, and the home agent is configured to: determine that the second processor core of the data processing system will be the hiding target of the hidden message and send the hidden message to the second processor core.

11. The method according to claim 10, wherein, The determination includes accessing a first entry in the hidden target table, the first entry being associated with the first data address.

12. The method of claim 11, further comprising, prior to the determination: In response to receiving a previous hide request for the first data address from the first processor core, the home agent generates the first entry for the first data address in the hide target table.

13. The method of claim 12, further comprising, prior to the determination: The home agent forwards read requests for the data associated with the first data address from the second processor core to the first processor core; The home agent updates or creates the first entry in the hidden target table to identify the second processor core as a hidden target for the first data address; as well as The first processor core forwards the data associated with the first data address to the second processor core for storage in the cache of the second processor core.

14. The method of claim 12, further comprising: In response to a change in the consistency status of the data associated with the first data address in the cache of the first processor core from unique to shared or from shared to unique, the first entry in the hidden target table is updated.

15. The method according to claim 10, wherein, The second processor core stores the data associated with the first data address in the cache of the second processor core, including: The second processor core sends a request to the home agent; The home agent sends a message to the first processor core; and The first processor core forwards the data associated with the first data address to the second processor core.

16. A data transmission method, the data transmission method comprising: Monitor transaction processing from multiple processor cores of a data processing system, which allocate data to and deallocate the data in their caches. Based at least in part on the monitored transaction processing, it is predicted that one or more of the plurality of processor cores will be the hidden target core for data associated with the first data address; The first processor core among the plurality of processor cores executes a first hidden instruction targeting the first data address; A hidden message is sent to the hidden target kernel, the hidden message notifying the hidden target kernel of the data associated with the first data address and generated by the first processor kernel; as well as In response to receiving the hidden message, the second processor core in the one or more hidden target kernels stores the data associated with the first data address in the cache of the second processor core.

17. The method of claim 16, further comprising, before executing the first hidden instruction: The first processor core executes a second hidden instruction targeting the first data address; In response to executing the second hiding instruction, an entry for the first data address is stored in the hiding target table; and, In response to the second processor core becoming or ceasing to become a sharer of the data associated with the first data address, the entry in the hidden target table is updated to identify the second processor core as a hidden target core. in, Predicting that one or more of the plurality of processor cores will be the hidden target core for data associated with the first data address includes accessing the entry for the first data address in the hidden target table.

18. The method of claim 16, further comprising, before executing the first hidden instruction: The second processor core executes the registration instruction for the first data address; and In response to the registration instruction, an entry is created or updated in the hidden target table, the entry identifying the second processor core as a hidden target core for the first data address. in, Predicting that one or more of the plurality of processor cores will be the hidden target core for data associated with the first data address includes accessing the entry for the first data address in the hidden target table.

19. A data processing system, the data processing system comprising: Interconnection structure; Multiple processor cores interconnected via the interconnect structure, wherein a first processor core is configured to write data associated with a first data address to a cache and execute a first hidden instruction for the first data address; The target table control circuit is hidden, and the target table control circuit is configured to: Monitor transaction processing from multiple processor cores of a data processing system, which allocate data to and deallocate the data in their caches. Create and update entries in the hidden target table; In response to the first hiding instruction, it is predicted that one or more of the plurality of processor cores will be the hidden target core for data associated with the first data address; A hidden message is sent to the hidden target kernel, the hidden message being configured to notify the hidden target kernel of the data associated with the first data address and generated by the first processor kernel; and The second processor core in the one or more hidden target kernels is configured to, in response to receiving the hidden message, store the data associated with the first data address in the cache of the second processor core.

20. The data processing system according to claim 19, further comprising: A home agent, coupled to the plurality of processor cores via the interconnect structure, is configured to provide a consistency and serialization point for the data processing system. The attribution agent includes the hidden target table control circuit.

21. The data processing system according to claim 19, wherein, The first processor core includes the hidden target table control circuit.

22. The data processing system according to claim 19, wherein, The hidden target table control circuit is further configured as follows: In response to a hidden instruction from the first processor core or a registration request from the second processor core, an entry is created in the hidden target table; In response to a read request or a hidden registration request sent from the second processor core, the second processor core is inserted into the entry as a hidden target; as well as In response to a hidden instruction from the first processor core or a change in the consistency state of the data associated with the first data address from shared to owned by the first processor core, a sharer of the data other than the first processor core is inserted into the entry as a hidden target.

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