Packaged transistors with channeled die attach material and processes for implementing the same

Abstract

A package includes a circuit having at least one active area and at least one secondary device area, a support configured to support the circuit, and a chip attach material. The circuit is mounted on the support using the chip attach material, and the chip attach material includes at least one channel configured to allow gases generated during curing of the chip attach material to be released from the chip attach material.

Description

[0001] Cross-references to related applications

[0002] This application is a partial continuation of U.S. Patent Application No. 16 / 868,639, filed May 7, 2020, which is incorporated herein by reference in its entirety. This application also claims the benefit of U.S. Provisional Application No. 63 / 055,541, filed July 23, 2020, the entire contents of which are incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] This disclosure relates to semiconductor chip attachment materials having at least one channel. This disclosure further relates to a radio frequency (RF) package having a semiconductor chip, such as a group III nitride-based chip, having a chip attachment material with at least one channel, including but not limited to multiple, intersecting, and / or differently shaped channels or recesses, such as a mesh configuration. Background Technology

[0004] One of the main modern chip attachment materials that replaces AuSn (gold-tin solder) in low-cost packaging is silver sintered chip attachment. These materials consist of 75-90% tiny silver particles by mass and the remainder being volatile organic compounds (VOCs). The material can be dispensed via needle, screen printing, or inkjet printing. Chip attachment materials provide a high thermal conductivity path, dissipating high power through the material and also providing strong mechanical bonding to the package in which the chip is attached. Once the material is dispensed or screen-printed onto a support, such as a lead frame or base, and the chip is placed on the material, it is then cured and hardened. During the curing of such chip attachment materials, which are made of metal particles and VOCs (such as plastics, polymers, or resins), the VOCs are released; that is, they form bubbles. These bubbles freeze within the chip attachment material as it hardens. For high-power dissipation applications on large-area semiconductor chips, such as III-nitride-based microwave monolithic integrated circuits or large-area III-nitride-based GaN HEMTs, voids formed during the curing or attachment process can be located beneath the transistor portions of the semiconductor chip and suppress heat transfer from the transistors. The location of the generated gases is partially random, and because the sintered material is typically viscous, minimal void aggregation or bubble "escape" to the material edges before the material is fully hardened. Generally, the larger the semiconductor chip, such as a typically larger MMIC, the higher the degree of void aggregation can be found in the central region of the semiconductor chip, which can lead to voids beneath critical active transistor regions.

[0005] Attaching a group III nitride-based chip (e.g., a MMIC) to a support structure (such as a metal leadframe, metal flange, or other suitable sub-mount or support structure) is part of the packaging process. Packaging typically includes a protective material formed on or around the chip, and this protective material adheres to various parts of the chip and / or support structure. However, the protective material may not reliably adhere to the various parts of the chip and / or support structure, potentially leading to package failure. In particular, protective packaging materials, such as plastics, synthetic materials, or other suitable materials, may not reliably adhere to the various metal portions of the support.

[0006] Therefore, a device and process are needed to limit void generation in the chip bonding material of semiconductor chips. Furthermore, a device and process are needed to improve the adhesion of protective materials used to package semiconductor chips. Summary of the Invention

[0007] One aspect of this disclosure includes a semiconductor device comprising a semiconductor chip; a support; and a chip attachment material including at least one channel, at least a portion of which is located between the semiconductor chip and the support to allow gas generated during attachment of the semiconductor chip to the support to be released from the chip attachment material.

[0008] One aspect of this disclosure includes a method of implementing a semiconductor device, the method comprising providing a semiconductor chip; providing a support; and forming a chip attachment material including at least one channel, at least a portion of the at least one channel being located between the semiconductor chip and the support to allow gas generated during attachment of the semiconductor chip to the support to be released from the chip attachment material.

[0009] One aspect of this disclosure includes a semiconductor device comprising a semiconductor chip; a support; and a chip attachment material including at least one channel, at least a portion of which is located between at least one secondary device region of the semiconductor chip and the support to allow gases generated during attachment of the semiconductor chip to the support to be released from the chip attachment material.

[0010] One aspect of this disclosure includes a semiconductor device comprising a semiconductor chip; a support; and a chip attachment material including at least one channel; and an outer mold configuration at least surrounding the semiconductor chip, the outer mold configuration being at least partially attached to the chip attachment material.

[0011] Additional features, advantages, and aspects of this disclosure will be set forth or become apparent upon consideration of the following detailed description, accompanying drawings, and claims. Furthermore, it should be understood that the foregoing summary and the following detailed description of this disclosure are exemplary and intended to provide further explanation, without limiting the scope of the claimed disclosure. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, are included to provide a further understanding of this disclosure. They illustrate various aspects of this disclosure and, together with the detailed description, serve to explain the principles of this disclosure. No attempt is made to show the structural details of this disclosure in greater detail, which may be necessary for a basic understanding of this disclosure and for practicing its various forms. In the drawings:

[0013] Figure 1 A perspective view of the package according to this disclosure is shown.

[0014] Figure 2 It shows that according to Figure 1 A partial top view of the encapsulation.

[0015] Figure 3A It shows along Figure 2 A partial cross-sectional view of the package taken from line III-III.

[0016] Figure 3B It shows Figure 3A A partial cross-sectional view of another aspect.

[0017] Figure 4 It shows Figure 3A A partial view.

[0018] Figure 5 An exemplary layout of a chip attachment material according to this disclosure is shown.

[0019] Figure 6 Various exemplary dimensions of the channels for chip attachment materials according to this disclosure are shown.

[0020] Figure 7 An exemplary layout of chip attachment material according to this disclosure is shown.

[0021] Figure 8 An exemplary layout of a chip attachment material according to this disclosure is shown.

[0022] Figure 9 An exemplary layout of a chip attachment material according to this disclosure is shown.

[0023] Figure 10 An exemplary layout of a chip attachment material according to this disclosure is shown.

[0024] Figure 11 It shows that according to Figure 1 A partial top view of the encapsulation.

[0025] Figure 12 It shows that according to Figure 11 A partial top view of the encapsulation.

[0026] Figure 13 It shows that according to Figure 11 A partial top view of the encapsulation.

[0027] Figure 14 It shows that according to Figure 13 A partial top view of the encapsulation.

[0028] Figure 15A It shows along Figure 14 A partial cross-sectional view of the package taken along the center line XV-XV.

[0029] Figure 15B It shows Figure 15A A partial cross-sectional view of another aspect.

[0030] Figure 16 It shows that according to Figure 11 A partial top view of the encapsulation.

[0031] Figure 17 Various exemplary dimensions of the channels for chip attachment materials according to this disclosure are shown.

[0032] Figure 18 It shows along Figure 14 A partial cross-sectional view of the package taken along the center line XV-XV.

[0033] Figure 19 It shows that according to Figure 11 A partial top view of the encapsulation.

[0034] Figure 20 It shows that according to Figure 11 A partial top view of the encapsulation.

[0035] Figure 21 The process of manufacturing a package according to this disclosure is illustrated.

[0036] Figure 22 It shows that according to Figure 1 A top view of an exemplary implementation of the encapsulation.

[0037] Figure 23 yes Figure 22 A magnified schematic diagram of a subset of unit transistors in a transistor amplifier.

[0038] Figure 24 It is along Figure 23 A schematic cross-sectional view taken from the midline XXIV-XXIV.

[0039] Figure 25 A partial top view of the package according to this disclosure is shown. Detailed Implementation

[0040] The aspects of this disclosure, along with their various features and advantageous details, are explained more fully with reference to the non-limiting aspects and examples described and / or illustrated in the accompanying drawings and in detail in the following description. It should be noted that the features shown in the drawings are not necessarily drawn to scale, and features of one aspect may be used in conjunction with other aspects, as those skilled in the art will recognize, even if not explicitly stated herein. Descriptions of well-known components and processing techniques may be omitted to avoid unnecessarily obscuring aspects of this disclosure. The examples used herein are intended only to aid in understanding how this disclosure can be practiced and to further enable those skilled in the art to practice various aspects of this disclosure. Therefore, the examples and aspects herein should not be construed as limiting the scope of this disclosure, which is defined only by the appended claims and applicable law. Furthermore, it should be noted that the same reference numerals denote similar parts in various views of the drawings and in different embodiments disclosed.

[0041] It should be understood that although the terms first, second, etc., can be used to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0042] It should be understood that when an element (such as a layer, region, or substrate) is referred to as being "on" or "extending" to another element, it can be directly on or directly extended to the other element, or intermediate elements may also be present. Conversely, when an element is referred to as being "directly on" or "directly extended" to another element, no intermediate elements are present. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" or "extending" to another element, it can be directly on or directly extended to the other element, or intermediate elements may also be present. Conversely, when an element is referred to as being "directly on" or "directly extended" to another element, no intermediate elements are present. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0043] In this document, relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used to describe the relationship between an element, layer, or region and another element, layer, or region, as shown in the figure. It should be understood that these terms, and those discussed above, are intended to include different orientations of the device other than those shown in the figure.

[0044] The terminology used herein is for descriptive purposes only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” also include the plural forms, unless the context clearly specifies otherwise. It should be further understood that the terms “comprising,” “including,” “containing,” and / or “containing” as used herein specify the presence of the said feature, integer, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0045] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and related art, unless expressly limited herein.

[0046] Various aspects of this disclosure can be used for low-cost packaging utilizing silver-sintered chip attachment materials. The material may comprise, for example, 75%-90% by weight of tiny silver particles and the remainder of volatile organic compounds. The material can be dispensed via needle application, screen printing, inkjet application, and / or similar methods. The chip attachment material can provide a high thermal conductivity path, dissipating high power through the material and also providing strong mechanical bonding to the package in which the chip is attached. Once the material is dispensed, screen-printed, and / or similarly applied to a support, such as a lead frame, base, and / or the like, and the chip is placed on the material, it is subsequently cured and hardened. During the curing of such chip attachment materials made of metal particles and volatile organic compounds (e.g., plastics, polymers, or resins), volatile organic compounds are released, and bubbles may be generated, which may freeze within the chip attachment material as it hardens.

[0047] For high-power dissipation applications on large-area semiconductor chips (such as group III nitride-based microwave monolithic integrated circuits or large-area group III nitride-based GaN HEMTs), this disclosure provides various configurations and processes to ensure at least a reduction in voids formed during curing or attachment processes, voids located below the transistor portions of the semiconductor chip and preventing heat transfer from the transistors. The location of the generated gases is partially random, and since the sintering material is typically viscous, this disclosure utilizes embodiments to encourage bubbles to “escape” to the material edges before the material is fully hardened. Generally, the larger the semiconductor chip, such as a typically large MMIC, the more advantageous various aspects of this disclosure become in reducing and / or eliminating voids that may be present in the central region of the semiconductor chip, which may be a critical active transistor region.

[0048] In some embodiments, the chip attachment material comprises metal particles in an organic material, such as a sintered chip attachment material. In some embodiments, the sintered chip attachment material is a silver-sintered chip or a copper-sintered chip attachment material. This material may comprise tiny silver particles that make up the majority of the volume, with the remainder being volatile organic compounds. The material can be dispensed via needle application, screen printing, inkjet application, and / or similar methods. The chip attachment material provides a high thermal conductivity path, both for dissipating high power through the chip attachment material and for strong mechanical bonding to the package in which the chip is attached.

[0049] Once the chip attachment material is dispensed or screen-printed onto the substrate or lead frame, and the chip is placed onto the chip attachment material, it is subsequently cured and hardened. During the curing process, volatile organic compounds (VOCs) from the chip attachment material are released. Specifically, the VOCs generate small bubbles whose shapes are frozen within the chip attachment material as it hardens. For high-power dissipation applications on large-area integrated circuits, such as monolithic integrated circuits, monolithic microwave integrated circuits (MMICs), multi-cell transistor integrated circuits, integrated circuits with field-effect transistor (FET) arrays, multi-transistor integrated circuits, multi-circuit integrated circuits, multi-cell integrated circuits, multi-region integrated circuits, multi-active-region integrated circuits, compound semiconductor devices, high-power compound semiconductor devices, high-frequency compound semiconductor devices, and / or similar applications, it is important that the voids formed during curing do not form beneath the active portions of the integrated circuit (such as transistor portions). Similarly, for discrete devices, discrete transistors, large form factor discrete transistors, large form factor discrete devices, multi-region discrete devices, and / or similar devices, it is important that voids formed during curing do not form beneath the active portions of the discrete device (such as transistor portions). This is because voids suppress heat transfer from the active regions (such as the regions where transistors are implemented). Typically, the location of the generated gases is partially random, and because the sintering material is usually very viscous, during curing, the smallest voids aggregate or void bubbles “escape” to the edges of the chip material before it is fully hardened. Generally, the larger the integrated circuit, the higher the density of voids. Furthermore, a higher density of voids can be found in the central region of the integrated circuit. Such voids can be identified using X-rays.

[0050] In various aspects, this disclosure relates to an intentionally constructed channel, for example, constructed using a screen-printed stencil, which will allow venting voids to escape in a region near, but not directly below, the active region (such as an active transistor). It is noteworthy that sintered materials, such as silver sintered materials, possess properties entirely different from conventional solders. Therefore, the application of the channelization void reduction techniques described in this disclosure using sintered chip attachment materials provides unexpected results in terms of improved cooling and / or robustness. Furthermore, the application of the channelization void reduction techniques described in this disclosure to GaN-based HEMTs and MMICs using sintered chip attachment materials provides unexpected results in terms of improved cooling and / or robustness. Furthermore, applying the channelization void reduction techniques described in this disclosure to discrete devices, discrete transistors, large form factor discrete transistors, large form factor discrete devices, multi-region discrete devices, and / or similar devices using sintered chip attachment materials can provide unexpected results in improving cooling and / or robustness. In particular, the applicant has tested many different void reduction methods and found that the disclosed channelization method demonstrates and provides the best results.

[0051] In industry, silver-sintered chip attachment materials are primarily used to connect discrete transistors. Typically, discrete transistors do not have the same voiding issues because they have long, thin form factors, e.g., paths less than 0.6 mm, which generally allows any voids to escape to the free edge. As the industry migrates to larger chips with higher power levels and higher integration, and especially to more MMIC-based implementations, unavoidable outgassing leading to chip attachment failure has become a greater problem. One approach to this problem is to perform X-ray inspection on each device during production as a “screening” procedure, discarding devices with noticeable voids beneath the active transistor region. Using the technology disclosed herein, voids beneath the active transistor region can be reduced to near zero, eliminating the need for “screening.” Therefore, the technology described in this disclosure offers the advantage of increased yield, in addition to its supportive applications for current and future low-cost, high-power GaN MMIC-based solutions. Furthermore, the disclosed technology adds little to no additional processing or screening steps during production. While clearly advantageous in cases of typically large MMICs, the present invention can also provide improved chip attachment for discrete transistors, such as group III nitride-based HEMTs and their packages. Specifically, the present invention can also provide improved chip attachment discrete devices, discrete transistors, large form factor discrete transistors, large form factor discrete devices, multi-region discrete devices, and / or the like.

[0052] This technology has many potential embodiments. In this regard, this disclosure describes processes and devices using silver-sintered chip attachment materials. However, the disclosed processes and devices can also be applied to future chip attachment materials, such as copper-sintered materials currently under development. Furthermore, this disclosure proposes many potential channel locations. However, this disclosure is not limited to these potential locations, and any number of potential embodiments can be considered to determine where channels can be laid and / or positioned. In certain aspects of using monolithic integrated circuits (e.g., MMICs), there may be elongated portions of active regions (e.g., transistor regions) and numerous matching components (e.g., resistors, capacitors, inductors, and / or the like), collectively referred to as passive regions. In certain aspects, this disclosure contemplates arranging long, thin channels beneath passive regions near active regions. In some aspects of this disclosure, a single channel may be arranged on one side of an active region, channels may be arranged on both sides of an active region, and / or the like. In various aspects of this disclosure, channels need not be straight. Specifically, channels may be angled, curved, and / or similar to provide targeted void reduction and avoid sensitive areas.

[0053] Furthermore, this disclosure considers the use of screen printing to apply chip attachment materials to form channels. However, chip attachment materials with channels can be used with other chip attachment application methods, such as pin distribution, jet distribution, etc. The applicant has implemented the disclosed process and devices and has discovered many beneficial applications. For example, the disclosed process and devices have been implemented using sintered chip attachment materials on GaN on SiC (silicon carbide). However, it is believed that similar beneficial applications can be achieved with sintered chip attachment materials for GaN on Si, LDMOS (laterally diffused metal oxide semiconductor), and / or the like. Specifically, the applicant notes that high-power applications, in particular, can benefit from the disclosed process. For example, the applicant considers utilizing the process of this disclosure using MMIC or any other disclosed device type manufactured using the above-described technology. Furthermore, the applicant notes that custom templates for screen printing sintered chip attachment materials, containing venting channels for various applications such as MMIC chip attachment, are very inexpensive.

[0054] Applications of this disclosure may relate to sintered chip bonding materials, such as sintered silver, sintered copper, and / or the like. It is anticipated that the generation of gas voids is virtually impossible to eliminate. In this regard, this disclosure provides processes that allow escape paths or predefined accumulation regions for these voids to prevent their formation and sealing beneath thermally active regions, such as transistor regions of MMIC chips, multi-cell transistor integrated circuit chips, chips of integrated circuits with field-effect transistor (FET) arrays, chips of multi-transistor integrated circuits, chips of multi-circuit integrated circuits, chips of multi-cell integrated circuits, chips of multi-region integrated circuits, chips of multi-active-region integrated circuits, compound semiconductor devices, high-power compound semiconductor devices, high-frequency compound semiconductor devices, and / or the like. Furthermore, this disclosure can also be applied to discrete devices, discrete transistors, large form factor discrete transistors, large form factor discrete devices, multi-region discrete devices, and / or the like. However, the disclosed processes offer particular benefits in chip bonding of integrated circuits (such as MMICs) because they utilize a larger area and incorporate a significant amount of passive regions.

[0055] Figure 1 A perspective view of the package according to this disclosure is shown.

[0056] Figure 2 It shows that according to Figure 1 A partial top view of the encapsulation.

[0057] Figure 3A It shows along Figure 2 A partial cross-sectional view of the package taken from line III-III.

[0058] Specifically, Figure 1 , Figure 2 and Figure 3A An exemplary embodiment of package 100 is shown, which may include any one or more features, components, arrangements, etc. described herein. Specifically, Figure 1 , Figure 2 and Figure 3A Package 100, and / or the like, as described herein, can be implemented as a power package, power amplifier package, microwave power package, microwave power amplifier package, radio frequency (RF) package, RF amplifier package, RF power amplifier package, and RF power transistor package. Reference Figure 1 Package 100 may include one or more input / output pins 134.

[0059] refer to Figure 2 and Figure 3A Package 100 may include a semiconductor chip 200 having one or more active regions 400. In this respect, Figure 2 and Figure 3AThe package 100 shown illustrates two active regions out of one or more active regions 400. However, the package 100 may include any number of one or more active regions 400. The semiconductor chip 200 may be coupled to one or more input / output pins 134 via one or more interconnects 120, one or more interconnects 190, and / or other connections.

[0060] One or more interconnects 120 and / or one or more interconnects 190 may utilize one or more wires, leads, through-holes, edge plates, circuit traces, tracks, ball bonding, wedge bonding, flexible bonding, strip bonding, metal clip attachments, and / or similar methods. In one aspect, one or more interconnects 120 and / or one or more interconnects 190 may use the same type of connection. In another aspect, one or more interconnects 120 and / or one or more interconnects 190 may utilize different types of connections.

[0061] One or more interconnect portions 120 and / or one or more interconnect portions 190 may comprise various metallic materials, including one or more of aluminum, copper, silver, gold, and / or the like. In one aspect, one or more interconnect portions 120 and / or one or more interconnect portions 190 may use the same type of metal. In another aspect, one or more interconnect portions 120 and / or one or more interconnect portions 190 may use different types of metal.

[0062] One or more interconnects 120 and / or one or more interconnects 190 may be connected by adhesives, soldering, sintering, eutectic bonding, thermoforming, ultrasonic bonding / welding, clamping assemblies and / or the like described herein. In one aspect, the connection may use the same type of connection. In another aspect, the connection may utilize different types of connections.

[0063] One or more active regions 400 can be any region within the semiconductor chip 200 that generates heat and / or can benefit from heat flow, heat transfer, cooling, and / or the like. One or more active regions 400 can be regions containing one or more transistors, regions containing one or more transistor amplifiers, regions containing one or more transformers, regions containing one or more voltage regulators, regions containing one or more devices that can benefit from lower temperature operation, regions containing one or more semiconductor devices, and / or combinations thereof.

[0064] One or more active regions 400 can be any region where one or more semiconductor devices are located. One or more semiconductor devices can be wide-bandgap semiconductor devices, ultra-wide-bandgap devices, GaN-based devices, GaN-on-SiC devices, GaN-on-Si devices, metal-semiconductor field-effect transistors (MESFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), bipolar junction transistors (BJTs), laterally diffused metal-oxide-semiconductor (LDMOS), insulated-gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), wide-bandgap (WBG) semiconductors, field-effect transistors (FETs), and the like, and / or combinations thereof.

[0065] One or more semiconductor devices can implement amplifiers, radar amplifiers, radar components, microwave radar amplifiers, power modules, gate drivers, and components (such as general broadband components, telecommunications components, L-band components, S-band components, X-band components, C-band components, Ku-band components, satellite communication components, Doherty configurations, and / or the like). The L-band is the Institute of Electrical and Electronics Engineers' (IEEE) designation of the radio spectrum from 1 to 2 GHz. The S-band is the IEEE designation of a portion of the microwave spectrum covering frequencies from 2 to 4 GHz. The X-band is the designation of a band of frequencies in the microwave radio region, indefinitely defined, from approximately 7.0–11.2 GHz. The C-band is the designation of radio frequencies from 500 to 1000 MHz. The Ku-band is a portion of the electromagnetic spectrum in the microwave frequency range from 12 to 18 GHz.

[0066] Semiconductor chip 200 may further include at least one secondary device region 300. This at least one secondary device region 300 may be defined as a passive region. The at least one secondary device region 300 may be implemented as an RF device as described herein. The at least one secondary device region 300 may implement one or more of the following: resistors, inductors, capacitors, silicon metal oxide (MOS) capacitors, impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic filters, harmonic terminations, couplers, baluns, power combiners, power dividers, radio frequency (RF) circuits, radial stub circuits, transmission line circuits, baseband matching circuits, baseband termination circuits, second harmonic termination circuits, integrated passive devices (IPDs), matching networks and / or the like, and / or combinations thereof, to support various functional technologies as input, output, and / or in-stage functions and / or the like of package 100.

[0067] Package 100 may include support 102. Support 102 may be implemented as a support, surface, package support, package surface, package support surface, metal base, flange, metal flange, heat sink, common source support, common source surface, common source package support, common source package surface, common source package support surface, common source package support surface, common source flange, common source heat sink, lead frame, metal lead frame and / or similar and / or combinations thereof. Support 102 may include metallic material, insulating material, dielectric material and / or similar, and / or combinations thereof. Support 102 may dissipate heat generated by semiconductor chip 200, one or more active regions 400, at least one secondary device region 300 and / or the like, while isolating and protecting semiconductor chip 200, one or more active regions 400 and / or the like from the external environment.

[0068] refer to Figure 3A A semiconductor chip 200 can be mounted on a support 102 using a chip attachment material 124. The chip attachment material 124 may include one or more channels 122. Specifically, the one or more channels 122 may be vertically positioned below one or more active regions 400 along the y-axis, but not directly below one or both active regions 400. In other words, the one or more channels 122 may be vertically positioned below one or more active regions 400 along the y-axis and offset from the active regions 400 along the x-axis, as further described herein. In one or more aspects, the chip attachment material 124 may not form an electrical connection with the semiconductor chip 200. More specifically, the chip attachment material 124 may be specifically designed to attach the semiconductor chip 200 to the support 102. Therefore, in this aspect, the bottom of the semiconductor chip 200 has no electrical contact. In one or more aspects, the chip attachment material 124 may form a single electrical connection with the semiconductor chip 200. More specifically, the chip attachment material 124 can be used for a single electrical connection between the semiconductor chip 200 and the support 102, so that a single electrical connection can be formed on the bottom of the semiconductor chip 200 in this respect.

[0069] One or more channels 122 may be disposed below at least one secondary device region 300. In a particular aspect, one or more channels 122 may be disposed directly below at least one secondary device region 300 along the y-axis. For example, one or more channels 122 may be disposed below or directly below at least one secondary device region 300, flux pads, and / or the like along the y-axis and x-axis.

[0070] The chip attachment material 124 may include one or more metallic materials and one or more non-metallic materials. The one or more metallic materials may include silver, copper, gold, tin, lead, and / or combinations thereof. The one or more metallic materials may include powdered metallic materials configured for sintering. In one aspect, the chip attachment material 124 may include 75%-90% by volumetric weight of metal particles as metallic materials, and the remainder may be non-metallic materials. In one aspect, the chip attachment material 124 includes sintered materials. In one aspect, the chip attachment material 124 includes at least one of silver sintered and copper sintered materials.

[0071] One or more non-metallic materials may include organic materials, volatile organic materials, epoxy-based materials, epoxy resins, adhesive materials, gas-generating materials, and / or combinations thereof. In one aspect, the chip attachment material 124 may include silver, silver configured for sintering, silver sintered materials, and / or combinations thereof. In one aspect, the chip attachment material 124 may include 75%-90% by volumetric weight of silver particles as a metallic material, with the remainder being non-metallic materials. In another aspect, the chip attachment material 124 may include 75%-90% by volumetric weight of silver particles as a metallic material, with the remaining portion being volatile organic compounds as non-metallic materials.

[0072] Furthermore, within the package 100, the semiconductor chip 200 can be arranged on the support member 102. (See reference) Figure 1 Package 100 may include an outer mold 130 and / or the like. The outer mold 130 may generally surround the semiconductor chip 200, one or more active regions 400, and / or other components of package 100. The outer mold 130 may be formed of plastic materials, molding compounds, synthetic materials, plastic polymer compounds, and / or combinations thereof, and may be injection molded or compression molded around the support 102 and the semiconductor chip 200 to provide protection relative to the external environment.

[0073] Alternatively, package 100 may be implemented as including an open cavity configuration suitable for semiconductor chip 200. Specifically, the open cavity configuration may utilize an open cavity package design. In some aspects, the open cavity configuration may include a cover or other housing for protecting interconnects, circuit components, semiconductor chip 200, etc. Package 100 may include a ceramic body, a cover, and / or one or more metal contacts.

[0074] Package 100 may be implemented as an MMIC RF package and may house an RF device. The RF device may be configured and implemented at least partially in at least one secondary device region 300. Specifically, the RF device may be configured and implemented within at least one primary device region 300 and may be implemented as one or more of the following: resistors, inductors, capacitors, metal-oxide-semiconductor (MOS) capacitors, impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic filters, harmonic terminations, couplers, baluns, power combiners, power dividers, radio frequency (RF) circuits, radial stub circuits, transmission line circuits, baseband matching circuits, baseband termination circuits, second harmonic termination circuits, integrated passive devices (IPDs), matching networks, etc., to support various functional technologies as inputs, outputs, and / or in-stage functions of package 100. Package 100, implemented as an MMIC package, may further include one or more active regions 400. The package 100, as an implementation of the MMIC package, may further implement one or more active regions 400 and at least one secondary device region 300, the secondary device region 300 being configured to include, connect to, and support radar transmitters, radar transmitter functions, microwave radar transmitters, microwave radar transmitter functions, radar receivers, radar receiver functions, microwave radar receivers, microwave radar receiver functions, etc.

[0075] Package 100 can be implemented as a power package, power amplifier package, microwave power package, microwave power amplifier package, radio frequency (RF) package, RF amplifier package, RF power amplifier package, and RF power transistor package, RF power amplifier transistor package, etc., and at least one secondary device region 300 and one or more active regions 400 can be implemented as RF devices, and can include, connect to, support, etc., transmitters, transmitter functions, receivers, receiver functions, transceivers, transceiver functions, matching network functions, harmonic termination circuits, integrated passive devices (IPDs), etc., and / or combinations thereof, as described herein. At least one secondary device region 300 and / or one or more active regions 400 implemented as RF devices can be configured, as described herein, to support transmitting radio waves and modulating the radio waves to carry data having permissible transmitter power output, harmonics, band edge requirements, etc., and / or combinations thereof. At least one secondary device region 300 and one or more active regions 400 implemented as RF devices can be configured to support receiving radio waves and demodulating radio waves. At least one secondary device region 300, implemented as a radio frequency device, can be configured to support transmitting radio waves and modulating the radio waves to carry data with permissible transmitter power output, harmonics, and / or band edge requirements; and can be configured to support receiving radio waves and demodulating the radio waves.

[0076] Figure 3B It shows Figure 3A Another aspect of the partial cross-section.

[0077] Specifically, Figure 3B An embodiment of a package 100 implementing multiple semiconductor chips 200 is shown. Each of the aspects, configurations, components, processes, etc., described herein can be combined. Figure 3B This will be implemented using the methods described above. Further reference is available. Figure 3B One or more of the semiconductor chips 200 may be configured to be implemented as at least one secondary device region 300; and one or more of the semiconductor chips 200 may be configured to be implemented as an active region 400. In a particular aspect, one or more of the plurality of semiconductor chips 200 may be implemented as discrete devices. In a particular aspect, each of the plurality of semiconductor chips 200 may be implemented as a discrete device.

[0078] refer to Figure 3B Multiple semiconductor chips 200 can be mounted on the support 102 using chip attachment material 124. Chip attachment material 124 may include one or more channels 122. Specifically, one or more channels 122 may be vertically below the semiconductor chip 200 implemented as one or more active regions 400 along the y-axis; in other words, the one or more channels 122 may be vertically below the semiconductor chip 200 implemented as one or more active regions 400 along the y-axis and offset from the active region 400 along the x-axis, as further described herein.

[0079] Further reference Figure 3B One or more channels 122 may be disposed beneath a semiconductor chip 200 implemented as at least one secondary device region 300. In a particular aspect, one or more channels 122 may be disposed directly beneath a semiconductor chip 200 implemented as at least one secondary device region 300 along the y-axis. For example, one or more channels 122 may be disposed beneath or directly beneath a semiconductor chip 200 implemented as at least one secondary device region 300, flux pads, etc., along both the y-axis and x-axis.

[0080] Figure 4 It shows Figure 3A A partial view.

[0081] Figure 5 An exemplary layout of a chip attachment material according to this disclosure is shown.

[0082] Specifically, Figure 4 It shows Figure 3A Detailed views of one or more channels 122 shown herein are applicable to any aspect described herein. References Figure 4 One or more channels 122 may be defined by the lower surface 280 of the semiconductor chip 200 and the upper surface 180 of the support 102. In one aspect, as Figure 4 As shown, the lower surface 280 of the semiconductor chip 200 can extend approximately parallel to the X-axis; the upper surface 180 of the support 102 can extend approximately parallel to the X-axis, as... Figure 4 As shown; and one or more side edges 128 may extend approximately parallel to the Y-axis, as... Figure 4 As shown. In this respect, the generally parallelism can be defined as 0°-15°, 0°-2°, 2°-4°, 4°-6°, 6°-8°, 8°-10°, 10°-12°, or 12°-15°. In other respects, one or more channels 122 may be constructed and defined by other components of the package 100.

[0083] However, during the manufacturing process of package 100, one or more channels 122 may change shape, such as bulging or moving. Therefore, the various embodiments of one or more channels 122 described herein may differ slightly in the manufacturing process.

[0084] Figure 5 An exemplary arrangement of chip attachment material 124 disposed on support 102 is shown. Specifically, chip attachment material 124 may include one or more channels 122. The one or more channels 122 may be vertically located along the y-axis in one or more active regions 400. Figure 5 Below (shown by the dashed line), but not directly below one or more active regions 400. In other words, one or more channels 122 may be vertically located below one or more active regions 400 along the y-axis and offset relative to the active regions 400 along the x-axis.

[0085] One or more channels 122 may be disposed below at least one secondary device region 300. In a particular aspect, one or more channels 122 may be disposed directly below at least one secondary device region 300 along the y-axis. For example, one or more channels 122 may be disposed below or directly below at least one secondary device region 300, flux pads, etc., along both the y-axis and x-axis.

[0086] One or more channels 122 may include one or more vents 126 and one or more side edges 128. One or more channels 122 may be located in the x-axis and z-axis plane parallel to the upper surface 180 of the support member 102, and may be rectangular, polygonal, circular, free-form continuous, irregular, discontinuous, etc., and / or combinations thereof.

[0087] One or more channels 122 can cut the chip attachment material 124 in the x-axis and z-axis planes parallel to the upper surface 180 of the support 102. For example... Figure 5 As shown, two of the one or more channels 122 cut the chip attachment material 124 into three distinct portions. Package 100 may include any number of one or more channels 122 and any number of portions of chip attachment material 124.

[0088] One or more side edges 128 of one or more channels 122 may form a surface of the chip attachment material 124, which allows gases generated during the curing of the chip attachment material 124 to be released from the chip attachment material 124. Specifically, one or more channels 122 may utilize one or more side edges 128 of the chip attachment material 124 to form a surface that allows gases generated during curing to be released from the chip attachment material 124 below the active region 400. More specifically, as... Figure 5 As shown by the arrows partially located in the chip attachment material 124, gases generated during curing below the active region 400 can travel toward and enter one or more side edges 128 of one or more channels 122, by providing locations where gases generated during curing can escape from below the active region 400 and enter one or more channels 122. Therefore, the one or more channels 122 coupled with one or more side edges 128, by providing locations where gases generated during curing can escape from below the active region 400 and enter one or more channels 122, help reduce the formation of voids below the active region 400.

[0089] Subsequently, the gas generated below the active region 400 during curing can enter one or more channels 122. Once the gas enters one or more channels 122, it can travel along one or more channels 122 and be discharged from one or more channels 122 through the exhaust port 126, such as... Figure 5 As shown in the diagram, as indicated by the arrows located within one or more channels 122.

[0090] In this regard, one or more channels 122 allow gases generated below the active region 400 during curing to be released and reduce void formation below the active region 400. Therefore, one or more channels 122 increase the cooling capacity of the support 102 below the active region 400 by increasing the ability of heat generated by the active region 400 to be transferred from the semiconductor chip 200 to the support 102. Furthermore, implementing one or more channels 122 within the chip attachment material 124 may be more advantageous in addressing various temperature limits more likely to occur in high-power applications of the package 100. In this regard, it is highly beneficial to keep the active region 400 within 5°C of the desired operating temperature range to ensure higher performance, higher reliability, etc.

[0091] Further reference Figure 5 One or more channels 122 may have a generally straight and / or linear configuration 122-1. The generally straight and / or linear configuration 122-1 may include a first exhaust port 126 at one end and a second exhaust port 126 at the other end. However, typically the straight and / or linear configuration 122-1 may include only one exhaust port 126 at one end.

[0092] One or more channels 122 may have multiple connecting segments, which are typically straight and / or linear structures 122-2. Each connecting segment can be connected at any angle. Angles may include 1°-359°, 1°-40°, 40°-80°, 80°-120°, 120°-160°, 160°-200°, 200°-240°, 240°-280°, 280°-320°, or 320°-359°. Figure 5 As shown, the multiple connecting segments of the typically straight and / or linear structure 122-2 are typically connected at 90° angles. Furthermore, the multiple connecting segments of the typically straight and / or linear structure 122-2 may include a first exhaust port 126 at one end and a second exhaust port 126 at the other end. However, the multiple connecting segments of the typically straight and / or linear structure 122-2 may include only one exhaust port 126 at one end.

[0093] One or more channels 122 can increase the robustness of the chip attachment material 124, increase its lifetime, and / or provide other beneficial improvements. In this regard, it has been found that large areas of the chip attachment region are affected by various failure mechanisms, such as delamination and cracking. These failure mechanisms may be the result of thermal expansion of materials associated with the chip attachment material 124, the semiconductor chip 200, the support 102, etc. In this respect, the materials associated with the chip attachment material 124, the semiconductor chip 200, the support 102, etc., can be different materials and can have different coefficients of thermal expansion. Therefore, when the semiconductor chip 200 operates at various temperature limits, different materials with different coefficients of thermal expansion may cause different expansions. This increases the likelihood that the package 100, the semiconductor chip 200, the chip attachment material 124, etc., will experience failure mechanisms.

[0094] One or more channels 122 can reduce the size of a large chip attachment area. Specifically, one or more channels 122 can divide a large chip attachment area into one or more smaller chip attachment areas. Specifically, as... Figure 5 As shown, two of the one or more channels 122 divide the chip attachment material 124 into three distinct smaller portions. Therefore, when the semiconductor chip 200 operates at various temperature limits, different materials that may have different coefficients of thermal expansion leading to different thermal expansion can have reduced expansion due to the smaller portions of the chip attachment material 124. This reduces the likelihood that the package 100 will experience a failure mechanism.

[0095] The chip attachment material 124 can be made using screen printing, preforming, needle dispensing system, inkjet dispensing system, masking, photolithography, printing to transparent film, photomask process combined with etching, photosensitive process, laser resist ablation process, milling process, laser etching process, direct metal printing process, combinations thereof and / or similar processes.

[0096] In one aspect, the chip attachment material 124 can be applied using a screen printing process. In this regard, a stencil can be formed having openings consistent with various shapes of the chip attachment material 124; and the stencil can be formed with portions that do not allow the application of chip attachment material 124 at different locations corresponding to one or more channels 122. Subsequently, the stencil can be applied to the upper surface 180 of the support 102, and the chip attachment material 124 can be applied to the stencil. A squeegee can be applied to the stencil to force the chip attachment material 124 through the stencil onto the upper surface 180 of the support 102 to form the chip attachment material 124 and one or more channels 122.

[0097] In one aspect, the chip attachment material 124 can be formed using a preforming process. In this regard, the preform can be formed in accordance with various shaping of the chip attachment material 124; and the preform can be formed to have portions where the absence of chip attachment material 124 coincides with different locations of one or more channels 122. Subsequently, the preform can be applied to the upper surface 180 of the support 102 to form the chip attachment material 124 and one or more channels 122.

[0098] In one aspect, a pin dispensing system can be used to apply chip attachment material 124. In this respect, the pin dispensing system can be configured and operated to apply chip attachment material 124 to the upper surface 180 of the support 102; and the pin dispensing system can be configured and operated to not apply chip attachment material 124 to the upper surface 180 of the support 102 at different locations corresponding to one or more channels 122.

[0099] In one aspect, a chip attachment material 124 can be applied using an inkjet dispensing system. In this respect, the inkjet dispensing system can be configured and operated to apply the chip attachment material 124 to the upper surface 180 of the support 102; and the inkjet dispensing system can be configured and operated to not apply the chip attachment material 124 to the upper surface 180 of the support 102 at different locations corresponding to one or more channels 122.

[0100] In one aspect, a mask process can be used to apply chip attachment material 124. In this respect, a mask can be formed having openings that correspond to various shapes of the chip attachment material 124; and the mask can be formed with portions that do not allow the application of chip attachment material 124 that correspond to different locations of one or more channels 122.

[0101] Figure 6 Various exemplary dimensions of the channels for chip attachment materials according to this disclosure are shown.

[0102] Specifically, the position of one or more channels 122 relative to the active region 400 can be optimized to ensure maximum heat transfer from the active region 400 to the support 102. Furthermore, the position of one or more channels 122 relative to the active region 400 can be optimized to ensure minimal voids and / or venting of gas generated below the active region 400 during curing. More specifically, the width of one or more channels 122 is shown and defined as a distance D1 along the x-axis; the distance from the active region 400 to one or more channels 122 is defined as a distance D2 along the x-axis; the length of the entire portion of the chip attachment material 124 is defined as a distance D3 along the x-axis; and the width of the active region 400 is defined as a distance D4 along the x-axis.

[0103] For example, distance D1 can be related to distance D2 as a relationship between the width of one or more channels 122 and the distance from one or more side edges 128 of one or more channels 122 to the edge of the active region 400. Distance D1 can be 20%–300% of distance D2, 20%–60% of distance D2, 60%–100% of distance D2, 100%–140% of distance D2, 140%–180% of distance D2, 180%–220% of distance D2, 220%–260% of distance D2, or 260%–300% of distance D2.

[0104] For example, distance D1 can be related to distance D4 as a relationship between the width of one or more channels 122 and the width of the active region 400. Distance D1 can be 20%–300% of distance D4, 20%–60% of distance D4, 60%–100% of distance D4, 100%–140% of distance D4, 140%–180% of distance D4, 180%–220% of distance D4, 220%–260% of distance D4, or 260%–300% of distance D4.

[0105] For example, distance D1 can be related to distance D3 as a relationship between the width of one or more channels 122 and the width of the chip attachment material 124. Distance D1 can be 2%-40%, 2%-10%, 10%-20%, 20%-30%, or 30%-40% of distance D3.

[0106] For the configuration of one or more channels 122, active regions 400, etc. formed along the z-axis, various distances D1, D2, D3, and D4 can also be defined along the z-axis.

[0107] Figure 7 An exemplary layout of a chip attachment material according to this disclosure is shown.

[0108] Specifically, Figure 7 Alternative embodiments of one or more channels 122 forming multiple portions of chip attachment material 124 are shown. Each of the aspects, configurations, components, processes, etc. described herein can be combined. Figure 7 Layout and implementation. For example... Figure 7 As shown, various embodiments of one or more channels 122 can be connected to form various portions of the chip attachment material 124, such as Figure 7As shown in the diagram. In this respect, one or more channels may be connected to form an intersection 170. In one aspect, one or more channels 122 include a plurality of channels. In one aspect, one or more channels 122 include at least two intersecting channels. In one aspect, one or more channels 122 include more than two intersecting channels. In one aspect, one or more channels 122 may form a channel network.

[0109] Figure 8 An exemplary layout of a chip attachment material according to this disclosure is shown.

[0110] Specifically, Figure 8 Alternative embodiments of one or more channels 122 forming multiple portions of chip attachment material 124 are shown. Each of the aspects, configurations, components, processes, etc. described herein can be combined. Figure 8 Layout and implementation. For example... Figure 8 As shown, various embodiments of one or more channels 122 can be arranged on both sides 172 of one or more active regions 400 to form as shown in the figure. Figure 8 The chip attachment material 124 shown is divided into various portions. Furthermore, Figure 8 One or more channels 122 with curved structures 122-3 are shown.

[0111] Figure 9 An exemplary layout of a chip attachment material according to this disclosure is shown.

[0112] Specifically, Figure 9 Alternative embodiments of one or more channels 122 forming multiple portions of chip attachment material 124 are shown. Each of the aspects, configurations, components, processes, etc. described herein can be combined. Figure 9 Layout and implementation. For example... Figure 9 As shown, one or more channels 122 can be connected in various embodiments to form, as shown in the figure. Figure 9 The chip attachment material 124 shown is divided into various portions. Furthermore, Figure 9 One or more channels 122 are shown having a configuration 122-4 that is angular to both the z-axis and x-axis. In one aspect, the one or more channels 122 include a plurality of channels. In one aspect, the one or more channels 122 include at least two intersecting channels. In one aspect, the one or more channels 122 include more than two intersecting channels. In one aspect, the one or more channels 122 may form a channel network.

[0113] Figure 10 An exemplary layout of a chip attachment material according to this disclosure is shown.

[0114] Specifically, Figure 10Alternative embodiments of one or more channels 122 forming multiple portions of chip attachment material 124 are shown. Each of the aspects, configurations, components, processes, etc. described herein can be combined. Figure 10 Layout and implementation. For example... Figure 10 As shown, one or more channels 122 can be connected in various embodiments to form, as shown in the figure. Figure 10 The chip attachment material 124 shown is divided into various portions. Furthermore, Figure 10 An embodiment is shown in which one or more channels 122 defining a chip attachment material 124 are formed without one or more active regions 400. For example, one or more channels 122 defining a chip attachment material 124 are formed without implementing one or more active regions 400 in adjacent portions of the chip attachment material 124. Furthermore, a larger portion of the chip attachment material 124 may have some advantages. In this respect, the thickness of the chip attachment material 124 can vary in specific areas during manufacturing, and a larger area of ​​the chip attachment material 124 can allow for a degree of self-leveling during the curing process to provide a more uniform thickness and / or a more uniform adhesion. In one aspect, the one or more channels 122 include a plurality of channels. In one aspect, the one or more channels 122 include at least two intersecting channels. In one aspect, the one or more channels 122 include more than two intersecting channels. In one aspect, the one or more channels 122 may form a channel mesh.

[0115] Figures 5 to 10 Each of the various configurations of one or more channels 122 and chip attachment material 124 shown herein can be used in combination or selectively in the package 100 described herein. More specifically, the package 100 can utilize any number or any configuration of one or more channels 122 shown and described herein; and the package 100 can utilize any number or any configuration of chip attachment material 124 as shown and described herein.

[0116] Figure 11 It shows that according to Figure 1 A partial top view of the encapsulation.

[0117] Specifically, Figure 11 An exemplary embodiment of encapsulation 100, which may include any one or more features, components, arrangements, etc., described herein, is shown. More specifically, for ease of understanding, Figure 11 Package 100 is shown, but the components of package 100 are not shown. (Reference) Figure 11Package 100 may include a support member 102. In one aspect, the support member 102 may be implemented as a paddle. The paddle-shaped support member 102 may include a metallic material, such as copper and / or the like. Furthermore, the paddle-shaped support member 102 may include a metal plating material. The metal plating material may include any metallic material, such as silver. In one aspect, the support member 102 is implemented as a paddle and includes copper and a metal plating material including silver. The support member 102 may be connected to and / or supported by a lead frame 192. The lead frame 192 may include or be connected to one or more input / output pins 134.

[0118] The support member 102 may also be implemented as a surface, a package support, a package surface, a package support surface, a metal base, a flange, a metal flange, a heat sink, a common source support, a common source surface, a common source package support, a common source package surface, a common source package support surface, a common source flange, a common source heat sink, a lead frame, a metal lead frame, etc., and / or combinations thereof. The support member 102 may include metallic materials, insulating materials, dielectric materials, etc., and / or combinations thereof.

[0119] Figure 12 It shows that according to Figure 11 A partial top view of the encapsulation.

[0120] Specifically, for ease of understanding, Figure 12 Package 100 is shown, but the various components of package 100 are not shown. Further reference. Figure 12 The illustrated package 100 has an exemplary arrangement of chip attachment material 124 disposed on a support 102. The chip attachment material 124 may be located at multiple specific locations on the support 102, as further described herein. The arrangement of the chip attachment material 124 may form and / or include one or more channels 122. In one aspect, the chip attachment material 124 may form a mesh of one or more channels 122. Note that the configuration shown in the figures includes multiple portions of the chip attachment material 124 and one or more channels 122, and for ease of illustration, each portion may not include reference numerals.

[0121] In one aspect, the chip attachment material 124 may form a mesh of one or more channels 122 and may be arranged in a square and / or rectangular shape. However, the chip attachment material 124 may be configured in any shape. Figure 12The dimensions, arrangement, location, quantity, etc., of the chip attachment material 124 shown elsewhere in this disclosure are merely exemplary. Other configurations of the chip attachment material 124 are also contemplated. In one aspect, one or more channels 122 include a plurality of channels. In one aspect, one or more channels 122 include at least two intersecting channels. In one aspect, one or more channels 122 include more than two intersecting channels. In one aspect, one or more channels 122 may form a channel mesh.

[0122] Figure 13 It shows that according to Figure 11 A partial top view of the encapsulation.

[0123] Specifically, for ease of understanding, Figure 13 Package 100 is shown, but the components of package 100 are not shown. (Reference) Figure 13 Package 100 may include a semiconductor chip 200 having one or more active regions 400. In this respect, Figure 13 The package 100 shown illustrates two of one or more active regions 400. However, the package 100 may contain any number of one or more active regions 400. Furthermore, the semiconductor chip 200 may be attached to the package 100 and the support 102 via chip attachment material 124.

[0124] Figure 14 It shows that according to Figure 13 A partial top view of the encapsulation.

[0125] Specifically, Figure 14 A transparent view of the semiconductor chip 200 in package 100 is shown to illustrate the arrangement of one or more active regions 400 relative to the chip attachment material 124. This arrangement will be discussed in further detail herein.

[0126] Figure 15A It shows along Figure 14 A partial cross-sectional view of the package taken along the center line XV-XV.

[0127] refer to Figure 15AA semiconductor chip 200 can be mounted on a support 102 using chip attachment material 124. The arrangement of the chip attachment material 124 can form a mesh of one or more channels 122 and / or include one or more channels 122. As further described herein, the arrangement and location of the chip attachment material 124 and the one or more channels 122 can be specific to one or more active regions 400. Specifically, the one or more channels 122 can be vertically positioned below the one or more active regions 400 along the y-axis, but not directly below the one or more active regions 400. In other words, the one or more channels 122 can be vertically positioned below the one or more active regions 400 along the y-axis and offset from the active regions 400 along the x-axis.

[0128] One or more channels 122 may be disposed below at least one secondary device region 300. In a particular aspect, one or more channels 122 may be disposed directly below at least one secondary device region 300 along the y-axis. For example, one or more channels 122 may be disposed below or directly below at least one secondary device region 300, flux pads, etc., along both the y-axis and x-axis.

[0129] Figure 15B It shows Figure 15A A partial cross-sectional view of another aspect.

[0130] Specifically, Figure 15B An embodiment of a package 100 implementing multiple semiconductor chips 200 is shown. Each of the aspects, configurations, components, processes, etc. described herein can be combined with Figure 15B This will be implemented using the methods described above. Further reference is available. Figure 15B One or more semiconductor chips 200 may be configured to be implemented as at least one secondary device region 300; and one or more of the semiconductor chips 200 may be configured to be implemented as an active region 400. In a particular aspect, one or more of the plurality of semiconductor chips 100 may be implemented as discrete devices. In a particular aspect, each of the plurality of semiconductor chips 200 may be implemented as a discrete device.

[0131] refer to Figure 15BMultiple semiconductor chips 200 can be mounted on the support 102 using chip attachment material 124. Chip attachment material 124 may include one or more channels 122. Specifically, one or more channels 122 may be vertically below, but not directly below, the semiconductor chips 200 implemented as one or more active regions 400 relative to the y-axis. In other words, one or more channels 122 may be vertically below, along the y-axis, the semiconductor chips 200 implemented as one or more active regions 400, and offset from the active regions 400 along the x-axis, as further described herein.

[0132] Further reference Figure 15B One or more channels 122 may be disposed below a semiconductor chip 200 implemented as at least one secondary device region 300. In a particular aspect, one or more channels 122 may be disposed along the y-axis directly below a semiconductor chip 200 implemented as at least one secondary device region 300. For example, one or more channels 122 may be disposed along both the y-axis and the x-axis below or directly below a semiconductor chip 200 implemented as at least one secondary device region 300, flux pads, etc.

[0133] Figure 16 It shows that according to Figure 11 A partial top view of the encapsulation.

[0134] Specifically, Figure 16 An exemplary arrangement of chip attachment material 124 disposed on support 102 is shown. Specifically, chip attachment material 124 may include one or more channels 122. The one or more channels 122 may be located vertically below one or more active regions 400 along the y-axis. Figure 16 (As shown by the dashed line), but not directly below one or more active regions 400. In other words, one or more channels 122 may be vertically below one or more active regions 400 along the y-axis and offset along the x-axis relative to the active regions 400.

[0135] One or more channels 122 may be disposed below at least one secondary device region 300. In a particular aspect, one or more channels 122 may be disposed directly below at least one secondary device region 300 along the y-axis. For example, one or more channels 122 may be disposed below or directly below at least one secondary device region 300, flux pads, etc., along both the y-axis and x-axis.

[0136] One or more channels 122 may include one or more vents 126 and one or more side edges 128. One or more channels 122 may be located in the x-axis and z-axis plane parallel to the upper surface 180 of the support member 102, and may be rectangular, polygonal, circular, free-form, continuous, discontinuous, etc., and / or combinations thereof.

[0137] One or more channels 122 can cut the chip attachment material 124 in the x-axis and z-axis planes parallel to the upper surface 180 of the support 102. For example... Figure 16 As shown, there are multiple channels 122 that divide the chip attachment material 124 into multiple different portions. Package 100 may include any number of channels 122 and any number of portions of chip attachment material 124.

[0138] One or more side edges 128 of one or more channels 122 may form a surface of the chip attachment material 124, which allows gases generated during the curing of the chip attachment material 124 to be released from the chip attachment material 124. Specifically, one or more channels 122 may utilize one or more side edges 128 of the chip attachment material 124 to form a surface that allows gases generated during curing to be released from the chip attachment material 124 below the active region 400. More specifically, as Figure 16 As shown by the arrows partially located in the chip attachment material 124, gas generated below the active region 400 during curing can travel toward and enter one or more side edges 128 of one or more channels 122. Therefore, the one or more channels 122 coupled with the one or more side edges 128 help reduce void formation below the active region 400 by providing a location where gas generated during curing can escape from below the active region 400 and enter the one or more channels 122.

[0139] Subsequently, the gas generated below the active region 400 during curing can enter one or more channels 122. Once the gas enters the one or more channels 122, it can travel along the one or more channels 122 and be discharged from the one or more channels 122 through the exhaust port 126, as... Figure 16 As shown by the arrows located within one or more channels 122.

[0140] In this regard, one or more channels 122 allow gases generated below the active region 400 during curing to be released and reduce void formation below the active region 400. Therefore, one or more channels 122 increase the cooling capacity of the support 102 below the active region 400 by increasing the ability to transfer heat generated in the active region 400 from the semiconductor chip 200 to the support 102. Furthermore, implementing one or more channels 122 within the chip attachment material 124 is even more advantageous for addressing various temperature limits more likely to occur in high-power applications of the package 100. In this regard, maintaining the active region 400 within 5°C of the desired operating temperature range is highly beneficial for ensuring high performance, high reliability, etc.

[0141] Further reference Figure 16 One or more channels 122 may have a generally straight and / or linear configuration. A generally straight and / or linear configuration may include a first exhaust port 126 at one end and a second exhaust port at the other end. However, a generally straight and / or linear configuration may typically include only one exhaust port 126 at one end.

[0142] One or more channels 122 may have multiple connecting segments, typically straight and / or linearly constructed. Each segment may be connected at any angle. Angles may include 1°-359°, 1°-40°, 40°-80°, 80°-120°, 120°-160°, 160°-200°, 200°-240°, 240°-280°, 280°-320°, or 320°-359°. Figure 16 As shown, multiple connecting segments that are typically straight and / or linearly constructed are usually connected at a 90° angle. Furthermore, multiple connecting segments that are typically straight and / or linearly constructed may include a first exhaust port 126 at one end and a second exhaust port 126 at the other end. However, multiple connecting segments that are typically straight and / or linearly constructed may include only one exhaust port 126 at one end.

[0143] One or more channels 122 can increase the robustness of the chip attachment material 124, increase its lifetime, and / or provide other beneficial improvements. In this regard, it has been found that large areas of the chip attachment region are affected by various failure mechanisms, such as delamination and cracking. These failure mechanisms may be the result of thermal expansion of materials associated with the chip attachment material 124, the semiconductor chip 200, the support 102, etc. In this respect, the materials associated with the chip attachment material 124, the semiconductor chip 200, the support 102, etc., can be different materials and can have different coefficients of thermal expansion. Therefore, when the semiconductor chip 200 operates at various temperature limits, different materials with different coefficients of thermal expansion may cause different expansions. This increases the likelihood that the package 100, the semiconductor chip 200, the chip attachment material 124, etc., will experience failure mechanisms.

[0144] One or more channels 122 can reduce the size of a large chip attachment area. Specifically, one or more channels 122 can divide a large chip attachment area into one or more smaller chip attachment areas. Specifically, as... Figure 16 As shown, there are multiple channels 122 in one or more that cut the chip attachment material 124 into many different smaller portions. Therefore, when the semiconductor chip 200 operates at various temperature limits, it may have different materials with different coefficients of thermal expansion that result in different expansions, and due to the smaller portions of the chip attachment material 124, it may have a reduced amount of expansion. This reduces the likelihood that the package 100 will experience a failure mechanism.

[0145] The chip attachment material 124 can be made using screen printing, preforming, needle dispensing systems, inkjet dispensing systems, masking, photolithography, printing to a transparent film, photomask processes combined with etching, photosensitive processes, laser resist ablation, milling, laser etching, direct metal printing, combinations thereof, and / or similar processes described herein.

[0146] Figure 17 Various exemplary dimensions of the channels for chip attachment materials according to this disclosure are shown.

[0147] Specifically, the position of one or more channels 122 relative to the active region 400 can be optimized to ensure maximum heat transfer from the active region 400 to the support 102. Furthermore, the position of one or more channels 122 relative to the active region 400 can be optimized to ensure minimal voids and / or venting of gas generated below the active region 400 during curing. More specifically, the width of one or more channels 122 is shown and defined as a distance D5 along the x-axis; the distance from the active region 400 to one or more channels 122 is defined as a distance D6 along the x-axis; the length of the entire portion of the chip attachment material 124 is defined as a distance D7 along the x-axis; and the width of the active region 400 is defined as a distance D8 along the x-axis.

[0148] For example, distance D5 can be related to distance D6 as a relationship between the width of one or more channels 122 and the distance from one or more side edges 128 of one or more channels 122 to the edge of the active region 400. Distance D5 can be 20%–300% of distance D6, 20%–60% of distance D6, 60%–100% of distance D6, 100%–140% of distance D6, 140%–180% of distance D6, 180%–220% of distance D6, 220%–260% of distance D6, or 260%–300% of distance D6.

[0149] For example, distance D5 can be related to distance D8 as a relationship between the width of one or more channels 122 and the width of the active region 400. Distance D5 can be 20%–300% of distance D8, 20%–60% of distance D8, 60%–100% of distance D8, 100%–140% of distance D8, 140%–180% of distance D8, 180%–220% of distance D8, 220%–260% of distance D8, or 260%–300% of distance D8.

[0150] For example, distance D5 can be related to distance D7 as a relationship between the width of one or more channels 122 and the width of the chip attachment material 124. Distance D5 can be 2%-40%, 2%-10%, 10%-20%, 20%-30%, or 30%-40% of distance D7.

[0151] For the configuration of one or more channels 122, active regions 400, etc. formed along the z-axis, various distances D5, D6, D7 and D8 can also be defined along the z-axis.

[0152] Figure 18 It shows along Figure 14 A partial cross-sectional view of the package taken along the center line XV-XV.

[0153] Figure 19 It shows that according to Figure 11 A partial top view of the encapsulation.

[0154] refer to Figure 1 The package 100 may include an outer mold 130, etc. The outer mold 130 may be formed of plastic materials, synthetic materials, plastic polymer compounds, etc., and / or combinations thereof, and may be injection molded around the support 102 and the semiconductor chip 200 to provide protection relative to the external environment. The outer mold 130 may generally surround the semiconductor chip 200, one or more active regions 400, and / or other components of the package 100.

[0155] refer to Figure 18 and Figure 19 Some portions of the chip attachment material 124 may extend beyond the semiconductor chip 200 covering the support 102. These portions of the chip attachment material 124 can improve the plastic adhesion between the outer mold 130 of the package 100 and the outer mold of the support 102. Furthermore, these portions of the chip attachment material 124 can avoid selective electroplating of the support 102. Additionally, this structure allows for a common package lead frame for all chip sizes of the semiconductor chips 200 used in the package type.

[0156] In one aspect of implementing chip attachment material 124 that can extend beyond semiconductor chip 200, outer mold 130 can adhere to the chip attachment material 124 and the side edges of semiconductor chip in portion 502. Furthermore, outer mold 130 can adhere to portion 504 on the top surface of semiconductor chip 200. Additionally, outer mold 130 can adhere to the side edges of semiconductor chip 200 in portion 506. Furthermore, outer mold 130 can adhere to the upper surface of one or more chip attachment materials 124 in portion 508 and can extend to a portion of one or more channels 122. In this respect, the composite material can adhere more reliably to one or more channels 122 and chip attachment material 124, thereby reducing failures of package 100. Specifically, outer mold 130 disposed on chip attachment material 124 and / or one or more channels 122 can facilitate adhesion of outer mold 130 to the molding compound of semiconductor chip 200 within package 100. Furthermore, before mounting and / or arranging the outer mold 130 on the semiconductor chip 200, the package 100 can be subjected to a cleaning process, such as a plasma cleaning process. In this regard, the cleaning process can physically modify the chip attachment material 124. Specifically, the cleaning process can create pores or increase the porosity of the chip attachment material 124. This physical modification further promotes the adhesion of the outer mold 130 to the molding compound of the semiconductor chip 200 within the package 100.

[0157] Alternatively, package 100 may be implemented as including an open cavity configuration suitable for semiconductor chip 200. Specifically, the open cavity configuration may utilize an open cavity package design. In some aspects, the open cavity configuration may include a cover or other housing for protecting interconnects, circuit components, semiconductor chip 200, etc. Package 100 may include a ceramic body, a cover, and one or more metal contacts.

[0158] Figure 20 It shows that according to Figure 11 A partial top view of the encapsulation.

[0159] Specifically, Figure 20 Alternative embodiments of chip attachment material 124 and one or more channels 122 with various configurations are shown. Specifically, the chip attachment material 124 may have a circular, triangular, or free-form shape, etc. Furthermore, as... Figure 20 As shown, one or more channels 122 may have different sizes and shapes.

[0160] Figure 21 The encapsulation process implemented according to this disclosure is illustrated.

[0161] Specifically, Figure 21 The processes for implementing the package (box 600) related to the implementation, fabrication, manufacturing, and formation of the package 100 as described herein are illustrated. It should be noted that aspects of the implementation package processes (box 600) may be performed in a different order consistent with the aspects described herein. Furthermore, the implementation package processes (box 600) may be modified to have more or fewer processes consistent with the aspects disclosed herein.

[0162] Initially, the encapsulation process (box 600) may include the process of forming the support 102 (box 602). More specifically, the support 102 may be constructed, configured, and / or arranged as described herein.

[0163] Specifically, the support 102 may be implemented as a paddle. The paddle-shaped support 102 may include a metallic material, such as copper. Furthermore, the paddle-shaped support 102 may include a metal plating material. The metal plating material may include any metallic material, such as silver. In one aspect, the support 102 is implemented as a paddle and includes copper and a metal plating material including silver. The support 102 may be connected to and / or supported by the lead frame 192. The lead frame 192 may include or be connected to one or more input / output pins 134. Alternatively, the support may be formed as a support, surface, package support, package surface, package support surface, metal base, flange, metal flange, heat sink, common source support, common source surface, common source package support, common source package surface, common source assembly support surface, common source flange, common source heat sink, lead frame, metal lead frame, etc., and / or combinations thereof. The support member 102 may be formed of metallic materials, insulating materials, dielectric materials, and / or combinations thereof.

[0164] Furthermore, the encapsulation process (box 600) may include forming a chip attachment material 124 and one or more channels 122 (box 604). More specifically, the chip attachment material 124 and one or more channels 122 may be constructed, configured, and / or arranged on at least a portion of the support 102 as described herein.

[0165] Specifically, the chip attachment material 124 and one or more channels 122 can utilize screen printing, preforming, needle dispensing systems, inkjet dispensing systems, masking, photolithography, printing to a transparent film, photomask processes combined with etching, laser resist ablation, milling, laser etching, direct metal printing, combinations thereof, and / or similar processes as described herein.

[0166] Furthermore, the packaging process (box 600) may include placing the semiconductor chip 200 on the support 102, the chip attachment material 124, and one or more channels 122 (box 606). More specifically, the semiconductor chip 200 may be constructed, configured, and / or arranged as described herein. Thereafter, as described herein, the semiconductor chip 200 may be arranged on the support 102, the chip attachment material 124, and one or more channels 122.

[0167] More specifically, arranging the semiconductor chip 200 on the support 102, the chip attachment material 124 and one or more channels 122 (box 606) may include using and / or implementing pick-and-place components to place the semiconductor chip 200 on the support 102.

[0168] Furthermore, the encapsulation process (box 600) may include curing the chip attachment material 124 as described herein (box 608). Specifically, the semiconductor chip 200, support 102, chip attachment material 124, one or more channels 122, etc., may be placed in a high-temperature environment, such as an oven. In this regard, one or more side edges 128 of one or more channels 122 may form a surface of the chip attachment material 124, which allows gases generated during the curing of the chip attachment material 124 to be released from the chip attachment material 124. Specifically, one or more channels 122 may utilize one or more side edges 128 of the chip attachment material 124 to form a surface that allows gases generated during curing to be released from the chip attachment material 124 from below the active region 400.

[0169] Furthermore, the encapsulation process (box 600) may include forming one or more interconnect portions 120 and one or more interconnect portions 190 (box 610). More specifically, the one or more interconnect portions 190 may be constructed, configured, and / or arranged as described herein. In one aspect, the process of forming one or more interconnects may include forming one or more interconnect portions 120 and one or more interconnect portions 190 by forming one or more conductors, leads, vias, edge plates, circuit traces, tracks, etc. In one aspect, forming one or more interconnect portions 120 and one or more interconnect portions 190 (box 610) may include forming one or more interconnect portions 120 and one or more interconnect portions 190 by connection methods such as adhesives, soldering, sintering, eutectic bonding, ultrasonic welding, clamping components, etc., as described herein.

[0170] Furthermore, the encapsulation process (box 600) may include enclosing the package 100 (box 612). More specifically, the package 100 may be constructed, configured, and / or arranged as described herein. In one aspect, the encapsulation process (box 612) may include forming an open cavity configuration, an outer mold configuration, etc.

[0171] Figure 22 It shows that according to Figure 1 A top view of an exemplary implementation of the encapsulation.

[0172] Specifically, Figure 22 A top view of an exemplary embodiment of package 100, at least partially implemented as an MMIC transistor amplifier, is shown. In this respect, as described herein, package 100 can be implemented using various types of device technologies, device topologies, semiconductor types, transistor types, embodiments of semiconductor chip 200, embodiments of at least one secondary device region 300, embodiments of one or more active regions 400, etc. Therefore, Figure 22 This is just an example.

[0173] like Figure 22 As shown, the MMIC transistor amplifier includes a semiconductor chip 200 contained within a package 100. The package 100 may include input leads 112 and output leads 118. Input leads 112 can be mounted to input lead pads 114 by means of, for example, adhesives, soldering, sintering, eutectic bonding, thermoforming, ultrasonic bonding / soldering, clamping assemblies, etc. One or more interconnects 120 (such as input bonding wires) can electrically connect the input lead pads 114 to input bonding pads 232 on the semiconductor chip 200. A first end of one or more interconnects 120 can be directly connected to the input lead pads 114, and a second end of each of the one or more interconnects 120 can be connected to the input bonding pads 232.

[0174] The semiconductor chip 200 may further include a power supply network 238, which may include an input decoupling node 236 connected to an input bonding pad 232 via a transmission line 234. A first secondary device region in at least one secondary device region 300 may be implemented as an input impedance matching network 350. A first active region in one or more active regions 400 may be implemented as a first transistor stage 460. A second secondary device region in at least one secondary device region 300 may be implemented as an intermediate impedance matching network 340. A second active region in one or more active regions 400 may be implemented as a second transistor stage 462. A third secondary device region in at least one secondary device region 300 may be implemented as an output impedance matching network 370.

[0175] Semiconductor chip 200 may further include output bonding pads 288 and output combination nodes 285. Output leads 118 can be connected to output lead pads 116 via, for example, adhesives, soldering, sintering, eutectic bonding, thermoforming, ultrasonic bonding / soldering, clamping components, etc. One or more interconnects 190, such as output bonding wires, can electrically connect output lead pads 116 to output bonding pads 288. A first end of each of the one or more interconnects 190 can be directly connected to output lead pads 116, and a second end of the one or more interconnects 190 can be connected to output pads 288. Transmission line 287 can connect output pads 288 to a corporate power supply network 282.

[0176] The input impedance matching network 350 may include reactive components, such as capacitors and inductors as described herein, which can improve impedance matching between the input lead 112 and the first transistor stage 460. Similarly, the output impedance matching network 370 may include reactive components, such as capacitors and inductors as described herein, which can be used to match the impedance of the output of the second transistor stage 462 to the output lead 118 of the package 100.

[0177] Intermediate impedance matching network 340 may include reactive components, such as capacitors, inductors, etc., as described herein, which can be used to better match the impedance at the output of the first transistor stage 460 with the impedance at the input of the second transistor stage 462, and may be similar to input impedance matching network 350.

[0178] The first transistor stage 460 and the second transistor stage 462 may include multiple unit transistors arranged in parallel. The first transistor stage 460 and the second transistor stage 462 may be arranged in an MMIC amplifier to provide increased gain. It should be understood that, in other cases, only a single transistor stage may be provided, or more than two transistor stages may be provided, and the number of impedance matching stages may be adjusted accordingly.

[0179] like Figure 22 As further shown, the input separation node 236 and the output combination node 285 can both be on the semiconductor chip 200. Therefore, one or more interconnects 120 and one or more interconnects 190 can be outside the loop defined by the parallel amplification path included in the MMIC amplifier, which extends between the input separation node 236 and the output combination node 285.

[0180] Figure 23 yes Figure 22 A magnified schematic diagram of a subset of the unit transistors in a transistor amplifier.

[0181] like Figure 23 As shown, one or more active regions 400 may include a gate bus 402 connected along a first direction (e.g., Figure 23 Multiple gate fingers 406 extend parallel to each other (in the x-direction shown). A source bus 410 is connected to multiple source contacts 416 connected in parallel. The source bus 410 can be connected to a ground voltage node on the underside of the semiconductor chip 200. A drain bus 420 can be connected to multiple drain contacts 426.

[0182] like Figure 23 As shown, each gate finger 406 extends along the X direction between a pair of adjacent source contacts 416 and drain contacts 426. The semiconductor chip 200 may include a plurality of unit cells 430, each of which includes a single transistor. One of the unit cells 430 is composed of... Figure 23The dashed box in the diagram shows and includes the gate finger 406 extending between adjacent contacts in the source contact 416 and drain contact 426. "Gate width" refers to the distance by which the gate finger 406 overlaps with the corresponding contacts of the source contact 406 and drain contact 426 in the X direction. That is, the "width" of the gate finger 406 refers to the dimension (distance along the z direction) by which the gate finger 406 extends parallel to the adjacent source contact 416 / drain contact 426. Each of the plurality of unit cells 430 may share one of the source contact 416 and / or drain contact 426 with one or more adjacent unit cells in the plurality of unit cells 430. Although... Figure 23 A specific number of unit cells among multiple unit cells 430 are shown, but it should be understood that the semiconductor chip 200 may include more or fewer unit cells 430.

[0183] Figure 24 It is along Figure 23 A schematic cross-sectional view taken from the midline XXIV-XXIV.

[0184] refer to Figure 24 The semiconductor chip 200 and / or active region 400 may include a semiconductor structure 440, which includes a substrate 202, which may include, for example, 4H-SiC or 6H-SiC. A channel layer 490 may be disposed on the substrate 202, and a barrier layer 470 may be disposed on the channel layer 490, such that the channel layer 490 is located between the substrate 202 and the barrier layer 470. The channel layer 490 and the barrier layer 470 may include a group III nitride-based material, wherein the material of the barrier layer 470 has a higher band gap than the material of the channel layer 490. For example, the channel layer 490 may include GaN, and the barrier layer 470 may include AlGaN.

[0185] Due to the bandgap difference between the barrier layer 470 and the channel layer 490, and the piezoelectric effect at the interface between the barrier layer 470 and the channel layer 490, a two-dimensional electron gas (2DEG) is induced at the bonding site between the channel layer 490 and the barrier layer 470 in the channel layer 490. The 2DEG serves as a highly conductive layer allowing conductivity between the source and drain regions of the device, which can be located below the source contact 416 and drain contact 426, respectively. The source contact 416 and drain contact 426 can be on the barrier layer 470. A gate finger 406 can be on the barrier layer 470 between the source contact 406 and the drain contact 426. Although the gate finger 406 and the source contact 416 and drain contact 426 are... Figure 23 All are shown as having the same "length". In practice, the gate finger 406 can have a much shorter length than the source contact 416 and the drain contact 426, and it can also be understood that the source contact and the drain contact 426 do not have to have the same length.

[0186] The material of the gate contact 406 can be selected based on the composition of the barrier layer 470. However, in some embodiments, materials capable of Schottky contacts with nitride-based semiconductor materials, such as Ni, Pt, NiSix, Cu, Pd, Cr, W, and / or WSiN, can be used. The source contact 416 and drain contact 426 can include metals such as TiAlN, which can form ohmic contacts with GaN.

[0187] Input lead pad 114, input bonding pad 232, output bonding pad 288, output lead pad 116, and any other bonding pad area can be formed from a metal surface and can include metal materials such as copper, gold, nickel, palladium, silver, etc., and combinations thereof.

[0188] Semiconductor chip 200 may include a metallization layer located on the lower surface of substrate 202. The metallization layer may be located in a plane generally parallel to the z-axis and / or x-axis. In one aspect, the metallization layer may be implemented as a full-surface metallization layer on the lower surface of substrate 202. Alternatively or additionally, semiconductor chip 200 may be single-sided (one metal layer), double-sided (two metal layers on either side of a substrate layer), or multi-layered (outer and inner layers of aluminum, copper, silver, gold, etc., alternating with substrate layers). Semiconductor chip 200 may include individual wires, tracks, circuit traces, pads for connections, vias for connections between layers of aluminum, copper, silver, gold, etc., and features such as solid conductive regions for EM shielding or other purposes. In one or more aspects, chip attachment material 124 may not form an electrical connection with semiconductor chip 200. More specifically, chip attachment material 124 may be specifically designed to attach semiconductor chip 200 to support 102. Therefore, in this aspect, the bottom of semiconductor chip 200 has no electrical contact. In one or more aspects, the chip attachment material 124 can form a single electrical connection with the semiconductor chip 200. More specifically, the chip attachment material 124 can be used for a single electrical connection between the semiconductor chip 200 and the support 102, and thus, in this aspect, the bottom of the semiconductor chip 200 does not have any electrical contacts. Therefore, in these aspects, the structure of the package 100 of this disclosure differs from the multi-connection type circuits used in flip chips, controlled collapse chip connections, C4, etc.

[0189] Figure 25 A partial top view of the package according to this disclosure is shown.

[0190] Specifically, Figure 25 An exemplary implementation of encapsulation 100 is shown, which may include any one or more features, components, arrangements, etc. described herein. More specifically, Figure 25Package 100 is shown, which implements semiconductor chip 200 as a large-area integrated circuit, monolithic integrated circuit, monolithic microwave integrated circuit (MMIC), multi-unit transistor integrated circuit, integrated circuit with field-effect transistor (FET) array, multi-transistor integrated circuit, multi-circuit integrated circuit, multi-unit integrated circuit, multi-region integrated circuit, multi-active-region integrated circuit, composite semiconductor device, high-power semiconductor device, high-frequency semiconductor device, high-power / frequency semiconductor device, composite high-power semiconductor device, composite high-frequency semiconductor device, composite high-power / frequency semiconductor device, composite semiconductor device, high-power composite semiconductor device, high-frequency composite semiconductor device, etc. For example, this disclosure can be used for high-power and / or high-frequency composite semiconductor devices, such as group III nitride transistors, such as GaN-based FETs, HEMTs and / or similar devices, or MMICs containing them. Furthermore, this disclosure can be used for multi-level FET topologies, multi-path FET topologies and / or similar structures including Doherty configurations using MMICs and / or discrete components. Additionally, this disclosure can also be applied to discrete devices, discrete transistors, large form factor discrete transistors, large form factor discrete devices, multi-region discrete devices, etc.

[0191] In one or more aspects, Figure 25 The package 100 illustrates various aspects of this disclosure that can be used in any embodiment of a semiconductor chip 200, which includes one or more active regions 400, and at least one embodiment of regions of the semiconductor chip not implementing one or more active regions. For example, regions implementing at least one secondary device region 300.

[0192] As a specific example, Figure 25 The package 100 shown may include an implementation as a Doherty circuit, wherein at least one or more active regions 400 include a carrier amplifier and a peak amplifier. Specifically, the package 100 may include a carrier amplifier and a peak amplifier configured such that the package 100 power-combines the outputs of the carrier amplifier and the peak amplifier. In one aspect, the two amplifiers may be biased differently. In one aspect, the carrier amplifier may operate at normal Class AB or Class B. In one aspect, the peak amplifier may operate at Class C. Other operating classes may also be considered.

[0193] Therefore, this disclosure includes devices and processes disclosed for implementing intentionally constructed channels or meshes of one or more channels, which will allow venting voids to escape in regions near but not directly below active regions (such as active transistors). Thus, the application of the channelization void reduction techniques described in this disclosure using sintered chip attachment materials provides unexpected results in terms of improved cooling and / or robustness. Furthermore, for GaN packages using sintered chip attachment materials, the application of the channelization void reduction techniques described in this disclosure provides unexpected results in terms of improved cooling and / or robustness. Specifically, the applicant has tested many different void reduction methods and found that the disclosed channelization method demonstrates and provides the best results. Specifically, this disclosure can be applied to large-area integrated circuits, monolithic integrated circuits, monolithic microwave integrated circuits (MMICs), multi-unit transistor integrated circuits, integrated circuits with field-effect transistor (FET) arrays, multi-transistor integrated circuits, multi-circuit integrated circuits, multi-unit integrated circuits, multi-region integrated circuits, multi-active-region integrated circuits, composite semiconductor devices, high-power semiconductor devices, high-frequency semiconductor devices, high-power / frequency semiconductor devices, composite high-power semiconductor devices, composite high-frequency semiconductor devices, composite high-power / frequency semiconductor devices, composite semiconductor devices, high-power composite semiconductor devices, and high-frequency composite semiconductor devices. For example, this disclosure can be applied to high-power and / or high-frequency composite semiconductor devices, such as group III nitride transistors, such as GaN-based FETs, HEMTs, etc., or MMICs containing them. Furthermore, this disclosure can be applied to multi-level FET topologies, multi-path FET topologies, and / or similar structures including Doherty configurations that use MMICs and / or discrete components. Additionally, this disclosure can also be applied to discrete devices, discrete transistors, large form factor discrete transistors, large form factor discrete devices, multi-region discrete devices, etc.

[0194] Furthermore, this disclosure also discloses devices and processes for implementing an outer mold 130 disposed on chip attachment material 124 and / or one or more channels 122, which can facilitate molding compound adhesion between the outer mold 130 and the semiconductor chip 200 within the package 100. In this regard, some portions of the chip attachment material 124 may extend beyond the semiconductor chip 200 covering the support 102. These portions in the chip attachment material 124 can improve the plastic adhesion between the outer mold 130 of the package 100 and the outer mold of the support 102. In addition, these portions on the chip attachment material 124 can avoid selective electroplating of the support 102. Furthermore, this structure can allow for a common package lead frame for all chip sizes of the semiconductor chip 200 used in the package type. In this regard, implementing the outer mold 130 of the package 100 onto various aspects of the support 102 as described herein allows for considerable variability in the size and implementation of the semiconductor chip 200.

[0195] Furthermore, this disclosure discloses devices and processes that lead to reduced manufacturing costs. Additionally, this disclosure also discloses devices and processes that can implement various component configurations to reduce packaging costs, reduce packaging manufacturing costs, reduce manufacturing complexity, reduce yield losses, etc.

[0196] The adhesive disclosed herein can be used in adhesive bonding processes that may include applying an intermediate layer to bond surfaces to be bonded. The adhesive may be organic or inorganic; and the adhesive may be deposited on one or both surfaces to be bonded. The adhesive can be used in adhesive bonding processes that may include applying an adhesive material with a specific coating thickness at a specific bonding temperature, for a specific processing time, and in an environment that may include applying specific tooling pressure. In one aspect, the adhesive may be a conductive adhesive, an epoxy-based adhesive, a conductive epoxy-based adhesive, etc.

[0197] The solder disclosed herein can be used to form a solder interface that may include solder and / or be formed by solder. The solder can be any fusible metal alloy that can be used to form a bond between surfaces to be joined. The solder can be lead-free solder, lead solder, eutectic solder, etc. Lead-free solder may contain traces of tin, copper, silver, bismuth, indium, zinc, antimony, other metals, etc. Lead solder may contain lead, other metals such as tin, silver, etc. The solder may further include flux as needed.

[0198] The sintering disclosed herein can utilize a process of compacting and forming a solid material block by heating and / or pressure. The sintering process can be performed without melting the material to its liquefaction point. The sintering process can include the sintering of metal powders. The sintering process can include sintering in a vacuum. The sintering process can include sintering using a protective gas.

[0199] The eutectic bonding disclosed herein can be achieved using a bonding process with an intermediate metal layer, which can form a eutectic system. This eutectic system can be used between surfaces to be joined. Eutectic bonding can utilize a eutectic metal, which can be an alloy that transforms from a solid to a liquid state or from a liquid to a solid state at specific compositions and temperatures, without two-phase equilibrium. Eutectic alloys can be deposited via sputtering, dual-source evaporation, electroplating, etc.

[0200] The ultrasonic welding disclosed herein can utilize a process in which high-frequency ultrasonic acoustic vibrations are locally applied to components held together under pressure. Ultrasonic welding can form a solid weld between surfaces to be joined. In one aspect, ultrasonic welding may include applying ultrasonic force.

[0201] While this disclosure has been described with reference to exemplary aspects, those skilled in the art will recognize that modifications can be made to practice this disclosure within the spirit and scope of the appended claims. The examples given above are merely illustrative and are not intended to be an exhaustive list of all possible designs, aspects, applications, or modifications of this disclosure.

Claims

1. A semiconductor device, comprising: Semiconductor chips; Support components; as well as A chip attachment material is configured to attach the lower surface of the semiconductor chip to the upper surface of the support. The chip attachment material is constructed and disposed on the support and includes at least one channel; The semiconductor chip is disposed on at least a portion of the at least one channel arranged on the support member; Wherein, the at least one channel is disposed vertically below and laterally offset from the active region of the semiconductor chip, and The at least one channel is configured to allow gas generated during the attachment of the semiconductor chip to the support to be released from the chip attachment material.

2. The semiconductor device according to claim 1, wherein: The semiconductor chip is a high electron mobility transistor (HEMT) based on group III nitrides.

3. The semiconductor device according to claim 1, wherein: The semiconductor chip is a monolithic microwave integrated circuit (MMIC) based on group III nitrides.

4. The semiconductor device according to claim 3, wherein: The group III nitride-based MMIC includes multiple group III nitride-based high electron mobility transistors (HEMTs) and at least one secondary device region.

5. The semiconductor device of claim 1, further comprising at least one secondary device region on the support, wherein, The chip attachment material includes at least a portion of the at least one channel located between the at least one secondary device region and the support.

6. The semiconductor device of claim 1, further comprising a protective material on the support, wherein, The chip attachment material includes at least a portion of the at least one channel located between the protective material and the support.

7. The semiconductor device according to claim 1, wherein: The at least one channel includes multiple channels.

8. The semiconductor device according to claim 1, wherein: The at least one channel includes at least two intersecting channels.

9. The semiconductor device according to claim 1, wherein: Two or more of the at least one channel intersect.

10. The semiconductor device according to claim 1, wherein: The at least one channel forms a mesh.

11. The semiconductor device according to claim 1, wherein: The chip attachment material includes metal particles in organic materials.

12. The semiconductor device according to claim 1, wherein: The chip attachment material includes sintered materials.

13. The semiconductor device according to claim 1, wherein: The chip attachment material includes at least one of silver sintered material and copper sintered material.

14. The semiconductor device according to claim 1, wherein: The semiconductor chip includes an integrated circuit.

15. The semiconductor device according to claim 1, wherein: The at least one channel is disposed below at least one secondary device region; and The semiconductor chip includes a monolithic microwave integrated circuit (MMIC).

16. The semiconductor device according to claim 1, wherein, The at least one channel includes at least one exhaust port and at least one side edge.

17. The semiconductor device according to claim 1, wherein, The at least one channel includes at least one of the following: continuous shape, discontinuous shape, and combination thereof.

18. The semiconductor device according to claim 1, wherein, The at least one channel cuts the chip attachment material.

19. The semiconductor device according to claim 1, wherein, At least one side edge of the at least one channel is configured to form a surface of the chip attachment material to allow gases generated during the curing of the chip attachment material to be released from the chip attachment material.

20. The semiconductor device according to claim 1, wherein, The at least one channel is configured to receive gas generated below at least one active area during curing, and once the gas is in the at least one channel, the at least one channel is configured to allow the gas to travel along the at least one channel and be discharged from the at least one channel through an exhaust port.

21. The semiconductor device according to claim 1, wherein, The chip attachment material is configured to utilize one of the following: screen printing, preforming, needle dispensing, and inkjet dispensing.

22. The semiconductor device according to claim 1, wherein, The chip attachment material is configured using a screen printing process, the screen printing process having a template with an opening consistent with the forming of the chip attachment material, and the template having a portion of the chip attachment material that is not allowed to be applied at a position consistent with the at least one channel.

23. The semiconductor device according to claim 1, further comprising: Encapsulation; as well as The package includes at least one of the following: an L-band component package implementing a frequency range in the radio spectrum from 1 to 2 GHz; an S-band component package covering a frequency range from 2 to 4 GHz; an X-band component package implementing a frequency range in the radio spectrum from 7.0 to 11.2 GHz; a C-band component package implementing a frequency range in the radio spectrum from 500 to 1000 MHz; and a Ku-band component package implementing an electromagnetic spectrum in the microwave frequency range from 12 to 18 GHz; and The semiconductor chip includes an integrated circuit.

24. The semiconductor device of claim 1, wherein, The semiconductor chip includes at least one active region, which includes at least one of the following: a region containing one or more transistors, a region containing one or more transistor amplifiers, a region containing one or more transformers, and a region containing one or more voltage regulators.

25. The semiconductor device according to claim 1, wherein: The semiconductor chip includes at least one active region, which is the region where one or more radio frequency (RF) semiconductor devices are located; The semiconductor chip includes at least one of the following: GaN-based field-effect transistors (FETs) and GaN-based high electron mobility transistors (HEMTs); and The semiconductor chip includes at least one secondary device region, which includes one or more of the following: an input matching circuit, an output matching circuit, an intermediate matching circuit, a harmonic termination circuit, and a matching network.

26. The semiconductor device according to claim 1, wherein: The semiconductor chip includes at least one active region, which is a region where one or more semiconductor devices are located; and The semiconductor chip includes at least one of the following: metal-semiconductor field-effect transistor (MESFET), metal-oxide field-effect transistor (MOSFET), junction field-effect transistor (JFET), bipolar junction transistor (BJT), laterally diffused metal-oxide semiconductor (LDMOS), insulated gate bipolar transistor (IGBT), high electron mobility transistor (HEMT), and wide bandgap semiconductor (WBG).

27. The semiconductor device of claim 1, wherein, The semiconductor chip includes at least one secondary device region, which includes one or more of the following: resistors, inductors, capacitors, input matching circuits, output matching circuits, intermediate matching circuits, harmonic filters, harmonic terminations, couplers, baluns, power combiners, power dividers, radio frequency (RF) circuits, radial stub circuits, transmission line circuits, baseband matching circuits, baseband termination circuits, second harmonic termination circuits, integrated passive device (IPD), and matching networks.

28. The semiconductor device of claim 1, wherein, The support includes at least one of the following: an encapsulation support, a metal base, a flange, a heat sink, and a lead frame.

29. The semiconductor device of claim 1, wherein, The chip attachment material includes one or more metallic materials and one or more non-metallic materials.

30. The semiconductor device of claim 1, further comprising at least an outer mold configuration surrounding the semiconductor chip. wherein The chip attachment material includes at least a portion of the at least one channel positioned between the outer mold configuration and the support.

31. A method for fabricating a semiconductor device, comprising: Provide semiconductor chips; Provide support components; as well as A chip attachment material is formed on the support member, the chip attachment material being configured to attach the lower surface of the semiconductor chip to the upper surface of the support member. The formation of the chip attachment material includes forming at least one channel in the chip attachment material on the support member. Wherein, the at least one channel is disposed vertically below and laterally offset from the active region of the semiconductor chip, and The at least one channel is configured to allow gas generated during the attachment of the semiconductor chip to the support to be released from the chip attachment material.

32. The method for fabricating a semiconductor device according to claim 31, wherein: The semiconductor chip is a high electron mobility transistor (HEMT) based on group III nitrides.

33. The method for fabricating a semiconductor device according to claim 31, wherein: The semiconductor chip is a monolithic microwave integrated circuit (MMIC) based on group III nitrides.

34. The method for fabricating a semiconductor device according to claim 33, wherein: The group III nitride-based MMIC includes multiple group III nitride-based high electron mobility transistors (HEMTs) and at least one secondary device region.

35. The method of fabricating a semiconductor device of claim 31, further comprising at least one secondary device region on the support, and wherein, The chip attachment material includes at least a portion of the at least one channel located between the at least one secondary device region and the support.

36. The method of fabricating a semiconductor device of claim 31, further comprising a protective material on the support, and wherein, The chip attachment material includes at least a portion of the at least one channel located between the protective material and the support.

37. The method for fabricating a semiconductor device according to claim 31, wherein: The at least one channel includes multiple channels.

38. The method for fabricating a semiconductor device according to claim 31, wherein: The at least one channel includes at least two intersecting channels.

39. The method for fabricating a semiconductor device according to claim 31, wherein: Two or more of the at least one channel intersect.

40. The method for fabricating a semiconductor device according to claim 31, wherein: The at least one channel forms a mesh.

41. The method for fabricating a semiconductor device according to claim 31, wherein: The chip attachment material includes metal particles in organic materials.

42. The method for fabricating a semiconductor device according to claim 31, wherein: The chip attachment material includes sintered materials.

43. The method for fabricating a semiconductor device according to claim 31, wherein: The chip attachment material includes at least one of silver sintered material and copper sintered material.

44. The method for fabricating a semiconductor device according to claim 31, wherein, The semiconductor chip includes an integrated circuit.

45. The method for fabricating a semiconductor device according to claim 31, further comprising arranging the at least one channel beneath at least one secondary device region. wherein The semiconductor chip includes a monolithic microwave integrated circuit (MMIC).

46. ​​The method of fabricating a semiconductor device according to claim 31, further comprising configuring the at least one channel to have at least one vent and at least one side edge.

47. The method of fabricating a semiconductor device according to Claim 31, wherein, The at least one channel includes at least one of the following: continuous shape, discontinuous shape, and combination thereof.

48. The method of fabricating a semiconductor device according to Claim 31, wherein, The at least one channel cuts the chip attachment material.

49. The method of fabricating a semiconductor device according to claim 31, further comprising configuring the at least one channel to have at least one side edge to form a surface of the chip attachment material to allow gases generated during curing of the chip attachment material to be released from the chip attachment material.

50. The method for fabricating a semiconductor device according to claim 31, further comprising: The at least one channel is configured to receive gas generated from below at least one active region during curing; as well as The at least one channel is configured such that once the gas is in the at least one channel, the at least one channel allows the gas to travel along the at least one channel and be discharged from the at least one channel through an exhaust port.

51. The method of fabricating a semiconductor device according to Claim 31, wherein, The chip attachment material is formed using one of the following: screen printing, preforming, needle dispensing, and inkjet dispensing.

52. The method of fabricating a semiconductor device according to Claim 31, wherein, Forming the chip attachment material includes using a screen printing process, the screen printing process having a stencil with an opening consistent with the forming of the chip attachment material, and the stencil having a portion of the chip attachment material that is not allowed to be applied at a location consistent with the at least one channel.

53. The method for fabricating a semiconductor device according to claim 31, further comprising: The packaging includes implementing at least one of the following: implementing an L-band component package covering a frequency range of 1 to 2 GHz in the radio spectrum; an S-band component package covering a frequency range of 2 to 4 GHz; an X-band component package covering a frequency range of 7.0 to 11.2 GHz in the radio spectrum; a C-band component package covering a frequency range of 500 to 1000 MHz in the radio spectrum; and a Ku-band component package covering an electromagnetic spectrum covering a microwave frequency range of 12 to 18 GHz.

54. The method of fabricating a semiconductor device according to Claim 31, wherein, At least one active region includes at least one of the following: a region containing one or more transistors, a region containing one or more transistor amplifiers, a region containing one or more transformers, and a region containing one or more voltage regulators.

55. The method for fabricating a semiconductor device according to claim 31, further comprising: Configure at least one active region as the region where one or more radio frequency (RF) semiconductor devices are located; The one or more radio frequency (RF) semiconductor devices are configured as at least one of: GaN-based field-effect transistors (FETs) and GaN-based high electron mobility transistors (HEMTs); and At least one secondary device region is configured as one or more of the following: input matching circuit, output matching circuit, intermediate matching circuit, harmonic termination, harmonic termination circuit, and matching network.

56. The method for fabricating a semiconductor device according to claim 31, further comprising: Configure at least one active region as the region where one or more semiconductor devices are located; as well as The one or more semiconductor devices are configured as at least one of the following: metal-semiconductor field-effect transistors (MESFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), bipolar junction transistors (BJTs), laterally diffused metal-oxide-semiconductor semiconductors (LDMOS), insulated-gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), and wide bandgap semiconductors (WBGs).

57. The method of fabricating a semiconductor device according to claim 31, further comprising configuring at least one secondary device region as one or more of the following: resistor, inductor, capacitor, input matching circuit, output matching circuit, intermediate matching circuit, harmonic filter, harmonic termination, coupler, balun, power combiner, power divider, RF circuit, radial stub circuit, transmission line circuit, baseband matching circuit, baseband termination circuit, second harmonic termination circuit, integrated passive device (IPD), and matching network.

58. The method of fabricating a semiconductor device according to Claim 31, wherein, The support includes at least one of the following: an encapsulation support, a metal base, a flange, a heat sink, and a lead frame.

59. The method of fabricating a semiconductor device according to Claim 31, wherein, The chip attachment material includes one or more metallic materials and one or more non-metallic materials.

60. The method of fabricating a semiconductor device according to claim 31, further comprising at least a molded arrangement surrounding the semiconductor chip. wherein The chip attachment material includes at least one channel positioned between the outer mold configuration and the support member at least a portion thereof.

61. A semiconductor device, comprising: A semiconductor chip, including at least one secondary device region; Support components; as well as A chip attachment material is configured to attach the lower surface of the semiconductor chip to the upper surface of the support. The chip attachment material is constructed and disposed on the support member, and includes at least one channel. The semiconductor chip is disposed on at least a portion of the at least one channel arranged on the support member. The at least one channel is disposed vertically below and laterally offset from the active region of the semiconductor chip. Wherein, at least a portion of the at least one channel is disposed between the at least one secondary device region of the semiconductor chip and the support member, and The at least one channel is configured to allow gas generated during the attachment of the semiconductor chip to the support to be released from the chip attachment material.

62. The semiconductor device according to claim 61, wherein: The semiconductor chip is a high electron mobility transistor (HEMT) based on group III nitrides.

63. The semiconductor device according to claim 61, wherein: The semiconductor chip is a monolithic microwave integrated circuit (MMIC) based on group III nitrides.

64. The semiconductor device according to claim 63, wherein: The group III nitride-based MMIC includes multiple group III nitride-based high electron mobility transistors (HEMTs) and the at least one secondary device region.

65. The semiconductor device of claim 61, further comprising a protective material on the support, and wherein, The chip attachment material includes at least a portion of the at least one channel located between the protective material and the support.

66. The semiconductor device according to claim 61, wherein: The at least one channel includes multiple channels.

67. The semiconductor device according to claim 61, wherein: The at least one channel includes at least two intersecting channels.

68. The semiconductor device according to claim 61, wherein: Two or more of the at least one channel intersect.

69. The semiconductor device according to claim 61, wherein: The at least one channel forms a mesh.

70. The semiconductor device according to claim 61, wherein: The chip attachment material includes metal particles in organic materials.

71. The semiconductor device according to claim 61, wherein: The chip attachment material includes sintered materials.

72. The semiconductor device according to claim 61, wherein: The chip attachment material includes at least one of silver sintered material and copper sintered material.

73. The semiconductor device according to claim 61, wherein: The semiconductor chip includes an integrated circuit.

74. The semiconductor device according to claim 61, wherein: The at least one channel is disposed below the at least one secondary device region; and The semiconductor chip includes a monolithic microwave integrated circuit (MMIC).

75. The semiconductor device of claim 61, wherein, The at least one channel includes at least one exhaust port and at least one side edge.

76. The semiconductor device of claim 61, wherein, The at least one channel includes at least one of the following: continuous shape, discontinuous shape, and combination thereof.

77. The semiconductor device of claim 61, wherein, The at least one channel cuts the chip attachment material.

78. The semiconductor device of claim 61, wherein, At least one side edge of the at least one channel is configured to form a surface of the chip attachment material to allow gases generated during the curing of the chip attachment material to be released from the chip attachment material.

79. The semiconductor device of claim 61, wherein, The at least one channel is configured to receive gas generated below at least one active area during curing, and once the gas is in the at least one channel, the at least one channel is configured to allow the gas to travel along the at least one channel and be discharged from the at least one channel through an exhaust port.

80. The semiconductor device of claim 61, wherein, The chip attachment material is configured to utilize one of the following: screen printing, preforming, needle dispensing, and inkjet dispensing.

81. The semiconductor device of claim 61, wherein, The chip attachment material is configured using a screen printing process, the screen printing process having a template with an opening consistent with the forming of the chip attachment material, and the template having a portion of the chip attachment material that is not allowed to be applied at a position consistent with the at least one channel.

82. The semiconductor device of claim 61, further comprising: Encapsulation; as well as The package includes at least one of the following: an L-band component package implementing a frequency range in the radio spectrum from 1 to 2 GHz; an S-band component package covering a frequency range from 2 to 4 GHz; an X-band component package implementing a frequency range in the radio spectrum from 7.0 to 11.2 GHz; a C-band component package implementing a frequency range in the radio spectrum from 500 to 1000 MHz; and a Ku-band component package implementing an electromagnetic spectrum in the microwave frequency range from 12 to 18 GHz; and The semiconductor chip includes an integrated circuit.

83. The semiconductor device of claim 61, wherein, The semiconductor chip includes at least one active region, which includes at least one of the following: a region containing one or more transistors, a region containing one or more transistor amplifiers, a region containing one or more transformers, and a region containing one or more voltage regulators.

84. The semiconductor device according to claim 61, wherein: The semiconductor chip includes at least one active region, which is the region where one or more radio frequency (RF) semiconductor devices are located; The semiconductor chip includes at least one of the following: GaN-based field-effect transistors (FETs) and GaN-based high electron mobility transistors (HEMTs); and The at least one secondary device region includes one or more of the following: an input matching circuit, an output matching circuit, an intermediate matching circuit, a harmonic termination, a harmonic termination circuit, and a matching network.

85. The semiconductor device according to claim 61, wherein: The semiconductor chip includes at least one active region, which is a region where one or more semiconductor devices are located; and The semiconductor chip includes at least one of the following: metal-semiconductor field-effect transistor (MESFET), metal-oxide field-effect transistor (MOSFET), junction field-effect transistor (JFET), bipolar junction transistor (BJT), laterally diffused metal-oxide semiconductor (LDMOS), insulated gate bipolar transistor (IGBT), high electron mobility transistor (HEMT), and wide bandgap semiconductor (WBG).

86. The semiconductor device of claim 61, wherein, The at least one secondary device region includes one or more of the following: resistors, inductors, capacitors, input matching circuits, output matching circuits, intermediate matching circuits, harmonic filters, harmonic terminations, couplers, baluns, power combiners, power dividers, RF circuits, radial stub circuits, transmission line circuits, baseband matching circuits, baseband termination circuits, second harmonic termination circuits, integrated passive device (IPD) devices, and matching networks.

87. The semiconductor device of claim 61, wherein, The support includes at least one of the following: an encapsulation support, a metal base, a flange, a heat sink, and a lead frame.

88. The semiconductor device of claim 61, wherein, The chip attachment material includes one or more metallic materials and one or more non-metallic materials.

89. The semiconductor device of claim 61, further comprising at least an outer mold configuration surrounding the semiconductor chip. wherein The chip attachment material includes at least a portion of the at least one channel positioned between the outer mold configuration and the support.

90. A semiconductor device, comprising: Semiconductor chips; Support components; as well as Chip attachment material, including at least one channel; as well as The outer mold configuration is at least surrounding the semiconductor chip, and the outer mold configuration is at least partially attached to the chip attachment material; The semiconductor chip is disposed on at least a portion of the at least one channel arranged on the support member. Wherein, the at least one channel is disposed vertically below and laterally offset from the active region of the semiconductor chip, and The at least one channel is configured to allow gas generated during the attachment of the semiconductor chip to the support to be released from the chip attachment material.

91. The semiconductor device according to claim 90, wherein: The semiconductor chip is a high electron mobility transistor (HEMT) based on group III nitrides.

92. The semiconductor device according to claim 90, wherein: The semiconductor chip is a monolithic microwave integrated circuit (MMIC) based on group III nitrides.

93. The semiconductor device according to claim 92, wherein: The group III nitride-based MMIC includes multiple group III nitride-based high electron mobility transistors (HEMTs) and at least one secondary device region.

94. The semiconductor device of claim 90, further comprising at least one secondary device region on the support, and wherein, The chip attachment material includes at least a portion of the at least one channel located between the at least one secondary device region and the support.

95. The semiconductor device of claim 90, further comprising a protective material on the support, and wherein, The chip attachment material includes at least a portion of the at least one channel located between the protective material and the support.

96. The semiconductor device according to claim 90, wherein: The at least one channel includes multiple channels.

97. The semiconductor device according to claim 90, wherein: The at least one channel includes at least two intersecting channels.

98. The semiconductor device according to claim 90, wherein: Two or more of the at least one channel intersect.

99. The semiconductor device according to claim 90, wherein: The at least one channel forms a mesh.

100. The semiconductor device according to claim 90, wherein: The chip attachment material includes metal particles in organic materials.

101. The semiconductor device according to claim 90, wherein: The chip attachment material includes sintered materials.

102. The semiconductor device according to claim 90, wherein: The chip attachment material includes at least one of silver sintered material and copper sintered material.

103. The semiconductor device according to claim 90, wherein: The semiconductor chip includes an integrated circuit.

104. The semiconductor device according to claim 90, wherein: The at least one channel is disposed below at least one secondary device region; and The semiconductor chip includes a monolithic microwave integrated circuit (MMIC).

105. The semiconductor device of claim 90, wherein, The at least one channel includes at least one exhaust port and at least one side edge.

106. The semiconductor device of claim 90, wherein, The at least one channel includes at least one of the following: continuous shape, discontinuous shape, and combination thereof.

107. The semiconductor device of claim 90, wherein, The at least one channel cuts the chip attachment material.

108. The semiconductor device of claim 90, wherein, At least one side edge of the at least one channel is configured to form a surface of the chip attachment material to allow gases generated during the curing of the chip attachment material to be released from the chip attachment material.

109. The semiconductor device of claim 90, wherein, The at least one channel is configured to receive gas generated below at least one active area during curing, and once the gas is in the at least one channel, the at least one channel is configured to allow the gas to travel along the at least one channel and be discharged from the at least one channel through an exhaust port.

110. The semiconductor device of claim 90, wherein, The chip attachment material is configured to utilize one of the following: screen printing, preforming, needle dispensing, and inkjet dispensing.

111. The semiconductor device of claim 90, wherein, The chip attachment material is configured using a screen printing process, the screen printing process having a template with an opening consistent with the forming of the chip attachment material, and the template having a portion of the chip attachment material that is not allowed to be applied at a position consistent with the at least one channel.

112. The semiconductor device of claim 90, further comprising: Encapsulation; as well as The package includes at least one of the following: an L-band component package implementing a frequency range in the radio spectrum from 1 to 2 GHz; an S-band component package covering a frequency range from 2 to 4 GHz; an X-band component package implementing a frequency range in the radio spectrum from 7.0 to 11.2 GHz; a C-band component package implementing a frequency range in the radio spectrum from 500 to 1000 MHz; and a Ku-band component package implementing an electromagnetic spectrum in the microwave frequency range from 12 to 18 GHz; and The semiconductor chip includes an integrated circuit.

113. The semiconductor device of claim 90, wherein, The semiconductor chip includes at least one active region, which includes at least one of the following: a region containing one or more transistors, a region containing one or more transistor amplifiers, a region containing one or more transformers, and a region containing one or more voltage regulators.

114. The semiconductor device according to claim 90, wherein: The semiconductor chip includes at least one active region, which is the region where one or more radio frequency (RF) semiconductor devices are located; The semiconductor chip includes at least one of the following: GaN-based field-effect transistors (FETs) and GaN-based high electron mobility transistors (HEMTs); and The semiconductor chip includes at least one secondary device region, which includes one or more of the following: an input matching circuit, an output matching circuit, an intermediate matching circuit, a harmonic termination circuit, and a matching network.

115. The semiconductor device according to claim 90, wherein: The semiconductor chip includes at least one active region, which is a region where one or more semiconductor devices are located; and The semiconductor chip includes at least one of the following: metal-semiconductor field-effect transistor (MESFET), metal-oxide field-effect transistor (MOSFET), junction field-effect transistor (JFET), bipolar junction transistor (BJT), laterally diffused metal-oxide semiconductor (LDMOS), insulated gate bipolar transistor (IGBT), high electron mobility transistor (HEMT), and wide bandgap semiconductor (WBG).

116. The semiconductor device of claim 90, wherein, The semiconductor chip includes at least one secondary device region, which includes one or more of the following: resistors, inductors, capacitors, input matching circuits, output matching circuits, intermediate matching circuits, harmonic filters, harmonic terminations, couplers, baluns, power combiners, power dividers, radio frequency (RF) circuits, radial stub circuits, transmission line circuits, baseband matching circuits, baseband termination circuits, second harmonic termination circuits, integrated passive device (IPD), and matching networks.

117. The semiconductor device of claim 90, wherein, The support includes at least one of the following: an encapsulation support, a metal base, a flange, a heat sink, and a lead frame.

118. The semiconductor device of claim 90, wherein, The chip attachment material includes one or more metallic materials and one or more non-metallic materials.

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