camera device

Abstract

An imaging device according to one aspect of the present disclosure includes a first electrode, a second electrode, a photoelectric conversion layer, a substrate, and a through electrode. The photoelectric conversion layer is positioned between the first electrode and the second electrode and converts light into electric charges. The substrate includes a through-hole and a first transistor. The first transistor includes a first impurity region functioning as one of a source and a drain, a second impurity region functioning as the other of the source and the drain, and a first gate electrode. The first impurity region includes a charge accumulation region that accumulates the electric charges. The through electrode is provided in the through-hole and electrically connects the first electrode and the charge accumulation region. In a plan view, the distance between the charge accumulation region and the through electrode is longer than the distance between the second impurity region and the through electrode.

Description

Technical Field

[0001] This disclosure relates to camera devices. Background Technology

[0002] CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used in digital cameras and other applications. These image sensors have photodiodes formed on a semiconductor substrate.

[0003] Patent documents 1 and 2 disclose a structure in which a photoelectric conversion unit having a photoelectric conversion layer is disposed above a semiconductor substrate. Imaging devices with such a structure are sometimes referred to as stacked imaging devices. In stacked imaging devices, the charge generated by photoelectric conversion is stored in a charge storage region. A signal corresponding to the amount of charge stored in the charge storage region is read out via a CCD circuit or a CMOS circuit formed on the semiconductor substrate.

[0004] Patent Document 3 discloses a back-illuminated imaging device. In the imaging device of Patent Document 3, a photodiode is formed within a semiconductor substrate. Furthermore, in the imaging device of Patent Document 3, a photoelectric conversion unit having a photoelectric conversion layer is provided on the light-receiving surface side of the semiconductor substrate, which is the back side.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: International Publication No. 2014 / 002330

[0008] Patent Document 2: International Publication No. 2012 / 147302

[0009] Patent Document 3: International Publication No. 2015 / 025723 Summary of the Invention

[0010] The problem that the invention aims to solve

[0011] This disclosure provides techniques suitable for suppressing leakage current into charge accumulation regions.

[0012] Methods used to solve problems

[0013] This disclosure provides an imaging device comprising: a first electrode; a second electrode; a photoelectric conversion layer located between the first electrode and the second electrode, for converting light into charge; a substrate including a through-hole and a first transistor, the first transistor including a first impurity region functioning as one of a source and a drain, a second impurity region functioning as the other of the source and the drain, and a first gate electrode, the first impurity region including a charge accumulation region for accumulating the charge; and a through electrode disposed within the through-hole, electrically connecting the first electrode and the charge accumulation region, wherein in a plan view, the distance between the charge accumulation region and the through electrode is longer than the distance between the second impurity region and the through electrode.

[0014] Invention Effects

[0015] The techniques disclosed herein are suitable for suppressing leakage current into charge accumulation regions. Attached Figure Description

[0016] Figure 1 This is a diagram illustrating an exemplary structure of the camera device according to the first embodiment of this disclosure.

[0017] Figure 2 This is a diagram illustrating an exemplary circuit structure of the camera device according to the first embodiment of the present disclosure.

[0018] Figure 3 This is a schematic top view illustrating the exemplary structure of the pixels in relation to the first embodiment of this disclosure.

[0019] Figure 4 This is a schematic cross-sectional view illustrating the exemplary structure of the pixels in relation to the first embodiment of this disclosure.

[0020] Figure 5 This is a diagram illustrating an example of an electrical path that runs through the electrode, the charge accumulation region, and the periphery of the gate electrode.

[0021] Figure 6 This is a diagram illustrating an example of an electrical path that runs through the electrode, the charge accumulation region, and the periphery of the gate electrode.

[0022] Figure 7 This is a diagram illustrating an example of an electrical path that runs through the electrode, the charge accumulation region, and the periphery of the gate electrode.

[0023] Figure 8 This is a diagram illustrating an example of an electrical path that runs through the electrode, the charge accumulation region, and the periphery of the gate electrode.

[0024] Figure 9 This is a diagram illustrating an example of a direct connection between a through electrode and an electrode structure.

[0025] Figure 10 This is a diagram illustrating an exemplary circuit structure of the camera device according to the second embodiment of the present disclosure.

[0026] Figure 11 This is a schematic top view illustrating the exemplary structure of the pixels in relation to the second embodiment of this disclosure.

[0027] Figure 12 This is a schematic cross-sectional view illustrating the exemplary structure of the pixels in relation to the second embodiment of this disclosure.

[0028] Figure 13 This is a diagram illustrating an exemplary circuit structure of the camera device according to the third embodiment of the present disclosure.

[0029] Figure 14 This is a schematic top view illustrating the exemplary structure of the pixels in relation to the third embodiment of this disclosure.

[0030] Figure 15 This is a schematic cross-sectional view illustrating the exemplary structure of the pixels in relation to the third embodiment of this disclosure.

[0031] Figure 16 This is a diagram illustrating an exemplary circuit structure of the camera device according to the fourth embodiment of the present disclosure.

[0032] Figure 17 This is a schematic top view illustrating the exemplary structure of the pixels in relation to the fourth embodiment of this disclosure.

[0033] Figure 18 This is a schematic cross-sectional view illustrating the exemplary structure of the pixels in relation to the fourth embodiment of this disclosure.

[0034] Figure 19 This is a diagram illustrating an exemplary circuit structure of the camera device according to the fifth embodiment of this disclosure.

[0035] Figure 20 This is a schematic top view illustrating the exemplary structure of the pixels in relation to the fifth embodiment of this disclosure.

[0036] Figure 21 This is a schematic cross-sectional view illustrating the exemplary structure of the pixels in relation to the fifth embodiment of this disclosure.

[0037] Figure 22 This is a diagram illustrating an exemplary structure of a photoelectric conversion stack.

[0038] Figure 23 This is a diagram illustrating an exemplary structure of a photoelectric conversion stack. Detailed Implementation

[0039] (Based on the understanding that forms the basis of this disclosure)

[0040] In stacked camera devices, leakage current can occur in areas where charge accumulates. This leakage current can degrade the image.

[0041] This disclosure provides techniques suitable for suppressing leakage current into charge accumulation regions.

[0042] (Summary of a technical solution related to this disclosure)

[0043] The imaging device according to the first technical solution of this disclosure includes: a first electrode; a second electrode; a photoelectric conversion layer located between the first electrode and the second electrode, which converts light into charge; a substrate including a through-hole and a first transistor, the first transistor including a first impurity region functioning as one of the source and drain, a second impurity region functioning as the other of the source and drain, and a first gate electrode, the first impurity region including a charge accumulation region for accumulating the charge; and a through electrode disposed in the through-hole, electrically connecting the first electrode and the charge accumulation region. In a plan view, the distance between the charge accumulation region and the through electrode is longer than the distance between the second impurity region and the through electrode.

[0044] The technology of the first technical solution is suitable for suppressing leakage current into the charge accumulation region.

[0045] In the second technical solution of this disclosure, for example in the imaging device of the first technical solution, in a plan view, the first gate electrode may also be located between the through electrode and the charge accumulation region.

[0046] The technology of the second technical solution is suitable for suppressing leakage current into the charge accumulation region.

[0047] In the third technical solution of this disclosure, for example, the imaging device of the first or second technical solution may also include a second transistor, which includes a second gate electrode electrically connected to the charge accumulation region. In a plan view, the distance between the charge accumulation region and the through electrode may be longer than the distance between the second gate electrode and the through electrode.

[0048] The third technical solution is suitable for suppressing leakage current to the charge accumulation region and suppressing noise in the electrical path between the second gate electrode and the through electrode of the second transistor.

[0049] In the fourth technical solution of this disclosure, for example in the imaging device relating to any of the first to third technical solutions, the area of ​​the charge accumulation region in the plan view may also be smaller than the area of ​​the second impurity region.

[0050] The technology of the fourth technical solution is suitable for suppressing leakage current into the charge accumulation region.

[0051] In the fifth technical solution of this disclosure, for example, the camera device of any of the first to fourth technical solutions may also include a first electrical path that electrically connects the through electrode to the charge accumulation region. In a plan view, at least a portion of the first electrical path may be bent.

[0052] According to the fifth technical solution, the degree of freedom in the layout of electrical paths can be increased.

[0053] In the sixth technical solution of this disclosure, for example, the camera device of the fifth technical solution may also have a gate wiring electrically connected to the first gate electrode. When the combination of the first gate electrode and the gate wiring is defined as the second electrical path, in the plan view, the first electrical path may also bypass the second electrical path.

[0054] According to the sixth technical solution, the coupling between the first electrical path and the second electrical path can be suppressed.

[0055] In the seventh technical solution of this disclosure, for example, the imaging device of any one of the first to fourth technical solutions may also include: a first electrical path that electrically connects the through electrode to the charge storage region; and a gate wiring that is connected to the first gate electrode. When the combination of the first gate electrode and the gate wiring is defined as the second electrical path, in a plan view, at least a portion of the first electrical path may be repeated with at least a portion of the second electrical path.

[0056] According to the seventh technical solution, coupling between the first electrical path and the second electrical path can be generated.

[0057] In the eighth technical solution of this disclosure, for example in the imaging device relating to any of the first to seventh technical solutions, in a plan view, at least a portion of the first electrode may overlap with at least a portion of the charge accumulation region.

[0058] According to the eighth technical solution, the first electrode can suppress the irradiation of light toward the charge accumulation region.

[0059] In the ninth technical solution of this disclosure, for example in the imaging device of any of the first to eighth technical solutions, the first transistor may also be a reset transistor that resets the potential of the charge accumulation region.

[0060] The reset transistor in the ninth technical solution is a specific example of the first transistor.

[0061] The imaging device of the tenth technical solution of this disclosure is an imaging device having multiple pixels, each of the multiple pixels comprising: a first electrode; a second electrode; a photoelectric conversion layer located between the first electrode and the second electrode, which converts light into charge; a substrate including a through-hole and a first transistor, one of the source and drain of the first transistor including a charge accumulation region for accumulating the charge; and a through electrode disposed in the through-hole, electrically connecting the first electrode and the charge accumulation region. In each of the multiple pixels, in a planar view, the distance between the charge accumulation region and the through electrode is longer than the distance between the other of the source and drain of the first transistor and the through electrode.

[0062] According to the 10th technical solution, the effect of the 1st technical solution can be obtained in multiple pixels.

[0063] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, the present disclosure is not limited to these embodiments.

[0064] In this manual, the terms "above", "below", "upper surface" and "lower surface" are used only to specify the mutual configuration between components and are not intended to limit the posture of the camera device during use.

[0065] A comprehensive or specific technical solution can also be implemented by components, devices, modules, systems, or methods. Furthermore, a comprehensive or specific technical solution can also be implemented by any combination of components, devices, modules, systems, and methods.

[0066] The additional effects and advantages of the disclosed embodiments will become clear from the description and accompanying drawings. The effects and advantages are provided individually by the various embodiments or features disclosed in the description and accompanying drawings, and not all of them are necessary to obtain more than one of them.

[0067] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, the embodiments described below are inclusive or specific examples. The numerical values, shapes, materials, constituent elements, arrangement and connection methods of constituent elements, steps, and order of steps shown in the following embodiments are examples and are not intended to limit the present disclosure. Various forms described in this specification can be combined with each other as long as they do not contradict each other. In addition, constituent elements in the following embodiments that are not described in the independent claims representing the highest-level concept are described as arbitrary constituent elements. In the following description, constituent elements having substantially the same function are indicated by common reference numerals, and descriptions may be omitted in some cases. Furthermore, to avoid making the drawings overly complex, illustrations of some elements may be omitted in some cases.

[0068] (First Embodiment)

[0069] Figure 1 The exemplary structure of the camera device according to the first embodiment of this disclosure is shown. Figure 1 The camera device 100 shown has a plurality of pixels 10 formed on a semiconductor substrate 1 and peripheral circuitry.

[0070] Each pixel 10 includes a photoelectric conversion unit 12. The photoelectric conversion unit 12 receives incident light and generates positive and negative charges, typically generating electron-hole pairs. The photoelectric conversion unit 12 may be a photoelectric conversion structure including a photoelectric conversion layer disposed above the semiconductor substrate 1. Furthermore, in Figure 1 The photoelectric conversion units 12 of each pixel 10 are shown to be spatially separated from each other, but this is only for the sake of explanation. It is also possible that the photoelectric conversion units 12 of multiple pixels 10 are arranged continuously on the semiconductor substrate 1 without spacing between them.

[0071] exist Figure 1 In the example shown, pixels 10 are arranged in multiple rows and columns of m rows and n columns. Here, m and n independently represent integers greater than 1. Pixels 10 are arranged, for example, in two dimensions on the semiconductor substrate 1, thereby forming an imaging area R1. When each pixel 10 has a photoelectric conversion structure as a photoelectric conversion unit 12 above the semiconductor substrate 1, the imaging area R1 can be defined as the area in the semiconductor substrate 1 covered by the photoelectric conversion structure.

[0072] The number and arrangement of pixels 10 are not limited to the example shown. For example, the imaging device 100 may contain only one pixel 10. In this example, the center of each pixel 10 is located at a grid point of a square grid. For example, multiple pixels 10 may be arranged such that the center of each pixel 10 is located at a grid point of a triangular grid, hexagonal grid, etc. For example, by arranging the pixels 10 in one dimension, the imaging device 100 can be used as a line sensor.

[0073] exist Figure 1 In the illustrated structure, the peripheral circuitry includes a vertical scanning circuit 52 and a horizontal signal readout circuit 54. For example... Figure 1 As illustrated, the peripheral circuitry may additionally include control circuitry 56 and voltage supply circuitry 58. The peripheral circuitry may also include signal processing circuitry, output circuitry, etc. Figure 1 In the example shown, the peripheral circuitry includes circuits disposed on the semiconductor substrate 1. However, a portion of the peripheral circuitry may also be disposed on a different substrate than the semiconductor substrate 1 on which the pixel 10 is formed.

[0074] The vertical scanning circuit 52, also known as the row scanning circuit, is connected to the address signal lines 44, which are arranged corresponding to each row of the plurality of pixels 10. As will be described later, the signal lines arranged corresponding to each row of the plurality of pixels 10 are not limited to the address signal lines 44; various signal lines can be connected to the vertical scanning circuit 52 for each row of the plurality of pixels 10. The horizontal signal readout circuit 54, also known as the column scanning circuit, is connected to the vertical signal lines 45, which are arranged corresponding to each column of the plurality of pixels 10.

[0075] The control circuit 56 receives instruction data, clock signals, etc., from external sources from the imaging device 100 and controls the imaging device 100 as a whole. Typically, the control circuit 56 has a timing generator that supplies drive signals to the vertical scanning circuit 52, the horizontal signal readout circuit 54, the voltage supply circuit 58, etc. Figure 1 In the diagram, arrows extending from control circuit 56 schematically represent the flow of output signals from control circuit 56. Control circuit 56 can be implemented by, for example, a microcontroller including one or more processors. The function of control circuit 56 can be implemented either through a combination of general-purpose processing circuitry and software, or through hardware customized for such processing.

[0076] The voltage supply circuit 58 supplies a predetermined voltage to each pixel 10 via voltage line 48. The voltage supply circuit 58 is not limited to a specific power supply circuit; it can be a circuit that converts the voltage supplied from a power source such as a battery into the predetermined voltage, or it can be a circuit that generates the predetermined voltage. The voltage supply circuit 58 can also be part of the aforementioned vertical scanning circuit 52. For example, in... Figure 1 As illustrated in the diagram, these circuits constituting the peripheral circuits are arranged in the peripheral region R2 outside the camera region R1.

[0077] Figure 2 The schematic diagram illustrates an exemplary circuit structure of the imaging device according to the first embodiment of this disclosure. Figure 2In the image, to avoid making the drawing too complex, four pixels (10A) arranged in a 2x2 grid are represented as an example. These pixels (10A) are... Figure 1 One example of pixel 10 shown includes a signal detection circuit 60 electrically connected to a photoelectric conversion unit 12, which is a photoelectric conversion structure. As will be described in detail below with reference to the accompanying drawings, the photoelectric conversion structure includes a photoelectric conversion layer disposed above the semiconductor substrate 1. That is, a stacked type imaging device is illustrated here as an imaging device 100. Furthermore, a back-illuminated type imaging device is illustrated here as an imaging device 100.

[0078] The vertical scanning circuit 52 is connected to the counter electrode power supply line 21. In this embodiment, the counter electrode power supply line 21 can also be referred to as the accumulation control line.

[0079] The photoelectric conversion unit 12, which is the photoelectric conversion structure of each pixel 10A, is connected to the counter electrode power supply line 21. When the imaging device 100 is operated, a predetermined voltage is applied to the counter electrode power supply line 21. For example, if the positive charge among the positive and negative charges generated by photoelectric conversion is used as the signal charge, then when the imaging device 100 is operated, a positive voltage of about 10V is applied to the counter electrode power supply line 21. In this embodiment, the case where holes are used as the signal charge is exemplified.

[0080] exist Figure 2 In the illustrated structure, one opposing electrode power line 21 is connected to a plurality of pixels 10A belonging to one row. However, it is also possible for one opposing electrode power line 21 to be connected to a plurality of pixels 10A belonging to multiple rows. Furthermore, it is also possible for one opposing electrode power line 21 to be connected to all the pixels 10A in the imaging device 100.

[0081] exist Figure 2 In the illustrated structure, the signal detection circuit 60 includes a signal detection transistor 22, an address transistor 24, and a reset transistor 26. Alternatively, the signal detection transistor 22 can also be referred to as an amplification transistor.

[0082] The signal detection transistor 22, address transistor 24, and reset transistor 26 are typically field-effect transistors formed on the semiconductor substrate 1 that supports the photoelectric conversion section 12, which is a photoelectric conversion structure. Hereinafter, unless otherwise specified, examples of using an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as a transistor will be described.

[0083] As in Figure 2As schematically shown, the gate electrode 22e of the signal detection transistor 22 is electrically connected to the charge storage region FD and the photoelectric conversion unit 12. By applying a predetermined voltage to the counter electrode power supply line 21 during operation, holes can be stored as signal charges in the charge storage region FD. Figure 2 In the illustrated structure, the charge storage region FD is an impurity region formed on the semiconductor substrate 1. In the illustrated example, the charge storage region FD has the function of temporarily retaining the charge generated by the photoelectric conversion unit 12. Alternatively, the charge storage region FD can also be referred to as a floating diffusion region.

[0084] The drain of the signal detection transistor 22 is connected to the power supply line 42, which supplies a power supply voltage VDD of, for example, about 3.3V to each pixel 10A when the imaging device 100 is operating. The source is connected to the vertical signal line 45 via the address transistor 24. By receiving the power supply voltage VDD at its drain, the signal detection transistor 22 outputs a signal voltage corresponding to the amount of signal charge stored in the charge storage region FD.

[0085] The address signal line 44 is connected to the gate electrode 24e of the address transistor 24, which connects the signal detection transistor 22 and the vertical signal line 45. Therefore, the vertical scan circuit 52 can read the output of the signal detection transistor 22 of the selected pixel 10A to the corresponding vertical signal line 45 by applying a row selection signal to the address signal line 44 to control the on / off state of the address transistor 24. Furthermore, the configuration of the address transistor 24 is not limited to… Figure 2 The example shown could also be between the drain of the signal detection transistor 22 and the power supply wiring 42.

[0086] A reset signal line 47, which is connected to the vertical scan circuit 52, is connected to the gate electrode 26e of the reset transistor 26. The reset signal line 47, like the address signal line 44, is arranged for each row of the plurality of pixels 10A. The vertical scan circuit 52 enables the reset transistor 26 to conduct by applying a reset signal, which controls the on / off state of the reset transistor 26, to the gate electrode 26e of the reset transistor 26 via the reset signal line 47. With the reset transistor 26 conducting, the potential of the charge accumulation region FD is reset.

[0087] (Device structure of pixel 10A)

[0088] Figure 3 This is an example of the layout of the elements in pixel 10A. Figure 4 This schematically illustrates an example of the device construction of pixel 10A. Figure 3 Indicatively representing Figure 4The image shows the arrangement of the elements formed on the semiconductor substrate 1 when viewed along the normal direction of the semiconductor substrate 1. If viewed along... Figure 3 If the IV-IV dashed line in the diagram cuts off pixel 10A and is then unfolded, we can obtain... Figure 4 The cross-section shown.

[0089] The term "first conductivity type" will be used in the following instances. In this embodiment, the first conductivity type is n-type. The second conductivity type is p-type. However, the first conductivity type can also be p-type. The second conductivity type can also be n-type.

[0090] exist Figure 3 and Figure 4 In this design, pixel 10A includes an insulating layer 71, an insulating layer 70, a semiconductor substrate 1, a photoelectric conversion unit 12, an insulating layer 31, and a microlens 30. The insulating layers 71, 70, 1, 12, 31, and 30 are stacked sequentially. Specifically, they are stacked along the thickness direction of the semiconductor substrate 1. Furthermore, pixel 10A includes a through electrode 81, a dielectric layer 32, and a fixed charge layer 33.

[0091] The semiconductor substrate 1 is, for example, a silicon substrate. The semiconductor substrate 1 has a first main surface 1A and a second main surface 1B. The first main surface 1A is the side on which light is incident. The second main surface 1B is the side opposite to the side on which light is incident. In this embodiment, the first main surface 1A and the second main surface 1B are perpendicular to the thickness direction of the semiconductor substrate 1.

[0092] exist Figure 4 In the example shown, the semiconductor substrate 1 has an impurity region 1i. The impurity region 1i can be, for example, a p+ region or an n+ region. "+" indicates a high concentration of p-type or n-type impurities. The impurity region 1i has a first main surface 1A.

[0093] A reset transistor 26, a signal detection transistor 22, and an address transistor 24 are provided on the semiconductor substrate 1. Specifically, the reset transistor 26, the signal detection transistor 22, and the address transistor 24 are disposed on the second main surface 1B.

[0094] In this embodiment, the reset transistor 26, the signal detection transistor 22, and the address transistor 24 are MOSFETs. Specifically, the reset transistor 26, the signal detection transistor 22, and the address transistor 24 are N-channel MOSFETs.

[0095] The reset transistor 26 includes a first diffusion region 67n, which is an example of a first impurity region, serving as one of the source and drain. The reset transistor 26 also includes a second diffusion region 68an, which is an example of a second impurity region, serving as the other of the source and drain. Furthermore, the reset transistor 26 includes a gate electrode 26e and an insulating layer 70. The insulating layer 70 is sandwiched between the gate electrode 26e and the semiconductor substrate 1. The reset transistor 26 is an example of a first transistor.

[0096] The signal detection transistor 22 includes a third diffusion region 68bn as one of the source and drain. The signal detection transistor 22 also includes a fourth diffusion region 68cn as the other of the source and drain. Furthermore, the signal detection transistor 22 includes a gate electrode 22e and an insulating layer 70. The insulating layer 70 is sandwiched between the gate electrode 22e and the semiconductor substrate 1. The signal detection transistor 22 is an example of a second transistor.

[0097] Address transistor 24 includes a fourth diffusion region 68cn as one of the source and drain. Address transistor 24 includes a fifth diffusion region 68dn as the other of the source and drain. Furthermore, address transistor 24 includes a gate electrode 24e and an insulating layer 70. The insulating layer 70 is sandwiched between the gate electrode 24e and the semiconductor substrate 1.

[0098] The first diffusion region 67n, the second diffusion region 68an, the third diffusion region 68bn, the fourth diffusion region 68cn, and the fifth diffusion region 68dn are located in the semiconductor substrate 1. The first diffusion region 67n, the second diffusion region 68an, the third diffusion region 68bn, the fourth diffusion region 68cn, and the fifth diffusion region 68dn contain impurities of the first conductivity type.

[0099] The first diffusion region 67n corresponds to the charge accumulation region FD. The first diffusion region 67n accumulates the photocharge converted by the photoelectric conversion unit 12. The fourth diffusion region 68cn is shared by the signal detection transistor 22 and the address transistor 24.

[0100] In this embodiment, the first diffusion region 67n is the drain of the reset transistor 26. The second diffusion region 68an is the source of the reset transistor 26. The third diffusion region 68bn is the drain of the signal detection transistor 22. The fourth diffusion region 68cn is the source of the signal detection transistor 22 and also the drain of the address transistor 24. The fifth diffusion region 68dn is the source of the address transistor 24.

[0101] The photoelectric conversion unit 12 includes a pixel electrode 13, a photoelectric conversion layer 14, and a counter electrode 15. The counter electrode 15 is opposite to the pixel electrode 13. The photoelectric conversion layer 14 is disposed between the pixel electrode 13 and the counter electrode 15.

[0102] The photoelectric conversion layer 14 has a film shape. The photoelectric conversion layer 14 comprises at least one material selected from the group consisting of organic and inorganic materials. Amorphous silicon is exemplified as an inorganic material. The photoelectric conversion layer 14 receives light incident via the counter electrode 15 and generates positive and negative charges through photoelectric conversion. The photoelectric conversion layer 14 is typically formed across multiple pixels 10A. The photoelectric conversion layer 14 may also comprise layers composed of organic materials and layers composed of inorganic materials.

[0103] The counter electrode 15 is a transparent electrode. Specifically, the counter electrode 15 comprises a transparent conductive material such as ITO (Indium Tin Oxide). The counter electrode 15 is disposed on the light-receiving side of the photoelectric conversion layer 14. Typically, the counter electrode 15 is formed across multiple pixels 10A, just like the photoelectric conversion layer 14.

[0104] exist Figure 4 The diagram is omitted, but the counter electrode 15 is connected to the aforementioned counter electrode power line 21. When the imaging device 100 is operating, by controlling the potential of the counter electrode power line 21, the potential of the counter electrode 15 is made different from the potential of the pixel electrode 13, allowing the pixel electrode 13 to collect the signal charge generated by photoelectric conversion. For example, the potential of the counter electrode power line 21 is controlled so that the potential of the counter electrode 15 is higher than the potential of the pixel electrode 13. Specifically, for example, a positive voltage of approximately 10V is applied to the counter electrode power line 21. Thus, the pixel electrode 13 can collect holes from the hole-electron pairs generated by the photoelectric conversion layer 14. The signal charge collected by the pixel electrode 13 is accumulated in the first diffusion region 67n via the through electrode 81 and the wiring structure 80.

[0105] The pixel electrode 13 may contain at least one material selected from the group consisting of metal, metal nitride, and polysilicon. Examples of metals include titanium and tantalum. Examples of metal nitrides include titanium nitride and tantalum nitride. Examples of polysilicon are polysilicon that has been made conductive by doping with impurities. The pixel electrode 13 is spatially separated from the pixel electrodes 13 of other adjacent pixels 10A and is electrically separated from the pixel electrodes 13 of other pixels 10A.

[0106] The microlens 30 has a light-focusing function. Light incident on the microlens 30 is supplied to the photoelectric conversion unit 12. The photoelectric conversion unit 12 converts the supplied light into electric charge.

[0107] An insulating layer 31 is disposed between the microlens 30 and the photoelectric conversion unit 12. The insulating layer 31 functions as a protective layer for the photoelectric conversion unit 12. The insulating layer 31 has a film shape.

[0108] A wiring structure 80 is provided within the insulating layer 71. Figure 4In the example shown, the wiring structure 80 includes a first wiring layer 80a, a second wiring layer 80b, and a third wiring layer 80c.

[0109] The first wiring layer 80a, the second wiring layer 80b, and the third wiring layer 80c typically contain at least one metal selected from the group consisting of metals and metal compounds. Examples of metals include copper and tungsten. Examples of metal compounds include metal nitrides and metal oxides.

[0110] Within the insulating layer 71, there are first contact plugs cp1, second contact plugs cp2, third contact plugs cp3, and fourth contact plugs cp4. Furthermore, within the insulating layer 71, there are gate electrodes 26e, 22e, and 24e.

[0111] Typically, the first contact plug cp1, the second contact plug cp2, the third contact plug cp3, and the fourth contact plug cp4 contain semiconductor materials. In this embodiment, the first contact plug cp1, the second contact plug cp2, the third contact plug cp3, and the fourth contact plug cp4 are polycrystalline silicon layers doped with impurities of a first conductivity type. However, the semiconductor materials contained in the first contact plug cp1, the second contact plug cp2, the third contact plug cp3, and the fourth contact plug cp4 can also be polycrystalline silicon, germanium, etc. The first contact plug cp1, the second contact plug cp2, the third contact plug cp3, and the fourth contact plug cp4 can also contain metal along with or instead of semiconductor materials.

[0112] If the first contact plug cp1 contains a semiconductor material, alloying reactions are less likely to occur at the interface between the charge accumulation region FD and the first contact plug cp1. This reduces the likelihood of crystal defects that may occur at the contact portion between the charge accumulation region FD and the first contact plug cp1, thereby reducing noise.

[0113] In this embodiment, the conductivity type of the charge accumulation region FD is the same as that of the semiconductor material contained in the first contact plug cp1. This reduces the likelihood of a potential difference between the charge accumulation region FD and the first contact plug cp1. Therefore, the contact resistance between the charge accumulation region FD and the first contact plug cp1 can be reduced.

[0114] A through-hole 82 is provided in the semiconductor substrate 1. Specifically, openings are provided on the first main surface 1A and the second main surface 1B of the semiconductor substrate 1, and the through-hole 82 connects these openings. Furthermore, the through-hole 82 extends along the thickness direction of the semiconductor substrate 1.

[0115] A through electrode 81 is provided within the through hole 82. The through electrode 81 can electrically connect elements that are electrically separated in the thickness direction of the semiconductor substrate 1 to each other through the semiconductor substrate 1.

[0116] The through electrode 81 typically contains at least one material selected from the group consisting of metals and metal compounds. Examples of metals include copper and tungsten. Examples of metal compounds include metal nitrides and metal oxides. However, the through electrode 81 may also contain the same semiconductor material as the semiconductor substrate 1, with impurities of a first conductivity type or a second conductivity type implanted. Examples of semiconductor materials that may be contained in the semiconductor substrate 1 and the through electrode 81 include silicon, polysilicon, and germanium.

[0117] In one specific example, the pixel electrode 13 contains at least one of titanium nitride and tantalum nitride, and the through electrode 81 contains copper. In this specific example, the copper originating from the through electrode 81 does not readily diffuse in the pixel electrode 13.

[0118] The pixel electrode 13, the through electrode 81, the second contact plug cp2, the first wiring layer 80a, the first contact plug cp1, and the charge storage region FD are electrically connected in sequence. Therefore, signal charge can be transferred from the pixel electrode 13 to the charge storage region FD via the through electrode 81, the second contact plug cp2, the first wiring layer 80a, and the first contact plug cp1. In this embodiment, holes, which are signal charges, can be transferred from the pixel electrode 13 to the charge storage region FD via the through electrode 81, the second contact plug cp2, the first wiring layer 80a, and the first contact plug cp1.

[0119] The charge storage region FD, the first contact plug cp1, the first wiring layer 80a, the third contact plug cp3, and the gate electrode 22e of the signal detection transistor 22 are electrically connected in sequence. Therefore, signal charge can be transferred from the charge storage region FD through the first contact plug cp1, the first wiring layer 80a, and the third contact plug cp3 to the gate electrode 22e.

[0120] The second diffusion region 68an and the fourth contact plug cp4 are electrically connected. Therefore, charge can flow between the second diffusion region 68an and the fourth contact plug cp4. Furthermore, the wiring connected to the fourth contact plug cp4 is omitted from the diagram.

[0121] The dielectric layer 32 is insulating. The dielectric layer 32 includes a first flat film portion 32A and a first cylindrical portion 32B. The first flat film portion 32A is disposed between the first main surface 1A and the pixel electrode 13. The first cylindrical portion 32B is disposed in a manner that surrounds the through electrode 81.

[0122] The dielectric layer 32 may include, for example, at least one selected from the group consisting of a silicon oxide film, a silicon nitride film, and a silicon oxide nitride film. The dielectric layer 32 may also include TEOS.

[0123] The fixed charge layer 33 has a fixed charge. The fixed charge layer 33 includes a second flat film portion 33A and a second cylindrical portion 33B. The second flat film portion 33A is disposed between the first main surface 1A and the first flat film portion 32A. The second cylindrical portion 33B is disposed in a manner that surrounds the first cylindrical portion 32B.

[0124] The fixed charge layer 33 can have either a positive or a negative fixed charge. Examples of materials that can be used for a layer with a negative fixed charge include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, titanium oxide, lanthanum oxide, praseodymium oxide, cerium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, thulium oxide, ytterbium oxide, lutetium oxide, yttrium oxide, aluminum nitride, hafnium oxynitride, or aluminum oxynitride. The fixed charge layer 33 can also be a stack of two or more layers.

[0125] As can be understood from the above description, in this embodiment, the imaging device 100 includes a pixel 10A. The pixel 10A has a pixel electrode 13 as a first electrode, a counter electrode 15 as a second electrode, a photoelectric conversion layer 14, a semiconductor substrate 1 as a substrate, and a through electrode 81. The photoelectric conversion layer 14 is located between the first electrode 13 and the second electrode 15. The photoelectric conversion layer 14 converts light into electrical charge. The semiconductor substrate 1 has a through hole 82 and a reset transistor 26 as a first transistor. A first diffusion region 67n, which is one of the source and drain of the reset transistor 26, includes a charge accumulation region FD for accumulating charge. The through electrode 81 is disposed in the through hole 82. The through electrode 81 electrically connects the pixel electrode 13 to the charge accumulation region FD.

[0126] The following describes the embodiment of "the through electrode 81 being disposed in the through hole 82". This embodiment includes the following concepts: with respect to the direction in which the through hole 82 extends, the through electrode 81 extends within the through hole 82 in a range shorter than the through hole 82. This embodiment also includes the following concepts: with respect to the direction in which the through hole 82 extends, the range in which the through electrode 81 extends is the same as the range in which the through hole 82 extends. Furthermore, this embodiment includes the following concepts: with respect to the direction in which the through hole 82 extends, the through electrode 81 extends out of the through hole 82. In this embodiment, it can also be described as "the through electrode 81 extending in a region including at least a portion of the through hole 82".

[0127] The following describes the behavior of "the through electrode 81 electrically connecting the pixel electrode 13 to the charge accumulation region FD". This behavior includes the concept of the through electrode 81 electrically connecting the pixel electrode 13 to the charge accumulation region FD only. The behavior also includes the concept of the through electrode 81 and one or more other components electrically connecting the pixel electrode 13 to the charge accumulation region FD. The same applies to other similar behaviors.

[0128] In this embodiment, the substrate corresponds to the semiconductor substrate 1. The first electrode corresponds to the pixel electrode 13. The second electrode corresponds to the counter electrode 15. The first transistor corresponds to the reset transistor 26. The reset transistor 26 resets the potential of the charge accumulation region FD.

[0129] In this embodiment, such as Figure 3 As shown in the planar diagram, the distance L1 between the charge accumulation region FD and the through electrode 81 is longer than the distance L2 between the second diffusion region 68an (which is the source and drain of the reset transistor 26) and the through electrode 81. L1 > L2 is suitable for suppressing leakage current into the charge accumulation region FD. Furthermore, leakage current can also be referred to as dark current.

[0130] In this embodiment, the first diffusion region 67n, which is one of the source and drain of the reset transistor 26, is the charge accumulation region FD.

[0131] The following explains why L1>L2 is suitable for suppressing leakage current in the charge accumulation region FD.

[0132] Typically, crystal defects are present in the portion surrounding the through-hole 82 of the substrate. Crystal defects can cause leakage current to the charge accumulation region FD. Crystal defects can occur for various reasons.

[0133] In one example, the substrate is a silicon semiconductor substrate 1, and a through-hole 82 is formed on the semiconductor substrate 1 by plasma etching. In this example, the area surrounding the through-hole 82 of the semiconductor substrate 1 is exposed to plasma during the formation of the through-hole 82. Therefore, the crystal structure of silicon atoms in this area is disrupted by energetic ions, and the area suffers physical damage. Thus, crystal defects may occur in the aforementioned area. Furthermore, in this example, a portion of the constituent elements of the etching gas may be introduced into the semiconductor substrate 1 through ion collisions. Crystal defects may also occur due to elements introduced in this way. In one specific example, the etching gas contains fluorine. SiF is formed by the reaction of fluorine with the silicon of the semiconductor substrate 1, thereby advancing the etching process. During this etching, fluorine may be introduced into the area surrounding the through-hole 82 of the semiconductor substrate 1. The fluorine diffuses during the heat treatment after etching. This means that crystal defects introduced by fluorine can easily become a cause of leakage current to the charge accumulation region FD.

[0134] However, when L1 > L2, it is easy to ensure the distance between the region containing crystal defects and the charge accumulation region FD. This is advantageous from the viewpoint of suppressing the PN junction leakage current to the charge accumulation region FD caused by crystal defects.

[0135] The following is an explanation of the terms associated with L1>L2.

[0136] In this embodiment, "top view" refers to the view taken along the thickness direction of the semiconductor substrate 1. The thickness direction of the semiconductor substrate 1 can also be referred to as the normal direction of the semiconductor substrate 1.

[0137] In the first definition of this embodiment, distance L1 is the distance between the geometric center of the charge accumulation region FD in the planar view and the geometric center of the through electrode 81. Distance L2 is the distance between the geometric center of the second diffusion region 68an, which is the other of the source and drain of the reset transistor 26, and the geometric center of the through electrode 81 in the planar view.

[0138] As described above, the charge accumulation region FD, the source, and the drain are diffusion regions. In the first definition of this embodiment, it is assumed that the boundary of the diffusion region is a junction. The junction is the portion where the concentration of N-type impurities is equal to the concentration of P-type impurities. In the first definition of this embodiment, the geometric center of the diffusion region in the plan view is set based on the idea of ​​such a boundary. The idea of ​​the geometric center of the diffusion region is the same in the following description.

[0139] In the second definition of this embodiment, distance L1 is the distance between the geometric center of the contact surface between the charge accumulation region FD and the electrode connected to the charge accumulation region FD in the planar diagram, and the geometric center of the through electrode 81. Figure 4 In the example shown, the electrode connected to the charge accumulation region FD is formed by the first contact plug cp1. Distance L2 is the distance between the geometric center of the contact surface between the second diffusion region 68an (which is the other of the source and drain of the reset transistor 26) and the electrode connected to the second diffusion region 68an, and the geometric center of the through electrode 81. Figure 4 In the example shown, the electrode connected to the second diffusion region 68an is composed of the fourth contact plug cp4.

[0140] In this embodiment, if at least one of the first and second definitions can be said to be L1>L2, then L1>L2 is assumed to be true.

[0141] In this embodiment, in the plan view, the gate electrode 26e of the reset transistor 26 is located between the through electrode 81 and the charge accumulation region FD. This positional relationship is suitable for suppressing leakage current to the charge accumulation region FD.

[0142] The following explains why the above positional relationship is suitable for suppressing leakage current into the charge accumulation region FD.

[0143] First, based on the aforementioned positional relationship, it is easy to ensure the distance between the region containing crystal defects and the charge accumulation region FD. Therefore, this positional relationship is suitable for suppressing leakage current to the charge accumulation region FD.

[0144] Secondly, given the aforementioned positional relationship, by controlling the voltage applied to the gate electrode 26e of the reset transistor 26, which is the first transistor, leakage current to the charge accumulation region FD can be suppressed. In one example, the control performed by the imaging device 100 includes negative bias control. Negative bias control is the control that maintains a negative bias voltage applied to the gate electrode 26e of the reset transistor 26, which is the first transistor. By negative bias control, portions of the semiconductor substrate 1 along the second main surface 1B that overlap with the gate electrode 26e in the plan view and portions that overlap with a portion of the charge accumulation region FD can become accumulation states. By performing negative bias control, the depletion layer in these portions can be reduced. This can contribute to the suppression of leakage current to the charge accumulation region FD. In this context, a portion becoming an accumulation state means that an accumulation layer is formed in that portion. An accumulation layer is a layer where the density of majority carriers is higher than that of the surrounding area. In this embodiment, the majority carriers are positive charges, specifically holes. The minority carriers are negative charges, specifically electrons. According to the negative bias control, through the potential gradient from the gate electrode 26e, minority carriers from the through electrode 81 easily propagate away from the second main surface 1B within the semiconductor substrate 1. This also contributes to the suppression of leakage current to the charge accumulation region FD. The negative bias control is performed, for example, when the operating mode of the imaging device 100 is a mode in which signal charge is accumulated in the charge accumulation region FD.

[0145] In a specific example of the above example, the first transistor is a reset transistor 26. The control performed by the imaging device 100 includes reset control. Reset control is the control that resets the potential of the charge accumulation region FD by applying a positive voltage to the gate electrode 26e of the reset transistor 26, causing the reset transistor 26 to be turned on. The absolute value of the voltage applied to the gate electrode 26e during negative bias control is smaller than the absolute value of the voltage applied to the gate electrode 26e during reset control.

[0146] The description of "in the plan view, the gate electrode 26e of the reset transistor 26, which is the first transistor, is located between the through electrode 81 and the charge accumulation region FD" will be explained. In the first definition of this embodiment, this description means that at least a portion of the gate electrode 26e of the reset transistor 26, which is the first transistor, repeats at least a portion of the line segment connecting the geometric center of the through electrode 81 and the geometric center of the charge accumulation region FD in the plan view. In the second definition of this embodiment, this description means that at least a portion of the gate electrode 26e of the reset transistor 26, which is the first transistor, repeats at least a portion of the line segment connecting the geometric center of the through electrode 81 and the geometric center of a contact surface, wherein the contact surface is the contact surface between the charge accumulation region FD and the electrode connected to the charge accumulation region FD.

[0147] In this embodiment, the description is considered valid if it can be described as "in a plan view, the gate electrode 26e of the reset transistor 26, which is the first transistor, is located between the through electrode 81 and the charge accumulation region FD" based on at least one of the first and second definitions.

[0148] In this embodiment, the imaging device 100 includes a signal detection transistor 22, which serves as a second transistor. The gate electrode 22e of the signal detection transistor 22 is electrically connected to the charge storage region FD.

[0149] In the planar view, the distance L1 between the charge accumulation region FD and the through electrode 81 is larger than the distance L3 between the gate electrode 22e of the signal detection transistor 22 (which is the second transistor) and the through electrode 81. If L1 > L3, it is easier to ensure the distance between the region with crystal defects and the charge accumulation region FD, and to shorten the electrical path between the gate electrode 22e of the signal detection transistor 22 (which is the second transistor) and the through electrode 81. Therefore, L1 > L3 is suitable for suppressing leakage current to the charge accumulation region FD, and is also suitable for suppressing noise generated in the electrical path between the gate electrode 22e of the signal detection transistor 22 (which is the second transistor) and the through electrode 81.

[0150] In this embodiment, the second transistor corresponds to the signal detection transistor 22.

[0151] In this embodiment, distance L3 is the distance between the geometric center of the gate electrode 22e of the signal detection transistor 22 (which is the second transistor) and the geometric center of the through electrode 81 in the plan view.

[0152] In this embodiment, in the plan view, the area S1 of the charge accumulation region FD is smaller than the area S2 of the second diffusion region 68an, which is the other of the source and drain of the reset transistor 26, which is the first transistor. Based on this area relationship, the probability of charge carriers from the through electrode 81 flowing into the charge accumulation region FD can be reduced. Therefore, this size relationship is suitable for suppressing leakage current to the charge accumulation region FD.

[0153] In the first definition of this embodiment, area S1 is the area in the plan view that extends inward from the junction of the charge accumulation region FD. Area S2 is the area in the plan view that extends inward from the junction of the second diffusion region 68an, which is the other of the source and drain of the reset transistor 26, which is the first transistor.

[0154] In one example, the ratio of area S1 to area S2, S1 / S2, is less than 4 / 5. The ratio S1 / S2 could also be less than 2 / 3 or less than 1 / 2.

[0155] However, the area S1 can be the same as the area S2. Furthermore, the area S1 can be larger than the area S2.

[0156] In this embodiment, the second cylindrical portion 33B of the fixed charge layer 33 is provided in such a way that it surrounds the through hole 82. The second cylindrical portion 33B can suppress leakage current to the charge accumulation region FD caused by crystal defects.

[0157] In this embodiment, pixel 10A has a first electrical path 83. The first electrical path 83 electrically connects the through electrode 81 to the charge storage region FD.

[0158] In this embodiment, the first electrical path 83 is constructed using the second contact plug cp2, the first wiring layer 80a, and the first contact plug cp1.

[0159] exist Figures 5 to 8 The example shown is the first electrical path 83.

[0160] exist Figures 5 to 7 In the example shown, at least a portion of the first electrical path 83 is curved in the plan view. This increases the degree of freedom in the layout of the electrical path.

[0161] The description of "at least a portion of the first electrical path 83 is bent in the plan view" is explained. In this embodiment, as... Figure 5 and Figure 7 As shown, this representation is a concept encompassing the bending shape of at least a portion of the first electrical path 83 in the plan view. Specifically, in Figure 5 and Figure 7In the example, in the plan view, the first electrical path 83 bends at portions 83j and 83k. Furthermore, as... Figure 6 As shown, the above representation is a concept encompassing at least a portion of the first electrical path 83 in the plan view, exhibiting a gently curving shape. Specifically, in Figure 6 In the example, in the plan view, the first electrical path 83 curves gently at part 83c.

[0162] In this embodiment, pixel 10A has a gate wiring 26w. The gate wiring 26w is electrically connected to the gate electrode 26e of the first transistor. Additionally, in... Figure 3 and Figure 4 The diagram of gate wiring 26w is omitted. In the example where the first transistor is reset transistor 26, gate wiring 26w may include reset signal line 47. Furthermore, in the example where the first transistor is reset transistor 26, gate wiring 26w may also be reset signal line 47.

[0163] The term "second electrical path 26m" will be used in the following context. Second electrical path 26m refers to the combination of the gate electrode 26e and the gate wiring 26w of the first transistor.

[0164] exist Figure 5 and Figure 6 In the example shown, in the plan view, the first electrical path 83 bypasses the second electrical path 26m. According to this example, coupling between the first electrical path 83 and the second electrical path 26m can be suppressed.

[0165] exist Figure 5 and Figure 6 In the specific example shown, the first transistor is a reset transistor 26. The control performed by the imaging device 100 includes reset control, which resets the potential of the charge accumulation region FD by applying a voltage to the gate electrode 26e of the reset transistor 26 to turn it on. When the reset transistor 26 is turned on or subsequently turned off during the reset control, the voltage of the gate electrode 26e switches. That is, the voltage of the second electrical path 26m switches. If this switching occurs, the voltage of the first electrical path 83 also changes due to the coupling between the first electrical path 83 and the second electrical path 26m, and this change may also cause a change in the voltage of the charge accumulation region FD. Such a change in the voltage of the charge accumulation region FD can be a cause of noise. However, if the first electrical path 83 bypasses the second electrical path 26m, the noise that may occur as described above can be suppressed.

[0166] The description of "in the plan view, the first electrical path 83 bypasses the second electrical path 26m" will be explained. In this embodiment, this means that in the plan view, at least a portion of the line segment 83s connecting the through electrode 81 and the charge accumulation region FD overlaps with at least a portion of the second electrical path 26m, while the first electrical path 83 and the second electrical path 26m are separate. In the first definition, the line segment 83s is the line segment connecting the geometric center of the through electrode 81 and the geometric center of the charge accumulation region FD. In the second definition, the line segment 83s is the line segment connecting the geometric center of the through electrode 81 and the geometric center of the contact surface between the charge accumulation region FD and the electrode connected to the charge accumulation region FD.

[0167] exist Figure 7 and Figure 8 In the example shown, in the plan view, at least a portion of the first electrical path 83 overlaps with at least a portion of the second electrical path 26m. According to Figure 7 and Figure 8 The example shown can generate coupling between the first electrical path 83 and the second electrical path 26m. For example, by generating coupling, the voltage of the charge accumulation region FD can be reduced, and the leakage current of the charge accumulation region FD can be suppressed.

[0168] exist Figure 7 In the example shown, at least a portion of the first electrical path 83 is bent in the plan view. Figure 8 In the example shown, in the plan view, the first electrical path 83 extends in a straight line. Regardless of... Figure 7 Or as Figure 8 In the plan view, at least a portion of the first electrical path 83 can be repeated with at least a portion of the second electrical path 26m.

[0169] In this embodiment, Figure 3 As shown in the planar view, at least a portion of the pixel electrode 13, which serves as the first electrode, overlaps with at least a portion of the charge accumulation region FD. Therefore, it is possible to suppress the illumination of light onto the charge accumulation region FD by means of the pixel electrode 13, which serves as the first electrode. This is advantageous from the viewpoint of suppressing leakage current in the charge accumulation region FD.

[0170] Specifically, in this embodiment, such as Figure 3 As shown in the plan view, the entire charge accumulation region FD overlaps with a portion of the pixel electrode 13, which serves as the first electrode.

[0171] In this embodiment, the pixel electrode 13, which serves as the first electrode, contains at least one of a metal and a metal compound. This allows for the construction of a first electrode 13 that provides the aforementioned leakage current suppression effect.

[0172] In this embodiment, the pixel electrode 13, which serves as the first electrode, contains metal. This makes it easy to construct the pixel electrode 13 as the first electrode that has the aforementioned leakage current suppression effect.

[0173] In this embodiment, the pixel electrode 13, serving as the first electrode, contains a material having at least one of the characteristics of lower light transmittance than the semiconductor substrate 1 and lower light transmittance than ITO. This characteristic also helps to ensure the aforementioned leakage current suppression effect. In this context, light transmittance refers to, for example, the transmittance of at least one of visible light and near-infrared light. The wavelength range of visible light is, for example, 400 nm to 780 nm. The wavelength range of near-infrared light is, for example, 780 nm to 2000 nm. Transmittance can be calculated using the method specified in Japanese Industrial Standard JIS R3106 (1998).

[0174] In this embodiment, no photodiode is provided within the semiconductor substrate 1. In this case, since light irradiation onto the photodiode can be disregarded, it is easy to employ a structure that suppresses light irradiation onto the charge accumulation region FD by repeating at least a portion of the pixel electrode 13 (serving as the first electrode) with at least a portion of the charge accumulation region FD in the planar view. However, even when a photodiode is provided within the semiconductor substrate 1, it is still possible to employ a structure that suppresses light irradiation onto the charge accumulation region FD by repeating at least a portion of the pixel electrode 13 (serving as the first electrode) with at least a portion of the charge accumulation region FD in the planar view.

[0175] In this embodiment, such as Figure 4 As shown, a second contact plug cp2 exists between the through electrode 81 and the first wiring layer 80a. However, as Figure 9 As shown, the through electrode 81 can also be directly connected to the first wiring layer 80a. This is also true in the embodiments described later.

[0176] In this embodiment, there are multiple pixels 10A. This is also true in the embodiments described later.

[0177] Several other embodiments will be described below. Hereinafter, elements common to the embodiments already described and those described subsequently will be given the same reference numerals, and some descriptions may be omitted. The descriptions of each embodiment are applicable to each other as long as they do not contradict each other technically. Embodiments may also be combined with each other as long as they do not contradict each other technically.

[0178] (Second Implementation)

[0179] Figure 10 This is a diagram illustrating an exemplary circuit structure for pixel 10B. Figure 12The diagram illustrates an example of the device structure for pixel 10B. Figure 11 Indicatively representing Figure 12 The pixel 10B shown is an arrangement of the elements formed on the semiconductor substrate 1 when viewed along the normal direction of the semiconductor substrate 1. Figure 11 If the dashed line XII-XII in the image cuts off pixel 10B and then expands it, we can obtain... Figure 12 The cross-section shown.

[0180] In the second embodiment, unlike the first embodiment, three photoelectric conversion layers are stacked. Typically, these three photoelectric conversion layers exhibit sensitivity to light in wavelength ranges of different colors. Specifically, these three photoelectric conversion layers exhibit sensitivity to light in the wavelength ranges of red (R), green (G), and blue (B). In the second embodiment, photoelectric conversion layers exhibiting optimal sensitivity to light in these wavelength ranges of colors can be used. The second embodiment is advantageous from the viewpoint of improving photoelectric conversion efficiency.

[0181] The second embodiment will now be described in detail.

[0182] like Figure 10 As shown, pixel 10B comprises three groups of a photoelectric conversion unit 12, a through electrode 81, a signal detection circuit 60, and a charge storage region FD. Hereinafter, the three groups will be referred to as the first group memX, the second group memY, and the third group memZ, respectively.

[0183] In the second embodiment, the photoelectric conversion unit 12, the through electrode 81, the signal detection circuit 60, and the charge accumulation region FD of the first assembly memX are sometimes referred to as photoelectric conversion unit 12X, through electrode 81X, signal detection circuit 60X, and charge accumulation region FDX, respectively. The pixel electrode 13, photoelectric conversion layer 14, and counter electrode 15 of the photoelectric conversion unit 12X are sometimes referred to as pixel electrode 13X, photoelectric conversion layer 14X, and counter electrode 15X, respectively. The signal detection transistor 22, address transistor 24, and reset transistor 26 of the signal detection circuit 60X are sometimes referred to as signal detection transistor 22X, address transistor 24X, and reset transistor 26X, respectively. The gate electrode 22e of the signal detection transistor 22X, the gate electrode 24e of the address transistor 24X, and the gate electrode 26e of the reset transistor 26X are sometimes referred to as gate electrode 22eX, gate electrode 24eX, and gate electrode 26eX, respectively.

[0184] In the second embodiment, the photoelectric conversion unit 12, the through electrode 81, the signal detection circuit 60, and the charge accumulation region FD of the second assembly memY are sometimes referred to as photoelectric conversion unit 12Y, through electrode 81Y, signal detection circuit 60Y, and charge accumulation region FDY, respectively. The pixel electrode 13, photoelectric conversion layer 14, and counter electrode 15 of the photoelectric conversion unit 12Y are sometimes referred to as pixel electrode 13Y, photoelectric conversion layer 14Y, and counter electrode 15Y, respectively. The signal detection transistor 22, address transistor 24, and reset transistor 26 of the signal detection circuit 60Y are sometimes referred to as signal detection transistor 22Y, address transistor 24Y, and reset transistor 26Y, respectively. The gate electrode 22e of the signal detection transistor 22Y, the gate electrode 24e of the address transistor 24Y, and the gate electrode 26e of the reset transistor 26Y are sometimes referred to as gate electrode 22eY, gate electrode 24eY, and gate electrode 26eY, respectively.

[0185] In the second embodiment, the photoelectric conversion unit 12, the through electrode 81, the signal detection circuit 60, and the charge accumulation region FD of the third assembly memZ are sometimes referred to as photoelectric conversion unit 12Z, through electrode 81Z, signal detection circuit 60Z, and charge accumulation region FDZ, respectively. The pixel electrode 13, photoelectric conversion layer 14, and counter electrode 15 of the photoelectric conversion unit 12Z are sometimes referred to as pixel electrode 13Z, photoelectric conversion layer 14Z, and counter electrode 15Z, respectively. The signal detection transistor 22, address transistor 24, and reset transistor 26 of the signal detection circuit 60Z are sometimes referred to as signal detection transistor 22Z, address transistor 24Z, and reset transistor 26Z, respectively. The gate electrode 22e of the signal detection transistor 22Z, the gate electrode 24e of the address transistor 24Z, and the gate electrode 26e of the reset transistor 26Z are sometimes referred to as gate electrode 22eZ, gate electrode 24eZ, and gate electrode 26eZ, respectively.

[0186] The first combination memX, the second combination memY, and the third combination memZ may have other elements described in the first embodiment. The first combination memX, the second combination memY, and the third combination memZ may be associated with other elements described in the first embodiment. Each element of the first combination memX, the second combination memY, and the third combination memZ may have the same features as each element in the first embodiment.

[0187] For example, in this embodiment, such as Figure 12As shown, a through electrode 81X for the first group memX is provided in a through hole 82 for the first group memX. Although not shown in the figure, a through electrode 81Y for the second group memY is provided in a through hole 82 for the second group memY. A through electrode 81Z for the third group memZ is provided in a through hole 82 for the third group memZ.

[0188] In this embodiment, such as Figure 12 As shown, in the first group memX, pixel electrode 13X, through electrode 81X, second contact plug cp2 for the first group memX, first wiring layer 80a, first contact plug cp1 for the first group memX, and charge accumulation region FDX are connected in sequence. Although omitted in the illustration, the second group memY also uses the second contact plug cp2 and the first contact plug cp1 for the second group memY for the same connection. The third group memZ also uses the second contact plug cp2 and the first contact plug cp1 for the third group memZ for the same connection.

[0189] In this embodiment, such as Figure 12 As shown, the photoelectric conversion unit 12X and the through electrode 81X of the first combination memX are associated with the dielectric layer 32 and the fixed charge layer 33 used in the first combination memX. According to Figure 4 and Figure 12 It is understood that they are also associated with the photoelectric conversion unit 12, the through electrode 81, the dielectric layer 32, and the fixed charge layer 33 of the first embodiment. Although the illustrations are omitted, the same applies to the second assembly memY and the third assembly memZ.

[0190] In this embodiment, an insulating layer 31X corresponding to the insulating layer 31 of Embodiment 1 is provided above the photoelectric conversion unit 12X of the first combination memX. An insulating layer 31Y corresponding to the insulating layer 31 of Embodiment 1 is provided above the photoelectric conversion unit 12Y of the second combination memY. An insulating layer 31Z corresponding to the insulating layer 31 of Embodiment 1 is provided above the photoelectric conversion unit 12Z of the third combination memZ.

[0191] In this embodiment, insulating layer 71, insulating layer 70, semiconductor substrate 1, photoelectric conversion unit 12X, insulating layer 31X, photoelectric conversion unit 12Y, insulating layer 31Y, photoelectric conversion unit 12Z, insulating layer 31Z, and microlens 30 are stacked sequentially. Specifically, they are stacked in the thickness direction of semiconductor substrate 1.

[0192] In this embodiment, the first group memX, the second group memY, and the third group memZ share the insulating layer 71, the insulating layer 70, the wiring structure 80, and the semiconductor substrate 1.

[0193] In this embodiment, the photoelectric conversion layer 14X of the first combination memX exhibits sensitivity to light in the red (R) wavelength range. The photoelectric conversion layer 14Y of the second combination memY exhibits sensitivity to light in the green (G) wavelength range. The photoelectric conversion layer 14Z of the third combination memZ exhibits sensitivity to light in the blue (B) wavelength range. Thus, in this embodiment, photoelectric conversion layers exhibiting sensitivity to red light, photoelectric conversion layers exhibiting sensitivity to green light, and photoelectric conversion layers exhibiting sensitivity to blue light are sequentially stacked. However, the stacking order of the photoelectric conversion layers is not particularly limited.

[0194] In this embodiment, in the plan view, the outer contour of pixel electrode 13Y is located inside the outer contour of pixel electrode 13Z. In the plan view, the outer contour of pixel electrode 13X is located inside the outer contour of pixel electrode 13Y.

[0195] In this embodiment, the horizontal signal readout circuit 54 is connected to the vertical signal lines 45X, 45Y, and 45Z.

[0196] In this embodiment, the vertical scanning circuit 52 is connected to address signal lines 44X, 44Y, and 44Z. The vertical scanning circuit 52 is also connected to the counter electrode power supply lines 21X, 21Y, and 21Z. Finally, the vertical scanning circuit 52 is connected to reset signal lines 47X, 47Y, and 47Z.

[0197] In this embodiment, the vertical signal line 45X, address signal line 44X, counter electrode power supply line 21X, reset signal line 47X, signal detection circuit 60X, photoelectric conversion unit 12X, and charge accumulation region FDX are similarly associated with the vertical signal line 45, address signal line 44, counter electrode power supply line 21, reset signal line 47, signal detection circuit 60, photoelectric conversion unit 12, and charge accumulation region FD in the first embodiment. The same applies to the vertical signal line 45Y, address signal line 44Y, counter electrode power supply line 21Y, reset signal line 47Y, signal detection circuit 60Y, photoelectric conversion unit 12Y, and charge accumulation region FDY. The same applies to the vertical signal line 45Z, address signal line 44Z, counter electrode power supply line 21Z, reset signal line 47Z, signal detection circuit 60Z, photoelectric conversion unit 12Z, and charge accumulation region FDZ.

[0198] For example, in this embodiment, photoelectric conversion unit 12X is connected to the counter electrode power supply line 21X. Photoelectric conversion unit 12Y is connected to the counter electrode power supply line 21Y. Photoelectric conversion unit 12Z is ​​connected to the counter electrode power supply line 21Z.

[0199] Specifically, the counter electrode 15X is connected to the counter electrode power line 21X. The counter electrode 15Y is connected to the counter electrode power line 21Y. The counter electrode 15Z is connected to the counter electrode power line 21Z.

[0200] The gate electrode 26eX of the reset transistor 26X is connected to the reset signal line 47X. The gate electrode 26eY of the reset transistor 26Y is connected to the reset signal line 47Y. The gate electrode 26eZ of the reset transistor 26Z is connected to the reset signal line 47Z.

[0201] In this embodiment, the same positional relationships as in the first embodiment regarding the plan view can also be established.

[0202] For example, in this embodiment, such as Figure 11 As shown, regarding the first combination memX, in the plan view, the distance L1X between the charge accumulation region FDX and the through electrode 81X is greater than the distance L2X between the second diffusion region 68an and the through electrode 81X, which is the other of the source and drain of the reset transistor 26X (which is the first transistor). In this embodiment, the first transistor corresponds to the reset transistor 26X.

[0203] In this embodiment, regarding the second combination memY, in the plan view, the distance L1Y between the charge accumulation region FDY and the through electrode 81Y is greater than the distance L2Y between the second diffusion region 68an (the other of the source and drain of the reset transistor 26Y, which is the first transistor) and the through electrode 81Y. In this embodiment, the first transistor corresponds to the reset transistor 26Y.

[0204] In this embodiment, regarding the third combination memZ, in the plan view, the distance L1Z between the charge accumulation region FDZ and the through electrode 81Z is greater than the distance L2Z between the second diffusion region 68an and the through electrode 81Z, which is the other of the source and drain of the reset transistor 26Z (which is the first transistor). In this embodiment, the first transistor corresponds to the reset transistor 26Z.

[0205] In this embodiment, regarding the first combination memX, in the plan view, the gate electrode 26eX of the first transistor 26X is located between the through electrode 81X and the charge accumulation region FDX.

[0206] In one example, the control performed by the imaging device 100 includes a first negative bias control. The first negative bias control maintains a state where a voltage is applied to the gate electrode 26eX of the reset transistor 26X, which is the first transistor. Through the first negative bias control, the portion of the semiconductor substrate 1 along the second main surface 1B that overlaps with the gate electrode 26eX in the planar view, and the portion that overlaps with a portion of the charge accumulation region FDX, can be in an accumulation state. The first negative bias control is performed, for example, when the operating mode of the imaging device 100 is a mode in which signal charge is accumulated in the charge accumulation region FD.

[0207] In one specific example, the first transistor is a reset transistor 26X. The control performed by the imaging device 100 includes a first reset control. The first reset control is a control that resets the potential of the charge accumulation region FDX by applying a positive voltage to the gate electrode 26eX of the reset transistor 26X to turn it on. The absolute value of the voltage applied to the gate electrode 26eX during the first negative bias control is smaller than the absolute value of the voltage applied to the gate electrode 26eX during the first reset control.

[0208] In this embodiment, regarding the second combination memY, in the plan view, the gate electrode 26eY of the reset transistor 26Y, which is the first transistor, is located between the through electrode 81Y and the charge accumulation region FDY.

[0209] In one example, the control performed by the imaging device 100 includes a second negative bias control. The second negative bias control maintains a state where a voltage is applied to the gate electrode 26eY of the reset transistor 26Y, which is the first transistor. Through the second negative bias control, portions of the semiconductor substrate 1 along the second main surface 1B that overlap with the gate electrode 26eY in the planar view and portions that overlap with a portion of the charge accumulation region FDY are in an accumulation state. The second negative bias control is performed, for example, when the operating mode of the imaging device 100 is a mode in which signal charge is accumulated in the charge accumulation region FD.

[0210] In one specific example, the first transistor is a reset transistor 26Y. The control performed by the imaging device 100 includes a second reset control. The second reset control is a control that resets the potential of the charge accumulation region FDY by applying a positive voltage to the gate electrode 26eY of the reset transistor 26Y to turn it on. The absolute value of the voltage applied to the gate electrode 26eY during the second negative bias control is smaller than the absolute value of the voltage applied to the gate electrode 26eY during the second reset control.

[0211] In this embodiment, regarding the third combination memZ, in the plan view, the gate electrode 26eZ of the reset transistor 26Z, which is the first transistor, is located between the through electrode 81Z and the charge accumulation region FDZ.

[0212] In one example, the control performed by the imaging device 100 includes a third negative bias control. The third negative bias control maintains a state where a voltage is applied to the gate electrode 26eZ of the reset transistor 26Z, which is the first transistor. Through the third negative bias control, the portion of the substrate 1 along the second main surface 1B that overlaps with the gate electrode 26eZ in the planar view, and the portion that overlaps with a portion of the charge accumulation region FDZ, can be in an accumulation state. The third negative bias control is performed, for example, when the operating mode of the imaging device 100 is a mode in which signal charge is accumulated in the charge accumulation region FD.

[0213] In one specific example, the first transistor is a reset transistor 26Z. The control performed by the imaging device 100 includes a third reset control. The third reset control is a control that resets the potential of the charge accumulation region FDZ by applying a positive voltage to the gate electrode 26eZ of the reset transistor 26Z to turn it on. The absolute value of the voltage applied to the gate electrode 26eZ during the third negative bias control is smaller than the absolute value of the voltage applied to the gate electrode 26eZ during the third reset control.

[0214] In this embodiment, regarding the first combination memX, in the plan view, the distance L1X between the charge accumulation region FDX and the through electrode 81X is larger than the distance L3X between the gate electrode 22eX of the signal detection transistor 22X (which is the second transistor) and the through electrode 81X. In this embodiment, the second transistor corresponds to the signal detection transistor 22X.

[0215] In this embodiment, regarding the second combination memY, in the plan view, the distance L1Y between the charge accumulation region FDY and the through electrode 81Y is larger than the distance L3Y between the gate electrode 22eY of the signal detection transistor 22Y (which is the second transistor) and the through electrode 81Y. In this embodiment, the second transistor corresponds to the signal detection transistor 22Y.

[0216] In this embodiment, regarding the third combination memZ, in the plan view, the distance L1Z between the charge accumulation region FDZ and the through electrode 81Z is larger than the distance L3Z between the gate electrode 22eZ of the signal detection transistor 22Z (which is the second transistor) and the through electrode 81Z. In this embodiment, the second transistor corresponds to the signal detection transistor 22Z.

[0217] In this embodiment, regarding the first combination memX, in the planar view, the area S1X of the charge accumulation region FDX is smaller than the area S2X of the other of the source and drain of the reset transistor 26X, which is the first transistor, namely the second diffusion region 68an. The ratio S1X / S2X of area S1X to area S2X can be 4 / 5 or less, 2 / 3 or less, or 1 / 2 or less. However, the areas S1X and S2X can also be the same. Furthermore, the area S1X can also be larger than the area S2X.

[0218] In this embodiment, regarding the second combination memY, in the planar view, the area S1Y of the charge accumulation region FDY is smaller than the area S2Y of the other of the source and drain of the reset transistor 26Y, which is the first transistor, namely the second diffusion region 68an. The ratio S1Y / S2Y of area S1Y to area S2Y can be 4 / 5 or less, 2 / 3 or less, or 1 / 2 or less. However, the areas S1Y and S2Y can also be the same. Furthermore, the area S1Y can also be larger than the area S2Y.

[0219] In this embodiment, regarding the third combination memZ, in the planar view, the area S1Z of the charge accumulation region FDZ is smaller than the area S2Z of the second diffusion region 68an, which is the other of the source and drain of the reset transistor 26Z, which is the first transistor. The ratio S1Z / S2Z of area S1Z can be 4 / 5 or less, 2 / 3 or less, or 1 / 2 or less. However, the areas S1Z and S2Z can also be the same. Furthermore, the area S1Z can also be larger than the area S2Z.

[0220] The first electrical path 83, through electrode 81X, and charge accumulation region FDX used in the first combination memX are also associated with the first electrical path 83, through electrode 81, and charge accumulation region FD of the first embodiment.

[0221] The first electrical path 83, through electrode 81Y, and charge accumulation region FDY used in the second combination memY are also associated with the first electrical path 83, through electrode 81, and charge accumulation region FD in the first embodiment.

[0222] The first electrical path 83, through electrode 81Z, and charge accumulation region FDZ used in the third combination memZ are also associated with the first electrical path 83, through electrode 81, and charge accumulation region FD in the first embodiment.

[0223] The gate wiring 26w used for the first combination memX can be electrically connected to the gate electrode 26eX of the first transistor. In the example where the first transistor is a reset transistor 26X, the gate wiring 26wX used for the first combination memX can correspond to the reset signal line 47X.

[0224] The gate wiring 26w used for the second combination memY can be electrically connected to the gate electrode 26eY of the first transistor. In the example where the first transistor is a reset transistor 26Y, the gate wiring 26wY used for the second combination memY can correspond to the reset signal line 47Y.

[0225] The gate wiring 26w used for the third combination memZ can be electrically connected to the gate electrode 26eZ of the first transistor. In the example where the first transistor is the reset transistor 26Z, the gate wiring 26wZ used for the third combination memZ can correspond to the reset signal line 47Z.

[0226] In one example, in the plan view, the first electrical path 83 for the first combination memX bypasses the second electrical path 26m for the first combination memX. Here, the second electrical path 26m for the first combination memX refers to the combination of the gate electrode 26eX of the first transistor and the gate wiring 26w for the first combination memX.

[0227] In one example, in the plan view, the first electrical path 83 for the second combination memY bypasses the second electrical path 26m for the second combination memY. Here, the second electrical path 26m for the second combination memY refers to the combination of the gate electrode 26eY of the first transistor and the gate wiring 26w for the second combination memY.

[0228] In one example, in the plan view, the first electrical path 83 used by the third combination memZ bypasses the second electrical path 26m used by the third combination memZ. Here, the second electrical path 26m used by the third combination memZ refers to the combination of the gate electrode 26eZ of the first transistor and the gate wiring 26w used by the third combination memZ.

[0229] In one example, in the plan view, at least a portion of the first electrical path 83 used by the first combination memX overlaps with the second electrical path 26m used by the first combination memX.

[0230] In one example, in the plan view, at least a portion of the first electrical path 83 used by the second combination memY overlaps with the second electrical path 26m used by the second combination memY.

[0231] In one example, in the plan view, at least a portion of the first electrical path 83 used by the third combination memZ overlaps with the second electrical path 26m used by the third combination memZ.

[0232] In this embodiment, in a plan view, at least a portion of the pixel electrode 13X, which serves as the first electrode of the first combination memX, overlaps with at least a portion of the charge accumulation region FDX of the first combination memX. Alternatively, in a plan view, the entire charge accumulation region FDX may overlap with a portion of the pixel electrode 13X, which serves as the first electrode.

[0233] In this embodiment, in a plan view, at least a portion of the pixel electrode 13Y, which serves as the first electrode for the second combination memY, overlaps with at least a portion of the charge accumulation region FDY for the second combination memY. Alternatively, in a plan view, the entire charge accumulation region FDY may overlap with a portion of the pixel electrode 13Y, which serves as the first electrode.

[0234] In this embodiment, in a plan view, at least a portion of the pixel electrode 13Z, which serves as the first electrode of the third combination memZ, overlaps with at least a portion of the charge accumulation region FDZ of the third combination memZ. Alternatively, in a plan view, the entire charge accumulation region FDZ may overlap with a portion of the pixel electrode 13Z, which serves as the first electrode.

[0235] In this embodiment, the light transmittance of the pixel electrode 13X, which serves as the first electrode of the first combination memX, may be lower than that of the substrate 1, the pixel electrode 13Y, which serves as the first electrode of the second combination memY, and the pixel electrode 13Z, which serves as the first electrode of the third combination memZ.

[0236] (Third Implementation)

[0237] Figure 13 This is a diagram illustrating an exemplary circuit structure for pixel 10C. Figure 15 The diagram illustrates an example of the device structure of pixel 10C. Figure 14 Indicatively representing Figure 15 The pixel 10C shown is an arrangement of the elements formed on the semiconductor substrate 1 when viewed along the normal direction of the semiconductor substrate 1. Figure 14 If the XV-XV dashed line in the image cuts off pixel 10C and then expands it, we can obtain... Figure 15 The cross-section shown.

[0238] In the third embodiment, unlike the second embodiment, two photoelectric conversion layers are stacked. Typically, these two photoelectric conversion layers exhibit sensitivity to light in wavelength ranges of different colors. Specifically, these two photoelectric conversion layers exhibit sensitivity to red (R) and blue (B) wavelength ranges. In the third embodiment, it is possible to use photoelectric conversion layers that exhibit optimal sensitivity to light in these color wavelength ranges. The third embodiment is advantageous from the viewpoint of increasing the freedom of design for photoelectric conversion film materials.

[0239] Furthermore, in the third embodiment, unlike the second embodiment, a photodiode is provided within the semiconductor substrate 1. Typically, this photodiode performs photoelectric conversion on light in a wavelength range that is not absorbed by the two photoelectric conversion layers described above. Specifically, this photodiode performs photoelectric conversion on light in the green (G) wavelength range.

[0240] Thus, in the third embodiment, by using two photoelectric conversion layers and one photodiode, sensitivity to light in three different wavelength ranges of color is obtained. This structure can be achieved without the use of color filters.

[0241] The third embodiment will now be described in detail.

[0242] like Figure 13 As shown, pixel 10C, like in the second embodiment, has a first combination memX and a third combination memZ. On the other hand, unlike in the second embodiment, pixel 10C has a second combination pdY.

[0243] Like the second group memY, the second group pdY has a signal detection circuit 60Y. On the other hand, unlike the second group memY, the second group pdY has a photodiode 27Y and a transmission transistor 28Y.

[0244] In this embodiment, insulating layer 71, insulating layer 70, semiconductor substrate 1, photoelectric conversion unit 12X, insulating layer 31X, photoelectric conversion unit 12Z, insulating layer 31Z, and microlens 30 are stacked sequentially. Specifically, they are stacked in the thickness direction of semiconductor substrate 1.

[0245] In this embodiment, in the plan view, the outer contour of pixel electrode 13X is located inside the outer contour of pixel electrode 13Z.

[0246] The photodiode 27Y exhibits sensitivity to light. Specifically, the photodiode 27Y is disposed within the semiconductor substrate 1. The photodiode 27Y performs photoelectric conversion on light in the green (G) wavelength range that is not absorbed by the photoelectric conversion units 12X and 12Z.

[0247] When light shines on photodiode 27Y, a charge is generated in photodiode 27Y. This generated charge is stored as a signal charge in photodiode 27Y. In this embodiment, unlike the previously described embodiment, the signal charge is a negative charge. Specifically, the signal charge is an electron. Photodiode 27Y is an N-type impurity layer.

[0248] Adjustments to various factors, such as changes in the conductivity of impurity regions and the resulting differences in the sign of the signal charge, can be made appropriately. Furthermore, changes to terminology arising from the different signs of the signal charge can be made appropriately.

[0249] Transmission transistor 28Y is disposed on semiconductor substrate 1. Specifically, transmission transistor 28Y is disposed on the second main surface 1B.

[0250] Transmitter 28Y is a MOSFET. Specifically, transmitter 28Y is an N-channel MOSFET.

[0251] Transmitting transistor 28Y transfers the signal charge stored in photodiode 27Y to charge storage region FDY. In the third embodiment, similar to the second embodiment, the charge storage region FDY is one of the source and drain of the reset transistor 26Y of the first transistor, namely the first diffusion region 67n.

[0252] A transmission signal line 49Y, which is connected to the vertical scan circuit 52, is connected to the gate electrode 28eY of the transmission transistor 28Y. The transmission signal line 49Y, like the address signal line 44Y, is arranged in each row of the plurality of pixels 10C. The vertical scan circuit 52 enables the transmission transistor 28Y to be turned on by applying a transmission signal controlling the on / off state of the transmission transistor 28Y to the gate electrode 28eY via the transmission signal line 49Y. When the transmission transistor 28Y is turned on, the signal charge accumulated in the photodiode 27Y is transferred to the charge accumulation region FDY.

[0253] (Fourth implementation)

[0254] Figure 16 This is a diagram illustrating an exemplary circuit structure for a 10D pixel. Figure 18 The diagram illustrates an example of the device construction of a pixel 10D. Figure 17 Indicatively representing Figure 18 The image shows the arrangement of elements formed on the semiconductor substrate 1 when the pixel 10D is viewed along the normal direction of the semiconductor substrate 1. If viewed along... Figure 17 The XVIII-XVIII dashed line in the image cuts and unfolds pixel 10D, thus obtaining... Figure 18 The cross-section shown.

[0255] In the fourth embodiment, unlike the second and third embodiments, a photoelectric conversion layer is provided. The photoelectric conversion layer exhibits sensitivity to light. Specifically, the photoelectric conversion layer exhibits sensitivity to light in the wavelength range of green (G).

[0256] In the fourth embodiment, unlike the second and third embodiments, two photodiodes are stacked within the semiconductor substrate 1. In a typical example, these two photodiodes perform photoelectric conversion on light in a wavelength range not absorbed by the aforementioned photoelectric conversion layer. Furthermore, in a typical example, these two photodiodes perform photoelectric conversion on light in wavelength ranges of different colors. Specifically, photodiode 27X performs photoelectric conversion on light in the red (R) wavelength range. Photodiode 27Z performs photoelectric conversion on light in the blue (B) wavelength range.

[0257] Thus, in the fourth embodiment, sensitivity to light in three different wavelength ranges of color is obtained through one photoelectric conversion layer and two photodiodes. This structure can be implemented without the use of color filters.

[0258] The fourth embodiment will now be described in detail.

[0259] like Figure 16 As shown, pixel 10D, like in the second embodiment, has a second combination memY. On the other hand, unlike in the second and third embodiments, pixel 10D has a first combination pdX and a third combination pdZ.

[0260] Like the first group of memX, the first group of pdX has a signal detection circuit 60X. On the other hand, unlike the first group of memX, the first group of pdX has a photodiode 27X and a transmission transistor 28X.

[0261] Like the third group of memZ, the third group of pdZ has a signal detection circuit 60Z. On the other hand, unlike the third group of memZ, the third group of pdZ has a photodiode 27Z and a transmission transistor 28Z.

[0262] In this embodiment, insulating layer 71, insulating layer 70, semiconductor substrate 1, photoelectric conversion unit 12Y, insulating layer 31Y, and microlens 30 are sequentially stacked. Specifically, they are stacked in the thickness direction of semiconductor substrate 1.

[0263] Photodiodes 27X and 27Z are disposed within the semiconductor substrate 1. Specifically, photodiodes 27X and 27Z are stacked within the semiconductor substrate 1. Specifically, they are stacked in the thickness direction of the semiconductor substrate 1. More specifically, photodiode 27X is disposed at a depth in the semiconductor substrate 1 capable of photoelectric conversion of light in the red (R) wavelength range. Photodiode 27Z is disposed at a depth in the semiconductor substrate 1 capable of photoelectric conversion of light in the blue (B) wavelength range.

[0264] Photodiodes 27X and 27Z exhibit sensitivity to light. Specifically, photodiodes 27X and 27Z perform photoelectric conversion on light in the wavelength range that is not absorbed by the photoelectric conversion unit 12Y. More specifically, photodiode 27X performs photoelectric conversion on light in the red (R) wavelength range. Photodiode 27Z performs photoelectric conversion on light in the blue (B) wavelength range.

[0265] When light shines on photodiode 27X, a charge is generated within it. This charge is stored as a signal charge within photodiode 27X. In this embodiment, the signal charge is a negative charge. Specifically, the signal charge is an electron. Photodiode 27X is an N-type impurity layer.

[0266] Transmission transistor 28X is disposed on semiconductor substrate 1. Specifically, transmission transistor 28X is disposed on the second main surface 1B.

[0267] If light is shone on the photodiode 27Z, a charge is generated in the photodiode 27Z. The generated charge is stored as a signal charge in the photodiode 27Z.

[0268] The transmission transistor 28Z is disposed on the semiconductor substrate 1. Specifically, the transmission transistor 28Z is disposed on the second main surface 1B.

[0269] Transistor 28X and transistor 28Z are MOSFETs. Specifically, transistor 28X and transistor 28Z are N-channel MOSFETs.

[0270] Transmission transistor 28X transfers the signal charge stored in photodiode 27X to charge storage region FDX. In the fourth embodiment, similar to the second and third embodiments, the charge storage region FDX is one of the source and drain of the reset transistor 26X of the first transistor, namely the first diffusion region 67n.

[0271] Transmission transistor 28Z transfers the signal charge stored in photodiode 27Z to charge storage region FDZ. In the fourth embodiment, similar to the second and third embodiments, the charge storage region FDZ is one of the source and drain of the reset transistor 26Z of the first transistor, namely the first diffusion region 67n.

[0272] A transmission signal line 49X, connected to the vertical scan circuit 52, is connected to the gate electrode 28eX of the transmission transistor 28X. The transmission signal line 49X, like the address signal line 44X, is arranged in each row of the plurality of pixels 10D. The vertical scan circuit 52 enables the transmission transistor 28X to be turned on by applying a transmission signal controlling the on / off state of the transmission transistor 28X to the gate electrode 28eX of the transmission transistor 28X via the transmission signal line 49X. When the transmission transistor 28X is turned on, the signal charge accumulated in the photodiode 27X is transferred to the charge accumulation region FDX.

[0273] A transmission signal line 49Z, connected to the vertical scan circuit 52, is connected to the gate electrode 28eZ of the transmission transistor 28Z. The transmission signal line 49Z, like the address signal line 44Z, is arranged in each row of the plurality of pixels 10D. The vertical scan circuit 52 enables the transmission transistor 28Z to conduct by applying a transmission signal controlling the on / off state of the transmission transistor 28Z to the gate electrode 28eZ of the transmission transistor 28Z via the transmission signal line 49Z. When the transmission transistor 28Z is conducted, the signal charge accumulated in the photodiode 27Z is transferred to the charge accumulation region FDZ.

[0274] (Fifth Embodiment)

[0275] Figure 19 This is a diagram illustrating an exemplary circuit structure for pixel 10E. Figure 21 The diagram illustrates an example of the device structure for pixel 10E. Figure 20 Indicatively representing Figure 21 The pixel 10E shown is an arrangement of the elements formed on the semiconductor substrate 1 when viewed along the normal direction of the semiconductor substrate 1. Figure 20 If the XXI-XXI dashed line cuts off pixel 10E and is then unfolded, we can obtain... Figure 21 The cross-section shown.

[0276] In the fifth embodiment, the photoelectric conversion unit 12 includes a pixel electrode 13, a photoelectric conversion stack 29, and a counter electrode 15.

[0277] The first flat film portion 32A of the dielectric layer 32, the pixel electrode 13 and the insulating layer 17A, the photoelectric conversion stack 29 and the insulating layer 17B, and the counter electrode 15 are sequentially stacked. Specifically, they are stacked in the thickness direction of the semiconductor substrate 1.

[0278] exist Figure 22 The diagram shows the structure of the photoelectric conversion stack 29. (Example:) Figure 22 As shown, the photoelectric conversion stack 29 has an oxide semiconductor layer 11A and a photoelectric conversion layer 14. Specifically, in the photoelectric conversion stack 29, the oxide semiconductor layer 11A and the photoelectric conversion layer 14 are sequentially stacked from the pixel electrode 13 toward the counter electrode 15. The oxide semiconductor layer 11A is connected to the photoelectric conversion layer 14.

[0279] The oxide semiconductor layer 11A contains, for example, at least one selected from the group consisting of indium oxide, gallium oxide, zinc oxide and tin oxide.

[0280] The pixel electrode 13 has a storage electrode 13a and a readout electrode 13b that are separated from each other. Specifically, the storage electrode 13a and the readout electrode 13b are separated by an insulating layer 17A.

[0281] In the insulating layer 17A, in addition to the storage electrode 13a and the readout electrode 13, there are also a connecting portion 19a, a connecting portion 19b, a pad portion 18a, and a pad portion 18b.

[0282] Insulating layer 17B is disposed on insulating layer 17A. Through hole is provided in insulating layer 17B.

[0283] A portion of the oxide semiconductor layer 11A enters the through-hole of the insulating layer 17B and contacts the readout electrode 13b. Another portion of the oxide semiconductor layer 11A is connected to the insulating layer 17B in a region in the plan view that does not overlap with the accumulation electrode 13a. Yet another portion of the oxide semiconductor layer 11A is connected to the insulating layer 17B in a region in the plan view that overlaps with the accumulation electrode 13a.

[0284] The storage electrode 13a and the pad portion 18a are electrically connected via the connecting portion 19a. The readout electrode 13b and the through electrode 81 are electrically connected sequentially via the connecting portion 19b and the pad portion 18b.

[0285] In this embodiment, the vertical scanning circuit 52 is connected to the pixel electrode power line 41. Voltage can be applied from the vertical scanning circuit 52 to the accumulation electrode 13a via the pixel electrode power line 41. Furthermore, voltage can be applied from the vertical scanning circuit 52 to the counter electrode 15 via the counter electrode power line 21.

[0286] In this embodiment, the accumulation period and the transfer period are achieved by adjusting the voltage of the counter electrode 15 and the voltage of the accumulation electrode 13a. During the accumulation period, the charge generated by the photoelectric conversion layer 14 is attracted by the accumulation electrode 13a and remains in the oxide semiconductor layer 11A, etc. During the accumulation period, the charge is thus accumulated in the oxide semiconductor layer 11A, etc. During the transfer period, the charge in the oxide semiconductor layer 11A, etc., is transferred to the charge accumulation region FD via the readout electrode 13b and the through electrode 81.

[0287] In one specific example, the potential of the charge accumulation region FD is reset by a reset control after the accumulation period and before the transmission period.

[0288] Alternatively, a transmission control electrode, separate from the accumulation electrode 13a and the readout electrode 13b, can be provided between the accumulation electrode 13a and the readout electrode 13b in the plan view. If the voltage of the transmission control electrode is adjusted together with the voltage of the counter electrode 15 and the voltage of the accumulation electrode 13a, it is easy to prevent the charge generated by the photoelectric conversion layer 14 from moving toward the readout electrode 13b during the accumulation period.

[0289] A light-shielding film 39 is provided within the insulating layer 31. The light-shielding film 39 is arranged in a manner that overlaps with the readout electrode 13b in the planar view. According to the light-shielding film 39, photoelectric conversion of the portion of the photoelectric conversion layer 14 that overlaps with the readout electrode 13b in the planar view can be suppressed. As a result, it is easy to reset all pixels at the same time, and it is easy to realize the global shutter function.

[0290] like Figure 23 As shown, the photoelectric conversion stack 29 may also have an oxide film 11B in addition to the oxide semiconductor layer 11A and the photoelectric conversion layer 14. Specifically, in Figure 23 In this example, in the photoelectric conversion stack 29, an oxide semiconductor layer 11A, an oxide film 11B, and a photoelectric conversion layer 14 are sequentially stacked from the pixel electrode 13 toward the counter electrode 15. The oxide semiconductor layer 11A is connected to the oxide film 11B. The oxide film 11B is connected to the photoelectric conversion layer 14. The oxide film 11B can stabilize the oxide semiconductor layer 11A. In this example, the oxide film 11B is sufficiently thin. Therefore, charge can move through the oxide film 11B through the trench effect.

[0291] The oxide film 11B includes, for example, at least one of a trench oxide film and a metal oxide. The trench oxide film, for example, contains components derived from SiO₂. X SiON, SiOC and AlO Y At least one of the following groups. Metal oxides include, for example, at least one of the following groups: tantalum oxide, titanium oxide, vanadium oxide, niobium oxide, tungsten oxide, zirconium oxide, hafnium oxide, scandium oxide, yttrium oxide, lanthanum oxide, gallium oxide, and magnesium oxide.

[0292] The technology of this embodiment can be applied to all the embodiments described above.

[0293] As explained above, according to the embodiments of this disclosure, the effects caused by leakage current can be suppressed, thus providing a camera device capable of capturing images with high image quality.

[0294] In the above embodiments, a back-illuminated imaging device was described as an example. However, this disclosure can also be applied to surface-illuminated imaging devices.

[0295] Industrial availability

[0296] According to embodiments of this disclosure, a camera device is provided that enables high-quality imaging by suppressing the effects of leakage current. This camera device is useful for applications such as image sensors and digital cameras. It can be used in medical cameras, robotic cameras, security cameras, and cameras mounted on vehicles.

[0297] Label Explanation

[0298] 1. Semiconductor substrate

[0299] 1A, 1B Main Face

[0300] 1i Impurity Region

[0301] 10, 10A, 10B, 10C, 10D, 10E pixels

[0302] 12, 12X, 12Y, 12Z photoelectric conversion unit

[0303] 13, 13X, 13Y, 13Z pixel electrodes

[0304] 13a Accumulation electrode

[0305] 13b Readout Electrode

[0306] 14, 14X, 14Y, 14Z photoelectric conversion layers

[0307] 15, 15X, 15Y, 15Z Opposite Electrodes

[0308] Insulation layers 17A, 17B, 31, 70, 71

[0309] 21. Power supply line for the opposite electrode

[0310] 22, 22X, 22Y, 22Z signal detection transistors

[0311] 24, 24X, 24Y, 24Z address transistors

[0312] 26, 26X, 26Y, 26Z Reset Transistors

[0313] 22e, 22eX, 22eY, 22eZ, 24e, 24eX, 24eY, 24eZ, 26e, 26eX, 26eY, 26eZ gate electrodes

[0314] 26W gate wiring

[0315] 26m, 83 electrical paths

[0316] 27X, 27Y, 27Z photodiodes

[0317] 28X, 28Y, 28Z transmission transistors

[0318] 29 Photoelectric conversion stack

[0319] 30 microlenses

[0320] 32 Dielectric layer

[0321] 33 Fixed charge layer

[0322] 32A, 33A Flat Film Section

[0323] 32B, 33B cylindrical part

[0324] 41-pixel electrode power line

[0325] 42 Power wiring

[0326] 44, 44X, 44Y, 44Z address signal lines

[0327] 45, 45X, 45Y, 45Z Vertical signal lines

[0328] 47, 47X, 47Y, 47Z Reset signal lines

[0329] 48 Voltage lines

[0330] 52 Vertical Scanning Circuit

[0331] 54 Horizontal Signal Readout Circuit

[0332] 56 Control Circuit

[0333] 58 Voltage Supply Circuit

[0334] 60 Signal Detection Circuit

[0335] Diffusion regions of 67n, 68an, 68bn, 68cn, and 68dn

[0336] 80 Wiring Structure

[0337] 80a, 80b, 80c wiring layers

[0338] 81 Through-electrode

[0339] 82 Through Holes

[0340] 83c, 83j, 83k parts

[0341] 83s line segment

[0342] 100 camera devices

[0343] CP1, CP2, CP3 contact plugs

[0344] FD, FDX, FDY, FDZ charge accumulation regions

[0345] memX, memY, memZ, pdX, pdY, pdZ combinations

[0346] R1 camera area

[0347] R2 surrounding area

Claims

1. A camera device, wherein, have: substrate; Electrode 1; Second electrode; A photoelectric conversion layer, located between the first electrode and the second electrode, converts light into electrical charge; The first transistor includes a first impurity region serving as one of the source and drain, a second impurity region serving as the other of the source and drain, and a first gate electrode; and A through electrode is formed, penetrating the substrate, to electrically connect the first electrode to the first impurity region. The aforementioned charge accumulates in the first impurity region. In the plan view, the distance between the first impurity region and the through electrode is longer than the distance between the second impurity region and the through electrode. The first transistor mentioned above is a reset transistor that resets the potential of the first impurity region.

2. The camera device as claimed in claim 1, wherein, In the plan view, the first gate electrode is located between the through electrode and the first impurity region.

3. The camera device as described in claim 1 or 2, wherein, It also includes a second transistor, which includes a second gate electrode electrically connected to the first impurity region. In the plan view, the distance between the first impurity region and the through electrode is longer than the distance between the second gate electrode and the through electrode.

4. The camera device as described in claim 1 or 2, wherein, In the plan view, the area of ​​the first impurity region is smaller than the area of ​​the second impurity region.

5. The camera device as described in claim 1 or 2, wherein, It also has a first electrical path that electrically connects the through electrode to the first impurity region. In the plan view, at least a portion of the first electrical path described above is bent.

6. The camera device as claimed in claim 1 or 2, wherein, It also has: The first electrical path electrically connects the aforementioned through electrode to the aforementioned first impurity region; and The gate wiring is connected to the first gate electrode mentioned above. When the combination of the first gate electrode and the gate wiring is defined as the second electrical path, in the plan view, the first electrical path bypasses the second electrical path.

7. The camera device as claimed in claim 1 or 2, wherein, It also has: The first electrical path electrically connects the aforementioned through electrode to the aforementioned first impurity region; and The gate wiring is connected to the first gate electrode mentioned above. When the combination of the first gate electrode and the gate wiring is defined as the second electrical path, in the plan view, at least a portion of the first electrical path is repeated with at least a portion of the second electrical path.

8. The camera device as claimed in claim 1 or 2, wherein, In the plan view, at least a portion of the first electrode overlaps with at least a portion of the first impurity region.

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