LDMOS architecture and method of formation

Abstract

A method for forming a semiconductor device relates to providing a semiconductor wafer having an active layer of a first conductivity type. First and second gates having first and second gate polysilicon are formed on the active layer. A first mask region is formed on the active layer. Using the first mask region, the first gate polysilicon, and the second gate polysilicon as masks, a deep well of a second conductivity type, a shallow well of a second conductivity type, a source region of the first conductivity type, and first and second channel regions of the second conductivity type are formed between the first gate and the second gate. Using one or more second mask regions, first and second drift regions of the first conductivity type, first and second drain regions of the first conductivity type, and a source connection region of the second conductivity type are formed in the active layer.

Description

[0001] Related applications

[0002] This application claims priority to U.S. nonprovisional patent application No. 16 / 879,046, entitled “LDMOS Architecture and Method for Forming,” filed May 20, 2020, which is incorporated herein by reference for all purposes. Background Technology

[0003] Metal-oxide-semiconductor field-effect transistors (MOSFETs) typically consist of a polysilicon gate, a source region, a drain region, and a channel region. The source and drain regions have a first conductivity type, while the channel region has a second conductivity type. In some MOSFET devices, the first conductivity type is n-type, and the second conductivity type is p-type. In other MOSFET devices, this relationship is reversed. When the MOSFET device is in the on state, current flows between the drain and source regions through the channel region in response to the applied gate voltage. When the MOSFET device is in the off state, current does not flow between the drain and source regions as long as the reverse bias voltage across the MOSFET does not exceed the breakdown voltage level. If the reverse bias voltage exceeds the breakdown voltage, a large uncontrolled current can flow between the source and drain regions regardless of whether a voltage is applied to the gate. When the reverse bias voltage increases above the breakdown voltage, an avalanche breakdown event can occur. During an avalanche breakdown event, the current flowing through the MOSFET increases at an increasing rate and can quickly exceed the MOSFET's maximum rated current, potentially damaging or destroying the MOSFET.

[0004] Laterally diffused MOSFETs (LDMOS) are a type of MOSFET that additionally includes a laterally drifted drain (LDD) region to increase the breakdown voltage compared to a typical MOSFET. The LDD region allows the LDMOS to withstand a higher voltage in the off-state by absorbing a portion of the electric field, which would otherwise cause the MOSFET to break down. Summary of the Invention

[0005] In some examples, a method for forming a semiconductor device involves providing a semiconductor wafer having a substrate layer and an active layer of a first conductivity type. A first gate is formed on the active layer, the first gate comprising first gate polysilicon. A second gate is formed on the active layer, the second gate being laterally disposed from the first gate and comprising second gate polysilicon. A first mask region is formed on the active layer. Using the first mask region, the first gate polysilicon, and the second gate polysilicon as a mask, a deep well of a second conductivity type, a shallow well of a second conductivity type, a source region of a first conductivity type, and a channel region of a second conductivity type are formed in the active layer between the first gate and the second gate, the channel region being divided into a first channel region of a second conductivity type and a second channel region of a second conductivity type. Using one or more second mask regions, a first drift region of the first conductivity type, a second drift region of the first conductivity type, a first drain region of the first conductivity type, a second drain region of the first conductivity type, and a source connection region of the second conductivity type are formed in the active layer.

[0006] In some examples, a semiconductor device includes a semiconductor wafer having an active layer of a first conductivity type. The active layer includes a deep well of a second conductivity type, a shallow well of the second conductivity type, a source region of the first conductivity type, a first channel region of the second conductivity type, a second channel region of the second conductivity type, a first drift region of the first conductivity type, a second drift region of the first conductivity type, a first drain region of the first conductivity type, a second drain region of the first conductivity type, and a source connection region of the second conductivity type. The semiconductor device includes a first gate polysilicon formed above the active layer. A first polysilicon gate spacer is laterally disposed adjacent to the first gate polysilicon. The semiconductor device includes a second gate polysilicon formed above the active layer. A second polysilicon gate spacer is laterally disposed adjacent to the second gate polysilicon. The source connection region is laterally disposed between the first polysilicon gate spacer and the second polysilicon gate spacer. A first gate shield is formed above the first gate polysilicon. A second gate shield is formed above the second gate polysilicon. A dielectric region is formed above the active layer. The semiconductor device includes a metal source contact that extends vertically from the top surface of the dielectric region to the source connection region. The metal source contact is laterally disposed between a first polysilicon gate spacer and a second polysilicon gate spacer and has a first width along a first vertical range of the metal source contact. The first width is wider than a second width along a second vertical range of the metal source contact. The first width of the first vertical range of the metal source contact laterally overlaps with and contacts the first gate shield. Attached Figure Description

[0007] Figure 1 This is a simplified cross-sectional view of an exemplary LDMOS device according to some implementation schemes.

[0008] Figures 2A and 2B are examples of prior art LDMOS devices.

[0009] Figure 3 This is a simplified cross-sectional view of an exemplary LDMOS device according to some implementation schemes.

[0010] Figures 4 to 14 It details the process of forming based on some implementation schemes. Figure 3 A simplified cross-sectional view of an exemplary process of the LDMOS device shown.

[0011] Figures 15 to 19B The following are examples of methods for forming according to some embodiments. Figure 3 A simplified step of a part of the exemplary process of the LDMOS device shown. Detailed Implementation

[0012] Compared to other metal-oxide-semiconductor field-effect transistors (MOSFETs) without a lightly doped drain (LDD) region, the LDD region of a laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS) provides an increased breakdown voltage for the LDMOS device, at the cost of increased on-resistance. The conductivity of the LDD region and the length of the LDD region are each proportional to the impedance of the region in the direction of current flow. Therefore, the breakdown voltage of the LDMOS device can be increased by reducing the doping level of the LDD region or by extending the lateral extent of the LDD. This relationship presents challenging design problems because it is generally desirable to keep the on-state resistance of the LDMOS device low, or the LDMOS device will consume significant power when it draws large currents from power devices such as LDMOS devices.

[0013] This document discloses a semiconductor structure comprising at least one LDMOS device having a single or multiple fingers, which advantageously improves several key features compared to conventional LDMOS devices. These features include enhanced robustness to process variations, enhanced stability associated with high electric fields and breakdown conditions, lower resistance connections to the channel regions of the LDMOS device for source / drain current, and / or increased robustness in handling avalanche-generated minority carriers. Additional advantages of the LDMOS device disclosed herein compared to conventional LDMOS devices include reduced specific Rdson or Rsp due to the compactness of the source region of the LDMOS device, improved manufacturability, and / or lower wafer costs.

[0014] Compared to conventional LDMOS devices, Figure 1 A portion of a cross-section of a laterally diffused MOSFET (LDMOS) device 102 according to some embodiments is shown, the LDMOS device having a device architecture that significantly improves device performance and reduces manufacturing variations. Figure 1 Some components of the LDMOS device 102 have been omitted to simplify the description of the LDMOS device 102. Generally, the LDMOS device 102 is a silicon-on-insulator (SOI) device, which includes a semiconductor wafer comprising a substrate 104, a buried oxide (BOX) layer 106 (e.g., SiO2) on the substrate 104, and an active layer 107 on the BOX layer 106. A gate and contact layer 108 is on the active layer 107, and a metallization layer (i.e., top metal) 109 is on the gate and contact layer 108.

[0015] As described herein, a first layer is formed, adhered to, or disposed on at least a portion of the second layer, or is "formed on" or "on the second layer". Generally, at least a portion of the lowest vertical extent of the first layer is in direct contact with at least a portion of the highest vertical extent of the second layer, or in direct contact with a bonding material (such as an adhesive or solder that connects the first layer to the second layer). For example, the active layer 107 of the LDMOS device 102 is above the substrate 104, but not "on" the substrate 104. More precisely, the active layer 107 of the LDMOS device 102 is formed "on" the BOX layer 106. In some embodiments, bonding elements (such as chemical adhesives or solders) may be inserted between the first layers formed on the second layer.

[0016] For an n-type LDMOS device, the active layer 107 typically includes an n-type conductive silicon 117, an n-type conductive source region 110, a p-type conductive source connection region 111, a p-type conductive shallow well 112, a p-type conductive deep well 114, a p-type conductive channel region 116, an n-type conductive drift region 118 (i.e., the LDD region), and an n-type conductive drain region 120. For a p-type LDMOS device, the region conductivity types are reversed. The gate and contact layer 108 typically includes a gate oxide layer 124, a gate polysilicon 122, a first portion 135 of a metal source contact, a first portion 134 of a metal drain contact, polysilicon gate spacers 128 and 129, a gate contact 126, a gate shield 130, a second portion 136 of a metal source contact, a second portion 138 of a metal drain contact, and a dielectric 139. The metallization layer 109 typically includes a third portion 140 of a metal source contact and a third portion 142 of a metal drain contact.

[0017] As disclosed herein, the source architecture, including source region 110, channel region 116, shallow well 112, deep well 114, and source connection region 111, advantageously provides a stable electrical plane from which the gate, drift, and drain regions of the LDMOS device 102 operate under a wide range of bias conditions. This source architecture is advantageously formed using an exemplary process 1500, as disclosed herein, which limits variations in critical source-controlled electrical parameters such as Vt and Ioff. Compared to the source architecture of a conventional LDMOS device, the source architecture of the LDMOS device 102 advantageously provides increased quick-back and unclamped inductive switching (UIS) robustness, lower source resistance presented to current when the LDMOS device 102 is turned on, and lower source leakage current when the LDMOS device 102 is turned off. The gate shield 130 advantageously reduces the capacitive coupling of the metallization from the gate polysilicon 122 to the drain region 120. Additionally, as disclosed herein, an exemplary process 1500 for forming an LDMOS device 102 involves using a single photomasking step to form the channel region 116, shallow well 112, deep well 114, and source region 110. Therefore, process 1500 advantageously reduces the total number of photomasking steps compared to conventional processes for forming conventional LDMOS devices, in which each of the aforementioned regions is processed in a separate photomasking step.

[0018] Drain region 120 is configured to receive a bias voltage (not shown), and gate polysilicon 122 controls the inversion / depletion of channel region 116 to control current flow between drain region 120 and source region 110 via drift region 118 and channel region 116. Channel region 116 is p-type doped in active layer 107 beneath gate polysilicon 122. The doping and lateral extent of channel region 116 contribute to generating the desired Vt of LDMOS device 102 and affect other parameters of LDMOS device 102, such as Rsp, Ids, Ioff, and Gm. Deep well 114 is heavily p-type doped beneath source region 110. Therefore, deep well 114 advantageously helps to weaken source-side parasitic bipolar transistors, enabling LDMOS device 102 to meet application requirements in terms of quick-turn and UIS. The source region 110 is heavily doped and shallower than the source region of a conventional LDMOS device to allow the deep well 114 to advantageously and efficiently collect avalanche-generated minority carriers without the source-side parasitic bipolar transistor being turned on.

[0019] The implantation conditions of the source region 110, channel region 116, deep well 114, and shallow well 112 ensure that the dopant does not penetrate the thickness of the gate polysilicon 122. This has the effect of doping the active layer 107 based on the location where the gate polysilicon 122 is etched from the active layer 107. In the case of the channel region 116, the dopant material is implanted at an angle and penetrates the edge of the gate polysilicon 122 to form the channel region 116. Compared to the conventional process for forming a conventional LDMOS device, introducing the dopant into the active layer 107 in this manner advantageously eliminates the processing differences in photoresist misalignment or critical size control. Therefore, compared to conventional LDMOS devices, the LDMOS device 102 formed using the process 1500 disclosed herein advantageously includes: i) a repeatable length (i.e., lateral range) of the channel region 116 below the gate polysilicon 122, thereby eliminating a significant source of variation in the electrical parameters of the LDMOS device 102; ii) a deep well 114 aligned directly below the source region 110, thereby achieving stable UIS and quick-return performance of the LDMOS device 102, which remains unchanged between the relative fingers of the multi-finger LDMOS device; and iii) a thermally driven source region 110 embedded at the edge of the gate polysilicon 122 and within a controlled distance, thereby advantageously providing good connectivity between the source region 110 and the channel inversion layer, thereby improving the source-to-drain current level Ids of the LDMOS device 102.

[0020] Figure 2A illustrates a basic prior art LDMOS device 200, which includes a source contact 201, a drain contact 202, an n+ source region 203, a p+ source contact region 204, an n+ drain region 205, a p-well 206, an n-epitaxial region 207, a gate 208, and a gate oxide 209. The p-well 206 forms a body region, and a channel region is formed in a portion of the body region below the gate 208. The n-epitaxial region 207 includes an n-drift region 210 near its top surface between the p-well 206 and the n+ drain region 205.

[0021] Compared to LDMOS device 102, the prior art LDMOS device 200 has several disadvantages. For example, the high voltage in the junction region formed between the channel region and the n-drift region 210 in the p-well 206 generally results in a relatively low breakdown voltage compared to the breakdown voltage BVdss achieved using the improved design of LDMOS device 102.

[0022] Figure 2B illustrates another prior art LDMOS device 220, which includes a source contact 221, a drain contact 222, an n+ source region 223, a p+ source connection region 224, an n+ drain region 225, a p-well region 226, a p-epitaxial region 227, a gate 228, a gate oxide 229, an n-drift region 230, and a localized oxide of silicon (LOCOS) isolation region 231. The p-well region 226 forms the body region, and a channel region is formed in a portion of the body region below the gate 228. The n-drift region 230 is embedded in the p-epitaxial region 227, and the LOCOS isolation region 231 is formed on the n-drift region 230. A portion of the gate 228 extends as a field plate above the LOCOS isolation region 231. The prior art LDMOS device 220 is a higher voltage device than the LDMOS device 200. To achieve the higher voltage capability, the n-drift region 230 must be extended and / or the doping of the n-drift region 230 must be reduced. The LOCOS isolation region 231 reduces the doping of the n-drift region 230. In these designs, the n+ drain region 225 must be moved further away from the p-well region 226 because the silicon of the LDMOS device 220 can handle ~30V / µm before avalanche breakdown occurs. In conventional LDMOS devices, 15V / µm to 20V / µm is the typical avalanche limit. Therefore, to increase BVdss, Rsp must be increased in these designs.

[0023] Figure 3 A cross-section of a multi-finger LDMOS device 302 according to some embodiments is shown. In some embodiments, the LDMOS device 302 typically includes two fingers 301a, 301b, each finger being similar to or identical to that of the LDMOS device 102. In other embodiments, the LDMOS device 302 includes more than two fingers. Generally, the LDMOS device 302 includes a substrate 304, a BOX layer 306 on the substrate 304, an n-type active layer 307 on the BOX layer 306, a gate and contact layer 308 on the active layer 307, and a metallization layer 309 on the gate and contact layer 308.

[0024] LDMOS device 302 is described herein as an n-type LDMOS device having an n-type conductive (“n-type”) region and a p-type conductive (“p-type”) region. However, LDMOS device 302 may alternatively be implemented as a p-type LDMOS device, thus swapping the conductivity of the respective regions (i.e., the n-type region becomes the p-type region).

[0025] Some regions of the active layer 307 are shared between the fingers 301a and 301b. The regions of the active layer 307 shared between the fingers 301a and 301b include a heavily doped p-type source connection region 311, a p-type shallow well 312, and a p-type deep well 314. A first portion of the active layer 307 specific to the first finger 301a includes a first n-type silicon region 317a, a first n-type source region 310a, a first p-type channel region 316a, a first n-type drift region 318a (i.e., the LDD region), and a first n-type drain region 320a. A second portion of the active layer 307 specific to the second finger 301b includes a second n-type silicon region 317b, a second n-type source region 310b, a second p-type channel region 316b, a second n-type drift region 318b (i.e., the LDD region), and a second n-type drain region 320b.

[0026] Some elements of the gate and contact layer 308 are shared between the fingers 301a and 301b. The shared elements between the fingers 301a and 301b include a first portion 335 of a metal source contact and a second portion 336 of a metal source contact. The first portion of the gate and contact layer 308 specific to the first finger 301a includes a first gate oxide layer 324a, a first gate polysilicon 322a, first polysilicon gate spacers 328a and 329a, a first gate contact 326a, a first gate shield 330a, a first portion 334a of a first metal drain contact, a second portion 338a of a first metal drain contact, and a first dielectric 339a. The second portion of the gate and contact layer 308, specific to the second finger 301b, includes a second gate oxide layer 324b, a second gate polysilicon 322b, second polysilicon gate spacers 328b and 329b, a second gate contact 326b, a second gate shield 330b, a first portion 334b ​​of the second metal drain contact, a second portion 338b of the second metal drain contact, and a second dielectric 339b. The metallization layer 309 typically includes a third portion 340 of the metal source contact, a third portion 342a of the first metal drain contact, and a third portion 342b of the second metal drain contact, shared between the fingers 301a and 301b. The advantages of the LDMOS device 302 compared to conventional LDMOS devices are similar to or the same as those described with reference to LDMOS device 102.

[0027] Figures 4 to 14 This is a simplified cross-sectional schematic diagram detailing the steps for forming an LDMOS device 102 or 302 at various stages of an exemplary process 1500, according to some embodiments. Figures 4 to 14 The details are briefly introduced below, followed by a reference. Figures 15 to 18 and Figures 19A to 19B A detailed discussion will follow.

[0028] Figure 4 This is a simplified cross-sectional view of a schematic diagram of the first step in forming an LDMOS device 402 that is the same as or similar to LDMOS devices 102 and 302 according to some embodiments. The LDMOS device 402 includes first and second portions of corresponding first fingers 401a and second fingers 401b. The area and elements of the LDMOS device 402 specified by "a" are understood to be part of the first finger 401a. The area and elements of the LDMOS device 402 specified by "b" are understood to be part of the second finger 401b. The area and elements of the LDMOS device 402 not specified by "a" or "b" are understood to be shared by the two fingers 401a, 401b. In some embodiments, the LDMOS device 402 formed by process 1500 may have one finger, two fingers, or more than two fingers.

[0029] The region of the LDMOS device 402 typically includes a substrate layer 404, a buried oxide (BOX) layer 406 formed on the substrate layer 404, and an n-type silicon active layer 407 formed on the BOX layer 406. The first gate of the first finger 401a includes a gate oxide 424a and a gate polysilicon 422a formed on the active layer 407. The second gate of the second finger 401b includes a gate oxide 424b and a gate polysilicon 422b, which are formed on the active layer 407 and laterally disposed from the gate oxide 424a and the gate polysilicon 422a. In some embodiments, the LDMOS device 402 includes shallow trench isolation (STI) structures (not shown) and deep trench isolation (DTI) structures (not shown), which are formed in the active layer 407 to provide isolation and / or termination between the LDMOS device 402 and other semiconductor structures formed on the box 406.

[0030] Figure 5 An LDMOS device 402 is shown after a first mask “Mask1” has been formed on the active layer 407. According to some embodiments, the first mask Mask1 includes photoresist regions 561a, 561b formed on the active layer 407 as part of an exemplary process 1500. Also shown are the exposed lateral extent 512 of the active layer 407 (i.e., where no photoresist or gate polysilicon is disposed), the first lateral extent 513a of the gate polysilicon 422a, the second lateral extent 514a of the gate polysilicon 422a, the first lateral extent 513b of the gate polysilicon 422b, and the second lateral extent 514b of the gate polysilicon 422b.

[0031] As shown in the figure, a first photoresist region 561a is formed on a first lateral region 513a of the first gate polysilicon 422a, and excludes both the second lateral region 514a of the gate polysilicon 422a and the exposed lateral region 512 of the active layer 407 (i.e., not formed on either of them). Similarly, a second photoresist region 561b is formed on a first lateral region 513b of the second gate polysilicon 422b, and excludes both the second lateral region 514b of the gate polysilicon 422b and the exposed lateral region 512 of the active layer 407 (i.e., not formed on either of them). In some implementations, the lateral range 512 can be selected based on design rules (e.g., the spacing between the gate polysilicon and the source contacts), desired operating parameters, and / or manufacturing capabilities; the lateral ranges 513a to 513b can be selected based on desired performance criteria of the LDMOS device 402 (such as IDsat and hot carrier robustness); and the lateral ranges 514a to 514b can be selected based on desired alignment criteria between the photoresist regions 561a to 561b and the gate polysilicon regions 422a to 422b.

[0032] Figure 6 A p-type channel region 616 is formed in an active layer 407 using photoresist regions 561a, 561b and gate polysilicon 422a, 422b as a mask for forming a channel region 616. Dopant 671 is implanted at a first tilt angle 652a (as shown by the dashed arrow) and a second tilt angle 652b (as shown by the solid arrow) to form the channel region 616. The implantation conditions of the channel region 616 ensure that the dopant does not penetrate the thickness of the gate polysilicon 422a, 422b. The channel region 616 extends laterally below the gate polysilicon 422a to a first lateral range 614a. Similarly, the channel region 616 extends laterally below the gate polysilicon 422b to a second lateral range 614b.

[0033] In some embodiments, dopant 671 is a p-type dopant comprising boron. The boron implantation condition of dopant 671 depends on the thickness of gate oxides 424a to 424b and the desired channel length of channel region 616 (e.g., the desired corresponding length of lateral ranges 614a to 614b). For example, in some embodiments, for a gate oxide thickness of 70 angstroms for gate oxides 424a to 424b, the implantation dose of dopant 671 can be 1e13 B / cm. 2 Up to 7e13B / cm 2Within this range, it depends on the degree to which other dopants in the LDMOS device 402 affect the doping of the channel region 616. In some embodiments, the tilt angles 652a to 652b (relative to a plane perpendicular to a horizontal plane parallel to the top surface of the active layer 407) are in the range of 7 degrees to 45 degrees, and can be selected to suit the desired lateral range 614a to 614b of the channel region 616. Shallower tilt angles (e.g., 7 degrees) within the range of tilt angles 652a to 652b will produce a shorter channel length for the channel region 616 compared to larger tilt angles (e.g., 45 degrees).

[0034] Figure 7 This diagram illustrates an LDMOS device 402, according to some embodiments, formed in the active layer 407 by using photoresist regions 561a, 561b and gate polysilicon 422a, 422b as masks (i.e., Mask 1) and dopant 772 implanted at an angle 753 to form p-type shallow wells 712 and p-type deep wells 714. The p-type shallow wells 712 and p-type deep wells 714 convert the implanted regions of n-type active silicon in the active layer 407 into p-type silicon, thereby forming the LDMOS device 402 and enabling it to exhibit the desired quick-return and UIS performance. As shown, wells 712, 714 now... Figure 6 The channel region 616 shown is divided into p-type channel regions 716a and 716b. Similar to channel region 616, the implantation conditions of wells 712 and 714 prevent dopant from penetrating the thickness of the gate polysilicon 422a and 422b. In some embodiments, the tilt angle 753 is perpendicular to the horizontal plane parallel to the top surface of the active layer 407; in other embodiments, the tilt angle 753 is in the range of 70 degrees to 120 degrees relative to the horizontal plane parallel to the top surface of the active layer 407. In some embodiments, the dopant 772 is a p-type dopant comprising boron and with a dopant ratio from 1e13 B / cm. 2 Up to 7e13 B / cm 2 Implantation at concentrations within a certain range.

[0035] Figure 8The diagram illustrates an LDMOS device 402 after forming an n-type source region 810 of depth 851 using photoresist regions 561a, 561b and gate polysilicon 422a, 422b as a mask (i.e., Mask 1) through dopant 873 at an angle 854. In some embodiments, the photoresist regions 561a to 561b extend to the outer edge of the LDMOS device 402. In some embodiments, the angle 854 is in the range of 70 to 120 degrees relative to a horizontal plane parallel to the top surface of the active layer 407. The implantation conditions of the source region 810 prevent the dopant 873 from penetrating the thickness of the gate polysilicon 422a, 422b. The source region 810 has a higher implantation concentration and a shallower depth compared to the source regions of conventional LDMOS devices. In some embodiments, the dopant 873 is an n-type dopant and includes arsenic, with a concentration from 1e14As / cm². 2 Up to 2.5e15 As / cm 2 The implantation is at a relatively high concentration within the range of [specific values]. To achieve shallow depth, low-energy implantation is used to implant the source region 810; for example, for an arsenic source, the low-energy implantation has a range of 7 keV to 20 keV. In some embodiments, the dopant 873 includes first and second arsenic implantations. The first arsenic implantation is a low-energy, high-concentration arsenic implantation to form an n-type source region 810 near the top surface of the active layer 407, such as [specific example]. Figure 8 The diagram shows the depth 851 of the n-type source region 810. In some embodiments, the depth 851 of the source region 810 is in the range of 80 nm to 200 nm. In some embodiments, the second arsenic implantation of dopant 873 is performed at a slightly higher energy and at a similar concentration compared to the first arsenic implantation of dopant 873. In these embodiments, the energy of the second arsenic implantation of dopant 873 is in the range of 20 keV to 70 keV. The source region 810 is aligned with the gate polysilicon 422a to 422b.

[0036] After forming the source region 810, the photoresist regions 561a to 561b of Mask1 are removed.

[0037] In the conventional process for forming an LDMOS device, source region doping is routinely performed at the standard N+ photo / implantation step. Therefore, the LDMOS device formed using the conventional process has a deeper n-junction compared to the LDMOS device 402 disclosed herein. Consequently, the deep p-well implantation of a conventional LDMOS device may need to be deeper than that of LDMOS device 402, and therefore may not be self-aligned with the gate polysilicon opening of the active layer of the device. In contrast, Figures 5 to 8The use of a single mask (Mask1) is illustrated, which includes photoresist (561a to 561b) and utilizes gate polysilicon 422a to 422b to advantageously form four self-aligned and gate polysilicon-aligned regions (616, 712, 714, 810) of the LDMOS device 402. Additionally, doping both sides of the source region adjacent to the gate polysilicon of a conventional LDMOS device using a conventional n-type photo / implantation step can leave long, thin lines of resist centered between the gate polysilicon of the device, allowing for the implantation of p-type source connection regions, which can lead to resist lift-up processing problems. The process 1500 disclosed herein avoids this problem by using a source region dopant concentration lower than the p-type dopant concentration of the source connection regions, thereby allowing p-type dopant to de-dope the source regions.

[0038] Figure 9 An LDMOS device 402 is shown according to some embodiments after a second mask Mask2, including a photoresist region 962, is formed on an active layer 407, and after drift regions 918a, 918b (i.e., LDD regions) are formed in the active layer 407 using the photoresist region 962 as a drift region mask through dopant 974 at an angle 955. The implantation module for forming the n-type drift regions 918a to 918b includes one or more implantation steps to customize the doping profile of the drift regions 918a to 918b. (The last sentence appears to be incomplete and possibly refers to a different implementation.) 2 Up to 7e12 P / cm 2 Individual doses of dopant 974 are implanted at concentrations within the range specified. In some embodiments, the tilt angle 955 is perpendicular to a horizontal plane parallel to the top surface of the active layer 407; in other embodiments, the tilt angle 955 is in the range of 70 to 120 degrees relative to a horizontal plane parallel to the top surface of the active layer 407. After forming drift regions 918a to 918b, the photoresist regions 962 of Mask 2 are removed.

[0039] Figure 10An LDMOS device 402 according to some embodiments is shown after a third mask Mask3, including a photoresist region 1063, has been formed on an active layer 407, and after n-drain regions 1020a and 1020b are formed in the active layer 407 using the photoresist region 1063 as a drain region mask through dopant 1075 at a tilt angle 1056. Polysilicon gate spacers 1028a, 1028b and 1029a, 1029b formed on the respective inner and outer sides of the gate polysilicon 422a and 422b are also shown. Polysilicon gate spacer 1029a is vertically disposed above drift region 918a, while polysilicon gate spacer 1028a is vertically disposed above source region 810. Similarly, polysilicon gate spacers 1029b are vertically disposed above drift region 918b, while polysilicon gate spacers 1028b are vertically disposed above source region 810. In some embodiments, the respective lateral ranges of gate spacers 1028a to 1028b and 1029a to 1029b are selected according to the desired lateral range of the source connection region of LDMOS device 402. In some embodiments, dopant 1075 is an n-type dopant comprising arsenic and phosphorus, and at, for example, 3e15 As / cm 2 and 8e13 P / cm 2 High-concentration implantation is used to form a low-resistance ohmic contact with the corresponding metal drain electrode. After forming drain regions 1020a to 1020b, the photoresist region 1063 of Mask3 is removed.

[0040] Figure 11AA first example of an LDMOS device 402, according to some embodiments, is shown after a fourth mask Mask4, including photoresist regions 1164a and 1164b, has been formed on an active layer 407, and after a heavily doped p-type source connection region 1111 has been formed in the active layer 407 using photoresist regions 1164a and 1164b as a mask through dopant 1176 implanted at an angle 1157. In some embodiments, photoresist regions 1164a to 1164b extend to the outer edge of the LDMOS device 402. Photoresist region 1164a extends on the active layer 407 beyond the inner edge of the polysilicon gate spacer 1028a to a lateral extent 1114a. Similarly, photoresist region 1164b extends on the active layer 407 beyond the inner edge of the polysilicon gate spacer 1028b to a lateral extent 1114b. Therefore, the photoresist region 1164a extends to or beyond the entire lateral extent of the polysilicon gate spacer 1028a, while the photoresist region 1164b extends to or beyond the entire lateral extent of the polysilicon gate spacer 1028b. The region of the active layer 407 between the lateral extents 1114a and 1114b is exposed to a dopant 1176 implanted at an angle 1157 to form the source connection region 1111. As shown in the figure, Figure 8 The source region 810 has been divided into n-type source regions 1110a and 1110b by the source connection region 1111. Figure 11A and Figure 11B The source connection region 1111 / 1111' shown is a heavily doped p-type region suitable for forming a good ohmic contact with the metal source contact. In some embodiments, the tilt angle 1157 is perpendicular to the horizontal plane parallel to the top surface of the active layer 407; in other embodiments, the tilt angle 1157 is in the range of 70 degrees to 120 degrees relative to the horizontal plane parallel to the top surface of the active layer 407. In some embodiments, the dopant 1176 is a p-type dopant comprising boron and with a dopant ratio from 1e15 B / cm 2 Up to 5e15B / cm 2 High-concentration implantation within a certain range. In some embodiments, the lateral ranges 1114a to 1114b have a width of 0 nm to 0.2 μm, while the lateral range of the exposed area of ​​the active layer 407 has a width of 0.1 μm to 0.4 μm.

[0041] Figure 11BAn alternative example of an LDMOS device 402, according to some embodiments, is shown where an alternative fourth mask Mask4', including photoresist regions 1164a' and 1164b', has been formed on the active layer 407, and where the photoresist regions 1164a', 1164b' and polysilicon gate spacers 1028a', 1028b have been used as masks after a heavily doped p-type connection region 1111' has been formed in the active layer 407 by dopant 1176 at an angle of 1157. In some embodiments, the photoresist regions 1164a' to 1164b' extend to the outer edge of the LDMOS device 402. As shown in the figure... Figure 8 The source region 810 has been divided into n-type source regions 1110a and 1110b by the source connection region 1111'.

[0042] Photoresist region 1164a' is not included in the lateral range 1116a of polysilicon gate spacer 1028a (i.e., not formed in said lateral range), and photoresist region 1164b' is not included in the lateral range 1116b of polysilicon gate spacer 1028b. The region of active layer 407 between polysilicon gate spacers 1028a and 1028b is exposed to dopant 1176 implanted at an angle 1157 to form source connection region 1111'. The lateral ranges 1116a to 1116b of polysilicon gate spacers 1028a to 1028b are operable to mask active layer 407 relative to dopant 1176, and thus, the source connection region 1111' formed by dopant 1176 is advantageously aligned with the inner edge 1115 of polysilicon gate spacers 1028a to 1028b. In some embodiments, the lateral ranges 1116a to 1116b have a width of 30 nm to 100 nm, while the lateral range of the exposed area of ​​the active layer 407 has a width of 0.2 μm to 0.6 μm.

[0043] In contrast, the photoresist regions typically separated between the gate polysilicon of a conventional LDMOS device during formation are usually sufficiently spaced to allow for source implantation and polysilicon gate spacers. However, in the illustrated embodiment, the photoresist regions 1164a', 1164b' are pulled close to or overlap with the polysilicon gate spacers 1028a, 1028b, thereby forming the source connection region 1111', which is self-aligned with the polysilicon gate spacers 1028a, 1028b. Therefore, the polysilicon gate spacers 1028a, 1028b shield the source regions 1110a, 1110b from the dopant 1176. As a result, a smaller source region 1110a to 1110b is advantageously produced in the LDMOS device 402 compared to conventional LDMOS devices.

[0044] Figure 12 This illustrates an LDMOS device 402 after some elements of the gate and contact layer 1208 are formed on the active layer 407, according to some embodiments. Figure 12 The elements of the gate and contact layer 1208 shown include a first portion 1234a of a first metal drain contact, a first gate shield 1230a, a first gate contact 1226a, a metal source contact 1235, a first portion 1234b of a second metal drain contact, a second gate shield 1230b, a second gate contact 1226b, and a dielectric 1239. As shown, the first gate contact 1226a is formed on the first gate polysilicon 422a. The first portion of the gate shield 1230a is formed above the first gate contact 1226a. The second portion of the gate shield 1230a extends laterally beyond the polysilicon gate spacer 1029a and is vertically disposed above the drift region 918a. The second portion of the gate shield 1230a is closer to the top surface of the active layer 407 than the first portion of the gate shield 1230a. Similarly, the second gate contact 1226b is formed on the second gate polysilicon 422b. A first portion of the gate shield 1230b is formed above the second gate contact 1226b. A second portion of the gate shield 1230b extends laterally beyond the polysilicon gate spacer 1029b and is vertically disposed above the drift region 918b. The second portion of the gate shield 1230b is closer to the top surface of the active layer 407 than the first portion of the gate shield 1230b. Figure 12 During the formation stage of the LDMOS device 402 shown, dielectric 1239 covers all components of the gate and contact layer 1208. Gate shields 1230a to 1230b advantageously reduce the capacitive coupling between the gate polysilicon 422a to 422b and the metallization of the corresponding drain regions 1020a to 1020b.

[0045] Figure 13 A first example of an LDMOS device 402 is shown after forming additional elements of the gate and contact layer 1208 and metallization layer 1309 on the active layer 407, according to some embodiments. Figure 13 The elements of the gate and contact layer 1208 shown include a second portion 1338a of a first metal drain contact, a second portion 1338b of a second metal drain contact, a first portion 1339a of a dielectric, and a dielectric (such as...) Figure 12As shown, the second portion 1339b of the dielectric 1239 is shown. The metallization layer 1309 includes a third portion 1342a of the first metal drain contact, a third portion 1340 of the metal source contact (i.e., the top metal), and a third portion 1342b of the second metal drain contact (i.e., the top metal). Dimension indicators for the lateral ranges 1358, 1359a, 1359b, and 1360 are also shown.

[0046] In some implementations, the layout dimensions of the source region of the LDMOS device 402 are determined by the lateral range 1358 between the gate polysilicon 422a and 422b, the width 1360 of the second portion 1336 of the metal source contact, the lateral range 1359a between the gate polysilicon 422a and the second portion 1336 of the metal source contact, and the lateral range 1359b between the gate polysilicon 422b and the second portion 1336 of the metal source contact, and depend on the technology node of the LDMOS device 402. As a first example, for the 0.18μm technology node, the lateral range 1358 (i.e., source width) between the gate polysilicon 422a and 422b can be equal to 0.25μm, the width 1360 of the second portion 1336 of the metal source contact can be equal to 0.22μm, and the lateral ranges 1359a and 1359b between the gate polysilicon 422a and 422b and the second portion 1336 of the metal source contact can each be equal to 0.16μm. As a second example, for the 90nm technology node, the lateral range 1358 between the gate polysilicon 422a and 422b can be equal to 0.17μm, the width 1360 of the second portion 1336 of the metal source contact can be equal to 0.12μm, and the lateral ranges 1359a and 1359b between the gate polysilicon 422a and 422b and the second portion 1336 of the metal source contact can each be equal to 0.10μm. In some implementations, the constraint rule for the minimum source width (i.e., lateral range 1358) of the LDMOS device 402 is equal to the width 1360 plus the lateral range 1359a plus the lateral range 1359b. Therefore, using the exemplary dimensions previously given in this paragraph, the source width of the LDMOS device 402 is 0.54 μm for the 0.18 μm node and 0.32 μm for the 90 nm technology node.

[0047] Figure 14 A second example of an LDMOS device 402 is shown after forming additional elements of the gate and contact layer 1208 and metallization layer 1309 on the active layer 407, according to some embodiments. Figure 14The elements of the gate and contact layer 1208 shown include a second example of a second portion 1436 of a metal source contact. In the illustrated exemplary embodiment, gate shield 1230a serves as a metal source contact etch stop layer for the second portion 1436 of the metal source contact, such that the second portion 1436 of the metal source contact partially overlaps with the gate shield 1430a along a first vertical width. The second portion 1436 of the metal source contact has a first width 1460a above the top surface of the first gate shield 1230a along the first vertical width, and a second narrower width 1460b below the top surface of the first gate shield 1230a and between the gate polysilicon 422a and 422b along a second vertical width. In the illustrated example, the first width 1460a is wider than the second width 1460b. By advantageously providing a wider area for forming a third portion 1340 of the metal source contact, the overlapping gate shield portion allows the source contact to narrow at the p-type source connection region 1111. That is, the width 1460b is narrower than the minimum contact feature size of the LDMOS device 402. As a result, the cell pitch of the LDMOS device 402 can be reduced compared to a conventional LDMOS device.

[0048] According to some implementation plans Figure 15 The exemplary process 1500 shown in the figure describes in a high-level manner the details for forming LDMOS devices 302 / 402. Figure 15 The specific steps, sequence of steps, and combinations of steps are shown for illustrative and explanatory purposes only. Other embodiments may implement different specific steps, sequences of steps, and combinations of steps to achieve similar functions or results. Reference Figures 4 to 14 describe Figure 15 The steps.

[0049] At step 1502, a semiconductor wafer (e.g., substrate 404 and BOX layer 406) having an active n-type layer 407 is provided. At step 1504, gate oxides 424a to 424b and gate polysilicon 422a to 422b are formed on the active layer 407. At step 1506, as part of a process designated as Mask 1, a p-type channel region 616, a p-type shallow well 712, a p-type deep well 714, and an n-type source region 810 are each formed in the active layer 407. At step 1508, as part of a process designated as Mask 2, n-type drift regions 918a and 918b are formed in the active layer 407. At step 1510, polysilicon gate spacers 1028a to 1028b and 1029a to 1029b are formed adjacent to the gate polysilicon 422a to 422b. At step 1512, as part of the process designated as Mask3, n-type drain regions 1020a to 1020b are formed in the active layer 407. At step 1514, as part of the process designated as Mask4, p-type source connection regions 1111 are formed in the active layer 407 (or p-type source connection regions 1111' are formed using Mask4'). At step 1516, gate shields 1230a to 1230b, gate contacts 1226a to 1226b, metal drain contacts 1234a to 1234b, 1338a to 1338b, metal source contacts 1235, 1336, and top metals 1340, 1342a to 1342b are formed, and dielectrics 1339a to 1339b are formed.

[0050] Figure 16 Details of an exemplary implementation of step 1506 (“Mask1 process”) according to some implementation schemes are shown. Figure 16 The specific steps, sequence of steps, and combinations of steps are shown for illustrative and explanatory purposes only. Other embodiments may implement different specific steps, sequences of steps, and combinations of steps to achieve similar functions or results. Reference Figures 5 to 8 describe Figure 16 The steps.

[0051] At step 1602, a masking region Mask1 is formed on the active layer 407. The masking region Mask1 includes photoresist regions 561a, 561b and gate polysilicon 422a to 422b advantageously operable to perform a masking function. At step 1604, as... Figure 6As shown, using photoresist regions 561a, 561b and gate polysilicon 422a to 422b as a mask, a p-type channel region 616 is formed in the active layer 407 by dopant 671. The dopant 671 is implanted at a first-range tilt angle 652a and thermally driven to form a first portion of the p-type channel region 616, the first portion extending horizontally below the gate polysilicon 422a to a lateral range 614a. Similarly, the dopant 671 is implanted at a second-range tilt angle 652b and thermally driven to form a second portion of the p-type channel region 616, the second portion extending horizontally below the gate polysilicon 422b to a lateral range 614b. A third portion of the p-type channel region 616 is formed by implantation at any of or a combination of tilt angles 652a to 652b, the third portion extending laterally between the inner edge 615 of the gate polysilicon 422a and the gate polysilicon 422b.

[0052] At step 1606, as Figure 7 As shown, photoresist regions 561a to 561b and gate polysilicon 422a to 422b are used as masks to form a p-type shallow well 712 in the active layer 407 using dopant 772. The dopant 772 is implanted at an angle 753, so that the p-type shallow well 712 is aligned with the inner edge 615 of the gate polysilicon 422a to 422b.

[0053] At step 1608, photoresist regions 561a to 561b and gate polysilicon 422a to 422b are used as masks for heavy p-type doping, and a p-type deep well 714 is formed in the active layer 407 by dopant 772. The dopant 772 is implanted at an angle 753 such that the deep well 714 is aligned with the inner edge 615 of the gate polysilicon 422a to 422b, but the dopant 772 can diffuse.

[0054] At step 1610, as Figure 8 As shown, photoresist regions 561a and 561b and gate polysilicon 422a and 422b are used as masks, and an n-type source region 810 is formed in the active layer 407 by dopant 873 implanted at an angle 854. In step 1612, the photoresist regions 561a and 561b of the Mask1 region are removed.

[0055] Figure 17 Details of an exemplary implementation of step 1508 (“Mask2 process”) according to some implementation schemes are shown. Figure 17 The specific steps, sequence of steps, and combinations of steps are shown for illustrative and explanatory purposes only. Other embodiments may implement different specific steps, sequences of steps, and combinations of steps to achieve similar functions or results. Reference Figure 9 describe Figure 17The steps.

[0056] At step 1702, a masking region Mask2 is formed on the active layer 407. In some embodiments, the masking region Mask2 includes a photoresist region 962, and the gate polysilicon 422a to 422b are advantageously operable to perform a masking function. At step 1704, as... Figure 9 As shown, using photoresist region 962 and gate polysilicon 422a to 422b as a mask, n-type drift regions 918a to 918b are formed in the active layer 407 by dopant 974 implanted at an angle 955. At step 1706, the photoresist region 962 of Mask2 is removed.

[0057] Figure 18 Details of an exemplary implementation of step 1512 (“Mask3 process”) according to some implementation schemes are shown. Figure 18 The specific steps, sequence of steps, and combinations of steps are shown for illustrative and explanatory purposes only. Other embodiments may implement different specific steps, sequences of steps, and combinations of steps to achieve similar functions or results. Reference Figure 10 describe Figure 18 The steps.

[0058] At step 1802, a masking region Mask3 is formed on the active layer 407. In some embodiments, the masking region Mask3 includes a photoresist region 1063. At step 1804, as... Figure 10 As shown, using photoresist region 1063 as a mask, n-type drain regions 1020a and 1020b are formed in the active layer 407 by dopant 1075 implanted at an angle of 1056. The dopant 1075 is deposited at an angle of 1056 such that the n-drain regions 1020a to 1020b are aligned with the outer edge of the photoresist region 1063. In some embodiments, the angle of 1056 is in the range of 70 degrees to 120 degrees relative to the top surface of the horizontal plane parallel to the active layer 407. At step 1806, the photoresist region 1063 of the Mask3 region is removed.

[0059] Figure 19A Details of a first exemplary implementation of step 1514 (“Mask4 process”) according to some implementation schemes are shown. Figure 19A The specific steps, sequence of steps, and combinations of steps are shown for illustrative and explanatory purposes only. Other embodiments may implement different specific steps, sequences of steps, and combinations of steps to achieve similar functions or results. Reference Figure 11A describe Figure 19AThe steps are as follows. In step 1902a, a masking region Mask4 is formed on the active layer 407. In some embodiments, the masking region Mask4 includes photoresist regions 1164a, 1164b. In step 1904a, as... Figure 11A As shown, photoresist regions 1164a to 1164b are used as a mask, and a p-type (i.e., P+) source connection region 1111 is formed in the active layer 407 using dopant 1176. Dopant 1176 is implanted at an angle of 1157, such that the p-type source connection region 1111 is aligned with the inner edges of the photoresist regions 1164a to 1164b. At step 1906a, the photoresist regions 1164a and 1164b of the Mask4 region are removed.

[0060] Figure 19B Details of a second exemplary implementation of step 1514 (“Mask4 process”) according to some implementation schemes are shown. Figure 19B The specific steps, sequence of steps, and combinations of steps are shown for illustrative and explanatory purposes only. Other embodiments may implement different specific steps, sequences of steps, and combinations of steps to achieve similar functions or results. Reference Figure 11B describe Figure 19B The steps.

[0061] At step 1902b, a masking region Mask4' is formed on the active layer 407. In some embodiments, the masking region Mask4' includes photoresist regions 1164a' to 1164b'. At step 1904b, as... Figure 11B As shown, photoresist regions 1164a' to 1164b' and polysilicon gate spacers 1028a to 1028b are used as masks to form p-type (i.e., P+) source connection regions 1111' in the active layer 407 using dopant 1176. Dopant 1176 is deposited at an angle 1157, such that the p-type source connection region 1111 is aligned with the inner edges 1115 of the polysilicon gate spacers 1028a to 1028b. At step 1906b, the photoresist regions 1164a' and 1164b' in the Mask4' region are removed.

[0062] Detailed reference has been made to embodiments of the disclosed invention, one or more of which are shown in the accompanying drawings. Each example has been provided by way of explanation rather than limitation of the invention. In fact, although this specification has been described in detail with respect to specific embodiments of the invention, it should be understood that substitutions, modifications, and equivalents of these embodiments will readily conceive of by those skilled in the art upon understanding the foregoing. For example, a feature shown or described as part of one embodiment may be used with another embodiment to produce yet another embodiment. Therefore, this subject matter is intended to cover all such modifications and modifications within the scope of the appended claims and their equivalents. These and other modifications and modifications may be practiced by those skilled in the art without departing from the scope of the invention, the scope of which is set forth more specifically in the appended claims. Furthermore, those skilled in the art should understand that the foregoing description is merely exemplary and not intended to limit the invention.

[0063] The terms "lateral" and "horizontal" refer to a direction or plane parallel to the plane or surface of the substrate, regardless of orientation. The term "vertical" refers to a direction perpendicular to the horizontal plane. Terms such as "on," "above," "bottom," "top," "side," "upper," and "above" are defined relative to the horizontal plane.

Claims

1. A method for forming a semiconductor device, comprising: A semiconductor wafer is provided, the semiconductor wafer having a substrate layer and an active layer of a first conductivity type; A first gate is formed on the functional layer, the first gate comprising first gate polysilicon; A second gate is formed on the active layer, the second gate being laterally disposed from the first gate and comprising second gate polysilicon; A first mask region is formed on the functional layer; Using the first mask region, the first gate polysilicon, and the second gate polysilicon as a mask, a deep well of the second conductivity type, a shallow well of the second conductivity type, a source region of the first conductivity type, and a channel region are formed between the first gate and the second gate in the active layer. The channel region is divided into a first channel region of the second conductivity type and a second channel region of the second conductivity type. as well as Using multiple second mask regions, a first drift region of the first conductivity type, a second drift region of the first conductivity type, a first drain region of the first conductivity type, a second drain region of the first conductivity type, and a source connection region of the second conductivity type are formed in the active layer.

2. The method according to claim 1, wherein: The first conductivity type is n-type conductivity; and The second type of conductivity is p-type conductivity.

3. The method according to claim 1, wherein the first mask region comprises: A first photoresist region is formed on the active layer and on a first lateral region of the first gate polysilicon. The first photoresist region does not include a second lateral region of the first gate polysilicon or the lateral region of the active layer. The lateral region of the active layer is disposed between the first gate polysilicon and the second gate polysilicon. The second photoresist region is formed on the active layer and on the first lateral region of the second gate polysilicon, the second photoresist region excluding the second lateral region of the second gate polysilicon and the lateral region of the active layer.

4. The method according to claim 3, wherein: The first photoresist region, the second photoresist region, the second lateral extent of the first gate polysilicon, and the second lateral extent of the second gate polysilicon shield the active layer from the dopant implanted at an implantation angle perpendicular to the horizontal plane of the active layer, the horizontal plane being parallel to the top surface of the active layer.

5. The method according to claim 4, wherein: Forming the first channel region includes implanting and thermally driving a dopant of the second conductivity type at an implantation angle of the first range, such that the dopant of the second conductivity type extends to a first lateral range under the first gate polysilicon, and the first photoresist region and the second photoresist region, as well as the second lateral range of the first gate polysilicon and the second lateral range of the second gate polysilicon, serve as a mask. and Forming the second channel region includes implanting and thermally driving the dopant of the second conductivity type at an implantation angle of the second range, such that the dopant of the second conductivity type extends to a second lateral range below the second gate polysilicon, wherein the first photoresist region and the second photoresist region, as well as the second lateral range of the first gate polysilicon and the second lateral range of the second gate polysilicon, serve as a mask.

6. The method of claim 4, wherein forming the shallow well comprises: The dopant of the second conductivity type is implanted at the implantation corner, such that the shallow well has a lateral range laterally aligned with the inner edge of the first gate polysilicon and the inner edge of the second gate polysilicon, and the first photoresist region and the second photoresist region, as well as the second lateral range of the first gate polysilicon and the second gate polysilicon, are used as a mask.

7. The method of claim 4, wherein forming the deep well comprises: The dopant of the second conductivity type is implanted at the implantation corner, such that the deep well is formed directly below the source region, and the first photoresist region and the second photoresist region, as well as the second lateral range of the first gate polysilicon and the second lateral range of the second gate polysilicon, are used as a mask.

8. The method of claim 4, wherein forming the source region comprises: The first type of dopant is implanted at the implantation corner, such that the source region is laterally aligned with the inner edge of the first gate polysilicon and the inner edge of the second gate polysilicon, and the first photoresist region and the second photoresist region, as well as the second lateral range of the first gate polysilicon and the second gate polysilicon, are used as a mask.

9. The method of claim 1, wherein forming the first drift region and the second drift region comprises: A drift region mask is formed on the active layer; as well as The first type of dopant is implanted at the implantation angle, such that the first drift region and the second drift region are laterally aligned with the corresponding edge of the drift region mask.

10. The method of claim 1, wherein forming the first drain region and the second drain region comprises: A drain region mask is formed on the active layer; as well as The first type of dopant is implanted at the implantation angle, such that the first drain region and the second drain region are laterally aligned with the corresponding edge of the drain region mask.

11. The method of claim 1, wherein before forming the source connection region, the method further comprises: A first polysilicon gate spacer is formed on the active layer, and the first polysilicon gate spacer is laterally disposed near the inner edge of the first gate polysilicon and vertically disposed above the source region. as well as A second polysilicon gate spacer is formed on the active layer, and the second polysilicon gate spacer is laterally disposed near the inner edge of the second gate polysilicon and vertically disposed above the source region.

12. The method of claim 11, wherein forming the source connection region comprises: A first photoresist region is formed on the active layer, on the first gate polysilicon, and in a first lateral range of the first polysilicon gate spacer, wherein the first photoresist region does not include the first lateral range of the active layer disposed between the first polysilicon gate spacer and the second polysilicon gate spacer. A second photoresist region is formed on the active layer, on the second gate polysilicon, and over a first lateral extent of the second polysilicon gate spacer, the second photoresist region excluding the first lateral extent of the active layer disposed between the first polysilicon gate spacer and the second polysilicon gate spacer; and A dopant of the second conductivity type is implanted in the first lateral region of the active layer disposed between the first polysilicon gate spacer and the second polysilicon gate spacer.

13. The method according to claim 12, wherein: The first lateral range of the first polysilicon gate spacer is the entire lateral range of the first polysilicon gate spacer, and the first photoresist region is formed on the active layer and extends beyond the first polysilicon gate spacer to the second lateral range of the active layer. The first lateral range of the second polysilicon gate spacer is the entire lateral range of the second polysilicon gate spacer, and the second photoresist region is formed on the active layer and extends beyond the second polysilicon gate spacer to the third lateral range of the active layer; and The first lateral range of the functional layer is positioned between the second lateral range of the functional layer and the third lateral range of the functional layer.

14. The method according to claim 12, wherein: The first photoresist region is formed on the first lateral extent of the first polysilicon gate spacer and does not include the second lateral extent of the first polysilicon gate spacer. The second photoresist region is formed on the first lateral extent of the second polysilicon gate spacer and does not include the second lateral extent of the second polysilicon gate spacer; The second lateral extent of the first polysilicon gate spacer shields the region of the active layer disposed below the first polysilicon gate spacer from the dopant of the second conductivity type; and The second lateral extent of the second polysilicon gate spacer shields the region of the active layer disposed below the second polysilicon gate spacer from the dopant of the second conductivity type.

15. The method of claim 11, further comprising: A third polysilicon gate spacer is formed on the active layer, and the third polysilicon gate spacer is laterally disposed near the outer edge of the first gate polysilicon and vertically disposed above the first drift region; and A fourth polysilicon gate spacer is formed on the active layer, and the fourth polysilicon gate spacer is laterally disposed near the outer edge of the second gate polysilicon and vertically disposed above the second drift region.

16. The method of claim 15, further comprising: A first gate shield is formed, the first gate shield having a first portion disposed above the first gate polysilicon and a second portion extending beyond the third polysilicon gate spacer on the outer edge of the first gate polysilicon, the second portion of the first gate shield being disposed above the first drift region and closer to the active layer than the first portion of the first gate shield. as well as A second gate shield is formed, the second gate shield having a first portion disposed above the second gate polysilicon and a second portion extending beyond the fourth polysilicon gate spacer on the outer edge of the second gate polysilicon, the second portion of the second gate shield being disposed above the second drift region and closer to the active layer than the first portion of the second gate shield.

17. The method of claim 16, further comprising: A dielectric region is formed on the active layer, on the first gate shield, and on the second gate shield; as well as A metal source contact is formed that extends vertically from the top surface of the dielectric region to the source connection region, and the metal source contact is laterally disposed between the first polysilicon gate spacer and the second polysilicon gate spacer.

18. The method of claim 17, wherein: The first width of the metal source contact along a first vertical range of the metal source contact is wider than the second width of the metal source contact along a second vertical range of the metal source contact. The first vertical range of the metal source contact extends from the top surface of the first portion of the first gate shield to the top surface of the dielectric region; The first width of the first vertical range of the metal source contact laterally overlaps and contacts the first portion of the first gate shield; and The second vertical extent of the metal source contact extends below the first gate shield.

19. The method according to claim 1, in, The second conductivity type deep well is located below the first channel region and the second channel region. A portion of the second conductivity type shallow well divides the first channel region and the second channel region. Another portion of the second conductivity type shallow well is located within the second conductivity type deep well. The first conductivity type source region is formed in the second conductivity type shallow well, the first channel region, and the second channel region. The second conductivity type source connection region is formed in the second conductivity type shallow well and the first conductivity type source region.

20. A method of forming a semiconductor device, comprising: A semiconductor wafer is provided, the semiconductor wafer having a substrate layer and an active layer of a first conductivity type; A first gate is formed on the functional layer, the first gate comprising first gate polysilicon; A second gate is formed on the functional layer, the second gate being laterally disposed from the first gate and comprising second gate polysilicon; Using the lateral extent of the first gate polysilicon, the lateral extent of the second gate polysilicon, and the first mask region as a mask, a deep well of a second conductivity type, a shallow well of a second conductivity type, a source region of a first conductivity type, and a channel region divided into a first channel region of a second conductivity type and a second channel region of a second conductivity type are formed in the active layer between the first gate and the second gate; and Multiple second mask regions are used to form a first drift region of a first conductivity type, a second drift region of a first conductivity type, a first drain region of a first conductivity type, a second drain region of a first conductivity type, and a source connection region of a second conductivity type in the active layer.

21. The method of claim 20, wherein: The lateral extent of the first gate polysilicon and the lateral extent of the second gate polysilicon shield the active layer from the dopant implanted at an implantation angle perpendicular to the horizontal plane of the active layer, which is parallel to the top surface of the active layer.

22. The method according to claim 21, wherein: Forming the first channel region includes implanting and thermally driving a dopant of the second conductivity type at an implantation angle of the first range, such that the dopant of the second conductivity type extends to a first lateral range below the first gate polysilicon, the lateral ranges of the first gate polysilicon and the second gate polysilicon and the first mask region being used as a mask; and Forming the second channel region includes implanting and thermally driving a dopant of the second conductivity type at a second implantation angle, such that the dopant of the second conductivity type extends to a second lateral range beneath the second gate polysilicon, the lateral ranges of the first gate polysilicon and the second gate polysilicon and the first mask region being used as a mask.

23. The method of claim 21, wherein forming the shallow well comprises: A dopant of a second conductivity type is implanted at the implantation corner, such that the shallow well has a lateral range laterally aligned with the inner edges of the first gate polysilicon and the second gate polysilicon, the lateral ranges of the first gate polysilicon and the second gate polysilicon and the first mask region being used as a mask.

24. The method of claim 21, wherein forming the deep well comprises: The dopant of the second conductivity type is implanted at the implantation angle, such that the deep well is formed directly below the source region, and the lateral extent of the first gate polysilicon and the second gate polysilicon and the first mask region are used as a mask.

25. The method of claim 21, wherein forming the source region comprises: A dopant of the first conductivity type is implanted at the implantation angle, such that the source region is laterally aligned with the inner edge of the first gate polysilicon and the inner edge of the second gate polysilicon, and the lateral extent of the first gate polysilicon and the second gate polysilicon and the first mask region are used as a mask.

26. The method of claim 20, wherein forming the first drift region and the second drift region comprises: A drift region mask is formed on the active layer; and The first type of dopant is implanted at the implantation angle, such that the first drift region and the second drift region are laterally aligned with the corresponding edge of the drift region mask.

27. The method of claim 20, wherein forming the first drain region and the second drain region comprises: A drain region mask is formed on the active layer; and The first type of dopant is implanted at the implantation angle, such that the first drain region and the second drain region are laterally aligned with the corresponding edge of the drain region mask.

28. The method of claim 20, wherein before forming the source connection region, the method further comprises: A first polysilicon gate spacer is formed on the active layer. The first polysilicon gate spacer is laterally disposed near the inner edge of the first gate polysilicon and vertically disposed above the source region. as well as A second polysilicon gate spacer is formed on the active layer. The second polysilicon gate spacer is laterally disposed near the inner edge of the second gate polysilicon and vertically disposed above the source region.

29. The method of claim 28, wherein forming the source connection region comprises: A first photoresist region is formed on the active layer, on the first gate polysilicon, and in a first lateral range of the first polysilicon gate spacer, wherein the first photoresist region does not include the first lateral range of the active layer disposed between the first polysilicon gate spacer and the second polysilicon gate spacer. A second photoresist region is formed on the active layer, on the second gate polysilicon, and over a first lateral extent of the second polysilicon gate spacer, the second photoresist region excluding the first lateral extent of the active layer disposed between the first polysilicon gate spacer and the second polysilicon gate spacer; and A dopant of the second conductivity type is implanted in the first lateral region of the active layer disposed between the first polysilicon gate spacer and the second polysilicon gate spacer.

30. The method according to claim 29, wherein: The first lateral range of the first polysilicon gate spacer is the entire lateral range of the first polysilicon gate spacer, and the first photoresist region is formed on the active layer and extends beyond the first polysilicon gate spacer to the second lateral range of the active layer. The first lateral range of the second polysilicon gate spacer is the entire lateral range of the second polysilicon gate spacer, and the second photoresist region is formed on the active layer and extends beyond the second polysilicon gate spacer to the third lateral range of the active layer; and The first lateral range of the functional layer is positioned between the second lateral range of the functional layer and the third lateral range of the functional layer.

31. The method according to claim 29, wherein: The first photoresist region is formed on the first lateral extent of the first polysilicon gate spacer and does not include the second lateral extent of the first polysilicon gate spacer. The second photoresist region is formed on the first lateral extent of the second polysilicon gate spacer and does not include the second lateral extent of the second polysilicon gate spacer; The second lateral extent of the first polysilicon gate spacer shields the region of the active layer disposed below the first polysilicon gate spacer from the dopant of the second conductivity type; and The second lateral extent of the second polysilicon gate spacer shields the region of the active layer disposed below the second polysilicon gate spacer from the dopant of the second conductivity type.

32. The method of claim 28, further comprising: A third polysilicon gate spacer is formed on the active layer, and the third polysilicon gate spacer is laterally disposed near the outer edge of the first gate polysilicon and vertically disposed above the first drift region; and A fourth polysilicon gate spacer is formed on the active layer, and the fourth polysilicon gate spacer is laterally disposed near the outer edge of the second gate polysilicon and vertically disposed above the second drift region.

33. The method of claim 32, further comprising: A first gate shield is formed, the first gate shield having a first portion disposed above the first gate polysilicon and a second portion extending beyond the third polysilicon gate spacer on the outer edge of the first gate polysilicon, the second portion of the first gate shield being disposed above the first drift region and closer to the active layer than the first portion of the first gate shield. as well as A second gate shield is formed, the second gate shield having a first portion disposed above the second gate polysilicon and a second portion extending beyond the fourth polysilicon gate spacer on the outer edge of the second gate polysilicon, the second portion of the second gate shield being disposed above the second drift region and closer to the active layer than the first portion of the second gate shield.

34. The method of claim 33, further comprising: A dielectric region is formed on the active layer, on the first gate shield, and on the second gate shield; as well as A metal source contact is formed that extends vertically from the top surface of the dielectric region to the source connection region, and the metal source contact is laterally disposed between the first polysilicon gate spacer and the second polysilicon gate spacer.

35. The method according to claim 34, wherein: The first width of the metal source contact along the first vertical range of the metal source contact is wider than the second width of the metal source contact along the second vertical range of the metal source contact; The first vertical range of the metal source contact extends from the top surface of the first portion of the first gate shield to the top surface of the dielectric region; The first width of the first vertical range of the metal source contact laterally overlaps and contacts the first portion of the first gate shield; and The second vertical extent of the metal source contact extends below the first gate shield.

36. The method according to claim 20, in, The second conductivity type deep well is located below the first channel region and the second channel region. A portion of the second conductivity type shallow well divides the first channel region and the second channel region. Another portion of the second conductivity type shallow well is located within the second conductivity type deep well. The first conductivity type source region is formed in the second conductivity type shallow well, the first channel region, and the second channel region. The second conductivity type source connection region is formed in the second conductivity type shallow well and the first conductivity type source region.

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