Faulty chip detection method, apparatus, computing device, and storage medium

Abstract

Embodiments of the present application provide a fault chip detection method, device, computing equipment and storage medium, wherein the fault chip detection method comprises: obtaining preset marking information and physical position information of a node chip in a communication link; determining a fault node chip according to the preset marking information, the physical position information and a preset association relationship. The technical solution of the embodiments of the present application quickly detects and locates the fault node chip in the communication link.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a method, apparatus, computing device, and storage medium for detecting faulty chips. Background Technology

[0002] Currently, with the application and development of machine learning, especially deep learning technology, in various fields, higher demands are being placed on the data processing capabilities of computing devices. To complete complex data computation tasks, parallel computing using multiple chips is commonly employed to improve data processing and computational capabilities. However, if a chip malfunctions, it becomes very difficult to identify and locate the faulty chip. Summary of the Invention

[0003] This application provides a method, apparatus, computing device, and storage medium for detecting faulty chips, in order to solve or alleviate one or more technical problems in the prior art.

[0004] In a first aspect, embodiments of this application provide a method for detecting faulty chips, including:

[0005] Obtain the preset tagging information and physical location information of the node chips in the communication link;

[0006] The faulty node chip is determined based on preset marking information, physical location information, and preset association relationships.

[0007] Secondly, embodiments of this application provide a fault detection device, including at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a method according to any implementation of this embodiment.

[0008] Thirdly, embodiments of this application provide a computing device, including a fault detection device according to any one of the embodiments of this application.

[0009] Fourthly, embodiments of this application provide a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform a method according to any implementation of this embodiment.

[0010] The embodiments of this application employ the above-described technical solution to detect and locate faulty chips in the communication link.

[0011] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of this application will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0012] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0013] Figure 1 A schematic diagram based on a communication link is shown;

[0014] Figure 2 A schematic diagram of the chip structure according to an embodiment of this application is shown;

[0015] Figure 3 A flowchart illustrating a faulty chip detection method according to an embodiment of this application is shown;

[0016] Figure 4 , Figure 5 , Figure 6 and Figure 7 A schematic diagram of a communication link according to an embodiment of this application is shown;

[0017] Figure 8 A block diagram of a fault chip detection apparatus according to an embodiment of this application is shown. Detailed Implementation

[0018] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0019] In some high-performance computing fields, multiple node chips can be used to compute together, connected by signal lines to form a communication link. During startup, a command broadcast is used to enumerate all node chips. During enumeration, upon receiving an enumeration command, a node chip increments the corresponding enumeration result by 1, stores it in a register, and continues transmitting it. Subsequent node chips repeat this process, incrementing by 1 sequentially. This allows all node chips on the communication link to determine their own physical location information, and thus respond to computation commands corresponding to that node chip based on this location information.

[0020] However, in some cases, a node chip in the communication link may fail and not respond to enumeration commands. This means the node chip cannot count and has no location information. In other words, the enumeration result of the preceding node chip is transmitted directly to the next node chip without being counted, resulting in the communication link being one node chip short. During maintenance, it becomes impossible to locate the faulty node chip.

[0021] For example, such as Figure 1 As shown, the communication link 10 may include seven node chips, namely M1, M2, M3...M7, whose physical locations are [1, 2, 3, 4, 5, 6, 7]. The enumeration process of the seven node chips includes: when a detection instruction (e.g., an enumeration instruction) is received, the value of the corresponding register of the node chip is incremented by 1 in sequence, finally obtaining the seven physical location information, namely A1, A2, A3, A4, A5, A6, A7, that is, the physical location n of each chip = physical location information A n .

[0022] When a node chip fails (taking M3 as an example), this node chip does not increment the enumeration count, but continues to transmit detection commands. Subsequent node chips execute the detection commands sequentially and count the received enumeration results. Ultimately, six physical location information points are obtained: A1, A2, A3, A4, A5, and A6. Therefore, of the actual seven node chips, only six are located, making it impossible to determine which node chip failed.

[0023] This application aims to provide a chip and a method for detecting faulty chips, wherein the chip can be used as a node chip in a communication link. The faulty chip detection method based on this chip can locate the faulty node chip in the communication link.

[0024] The communication link may include at least two node chips and enable communication between them. For example, the communication link may be unidirectional or bidirectional.

[0025] In one example, the communication link connects only two node chips, enabling point-to-point communication. In another example, the communication link can connect more than two node chips, enabling multi-point communication. The number of node chips in a single communication link is not limited in this embodiment.

[0026] In this embodiment, the node chips are connected by circuits to form a communication link. The node chips can be connected in series, in parallel, or in a combination of series and parallel. This embodiment does not limit the connection method of the node chips.

[0027] Figure 2 A schematic diagram of a node chip 100 according to an embodiment of this application is shown. The node chip 100 can be a chip in a communication link. Exemplarily, the node chip 100 in this embodiment can be an application-specific integrated circuit (ASIC) chip.

[0028] like Figure 2 As shown, the node chip 100 includes at least one preset tag pin IO_pos for receiving preset tag information V_pos. Exemplarily, existing input / output pins of the node chip 100 can be redefined as preset tag pins, or a new input / output pin can be added as a preset tag pin.

[0029] Each preset tag pin receives a preset tag information, and the received preset tag information can be the same or different. The preset tag information of at least one preset tag pin is consistent with a preset association relationship between the physical location information of the node chip 100 in the communication link and the preset tag information V_pos of at least one preset tag pin. For example, the relationship between the level value of the preset tag information V_pos of at least one preset tag pin and the detected physical location information of the node chip 100 in the communication link is consistent with a preset association relationship.

[0030] The preset association relationship is the correspondence between the actual physical location information of the node chip and the preset tag information.

[0031] In one embodiment, the preset association includes: when the actual physical location information of the node chip in the communication link is an odd number, a level value determined according to the preset marking information of the node chip is a first level value; when the actual physical location information of the node chip in the communication link is an even number, a level value determined according to the preset marking information of the node chip is a second level value, wherein the preset marking pin of the node chip is used to receive the preset marking information. For example, the first level value is low, and the second level value is high.

[0032] In this embodiment, a low level can represent "0" and a high level can represent "1". It should be noted that the definitions of high and low levels are relative values; a voltage above a certain high threshold is defined as high, and a voltage below a certain low threshold is defined as low. Therefore, the definitions of low and high levels may differ for different chips, and the voltage ranges corresponding to "0" and "1" may also differ. This embodiment does not impose any limitations on this.

[0033] Below are some examples of preset association relationships.

[0034] Example 1

[0035] In Example 1, the preset flag pin IO_pos can be one. The preset associations include: when the actual physical location information of node chip 100 in the communication link is an odd number, the preset flag information is a first level value, such as "0"; when the actual physical location information of node chip 100 in the communication link is an even number, the preset flag information is a second level value, such as "1"; or, when the actual physical location information of node chip 100 in the communication link is an odd number, the preset flag information is a second level value, such as "1"; when the actual physical location information of node chip 100 in the communication link is an even number, the preset flag information is a first level value, such as "0". The specific associations can be preset according to actual needs; this embodiment does not limit this.

[0036] Example 2

[0037] In Example 2, there can be multiple preset tag pins IO_pos. The result of a logical operation on the multiple preset tag information V_pos is consistent with the physical location information of the node chip 100 in the communication link and a preset association relationship. The logical operations include, but are not limited to, "OR", "AND", "NOT", and "XOR". The preset association relationship includes: when the actual physical location information of the node chip 100 in the communication link is an odd number, the result of the logical operation on the multiple preset tag information is a first level value, such as "0"; when the actual physical location information of the node chip 100 in the communication link is an even number, the result of the logical operation on the multiple preset tag information is a second level value, such as "1"; or, when the actual physical location information of the node chip 100 in the communication link is an odd number, the result of the logical operation on the multiple preset tag information is a second level value, such as "1"; when the actual physical location information of the node chip 100 in the communication link is an even number, the result of the logical operation on the multiple preset tag information is a first level value, such as "0". The specific relationships can be preset according to actual needs, and this embodiment does not limit them.

[0038] Example 3

[0039] The preset tag information V_pos can be used to determine the configuration number of the chip. The preset association can include the correspondence between the chip's actual physical location information and the configuration number.

[0040] For example, there can be N preset marker pins IO_pos, where N is greater than or equal to 2. The N preset marker information V_pos corresponding to the N preset marker pins includes either a first level value or a second level value, which are combined to generate 2. N One configuration result, 2N The configuration results are numbered 1, 2...2 respectively. N -1, 0, and the chips in the communication link are sequentially assigned configuration numbers 1, 2...2. N -1, 0, if the number of chips in the communication link is greater than 2 N Then from the 2nd N Starting with the first chip, each chip is repeatedly assigned configuration numbers 1, 2...2 in sequence. N -1, 0 (This embodiment can use N preset marker pins to achieve more than 2 N Fault detection of individual chips, and fault detection of multiple chips with fewer preset marker pins (N can be an integer greater than 1); preset association relationships include: when the value corresponding to the actual physical location information of node chip 100 in the communication link is divided by 2 N When the remainder is M, the configuration number corresponding to node chip 100 is M, where M is less than or equal to 2. N .

[0041] For example, when N equals 2, meaning there can be two IO_pos, the preset tag information V_pos of the two IO_pos are combined to generate four configuration results: 00, 01, 10, and 11, with configuration numbers of 1, 2, 3, and 0 respectively. These correspond to four node chips 1001, 1002, 1003, and 1004, and their actual physical locations are 1, 2, 3, and 4 respectively. When node chip 1003 fails, the actual physical location information of node chip 1004 corresponds to the value 3. The remainder of 3 / 4 is 3, which is not equal to the number "0" corresponding to the configuration result 11 of the preset tag information V_pos of the two IO_pos of node chip 1004. Therefore, it does not conform to the preset association relationship, and thus, it can be determined that a faulty chip exists.

[0042] Example 4

[0043] In Example 4, IO_pos can be a single value, corresponding to a preset flag information level of V_pos. The preset associations include: the preset flag information level of the chip and the preset flag information level values ​​of two adjacent chips in the communication link form an arithmetic progression. For example, V_posn = V_pos1 + (n-1)*d, where V_pos1 is the preset flag information level value of the first chip, V_posn is the preset flag information level value of the nth chip, and d is the tolerance. When the difference between the preset flag information level value of the enumerated chip and the level value of the previously enumerated preset flag information is not equal to d, it indicates the presence of a faulty chip. In this case, it can be determined that there is a faulty chip between the currently enumerated chip and the previously enumerated chip. Taking the i-th enumerated chip as an example, if the difference between the level value of its corresponding preset marker information and the level value of the preset marker information corresponding to the (i-1)-th chip enumerated before it is not equal to d, then it can be determined that the i-th chip in the actual communication link has failed, and the i-th enumerated chip is the (i+1)-th chip in the actual communication link.

[0044] In one implementation, such as Figure 2 As shown, the node chip 100 may also include a register 101. In response to a detection command in the communication link, the register 101 generates physical location information.

[0045] The detection instruction can be an enumeration instruction, and the physical location information can be the enumeration result. For example, register 101 counts based on the enumeration result of the previous chip, obtains the enumeration result of the current chip, and then generates the physical location information.

[0046] For example, a communication link includes multiple node chips 100, namely 1001, 1002...100. N Node chip 1001 is configured as the first node chip in the communication link. Node chip 1001 can receive detection commands from an external control device, count (e.g., increment by 1), generate and store the enumeration result of node chip 1001 [1], and transmit the detection command and enumeration result [1] to the next node chip 1002; Node chip 1002 responds to the detection command, counts according to the enumeration result [1] it receives (e.g., increment by 1), generates and stores the enumeration result of node chip 1002 [2], and transmits the detection command and enumeration result [2] to the next node chip 1003, and so on, thereby obtaining multiple physical location information.

[0047] It should be noted that this embodiment does not specifically limit the count value accumulated each time or the number system of the enumeration result.

[0048] This embodiment also provides a communication link, including multiple node chips, wherein the node chips are node chips 100 in any embodiment of this application.

[0049] This embodiment also provides a method for detecting faulty chips, wherein the entity executing the method may be a faulty chip detection device. For example, the faulty chip detection device may be an external control device outside the communication link, such as a control board.

[0050] like Figure 3 As shown, the faulty chip detection method includes:

[0051] Step S301: Obtain the preset tag information and physical location information of the node chips in the communication link;

[0052] Step S302: Determine the faulty node chip based on preset marking information, physical location information, and preset association relationships.

[0053] In step S301, obtaining the preset tag information of the node chip in the communication link may include: the node chip in the communication link is configured with a preset tag pin; and obtaining the preset tag information of the node chip through the preset tag pin.

[0054] The process of obtaining preset tag information of the node chip through preset tag pins includes: sending preset tag information to preset tag pins of the node chip; and obtaining preset tag information received by the node chip in the communication link.

[0055] Furthermore, in step S301, obtaining the physical location information of the node chip in the communication link may include: sending a detection command to the node chip in the communication link; and obtaining the physical location information of the node chip in the communication link.

[0056] The process of sending detection commands to node chips in the communication link to obtain the physical location information of the node chips in the communication link includes: sending detection commands to the communication link so that each node chip in the communication link generates physical location information in response to the detection commands; and obtaining each physical location information.

[0057] In other words, the physical location information in step S301 is information obtained based on the detection command, which may differ from the actual physical location information of the node chip.

[0058] For example, such as Figure 4 As shown, the communication link 20 includes multiple node chips 1001 to 100. NThe corresponding values ​​for the actual physical location information range from 1 to N. Each node chip is equipped with a preset marker pin IO_pos. Based on the actual physical location information of the node chip in the communication link and the preset association relationship, the preset marker information input to its IO_pos is configured.

[0059] A detection command is sent to each node chip in the communication link 20; each node chip responds to the detection command and generates physical location information; thus, multiple physical location information can be obtained. By detecting the input signal of the preset marker pin IO_pos of each node chip, multiple preset marker information can be obtained. Through preset association relationships, each preset marker information, and each physical location information, it is possible to quickly determine whether a node chip has failed and the location of the failed node chip.

[0060] It should be noted that the transmission direction of the detection command can be from node chip 1001 to node chip 100. N It can also be from node chip 100 N To node chip 1001. The number of IO_pos can also be multiple.

[0061] In a specific example, such as Figure 5 As shown, the transmission direction of the detection command of communication link 20 is from node chip 1001 to node chip 100. N The number of IO_pos is one. The preset association is that when the physical location is an odd number, the preset flag information is high ("1"), and when the actual physical location information is an even number, the preset flag information is low ("0"). The node chip can be node chip 100, which includes register 101. Register 101 generates physical location information in response to a detection command in the communication link. The detection command can be an enumeration command, and the physical location information can be the enumeration result. For example, register 101 counts based on the enumeration result received from the previous node chip and generates the enumeration result of the current node chip as the physical location information of the current node chip.

[0062] In one implementation, the preset association relationship corresponds to the mapping between the actual physical location information of the node chip and preset tag information. The setting of the preset association relationship can be referred to in Examples 1, 2, 3 and 4 above, and will not be repeated here.

[0063] In one implementation, step S302 may include: sequentially determining whether each physical location information and each preset marker information are consistent with a preset association relationship according to the transmission order of the detection command in the communication link; if not, then determining a faulty node chip based on the first node chip that is inconsistent with the preset association relationship. Specifically, the corresponding node chip may be determined based on the first physical location information that is inconsistent with the preset association relationship; and the corresponding node chip may be determined as a faulty node chip.

[0064] The following example, using Example 1, details the specific implementation of the fault chip detection method in this embodiment.

[0065] In this example, the faulty chip detection method includes:

[0066] (1) Send a detection command to the communication link so that each node chip can generate physical location information in response to the detection command;

[0067] (2) Obtain information on each physical location;

[0068] (3) According to the order in which the detection instructions are sent in the communication link, determine whether each physical location information and each preset marker information are consistent with the preset association relationship;

[0069] (4) If not, based on the first physical location information that is inconsistent with the preset association relationship, determine the corresponding node chip and determine the node chip of the corresponding node chip as the faulty node chip.

[0070] For ease of understanding, the following explanation uses communication link 30 as an example. Figure 6 As shown, the communication link 30 includes seven node chips 1001, 1002...1007. Each node chip has a preset flag pin IO_pos, which is associated with a preset level of 1 when the actual physical location of the node chip in the communication link is an odd number and a low level (0) when the actual physical location of the node chip in the communication link is an even number. This is used to introduce a fault chip detection method.

[0071] After the communication link 30 is started, a detection command is sent to the communication link 30. For example, the detection command can be sent to the communication link 30 based on the external interface of the external control device and the circuit board on which the communication link 30 is located. The node chip 1001 can receive the detection command from the external control device, count, such as incrementing by 1, generate and store the enumeration result of the node chip 1001 [1], and transmit the detection command and enumeration result [1] to the next node chip 1002; the node chip 1002 responds to the detection command, counts according to the detection result [1] it receives, such as incrementing by 1, generates and stores the enumeration result of the node chip 1002 [2], and transmits the detection command and enumeration result [2] to the next node chip 1003, and so on.

[0072] In scenario one, it is assumed that none of the node chips have failed. Based on the fault chip detection method of this embodiment, the enumeration result of communication link 30 is obtained as [1, 2, 3, 4, 5, 6, 7], thus obtaining multiple physical location information as A1, A2, A3, A4, A5, A6, A7. Further, the input signal of the preset marker pin IO_pos of each node chip is detected, thereby obtaining multiple preset marker information as [1, 0, 1, 0, 1, 0, 1]. It can be seen that the physical location information and preset marker information of each node chip conform to the preset association relationship. Therefore, none of the node chips have failed.

[0073] In scenario two, it is assumed that the third node chip 1003 is a faulty node chip. Based on the faulty chip detection method of this embodiment, detection signals are sent to each node chip in the communication link 30. Since the faulty node chip 1003 cannot respond to the detection command, it cannot generate physical location information, and the multiple physical location information obtained are A1, A2, A3, A4, A5, and A6 in sequence. Further, the input signal of the preset marker pin IO_pos of each node chip is detected. Since the input signal of the preset marker pin IO_pos of the faulty node chip 1003 cannot be detected, the multiple preset marker information obtained are [1, 0, 0, 1, 0, 1]. It can be seen that starting from A3, the physical location information and the preset marker information begin to be inconsistent with the preset association relationship. That is, the node chip corresponding to the first physical location information that is inconsistent with the preset association relationship is 1003. Therefore, it can be determined that the third node chip 1003 is a faulty node chip.

[0074] In one implementation, step S302 may include: determining, according to the transmission order of the detection command in the communication link, whether each physical location information and each preset tag information are consistent with a preset association relationship; if not, determining the faulty node chip based on the first node chip that is inconsistent with the preset association relationship. Specifically, the first node chip that is inconsistent with the preset association relationship and at least one subsequent node chip may be determined as the faulty node chip.

[0075] The following example, using Example 3, details the specific implementation of the fault chip detection method in this embodiment.

[0076] In this example, the faulty chip detection method includes:

[0077] (1) Send a detection command to the communication link so that each node chip can generate physical location information in response to the detection command;

[0078] (2) Obtain information on each physical location;

[0079] (3) According to the order in which the detection instructions are sent in the communication link, determine whether each physical location information and each preset marker information are consistent with the preset association relationship;

[0080] (4) If not, the first node chip that does not conform to the preset association relationship and at least one subsequent node chip are identified as faulty node chips.

[0081] For ease of understanding, the following explanation uses communication link 40 as an example. Figure 7 As shown, the communication link 40 includes seven node chips 2001, 2002...2007. There are two IO_pos. The preset tag information V_pos of the two IO_pos are combined to generate four configuration results, namely 00, 01, 10, and 11, and numbered 1, 2, 3, and 0 respectively. The preset association relationship includes: when the remainder of the value corresponding to the actual physical location information of the node chip in the communication link divided by 4 (i.e., 2 squared) is M, the configuration result of each preset tag information is numbered M.

[0082] Suppose that two consecutive node chips, 2003 and 2004, fail.

[0083] Based on the fault detection method of this embodiment, after the communication link 30 is started, a detection command is sent to the communication link 30. The multiple physical location information obtained are as follows: A1, A2, A3, A4, A5; the configuration results of multiple preset tag information obtained are as follows: 00, 01, 00, 01, 10, and the corresponding numbers of the configuration results of the multiple preset tag information are: 1, 2, 1, 2, 3. It can be seen that the remainder of the number of physical location information A3 divided by 4 is "3" (3%4=3), but the number of the corresponding preset tag information configuration result is "1". It can be determined that the first physical location information that is inconsistent with the preset association relationship is A3, and the corresponding node chip is 2003. Since the total number of node chips is 7, but the number of received physical location information is only 5, it can be known that there are two faulty node chips, namely 2003 and 2004.

[0084] Therefore, the chip, communication link, and faulty chip detection method based on the embodiments of this application can quickly, accurately, and conveniently identify the faulty node chip in the communication link.

[0085] In one embodiment, step S302 may include: determining whether each of the physical location information and each of the preset tag information are consistent with a preset association relationship according to the transmission order of the detection instruction in the communication link; if not, determining the faulty node chip based on the first node chip that is inconsistent with the preset association relationship; repairing the faulty node chip, and after repair, continuing to perform fault detection according to the method of steps S301 to S303.

[0086] Figure 8 A structural block diagram of a fault chip detection device according to an embodiment of this application is shown. Figure 8 As shown, the fault chip detection device includes a memory 801 and a processor 802. The memory 801 stores instructions that can be executed by the processor 802. When the processor 802 executes the instructions, it implements the method in the above embodiments. The number of memories 801 and processors 802 can be one or more. This fault chip detection device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The fault chip detection device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein.

[0087] The fault chip detection device may also include a communication interface 803 for communicating with external devices and exchanging data. The devices are interconnected using different buses and can be mounted on a common motherboard or otherwise as needed. The processor 802 can process instructions executed within the fault chip detection device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In other embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple fault chip detection devices can be connected, each providing some necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). The bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, Figure 8 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0088] Optionally, in a specific implementation, if the memory 801, processor 802, and communication interface 803 are integrated on a single chip, then the memory 801, processor 802, and communication interface 803 can communicate with each other through an internal interface.

[0089] It should be understood that the aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. General-purpose processors can be microprocessors or any conventional processor. It is worth noting that the processor can be a processor supporting Advanced Reduced Instruction Set Machines (ARM) architecture.

[0090] This application provides a computer-readable storage medium (such as the memory 801 described above) that stores computer instructions, which, when executed by a processor, implement the method provided in this application.

[0091] Optionally, memory 801 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the fault chip detection device, etc. Furthermore, memory 801 may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory 801 may optionally include memory remotely located relative to processor 802, and these remote memories can be connected to the fault chip detection device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0092] For example, the communication link is set on the circuit board, and the fault chip detection device can be the control device of the circuit board.

[0093] This application also provides a computing device that may include the fault chip detection device of any embodiment of this application. The computing device may also include the communication link of any embodiment of this application.

[0094] According to the chip, communication link, and faulty chip detection method, apparatus, and computing device of this embodiment, one or more chips that have failed in the communication link can be quickly and accurately identified, thereby improving testing efficiency and equipment stability.

[0095] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0096] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0097] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more (two or more) executable instructions for implementing a particular logical function or process. Furthermore, the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functionality involved.

[0098] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0099] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. All or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware, the program being stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiments.

[0100] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. This storage medium can be a read-only memory, a disk, or an optical disk, etc.

[0101] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for detecting faulty chips, characterized in that, include: Obtain the preset tagging information and physical location information of the node chips in the communication link; The communication link includes at least two node chips and enables communication between the at least two node chips; The physical location information is obtained based on enumeration instructions; The faulty node chip is determined based on the preset marking information, the physical location information, and the preset association relationship; The node chip is configured with at least one preset tag pin for receiving preset tag information, which is a voltage level.

2. The fault chip detection method according to claim 1, characterized in that, The preset association relationship corresponds to the relationship between the actual physical location information of the node chip and the preset tag information.

3. The fault chip detection method according to claim 1, characterized in that, in, The node chip has one preset marker pin, and the preset association relationship includes: When the actual physical location information of the node chip in the communication link is an odd number, the preset marker information is a first level value; when the actual physical location information of the node chip in the communication link is an even number, the preset marker information is a second level value.

4. The fault chip detection method according to claim 1, characterized in that, The node chip has multiple preset marker pins, and the preset association relationships include: When the actual physical location information of the node chip in the communication link is an odd number, the logical operation result of each preset marker information is a first level value; when the actual physical location information of the node chip in the communication link is an even number, the logical operation result of each preset marker information is a second level value.

5. The fault chip detection method according to claim 3 or 4, characterized in that, The first voltage level is low and the second voltage level is high; or, the first voltage level is high and the second voltage level is low.

6. The fault chip detection method according to any one of claims 2-4, characterized in that, The communication link includes at least two node chips connected in sequence. Determining the faulty node chip based on the preset marking information, the physical location information, and the preset association relationship includes: According to the transmission order of the detection command in the communication link, it is determined whether the preset tag information and physical location information of each node chip are consistent with the preset association relationship. If not, the faulty node chip is determined based on the first node chip that does not match the preset association relationship.

7. The fault chip detection method according to claim 6, characterized in that, Determining the faulty node chip based on the first node chip that does not match the preset association relationship includes: Based on the first physical location information that is inconsistent with the preset association relationship, the corresponding node chip is determined; The corresponding node chip is identified as a faulty node chip.

8. The fault chip detection method according to claim 1, characterized in that, The node chip is configured with at least two preset tag pins for receiving preset tag information, which is used to determine a configuration number for the node chip; The step of determining the faulty node chip based on the preset marking information, the physical location information, and the preset association relationship includes: The configuration number is determined for the node chip based on the preset marking information; The faulty node chip is determined based on the physical location information, the configuration number, and the preset association relationship.

9. The fault chip detection method according to claim 8, characterized in that, The preset association relationship is the correspondence between the actual physical location information of the node chip and the configuration number.

10. The fault chip detection method according to claim 9, characterized in that, The node chip is configured with N preset marker pins, where N is equal to or greater than 2. The N preset marker information corresponding to the N preset marker pins can be a first level value or a second level value, which are combined to generate 2. N The configuration results, the 2 N The configuration results are numbered 1, 2...2 respectively. N -1, 0.

11. The fault chip detection method according to claim 10, characterized in that, The preset association relationship includes: when the value corresponding to the actual physical location information is divided by 2 N When the remainder is M, the configuration number corresponding to the node chip is M.

12. The fault chip detection method according to claim 11, characterized in that, The communication link includes at least two node chips connected in sequence. The faulty node chip is determined based on the physical location information, the configuration number, and a preset association relationship, including: According to the transmission order of the detection command in the communication link, determine in turn whether the physical location information of each node chip and the configuration number of each node chip are consistent with the preset association relationship; If not, the faulty node chip is determined based on the first node chip that does not match the preset association relationship.

13. The fault chip detection method according to claim 12, characterized in that, Determining the faulty node chip based on the first node chip that does not match the preset association relationship includes: Based on the first physical location information that is inconsistent with the preset association relationship, the corresponding node chip is determined; The corresponding node chip is identified as a faulty node chip.

14. The fault chip detection method according to claim 1, characterized in that, The acquisition of preset marker information for node chips in the communication link includes: The node chips in the communication link are configured with preset marker pins; The preset tag information of the node chip is obtained through the preset tag pin.

15. The fault chip detection method according to claim 14, characterized in that, The step of obtaining the preset marker information of the node chip through the preset marker pin includes: Send preset tag information to the preset tag pin of the node chip; Obtain the preset tag information received by the node chip in the communication link.

16. The fault chip detection method according to claim 14, characterized in that, The acquisition of the physical location information of the node chip in the communication link includes: Send detection commands to the node chips in the communication link; Obtain the physical location information of the node chips in the communication link.

17. The fault chip detection method according to claim 16, characterized in that, Sending detection commands to node chips in the communication link to obtain the physical location information of the node chips in the communication link includes: Send the detection command to the communication link; Each node chip in the communication link generates physical location information in response to the detection command; Obtain the physical location information of each of the above.

18. A fault detection device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-17.

19. A computing device, characterized in that, Includes the fault detection device as described in claim 18.

20. A computer-readable storage medium, wherein, The computer-readable storage medium stores computer instructions for causing the computer to perform the method according to any one of claims 1-17.

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