A circuit timing analysis method and device and a storage medium
By using characteristic timing data and function expressions of circuit units in circuit timing analysis, the operating voltage range of the circuit path can be solved, which solves the problems of slow analysis speed and coverage omission in the prior art and achieves faster and more accurate circuit timing analysis.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2022-11-04
- Publication Date
- 2026-08-04
AI Technical Summary
Existing circuit timing analysis methods are slow and prone to omissions when dealing with multiple voltage points, wide range of variable voltage points, continuous variable voltage, and wide range of continuous variable voltage, leading to biased analysis results.
By acquiring the characteristic timing data of the circuit units along the circuit path, and substituting the functional expression with voltage or temperature as variables into the timing inequality of the circuit path to solve for the first operating voltage range, the circuit path is compared with the voltage range required by the design to determine whether the circuit path meets the timing requirements.
It saves analysis time, avoids analyzing each operating voltage point individually, improves the accuracy of circuit timing analysis, and eliminates analysis omissions.
Smart Images
Figure CN115618778B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit design technology, and more specifically, to a circuit timing analysis method, apparatus, and storage medium. Background Technology
[0002] Integrated circuits have different performance requirements when running different applications and calculations. To address these different applications and calculations, different voltages can be used, or continuously variable voltages can be employed. When the performance requirements of integrated circuits vary greatly across different applications, a wide range of variable voltages, or even a wide range of continuously variable voltages, can be used.
[0003] Circuit timing analysis is a crucial step in the integrated circuit design process. The characteristic data of circuit cells that circuit timing analysis relies on are the characteristic data corresponding to several discrete voltage points. Currently, for circuits operating with multiple voltage points, wide range of variable voltage points, continuously variable voltage, or wide range of continuously variable voltage, timing analysis requires first determining several discrete voltage points to be analyzed, and then performing timing analysis on each of these discrete operating points one by one. This approach results in a relatively large time overhead for traversing each operating voltage point, slow analysis speed, and the limited number of voltage points means that coverage may be missed, leading to biased analysis results. Summary of the Invention
[0004] In view of this, embodiments of this application disclose a circuit timing analysis method, apparatus, and storage medium to accelerate the circuit timing analysis process and improve the accuracy of circuit timing analysis.
[0005] The technical solutions provided in this application are as follows:
[0006] In a first aspect, embodiments of this application provide a circuit timing analysis method, the method comprising:
[0007] Obtain characteristic timing data of circuit units along the circuit path; the characteristic timing data includes: a function expression with voltage as a variable;
[0008] Substituting the functional expression with voltage as the variable into the circuit path timing inequality, the first operating voltage range is obtained by solving the problem.
[0009] Compare the first operating voltage range with the second operating voltage range required by the design;
[0010] If the first operating voltage range covers the second operating voltage range, then the circuit path is determined to meet the timing requirements;
[0011] If the first operating voltage range does not cover the second operating voltage range, then the circuit path is determined to not meet the timing requirements.
[0012] In one possible implementation, there are multiple circuit units, which together form a logic circuit between the source register and the destination register. The method further includes:
[0013] The timing inequality of the circuit path is established based on the distance between the time point when the data arrives at the data input terminal of the target register and the time point corresponding to the minimum setup time; and / or,
[0014] The timing inequality of the circuit path is established based on the distance between the minimum data retention time point and the data change time point at the data input terminal of the target register.
[0015] In one possible implementation, the method further includes:
[0016] Based on the reference voltage and voltage variation coefficient of the circuit unit, the function expression with voltage as the variable is established.
[0017] In one possible implementation, the method further includes:
[0018] Once it is determined that the circuit path meets the timing requirements, the operating voltage of the circuit path is reduced according to the first operating voltage range to obtain the optimized operating voltage of the circuit unit.
[0019] When it is determined that the circuit path does not meet the timing requirements, the operating voltage of the circuit path is increased according to the first operating voltage to obtain the optimized operating voltage of the circuit unit.
[0020] In one possible implementation, the circuit units are multiple, and the method further includes:
[0021] If at least two of the multiple circuit units share the same voltage regulation module, then the maximum value of the optimized operating voltages corresponding to the at least two circuit units is determined as the adjusted operating voltage.
[0022] The output of the voltage regulation module is adjusted according to the adjusted operating voltage.
[0023] In one possible implementation, the method further includes:
[0024] Perform thermal analysis on the circuit path to determine the temperature at the location of the circuit unit;
[0025] The characteristic timing data also includes a functional expression with temperature as a variable. Substituting the functional expression with voltage as a variable into the circuit path timing inequality to obtain the first operating voltage range includes:
[0026] Substituting the function expression with voltage as a variable, the function expression with temperature as a variable, and the temperature at the location of the circuit unit into the circuit path timing inequality, the first operating voltage range is obtained.
[0027] In one possible implementation, the method further includes:
[0028] Based on the reference temperature and temperature change coefficient of the circuit unit, the function expression with temperature as the variable is established.
[0029] Secondly, embodiments of this application provide a circuit timing analysis apparatus, the apparatus comprising:
[0030] An acquisition unit is used to acquire characteristic timing data of circuit units on the circuit path; the characteristic timing data includes: a function expression with voltage as a variable;
[0031] The solving unit is used to substitute the functional expression with voltage as a variable into the circuit path timing inequality to solve for the first operating voltage range.
[0032] A comparison unit is used to compare the first operating voltage range with the second operating voltage range required by the design.
[0033] The determining unit is configured to determine that the circuit path meets timing requirements if the first operating voltage range covers the second operating voltage range;
[0034] The determining unit is further configured to determine that the circuit path does not meet the timing requirements if the first operating voltage range does not cover the second operating voltage range.
[0035] Thirdly, embodiments of this application provide a circuit timing analysis device, the device comprising: a processor, a memory, and a system bus;
[0036] The processor and the memory are connected via the system bus;
[0037] The memory is used to store one or more programs, the one or more programs including instructions, which, when executed by the processor, cause the processor to perform the circuit timing analysis method described in any of the first aspects above.
[0038] Fourthly, embodiments of this application provide a computer-readable storage medium storing instructions that, when executed on a terminal device, cause the terminal device to perform the circuit timing analysis method described in any of the first aspects above.
[0039] Fifthly, embodiments of this application provide a computer program product that, when run on a terminal device, causes the terminal device to execute the circuit timing analysis method described in any of the first aspects above.
[0040] Based on the above technical solution, this application has the following beneficial effects:
[0041] This application discloses a circuit timing analysis method, apparatus, and storage medium. The method includes: acquiring characteristic timing data of circuit units along a circuit path; the characteristic timing data includes a function expression with voltage as a variable; substituting the function expression with voltage as a variable into a circuit path timing inequality to obtain a first operating voltage range; comparing the first operating voltage range with a second operating voltage range required by the design; if the first operating voltage range covers the second operating voltage range, then the circuit path is determined to meet the timing requirements; if the first operating voltage range does not cover the second operating voltage range, then the circuit path is determined to not meet the timing requirements. It is evident that this application avoids performing timing analysis on all operating voltage points explicitly. By solving the circuit path timing inequality, the first operating voltage range that meets the conditions is implicitly determined, while the second operating voltage range not covered by the first operating voltage range does not meet the timing conditions. Compared with existing timing analysis methods, this saves analysis time, accelerates the timing analysis process, and provides full coverage of circuit timing analysis, eliminating analysis omissions and improving the accuracy of circuit timing analysis. Attached Figure Description
[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the published drawings without creative effort.
[0043] Figure 1 This is a flowchart of a circuit timing analysis method disclosed in an embodiment of this application;
[0044] Figure 2 This is a schematic diagram of a circuit and signal waveform disclosed in an embodiment of this application;
[0045] Figure 3 This is a schematic diagram of another circuit and signal waveform disclosed in an embodiment of this application;
[0046] Figure 4 This is a flowchart of another circuit timing analysis method disclosed in an embodiment of this application;
[0047] Figure 5This is a flowchart of another circuit timing analysis method disclosed in an embodiment of this application;
[0048] Figure 6 This is a schematic diagram of the structure of a circuit timing analysis device disclosed in an embodiment of this application. Detailed Implementation
[0049] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0050] The terms “comprising,” “including,” “having,” and variations thereof, used in this specification, all mean “including but not limited to,” unless otherwise specifically emphasized. It should be noted that in the description of embodiments in this application, terms such as “first,” “second,” etc., are used only for descriptive purposes and should not be construed as indicating or implying relative importance or order.
[0051] Existing circuit timing analysis methods first determine several discrete voltage points to be analyzed, and then perform timing analysis on each of these discrete operating points one by one. This approach has at least two problems: first, traversing each operating voltage point is relatively time-consuming, and the analysis time increases at least linearly with the number of voltage points; second, for continuously variable voltage operations, especially those with wide voltage ranges, the limited number of voltage points inevitably leads to omissions, resulting in undetected timing issues at values not included in the continuously variable voltage range. Therefore, new circuit timing analysis methods are needed to handle the timing analysis of circuits operating with multiple voltage points, wide variable voltage points, continuously variable voltages, and wide continuously variable voltages, in order to improve analysis speed and eliminate omissions.
[0052] To address this, this application discloses a circuit timing analysis method, apparatus, and storage medium. The method includes: acquiring characteristic timing data of circuit units along a circuit path; the characteristic timing data includes a function expression with voltage as a variable; substituting the function expression with voltage as a variable into a circuit path timing inequality to obtain a first operating voltage range; comparing the first operating voltage range with a second operating voltage range required by the design; if the first operating voltage range covers the second operating voltage range, then the circuit path is determined to meet the timing requirements; if the first operating voltage range does not cover the second operating voltage range, then the circuit path is determined to not meet the timing requirements. It is evident that this application avoids performing timing analysis on all operating voltage points. By solving the circuit path timing inequality, the first operating voltage range that meets the conditions is implicitly determined, while the second operating voltage range not covered by the first operating voltage range does not meet the timing conditions. Compared with existing timing analysis methods, this saves analysis time, accelerates the timing analysis process, and provides full coverage of circuit timing analysis, eliminating analysis omissions and improving the accuracy of circuit timing analysis.
[0053] See Figure 1 The flowchart of a circuit timing analysis method disclosed in this application includes:
[0054] S101. Obtain the characteristic timing data of the circuit units on the circuit path; the characteristic timing data includes: a function expression with voltage as a variable;
[0055] It should be noted that there are multiple circuit units in the embodiments of this application. The function expression with voltage as a variable in the embodiments of this application can be a linear function, a multiplicative function, a piecewise linear function, etc., and there are no specific restrictions. It can be set according to actual needs.
[0056] In one possible implementation, in this embodiment of the application, a functional expression with voltage as a variable is established based on the reference voltage and voltage change coefficient of the circuit unit. Specifically, this functional expression with voltage as a variable can be:
[0057] T cell,i 1 = T cell,i,Vdd0 +K v,i *(V dd –V dd0 (1)
[0058] Among them, T cell,i,Vdd0 This indicates that the operating voltage of the i-th circuit unit is V. dd0 Characterized delay data of time, K v,i *(V dd –V dd0) indicates that the operating voltage of the i-th circuit unit is V. dd The characteristic delay data offset of time, K v,i V represents the coefficient that represents the characteristic delay of the i-th circuit unit as a function of voltage. dd0 This represents the reference operating voltage of the i-th circuit unit.
[0059] S102. Substitute the functional expression with voltage as a variable into the circuit path timing inequality and solve to obtain the first operating voltage range.
[0060] See Figure 2 This is a schematic diagram of a circuit and signal waveform disclosed in an embodiment of this application. Figure 2 REG1 is the source register, REG2 is the destination register, and Comb Logic is the combinational logic circuit on the data communication between REG1 and REG2. It is generally composed of several circuit units, that is, multiple circuit units form the logic circuit between the source register and the destination register.
[0061] It should be noted that, Figure 2 The relationships between the various parameters are as follows:
[0062] T = T Latch_Edge -T Launch_Edge (2)
[0063] T SKEW =T CLK2 -T CLK1 (3)
[0064] T data =∑T cell,I i = 1, 2, ..., N (4)
[0065] T setup_slack =T+T SKEW –T SU –T CO –T data (5)
[0066] Where T represents the clock signal period; T Latch_Edge This indicates the time point at which the target register REG2 latches data at the edge of the clock signal, corresponding to... Figure 2 The "Latch Edge" in the text refers to the time point corresponding to the edge; T Launch_Edge This indicates the time point at which data is emitted from the source register REG1 at the edge of the clock signal, corresponding to... Figure 2 The "Launch Edge" in the text refers to the time point corresponding to the edge.
[0067] T SKEWT represents the clock offset between the clock input of the destination register REG2 (REG2.CLK) and the clock input of the source register REG1 (REG1.CLK). CLK1 T represents the delay time from the rising edge of the clock signal CLK to the clock input (REG1.CLK) of the source register REG1. CLK2 This indicates the delay time from the rising edge of the clock signal CLK to the clock input (REG2.CLK) of the target register REG2.
[0068] T data T represents the delay time for data to be transmitted from the output (REG1.Q) of the source register REG1 to the data input (REG2.D) of the destination register REG2. It is the sum of the delays of the circuit units traversed along the circuit path from the output (REG1.Q) of the source register REG1 to the data input (REG2.D) of the destination register REG2. cell,i This represents the characteristic timing data of the i-th circuit unit. It can be understood that T here... cell,i The above can be expressed as a functional expression T with voltage as the variable. cell,i 1 = T cell,i,Vdd0 +K v,i *(V dd –V dd0 It can also be a functional expression T with temperature as the variable, as shown below. cell,i 2 = T cell,i,Tdd0 +K T,i *(T dd -T dd0 ).
[0069] T setup_slack This represents the setup time margin, which is the time from the point when data arrives at the data input terminal (REG2.D) of the target register REG2 to the minimum setup time T. SETUP The distance between the corresponding time points Figure 2 The “setup slack” in the text refers to; T SU This indicates the minimum time that the data signal at the data signal input (REG2.D) of the target register REG2 must remain stable before the rising edge of the clock signal at the clock input (REG2.CLK) of the target register REG2; T CO T represents the delay time between the rising edge of the clock signal at the clock input terminal (REG1.CLK) of the source register REG1 and the data transmission to the output terminal (REG1.Q) of the source register REG1. CO This includes the internal logic delay of the registers and the data output buffer delay.
[0070] See Figure 3This is a schematic diagram of another circuit and signal waveform disclosed in an embodiment of this application. It is understood that... Figure 3 Zhongyu Figure 2 The representation of the same parameters is the same, so it will not be elaborated further.
[0071] It should be noted that, Figure 3 The relationships between the various parameters are as follows:
[0072] T hold_slack =T SKEW +T CO +T data -T h (6)
[0073] Among them, T hold_slack This represents the hold time margin, which is the distance between the minimum data hold time point and the data change time point at the data input terminal (REG2.D) of the target register REG2. Figure 3 The "Hold Slack" in the text refers to; T h This indicates the minimum time after the clock's effective edge has arrived that the data must remain stable.
[0074] The inventors of this application discovered through research that when T... setup_slack When the value is positive, it means the data arrived at time T. SETUP When the corresponding time point is to the left, the timing requirements are met; when T setup_slack When the value is negative, the data arrival time point is T. SETUP When the corresponding time point is to the right, the timing requirements are not met. When T hold_slack When the value of T is positive, that is, when T is positive. h When the data changes to the left of the time point, the timing requirements are met; when T... hold_slack When the value of T is negative, that is, when T is negative. h When the data changes to the right of the time point, the timing requirements are not met. Therefore, in this embodiment, a circuit path timing inequality is established based on the distance between the time point when the data arrives at the data input terminal of the target register and the time point corresponding to the minimum setup time; and / or, a circuit path timing inequality is established based on the distance between the minimum data holding time point and the data change time point at the data input terminal of the target register.
[0075] In one possible implementation, the circuit path timing inequality in the embodiments of this application can specifically be:
[0076] T+T SKEW –T SU -T CO -T data ≥0 (7)
[0077] T SKEW +TCO +T data –T h ≥0 (8)
[0078] It should be noted that the clock signal period substituted into the timing inequality of the circuit path can also be an expression that varies with voltage. It can be a linear function with voltage as the variable, a multiplicative function, or a piecewise linear function; there are no specific limitations, and the choice can be made according to actual needs. In one possible implementation, T in this embodiment of the application... 、 T SU T CO、 T h It can be represented as follows.
[0079] Characterized delay T of source register REG1 as a function of operating voltage CO The data expression is:
[0080] T CO =T CO,Vdd0 +K v,reg,co *(V dd –V dd0 (9)
[0081] Among them, T CO,Vdd0 This indicates that the operating voltage of the source register REG1 is V. dd0 Characterized delay data of time, K v,reg,co *(V dd –V dd0 This indicates that the operating voltage of the source register REG1 is V. dd The data offset of time-delayed data, K v,reg,co The coefficient representing the characteristic delay of source register REG1 as a function of voltage.
[0082] Characterization of target register REG2 as a function of operating voltage T SU The data expression is:
[0083] T SU =T SU,Vdd0 +K v,reg,su *(V dd –V dd0 (10)
[0084] Among them, T SU,Vdd0 This indicates that the operating voltage of the target register REG2 is V. dd0 Characterized delay data of time, K v,reg,su *(V dd –V dd0 K represents the data offset of the characteristic delay data when the operating voltage of the target register REG2 is Vdd. v,reg,suThe coefficient representing the characteristic delay of the target register REG2 as a function of voltage.
[0085] Characterization T of registers (source register REG1 and destination register REG2) as a function of operating voltage h The data expression is:
[0086] T h =T h,Vdd0 +K v,reg,h *(V dd –V dd0 (11)
[0087] Among them, T h,Vdd0 This indicates that the register's operating voltage is V. dd0 The retention time of K v,reg,h *(V dd –V dd0 This indicates that the register operates at a voltage of V. dd The relative operating voltage is V dd0 The time offset of holding time, K v,reg,h This represents the coefficient that indicates the change in register hold time with respect to operating voltage offset.
[0088] The expression for the clock signal period as a function of voltage is:
[0089] T = T Vdd0 +K T *(V dd –V dd0 (12)
[0090] Where T represents the operating voltage of V dd The clock signal period, T Vdd0 Indicates the operating voltage is V dd0 The clock signal period, K T The coefficient representing the change of the clock signal cycle with voltage.
[0091] It should be noted that the working voltage range that meets the inequality conditions can be solved using analytical methods or numerical methods, etc. There are no restrictions on the specific method, and the choice can be made according to actual needs.
[0092] In one possible implementation, V will be used. dd Substituting the characteristic data expression of the variable into inequality (7), we obtain the following inequality:
[0093] [T Vdd0 +K T *(V dd –V dd0 )]+T SKEW –[T SU,Vdd0 +Kv,reg,su *(V dd –V dd0 )]–[T CO,Vdd0 +K v,reg,co *(V dd –V dd0 )]–∑[T cell,i,Vdd0 +K v,i *(V dd –V dd0 )]≥0
[0094] Calculate the working voltage boundary point 1:
[0095] V dd,setup ={(T Vdd0 -K T *V dd0 )+T SKEW –(T SU,Vdd0 -K v,reg,su *V dd0 )–(T CO,Vdd0 -K v,reg,co *V dd0 )–∑(T cell,i,Vdd0 -K v,i *V dd0 )} / {K v,reg,su +K v,reg,co +∑K v,i -K T}
[0096] If {K v,reg,su +K v,reg,co +∑K v,i -K T}>0
[0097] Then V dd ≤V dd,setup (a)
[0098] Otherwise V dd ≥V dd,setup (b)
[0099] Will be V dd Substituting the characteristic data expression as a variable into inequality (8), we obtain the following inequality:
[0100] T SKEW +[T CO,Vdd0 +K v,reg,co *(V dd –V dd0 )]+∑[T cell,i,Vdd0 +K v,i *(V dd –V dd0 )]-[T h,Vdd0 +Kv,reg,h *(V dd –V dd0 )]≥0
[0101] Calculate the working voltage boundary point 2:
[0102] V dd,hold ={T SKEW +[T CO,Vdd0 -K v,reg,co *V dd0 ]+∑[T cell,i,Vdd0 -K v,i *V dd0 ]-[T h,Vdd0 -K v,reg,h *V dd0 ]} / {K v,reg,h -∑K v,i -K v,reg,co}
[0103] If {K v,reg,h -∑K v,i -K v,reg,co}>0
[0104] Then V dd ≤V dd,hold (c)
[0105] Otherwise V dd ≥V dd,hold (d)
[0106] Based on the results (a), (b), (c), and (d), determine the first operating voltage range (V). DDL V DDH Specifically, (a) and (b) can be used to determine the first range; (c) and (d) can be used to determine the second range. The intersection of the first and second ranges can be taken as the first working voltage range (V). DDL V DDH ).
[0107] It should be noted that for multiple circuit units along a circuit path, some of these units may operate at several different but fixed operating voltages, which will be correspondingly different when substituting into the inequalities. For example, circuit unit 2 operates at a fixed voltage V. ddp8v At that time, the characteristic data substituted into it is T cell,2 =T cell,2,Vdd0 +K v,2 *(V ddp8v –V dd0 ), instead of T cell,2 =T cell,2,Vdd0 +K v,2 *(V dd –V dd0It is understandable that, since circuit unit 2 operates at a fixed operating voltage, the solution here is not to calculate the operating voltage of circuit unit 2, but rather to obtain the operating voltage of this unit circuit at V. ddp8v The delay value is calculated so that the inequality is accurately substituted with the delay. The above is merely illustrative and should not be construed as a limitation of this application.
[0108] It should be noted that for multiple basic circuit units along a circuit path, the operating voltage difference between one circuit unit A and another basic circuit unit B is fixed at ΔV. dd When substituting into the inequality, the operating voltage of basic circuit unit A is used as a reference. For example, if basic unit 2 operates at a fixed voltage ΔV lower than that of basic circuit unit 1... dd When the voltage is T, the characteristic data substituted into it is T. cell,2 =T cell,2,Vdd0 +K v,2 *(V dd -⊿V dd –V dd0 ), instead of T cell,2 =T cell,2,Vdd0 +K v,2 *(V dd –V dd0 It is understood that the above is merely illustrative and should not be construed as a limitation of this application.
[0109] S103. Compare the first operating voltage range with the second operating voltage range required by the design;
[0110] The first working voltage range (V) obtained DDL V DDH ) and the second operating voltage range required by the design (V DDL0 V DDH0 The results are compared to determine whether the obtained first operating voltage range covers the operating voltage range required by the design.
[0111] S104. If the first operating voltage range covers the second operating voltage range, then the circuit path is determined to meet the timing requirements.
[0112] S105. If the first operating voltage range does not cover the second operating voltage range, then it is determined that the circuit path does not meet the timing requirements.
[0113] This application discloses a circuit timing analysis method to obtain characteristic timing data of circuit units along a circuit path. This characteristic timing data includes: a function expression with voltage as a variable; substituting the function expression with voltage as a variable into a circuit path timing inequality to obtain a first operating voltage range; comparing the first operating voltage range with a second operating voltage range required by the design; if the first operating voltage range covers the second operating voltage range, the circuit path is determined to meet timing requirements; if the first operating voltage range does not cover the second operating voltage range, the circuit path is determined to not meet timing requirements. Therefore, this application avoids performing timing analysis on all operating voltage points explicitly. It implicitly determines the first operating voltage range that meets the conditions by solving the circuit path timing inequality, while the second operating voltage range not covered by the first operating voltage range does not meet the timing conditions. Compared with existing timing analysis methods, this saves analysis time, accelerates the timing analysis process, and provides full coverage of circuit timing analysis, eliminating analysis omissions and improving the accuracy of circuit timing analysis.
[0114] See Figure 4 Here is a flowchart of another circuit timing analysis method disclosed in an embodiment of this application, the method including:
[0115] S401. Obtain the characteristic timing data of the circuit units on the circuit path; the characteristic timing data includes: a function expression with voltage as a variable;
[0116] It is understandable that this step is the same as step S101 above, so it will not be repeated here.
[0117] S402. Substitute the functional expression with voltage as a variable into the circuit path timing inequality and solve to obtain the first operating voltage range.
[0118] It is understandable that this step is the same as step S102 above, so it will not be described again.
[0119] S403. Compare the first operating voltage range with the second operating voltage range required by the design;
[0120] It is understandable that this step is the same as step S103 above, so it will not be described again.
[0121] S404. If the first operating voltage range covers the second operating voltage range, then the circuit path is determined to meet the timing requirements.
[0122] It is understandable that this step is the same as step S104 above, so it will not be repeated here.
[0123] S405. After determining that the circuit path meets the timing requirements, reduce the operating voltage of the circuit path according to the first operating voltage range to obtain the optimized operating voltage of the circuit unit.
[0124] It should be noted that power consumption is a crucial consideration in integrated circuit design. While meeting performance requirements, it is essential to minimize circuit power consumption as much as possible. In this embodiment, the circuit path meeting timing requirements indicates that it meets performance requirements. Therefore, the operating voltage of the circuit path will be adjusted based on the first operating voltage to reduce power consumption.
[0125] S406. If the first operating voltage range does not cover the second operating voltage range, then it is determined that the circuit path does not meet the timing requirements.
[0126] It is understandable that this step is the same as step S105 above, so it will not be repeated here.
[0127] S407. When it is determined that the circuit path does not meet the timing requirements, the operating voltage of the circuit path is increased according to the first operating voltage to obtain the optimized operating voltage of the circuit unit.
[0128] It should be noted that if the circuit path in this embodiment does not meet the timing requirements, it means that it does not meet the working performance. Therefore, the working voltage of the circuit path will be adjusted according to the first working voltage to increase the working voltage and improve the circuit performance.
[0129] In one possible implementation, the circuit units in this application embodiment are multiple. If at least two of the multiple circuit units share the same voltage regulation module, the maximum value of the optimized working voltages corresponding to the at least two circuit units is determined as the adjustment working voltage. The output of the voltage regulation module is adjusted according to the adjustment working voltage, so that each circuit unit can meet the working performance requirements.
[0130] It is understandable that although the circuit timing analysis method disclosed in this application is mainly for timing analysis and optimization of circuits operating at variable voltages, for paths operating at fixed voltages, the timing analysis method disclosed in this application can also be used to further determine the optimized operating voltage to correct path timing, optimize path timing, and reduce power consumption. For paths operating at discrete voltage points, the timing analysis method disclosed in this application can also be used to further determine the new voltage value of each discrete voltage point to correct path timing, optimize path timing, and reduce power consumption for each discrete operating point. Correspondingly, after adjusting the operating voltage of the circuit units on the circuit path, the output of the voltage regulator needs to be optimized to meet the operating voltage requirements of the circuit units on the circuit path.
[0131] As can be seen, in this embodiment of the application, adjusting the operating voltage of the circuit path based on the first operating voltage obtained by the solution can reduce power consumption or improve operating performance to meet the requirements of integrated circuit design.
[0132] See Figure 5 This is a flowchart of another circuit timing analysis method disclosed in an embodiment of this application. The method further includes:
[0133] S501. Obtain the characteristic timing data of the circuit units on the circuit path; the characteristic timing data includes: a function expression with voltage as a variable and a function expression with temperature as a variable;
[0134] It should be noted that the function expression with temperature as a variable in the embodiments of this application can be a linear function, a multinomial function, a piecewise linear function, etc. There are no specific restrictions, and it can be set according to actual needs.
[0135] In one possible implementation, in this embodiment of the application, a functional expression with temperature as a variable is established based on the reference temperature and temperature change coefficient of the circuit unit. Specifically, this functional expression with temperature as a variable can be:
[0136] T cell,i 2 = T cell,i,Tdd0 +K T,i *(T dd -T dd0 (13)
[0137] Among them, T cell,i,Tdd0 The operating temperature of the i-th circuit unit is T. dd0 Characterized delay data of time, K T,i *(T dd -T dd0 () indicates that the operating temperature of the i-th circuit unit is T. dd The characteristic delay data offset of time, K T,i T represents the coefficient representing the characteristic delay of the i-th circuit unit as a function of temperature. dd0 This represents the reference operating temperature of the i-th circuit unit.
[0138] It is understandable that the function expression with voltage as the variable is the same as the function expression with voltage as the variable in S101 above, so it will not be repeated here.
[0139] S502. Perform thermal analysis on the circuit path to determine the temperature of the location of the circuit unit;
[0140] S503. Substitute the function expression with voltage as a variable, the function expression with temperature as a variable, and the temperature at the location of the circuit unit into the circuit path timing inequality to obtain the first operating voltage range.
[0141] It is understandable that the first operating temperature range (T) can be obtained by using a method similar to S102 described above. DDL T DDH Therefore, I will not go into details.
[0142] It should be noted that, in one possible implementation, the embodiments of this application combine the above-mentioned function expression with voltage as a variable and the function expression with voltage as a variable to obtain the function expression with voltage and temperature as variables. The specific combination will be handled differently in the specific implementation. The embodiments of this application do not discuss the specific implementation, and can be selected according to the actual situation without limitation.
[0143] S504. Compare the first operating voltage range with the second operating voltage range required by the design.
[0144] Understandably, this step is similar to S103 above, so it will not be described again.
[0145] S505. If the first operating voltage range covers the second operating voltage range, then the circuit path is determined to meet the timing requirements.
[0146] As is understandable, this step is similar to S104 above, so it will not be described again. S405 above can also be executed after this step, so it will not be described again.
[0147] S506. If the first operating voltage range does not cover the second operating voltage range, then the circuit path is determined to not meet the timing requirements.
[0148] As is understandable, this step is similar to S104 above, so it will not be described again. S407 above can also be executed after this step, so it will not be described again.
[0149] As can be seen, thermal analysis is performed on the integrated circuit design in this embodiment to determine the temperature of the circuit unit, thereby making the timing analysis more accurate by taking into account the temperature of the specific location.
[0150] See Figure 6 The present application discloses a schematic diagram of a circuit timing analysis device, which includes:
[0151] Acquisition unit 601 is used to acquire characteristic timing data of circuit units on the circuit path; the characteristic timing data includes: a function expression with voltage as a variable;
[0152] Solving unit 602 is used to substitute the functional expression with voltage as a variable into the circuit path timing inequality to solve for the first operating voltage range;
[0153] Comparison unit 603 is used to compare the first operating voltage range with the second operating voltage range required by the design;
[0154] The determining unit 604 is configured to determine that the circuit path meets timing requirements if the first operating voltage range covers the second operating voltage range;
[0155] The determining unit 604 is further configured to determine that the circuit path does not meet the timing requirements if the first operating voltage range does not cover the second operating voltage range.
[0156] This application discloses a circuit timing analysis device. An acquisition unit acquires characteristic timing data of circuit units along a circuit path. This characteristic timing data includes a function expression with voltage as a variable. A solution unit substitutes the function expression with voltage as a variable into a circuit path timing inequality to obtain a first operating voltage range. A comparison unit compares the first operating voltage range with a second operating voltage range required by the design. A first determination unit determines that the circuit path meets timing requirements if the first operating voltage range covers the second operating voltage range. A second determination unit determines that the circuit path does not meet timing requirements if the first operating voltage range does not cover the second operating voltage range. Therefore, this application avoids performing timing analysis on all operating voltage points. By solving the circuit path timing inequality, a first operating voltage range that meets the conditions is implicitly determined, while a second operating voltage range not covered by the first operating voltage range does not meet the timing conditions. Compared with existing timing analysis methods, this saves analysis time, accelerates the timing analysis process, and provides full coverage of circuit timing analysis, eliminating analysis omissions and improving the accuracy of circuit timing analysis.
[0157] In one possible implementation, the circuit timing analysis device provided in this application embodiment comprises multiple circuit units, which together form a logic circuit between a source register and a target register. The device further includes:
[0158] The setup unit is used to establish the timing inequality of the circuit path based on the distance between the time point when the data arrives at the data input terminal of the target register and the time point corresponding to the minimum setup time; and / or, to establish the timing inequality of the circuit path based on the distance between the minimum data holding time point and the data change time point at the data input terminal of the target register.
[0159] In one possible implementation, the circuit timing analysis apparatus provided in this application embodiment further includes:
[0160] The unit is also used to establish a function expression with voltage as a variable based on the reference voltage and voltage change coefficient of the circuit unit.
[0161] In one possible implementation, the circuit timing analysis apparatus provided in this application embodiment further includes:
[0162] The adjustment unit is configured to, when it is determined that the circuit path meets the timing requirements, reduce the operating voltage of the circuit path according to the first operating voltage range to obtain the optimized operating voltage of the circuit unit; when it is determined that the circuit path does not meet the timing requirements, increase the operating voltage of the circuit path according to the first operating voltage to obtain the optimized operating voltage of the circuit unit.
[0163] In one possible implementation, the circuit timing analysis device provided in this application embodiment has multiple circuit units;
[0164] The determining unit is further configured to determine the maximum value of the optimized operating voltages corresponding to the at least two circuit units as the adjusted operating voltage if at least two of the plurality of circuit units share the same voltage regulation module;
[0165] The adjustment unit is also used to adjust the output of the voltage regulation module according to the adjusted operating voltage.
[0166] In one possible implementation, the circuit timing analysis apparatus provided in this application embodiment further includes:
[0167] A thermal analysis unit is used to perform thermal analysis on the circuit path and determine the temperature of the location of the circuit unit.
[0168] The solving unit 502 is specifically used to substitute the function expression with voltage as a variable, the function expression with temperature as a variable, and the temperature at the location of the circuit unit into the circuit path timing inequality to obtain the first operating voltage range.
[0169] In one possible implementation, the circuit timing analysis device provided in this application embodiment includes a setup unit that is further configured to determine the function expression with temperature as a variable based on the reference temperature and temperature change coefficient of the circuit unit.
[0170] Furthermore, embodiments of this application also provide a circuit timing analysis method apparatus, including: a processor, a memory, and a system bus;
[0171] The processor and the memory are connected via the system bus;
[0172] The memory is used to store one or more programs, the one or more programs including instructions, which, when executed by the processor, cause the processor to perform any of the above-described implementations of the circuit timing analysis method.
[0173] Furthermore, embodiments of this application also provide a computer-readable storage medium storing instructions that, when executed on a terminal device, cause the terminal device to execute any of the above-described implementation methods of the circuit timing analysis method.
[0174] Furthermore, this application also provides a computer program product, which, when run on a terminal device, causes the terminal device to execute any of the above-described implementation methods of the circuit timing analysis method.
[0175] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network communication device such as a media gateway, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.
[0176] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0177] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0178] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0179] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method of circuit timing analysis, characterized by, The method includes: Obtain characteristic timing data of circuit units along the circuit path; the characteristic timing data includes: a function expression with voltage as a variable; Substituting the functional expression with voltage as the variable into the circuit path timing inequality, the first operating voltage range is obtained by solving the problem. Compare the first operating voltage range with the second operating voltage range required by the design; If the first operating voltage range covers the second operating voltage range, then the circuit path is determined to meet the timing requirements; If the first operating voltage range does not cover the second operating voltage range, then the circuit path is determined to be non-compliant with timing requirements. The circuit unit is multiple, and the multiple circuit units form a logic circuit between the source register and the target register. The method further includes: The circuit path timing inequality is established based on the distance between the time point when the data arrives at the data input terminal of the target register and the time point corresponding to the minimum setup time, and / or the distance between the minimum data hold time point and the time point when the data changes at the data input terminal of the target register.
2. The method according to claim 1, characterized in that, The method further includes: Based on the reference voltage and voltage variation coefficient of the circuit unit, the function expression with voltage as the variable is established.
3. The method according to claim 1, characterized in that, The method further includes: Once it is determined that the circuit path meets the timing requirements, the operating voltage of the circuit path is reduced according to the first operating voltage range to obtain the optimized operating voltage of the circuit unit. When it is determined that the circuit path does not meet the timing requirements, the operating voltage of the circuit path is increased according to the first operating voltage to obtain the optimized operating voltage of the circuit unit.
4. The method according to claim 3, characterized in that, The circuit unit is multiple, and the method further includes: If at least two of the multiple circuit units share the same voltage regulation module, then the maximum value of the optimized operating voltages corresponding to the at least two circuit units is determined as the adjusted operating voltage. The output of the voltage regulation module is adjusted according to the adjusted operating voltage.
5. The method according to claim 1, characterized in that, The method further includes: Perform thermal analysis on the circuit path to determine the temperature at the location of the circuit unit; The characteristic timing data also includes a functional expression with temperature as a variable. Substituting the functional expression with voltage as a variable into the circuit path timing inequality to obtain the first operating voltage range includes: Substituting the function expression with voltage as a variable, the function expression with temperature as a variable, and the temperature at the location of the circuit unit into the circuit path timing inequality, the first operating voltage range is obtained.
6. The method according to claim 5, characterized in that, The method further includes: Based on the reference temperature and temperature change coefficient of the circuit unit, the function expression with temperature as the variable is established.
7. A circuit timing analysis device, characterized in that, The device includes: An acquisition unit is used to acquire characteristic timing data of circuit units on the circuit path; the characteristic timing data includes: a function expression with voltage as a variable; The solving unit is used to substitute the functional expression with voltage as a variable into the circuit path timing inequality to solve for the first operating voltage range. A comparison unit is used to compare the first operating voltage range with the second operating voltage range required by the design. The determining unit is configured to determine that the circuit path meets timing requirements if the first operating voltage range covers the second operating voltage range; The determining unit is further configured to determine that the circuit path does not meet the timing requirements if the first operating voltage range does not cover the second operating voltage range; The circuit unit is multiple, and the multiple circuit units form a logic circuit between the source register and the destination register. The device further includes: The establishment unit is used to establish the circuit path timing inequality based on the distance between the time point when the data arrives at the data input terminal of the target register and the time point corresponding to the minimum establishment time, and / or the distance between the minimum data holding time point and the time point when the data changes at the data input terminal of the target register.
8. A circuit timing analysis device, characterized in that, The device includes: a processor, a memory, and a system bus; The processor and the memory are connected via the system bus; The memory is used to store one or more programs, the one or more programs including instructions that, when executed by the processor, cause the processor to perform the circuit timing analysis method according to any one of claims 1 to 6.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on a terminal device, cause the terminal device to perform the circuit timing analysis method according to any one of claims 1 to 6.