Method, device and equipment for verifying top interconnection in GPU architecture and storage medium
By using Shell scripts and assert statements, the low efficiency of top-level interconnect verification for GPU chips in existing technologies has been solved, significantly improving the verification efficiency of top-level interconnects for GPU racks.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGSHA JINGJIA MICROELECTRONICS
- Filing Date
- 2022-10-18
- Publication Date
- 2026-07-21
AI Technical Summary
In existing technologies, GPU chip top-level interconnect verification suffers from problems such as low efficiency of manual inspection, long time consumption, and difficulty in rapid regression verification.
A method is adopted to read the signals and bit width of the top-level module in a hierarchical manner, and to automatically verify them using Shell scripts and assert statements, thereby reducing human intervention and improving verification efficiency.
It significantly improves the efficiency of top-level interconnection verification, reducing the first verification time by 6 times and the regression verification time by 20 times, and reducing the risk of human error.
Smart Images
Figure CN115618794B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and more specifically, to a method, apparatus, device, and storage medium for verifying top-level interconnects in a GPU architecture. Background Technology
[0002] GPU chips are large-scale chips with complex top-level interconnects. Currently, with the exponential growth in chip size, the connections at the top level have become even more complex, and the number of interface signals used to connect various modules is also increasing exponentially, making it more difficult to verify the correctness of the top-level connections.
[0003] The current technology involves manually identifying the correspondence between input and output signals, and then having the person in charge of each module manually check the correspondence to ensure that the top-level wiring is correct.
[0004] The drawbacks of existing technologies are that they rely on manual inspection, which carries the risk of errors due to human negligence, is time-consuming and inefficient, and cannot perform regression verification quickly when the top-level connections are modified. Summary of the Invention
[0005] To address one of the aforementioned technical deficiencies, this application provides a method, apparatus, device, and storage medium for verifying top-level interconnects in a GPU architecture.
[0006] According to a first aspect of the embodiments of this application, a method for verifying top-level interconnects in a GPU architecture is provided, the method comprising:
[0007] Read the source signals and bit widths of all modules in the top layer hierarchically, and save the source signals and bit widths to the source file;
[0008] Read the source signal from the source file, find the target signal corresponding to the source signal, and save the source signal and target signal to the matching file;
[0009] Read the source signal from the matching file, check the target signal based on the source signal, and obtain the check result;
[0010] Verify the check results using shell scripts and assert statements.
[0011] In an optional embodiment of this application, the steps of reading the source signal in the source file, finding the target signal corresponding to the source signal, and saving the source signal and the target signal to the matching file further include:
[0012] If the target signal corresponding to the source signal is not found, the source signal will be filtered into the supplementary library file.
[0013] In an optional embodiment of this application, the steps of reading the source signal in the source file, finding the target signal corresponding to the source signal, and saving the source signal and the target signal to the matching file further include:
[0014] After the source signals in the source file are matched, the target signals after filtering in the library file are manually searched.
[0015] In an optional embodiment of this application, the steps of reading the source signal from the matching file, checking the target signal based on the source signal, and obtaining the check result further include:
[0016] The source signal in the matching file is read in a loop, and the target signal is checked based on the source signal to obtain the check result. The number of loops is equal to the bit width.
[0017] In an optional embodiment of this application, the steps of reading the source signal from the matching file, checking the target signal based on the source signal, and obtaining the check result further include:
[0018] If the check result shows that the source signal and the corresponding target signal are equal in value, but the other signal values are not equal to the target signal value, then wait for the source signal and target signal check to complete.
[0019] In an optional embodiment of this application, the steps of reading the source signal from the matching file, checking the target signal based on the source signal, and obtaining the check result further include:
[0020] If the check result is not that the source signal value is equal to the corresponding target signal value and other signal values are not equal to the target signal value, then the source signal in the matching file is read again, and the target signal is checked based on the source signal.
[0021] In an optional embodiment of this application, the step of verifying the check result using a shell script and an assert statement further includes:
[0022] After verification, check the information printed by the assert statement. If a connection error message is displayed, resolve the problem manually according to the prompt.
[0023] According to a second aspect of the embodiments of this application, a top-level interconnect verification device in a GPU architecture is provided, the device comprising a reading module, a searching module, a checking module, and a verification module:
[0024] The read module is used to read the source signals and bit widths of all modules in the top layer in a hierarchical manner, and save the source signals and bit widths to the source file;
[0025] The search module is used to read the source signal in the source file, find the target signal corresponding to the source signal, and save the source signal and the target signal to the matching file.
[0026] The inspection module is used to read the source signal in the matching file, inspect the target signal based on the source signal, and obtain the inspection result.
[0027] The verification module is used to verify the check results via shell scripts and assert statements.
[0028] According to a third aspect of the embodiments of this application, a computer device is provided, comprising: a memory; a processor; and a computer program; wherein the computer program is stored in the memory and configured to be executed by the processor to implement the steps of any of the methods of the first aspect of the embodiments of this application.
[0029] According to a fourth aspect of the embodiments of this application, a computer-readable storage medium is provided having a computer program stored thereon; the computer program is executed by a processor to implement the steps of any of the methods of the first aspect of the embodiments of this application.
[0030] In existing technologies, top-level interconnect network checks require manual extraction of top-level interface signals and signal connection relationships. After extraction, each module manager checks the top-level interconnects to determine if errors exist. This requires a large number of personnel, is inefficient, and carries the risk of human error. When the top level is modified, the interface signals need to be extracted and checked again, making the previously completed work unusable. The top-level interconnect verification method for GPU architecture provided in this application reduces the time required for the initial extraction and verification of top-level interface signals by at least 6 times compared to the original method, and reduces subsequent regression verification time by at least 20 times. Using this method, top-level interconnect verification no longer relies on module managers for signal checks; it can be performed by running scripts. This application has low reliance on personnel and reduces the risk of human error. Attached Figure Description
[0031] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0032] Figure 1 A flowchart of the top-level interconnect verification method in the GPU architecture provided in this application embodiment;
[0033] Figure 2 A flowchart of one embodiment of the GPU architecture top-level interconnect verification method provided in this application;
[0034] Figure 3 This is a structural diagram of the top-level interconnect verification device in the GPU architecture provided in the embodiments of this application;
[0035] Figure 4 This is a schematic diagram of a computer device structure provided in one embodiment of this application. Detailed Implementation
[0036] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.
[0037] The inventors of this application have discovered that checking the top-level interconnect network requires manual extraction of the top-level interface signals and signal connection relationships. After extraction, each module manager then checks the top-level interconnect for errors. This requires a large number of personnel, is inefficient, and carries the risk of human error. When the top level is modified, the interface signals need to be extracted and checked again, making the previous work unusable.
[0038] This application implements a method for verifying top-level interconnects in a GPU architecture. Based on the naming and signal connection rules of the top-level interfaces, a method for extracting interface signals is defined, and signals that do not conform to the rules are filtered out for manual inspection. After acquiring all top-level connection signals, the correctness of the target signal is determined by forcing the source signal bit by bit. The verification of top-level interconnects is implemented using the SHELL scripting language. This method greatly improves the verification efficiency of top-level interconnects, reduces the risk of manual inspection, and allows for rapid regression verification when top-level connections are modified.
[0039] Please see Figure 1 The top-level interconnect verification method in the GPU architecture of this application includes:
[0040] S1: Read the source signals and bit widths of all modules in the top layer in a hierarchical manner, and save the source signals and bit widths to the source file.
[0041] S2: Read the source signal from the source file, find the target signal corresponding to the source signal, and save the source signal and the target signal to the matching file. In specific implementations, this application embodiment can perform this by reading the source signal from the source file line by line.
[0042] In practice, if the target signal corresponding to the source signal is not found, the source signal is filtered into the supplementary library file. After the source signal in the source file is matched, the filtered target signal in the library file is manually searched, and finally the matched source signal, target signal and bit width are added to the previously saved matching file.
[0043] In practice, when extracting interface signals during the above steps, any object-oriented programming language capable of achieving the above objectives can be used, preferably Python.
[0044] Based on this, the method in this application embodiment first filters out signals that do not conform to the rules for manual inspection.
[0045] S3: Read the source signal from the matching file, check the target signal based on the source signal, and obtain the check result.
[0046] In practice, the source signal in the matching file is read cyclically, and the target signal is checked based on the source signal to obtain the check result. The number of iterations is equal to the bit width.
[0047] If the check result shows that the source signal and the corresponding target signal are equal in value, but the other signal values are not equal to the target signal value, then wait for the source signal and target signal check to complete.
[0048] If the check result is not that the source signal value is equal to the corresponding target signal value and other signal values are not equal to the target signal value, then the source signal in the matching file is read again, and the target signal is checked based on the source signal.
[0049] In some embodiments of this application, when performing the above steps, the source signal can be forced to 0 first, and then the source signal and bit width can be read in a line-by-line manner as in step S2. An initial value is set in a loop, and the value is forced to the source signal by shifting it left by a preset value in sequence.
[0050] In practice, after each force source signal, an embedded loop is used to check the target signal result. The value of the target signal corresponding to the source signal should be equal to the source signal, and the values of other target signals should all be 0. The number of loops is the number of target signals.
[0051] Based on this, the method provided in this application, after obtaining all top-level connection signals, determines whether the result of the target signal is correct by bit-forcing the source signal.
[0052] S4: Verify the check results using shell scripts and assert statements.
[0053] In practice, after verification, check the information printed by the assert statement. If a connection error message is displayed, manually resolve the problem according to the prompt.
[0054] In this application embodiment, using Shell script for verification is the preferred solution. In other embodiments of this application, the purpose of this application can also be achieved by languages such as PHP and Python. However, based on factors such as difficulty of mastering, development efficiency, and development habits, this application embodiment found that using Shell is more in line with the three basic principles of simplicity, ease of use, and efficiency.
[0055] Based on this, the method provided in this application uses the SHELL scripting language to verify the top-level interconnects. This method can greatly improve the verification efficiency of the top-level interconnects, reduce the risk of manual inspection, and quickly complete a regression verification when the top-level connections are modified. Furthermore, this application can also perform verification using any other scripting method that can achieve the aforementioned steps.
[0056] In some other embodiments of this application, the functions implemented by the aforementioned Shell script can also be implemented using Python or PHP.
[0057] In summary, the GPU architecture top-level interconnect verification method provided in this application reduces the time required for signal extraction and verification by 6 times compared to existing methods after the initial extraction and verification of top-level interface signals. Furthermore, the subsequent regression verification time is reduced by 20 times compared to existing methods. Using the GPU architecture top-level interconnect verification method provided in this application eliminates the need for module owners to check signals during top-level interconnect verification; scripts can be run directly, reducing reliance on personnel and minimizing human error risks.
[0058] Figure 2 For a flowchart of one embodiment of the GPU architecture top-level interconnect verification method provided in this application, please refer to [link to flowchart]. Figure 2 This application further illustrates the method through a detailed example:
[0059] Based on the GPU architecture and the hierarchical relationship of the top-level interconnect, the interface signals and bit widths of all modules at the top level are read in layers. The interface signals of all modules at the top level are used as source signals, and the source signals and bit widths are saved in the source file.
[0060] The source signals stored in the source files are read line by line. Based on the connection relationships of the top-level modules, the target signals and bit widths corresponding to the source signals are found and saved in the matching file. For source signals for which no corresponding target signal is found, they are filtered into the supplementary library file. After all source file signals have been matched once, the target signals corresponding to the filtered signals in the library file are manually searched. The matched source signals, target signals, and bit widths are added to the saved matching file. The method for extracting interface signals is implemented using Python.
[0061] The process reads the source signals from the matching file, first forcing all source signals to 0. Then, it reads the source signals and bit width line by line, using a loop. An initial value of 1 is set, and each time the previous value is shifted left by one bit, the value is forcibly applied to the source signal. The number of loop iterations is equal to the bit width. After each forced source signal iteration, an embedded loop checks the target signal result. The value of the target signal corresponding to the source signal should be equal to the source signal, and the values of other target signals should all be 0. The number of loop iterations is equal to the number of target signals.
[0062] The verification method uses a shell script, and the result is judged using an assert statement. After verification completes, check the information printed by the assert statement. If there are connection error messages, the timed module will display the problem, and you should manually resolve it according to the problem prompts.
[0063] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.
[0064] Please see Figure 3 One embodiment of this application provides a top-level interconnect verification device in a GPU architecture, including a reading module 10, a searching module 20, an checking module 30, and a verification module 40:
[0065] The reading module 10 is used to read the source signals and bit widths of all modules in the top layer in a hierarchical manner, and save the source signals and bit widths to the source file;
[0066] The search module 20 is used to read the source signal in the source file, find the target signal corresponding to the source signal, and save the source signal and the target signal to the matching file.
[0067] The inspection module 30 is used to read the source signal in the matching file, inspect the target signal based on the source signal, and obtain the inspection result;
[0068] Verification module 40 is used to verify the check results via shell scripts and assert statements.
[0069] For specific limitations regarding the top-level interconnect verification device in the aforementioned GPU architecture, please refer to the limitations of the top-level interconnect verification method in the GPU architecture above, which will not be repeated here. Each module in the top-level interconnect verification device of the aforementioned GPU architecture can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.
[0070] In one embodiment, a computer device is provided, the internal structure of which can be as follows: Figure 4 As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and the database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements a top-level interconnect verification method in a GPU architecture as described above. It includes: memory and a processor; the memory stores the computer program; and the processor executes the computer program to implement any step in the video signal processing method described above.
[0071] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, can implement any step of the top-level interconnect verification method in the GPU architecture described above.
[0072] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as C, VHDL, Verilog, the object-oriented programming language Java, and the interpreted scripting language JavaScript.
[0073] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0074] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0075] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0076] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0077] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0078] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.
[0079] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.
Claims
1. A method for verifying top-level interconnects in a GPU architecture, characterized in that, include: Read the source signals and bit widths of all modules in the top layer hierarchically, and save the source signals and bit widths to the source file; Read the source signal from the source file, find the target signal corresponding to the source signal, and save the source signal and the target signal to the matching file; Read the source signal from the matching file, check the target signal based on the source signal, and obtain the check result; Specifically, this includes: cyclically reading the source signal in the matching file, checking the target signal based on the source signal, and obtaining a check result, wherein the number of cycles is the bit width; if the check result is that the source signal and the corresponding target signal value are equal and other signal values are not equal to the target signal value, then wait for the source signal and the target signal check to complete; if the check result is not that the source signal value and the corresponding target signal value are equal and other signal values are not equal to the target signal value, then reread the source signal in the matching file and check the target signal based on the source signal. The inspection results were verified using a shell script and the assert statement.
2. The top-level interconnect verification method in GPU architecture according to claim 1, characterized in that, The step of reading the source signal in the source file, finding the target signal corresponding to the source signal, and saving the source signal and the target signal to the matching file further includes: If the target signal corresponding to the source signal is not found, the source signal is filtered into the supplementary library file.
3. The top-level interconnect verification method in GPU architecture according to claim 2, characterized in that, The step of reading the source signal in the source file, finding the target signal corresponding to the source signal, and saving the source signal and the target signal to the matching file further includes: After the source signals in the source file are matched, the target signals filtered in the library file are manually searched.
4. The top-level interconnect verification method in GPU architecture according to claim 1, characterized in that, The step of verifying the inspection results using shell scripts and assert statements further includes: After verification, check the information printed by the assert statement. If a connection error message is displayed, manually resolve the issue according to the message.
5. A top-level interconnect verification device in a GPU architecture, characterized in that, This includes modules for reading, searching, checking, and verifying. The reading module is used to read the source signals and bit widths of all modules in the top layer in a hierarchical manner, and save the source signals and bit widths to the source file; The searching module is used to read the source signal in the source file, find the target signal corresponding to the source signal, and save the source signal and the target signal to the matching file; The inspection module is used to read the source signal in the matching file, inspect the target signal based on the source signal, and obtain the inspection result; Specifically, this includes: cyclically reading the source signal in the matching file, checking the target signal based on the source signal, and obtaining a check result, wherein the number of cycles is the bit width; if the check result is that the source signal and the corresponding target signal value are equal and other signal values are not equal to the target signal value, then wait for the source signal and the target signal check to complete; if the check result is not that the source signal value and the corresponding target signal value are equal and other signal values are not equal to the target signal value, then reread the source signal in the matching file and check the target signal based on the source signal. The verification module is used to verify the inspection results through shell scripts and assert statements.
6. A computer device, characterized in that, include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and configured to be executed by the processor to implement the method as described in any one of claims 1-4.
7. A computer-readable storage medium, characterized in that, It stores a computer program thereon; the computer program is executed by a processor to implement the method as described in any one of claims 1-4.