加速结构的存储和读取方法、存储装置及图形处理器
By aligning the nodes of the accelerated structure with preset byte units and filling them with non-address data, the problem of read errors when storing ray tracing algorithms in GPU memory is solved, improving read efficiency and performance.
CN115619621BActive Publication Date: 2026-07-17VERISILICON MICROELECTRONICS (SHANGHAI) CO LTD +2
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- VERISILICON MICROELECTRONICS (SHANGHAI) CO LTD
- Filing Date
- 2022-11-09
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
In existing technologies, when the acceleration structure of ray tracing algorithms is stored in GPU memory, compact storage causes the access address to be no multiple of the read/write unit, resulting in read errors and repeated reads, which affects GPU performance.
Method used
Align the nodes of the accelerated structure with the preset byte units, and pad the end of the access address with non-address data to make the access address a multiple of the byte units of the reading device, and use compile-time constants for reading.
Benefits of technology
This improves the accuracy and efficiency of the reading device for accelerating structures, reduces reading errors and duplicate reads, and enhances the performance of the reading device.
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Abstract
本申请提供一种加速结构的存储和读取方法、存储装置及图形处理器，涉及图形处理领域。加速结构的存储方法包括：获取预设加速结构，所述预设加速结构包括多个结点；将所有所述结点分别与预设字节单位对齐，得到对齐后的加速结构，所述预设字节单位为读取设备对数据进行读取的字节单位，所述对齐用于使所述结点的访问地址为所述预设字节单位的倍数；将所述对齐后的加速结构存入所述读取设备。通过对加速结构的结点与预设字节单位进行对齐，可以使得读取设备能够准确地对加速结构进行读取，提高读取设备的读取效率。
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