SRAM with fast controllable peak current, high energy efficient array reset and data destroy mode for safety applications

Abstract

The present disclosure relates to SRAM with fast controllable peak current, high energy efficient array reset, and data destruction mode for safety applications. A method of destroying contents of a memory array includes asserting a signal at a reset node, thereby causing an undercurrent to a memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array containing storage cells whose contents are to be destroyed. For each desired column, logic states of its bit lines and complementary bit lines are forced to the same logic state. Each word line associated with a desired row of the memory array containing storage cells whose contents are to be destroyed is simultaneously asserted and then simultaneously de-asserted, thereby placing each storage cell whose contents are to be destroyed in a metastable state during a single clock cycle.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 221,067, filed July 13, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to the field of static random access memory (SRAM), and more particularly, to techniques for performing fast reset and fast content destruction of SRAM while reducing the power consumption of those processes. Background Technology

[0004] Static Random Access Memory (SRAM) is used in many electronic devices in the modern world. Some applications that use SRAM memory (such as Time-of-Flight (ToF) ranging and LiDAR applications) involve frequent “resets” of the SRAM memory, that is, writing the same logical values ​​(such as a default logical 0, or an alternative logical 1, or a predefined pattern of logical 1 and logical 0 such as a checkerboard pattern) to all the memory cells of at least a portion of the SRAM.

[0005] Now for reference Figure 1A This diagram shows a block diagram of memory circuitry 10 used in HistoRam (a memory used in histogram construction for ranging applications). Circuitry 10 includes an array 12 of memory cells C arranged in rows and columns. The array 12 has a size of m×n, where m is the number of columns and n is the number of rows. The memory cells in each row are controlled by word lines 14[0],...,14[n-1]. The memory cells in each column are connected to bit line / complementary bit line pairs 16[0],...,16[m-1]. Row decoder circuitry 18b receives a row address pre-decoded from the address and decodes the bits of the row address to select and actuate one of the word lines 14[0],...,14[n-1]. Column decoder circuitry 18a receives a column address pre-decoded from the address and decodes the bits of the column address to select multiple bit lines 16[0],...,16[m-1]. In read mode, data stored in the memory cell located at the intersection of one of the word lines 14[0],...,14[n-1] selected from the address and multiple bit lines 16[0],...,16[m-1] is read onto data input / output line 20. In write mode, data on data input / output line 20 is written to the memory cell located at the intersection of one of the word lines 14[0],...,14[n-1] selected from the address and multiple bit lines 16[0],...,16[m-1].

[0006] Since this disclosure focuses on write operations, the write operation will be discussed in more detail. Specifically, it should be noted that at the end of each memory access operation, the precharge circuit 24 precharges bit line pairs 16[0],...,16[m-1] to the voltage representing logic 1. Therefore, at the start of a write operation, the selected bit line pairs 16[0],...,16[m-1] have been precharged. Therefore, the precharge voltage applied to the selected bit line pairs 16[0],...,16[m-1] by the precharge circuit 24 is released, thereby allowing the selected bit line pairs 16[0],...,16[m-1] to float. Then, the selected word lines 14[0],...,14[n-1] are selected by the row decoder circuit 18b, which asserts the associated word lines 14[0],...,14[n-1], and the write driver 22 forces the selected memory cell to the desired logic value. In order to complete the write operation, the word line is deselected and the precharge of the selected bit line pair 16[0],...,16[m-1] is restored, thereby preparing the associated memory cell for the next memory access operation (whether it is a write operation or a read operation).

[0007] Typically, the memory cells of array 12 select one word at a time for a write operation. Typically, to reset some or all of the memory cells of array 12, a write operation is performed on each selected word to write logic zeros into, for example, the memory cell of that word. Typically, one clock cycle is used for each write operation to be performed. Therefore, the number of clock cycles used to reset a given number of words is equal to the given number of words (e.g., if ten words are to be reset, ten clock cycles are used to write logic zeros into the memory cell of each word). While the write cycle time of modern SRAM memories is relatively short, for some applications (such as ToF and LiDAR), it is necessary to reset large blocks of SRAM as quickly as possible, and even modern SRAM memories cannot perform this operation quickly on demand due to the potentially large number of clock cycles involved.

[0008] Furthermore, it should be noted that each write operation performed (and one per word to be reset) involves charging / discharging the bit lines in the bit line pair, followed by precharging of the bit line pair, thus consuming power per memory cell for each word to be reset. Furthermore, as in Figure 1A As can be observed, there is typically a separate reset data input “D” in HistoRam (or a regular SRAM with an existing D input), which allows the selected reset value (logic 0 or logic 1) to be directly read and written to the word to be reset, resulting in area consumption of the reset data input and associated wiring.

[0009] It is desirable to be able to reset multiple words of memory cell array 12 in a single clock cycle. For example, it might be desirable to be able to reset multiple words within a single column of memory cell array 12 in a single clock cycle. Unfortunately, this is not possible in existing designs.

[0010] For example, part of a storage cell row in array 12 is Figure 1B This is shown in the diagram. This is row 0 of array 12, and bit line BL[0] and complementary bit line BLN[0] are shown here. Row 0 is shown as containing two memory cells C[0,0] and C[0,1].

[0011] The memory cell C[0,0] is a standard six-transistor memory cell known to those skilled in the art, formed by cross-coupled CMOS inverter pairs. The first inverter is formed by PMOS transistor MP1 and NMOS transistor MN1, and the second inverter is formed by PMOS transistor MP2 and NMOS transistor MN2. The output of the first inverter is at node BLTI[0,0], and the input of the first inverter is at node BLFI[0,0]; the output of the second inverter is at node BLFI[0,0], and the input of the second inverter is at node BLTI[0,0]. The transmission gate NMOS transistor MN3 connects the output of the first inverter to bit line BL[0], and the transmission gate NMOS transistor MN4 connects the output of the second inverter to the complementary bit line BLN[0].

[0012] Memory cell C[0,1] is a standard six-transistor memory cell known to those skilled in the art, formed by cross-coupled CMOS inverter pairs. The first inverter is formed by a PMOS transistor MP5 and an NMOS transistor MN9, and the second inverter is formed by a PMOS transistor MP6 and an NMOS transistor MN10 pair. The output of the first inverter is at node BLTI[0,1], and the input of the first inverter is at node BLFI[0,1]. The output of the second inverter is at node BLFI[0,1], and the input of the second inverter is at node BLTI[0,1]. A transmission gate NMOS transistor MN11 connects the output of the first inverter to bit line BL[0], and a transmission gate NMOS transistor MN12 connects the output of the second inverter to the complementary bit line BLN[0].

[0013] In this example, assuming cell C[0,0] is storing a logic 1, node BLTI[0,0] will be logic high, and node BLFI[0,0] will be logic low. To write a logic 0 to cell C[0,0] when word line 14[0] is active, write driver 22 must draw sufficient current from node BLTI[0,0] to pull node BLTI[0,0] low. Pulling node BLTI[0,0] low turns on transistor MP2 and turns off transistor MN2, causing node BLFI[0,0] to change its state to logic high. This then causes transistor MP1 to turn off and transistor MN1 to turn on, keeping BLTI[0,0] at logic 0, allowing word line 14[0] to be deasserted to complete the write operation to cell C[0,0]. To draw sufficient current from node BLTI[0,0] to pull it low, write driver 22 must be able to overcome current sourced to node VDD.

[0014] When the memory cell C[0,0] is reset, the write driver 22 has sufficient current draw capability to overcome the current from VDD (e.g., the write driver 22 can draw more current than from VDD).

[0015] However, resetting memory cells C[0,0] and C[0,1] in a single clock cycle (assuming both cells store logic 1) requires word lines 14[0] and 14[1] to be active simultaneously, and also requires the write driver 22 to draw sufficient current from both nodes BLTI[0,0] and BLTI[0,1] simultaneously to pull these nodes low. Therefore, as the number of memory cells to be reset simultaneously in a single column increases, the current draw requirement on the write driver 22 increases, and the write driver 22 may not have this capability.

[0016] Therefore, there is a need to further develop circuits and techniques for operating the circuits to provide fast, low-power memory reset.

[0017] Furthermore, in certain situations, such as detecting unauthorized access attempts to the memory, it may be desirable for the memory contents to be rapidly corrupted and thus rendered useless in the event of such access. However, for the same reason that resetting multiple memory cells in a single column imposes a higher current draw requirement on the write driver 22, known operations for intentionally corrupting multiple memory cells within a single column also impose a higher current draw requirement on the write driver 22, and the write driver 22 may not possess this capability. Therefore, further development of circuitry and techniques for operating the memory to provide fast, low-power, and robust memory corruption operations is needed. Summary of the Invention

[0018] This paper discloses a method for corrupting the contents of a memory array, the method comprising: a) activating a signal at a reset node to cause insufficient current supply to the memory array; b) selecting a bit line and a complementary bit line associated with a desired row of the memory array containing the memory cells whose contents are to be corrupted; c) forcing the logic states of the bit lines and complementary bit lines to the same logic state for each desired column; and d) activating each word line associated with the desired row of the memory array containing the memory cells whose contents are to be corrupted simultaneously, and then deactivating these word lines simultaneously, thereby placing each memory cell whose contents are to be corrupted into a metastable state during a single clock cycle.

[0019] The method may further include: generating a virtual power supply voltage from the power supply voltage by coupling a power supply voltage node to a virtual power supply voltage node using multiple transistors, thereby generating a virtual power supply voltage at the virtual power supply voltage node; and using the virtual power supply voltage to power the memory array. By turning off one of the multiple transistors used to couple the power supply voltage node to the virtual power supply voltage node, a signal can be activated at the reset node, resulting in insufficient current supply to the memory array.

[0020] One of the transistors that is turned off to insufficiently supply current to the memory array can be the largest transistor among the multiple transistors.

[0021] It can be expected that all memory cells in the memory array will have their contents corrupted. B) This can include selecting all bit lines and all complementary bit lines. C) This can include, for each column, forcing the logic states of its bit lines and complementary bit lines to the same logic state. D) This can include making each word line active simultaneously, and then making each word line inactive simultaneously.

[0022] C) may include, for each column, forcing the logic state of its bit lines and complementary bit lines to logic 0.

[0023] C) may include, for each column, forcing the logic state of its bit lines and complementary bit lines to logic 1.

[0024] It can be expected that less than the contents of all memory cells in the memory array will cause its contents to be corrupted.

[0025] Fewer than all columns may contain storage units that are expected to corrupt their contents.

[0026] Fewer than all rows can contain storage units that are expected to corrupt their contents.

[0027] B), C), and D) can be executed in response to an internal clock pulse; invalidation of a word line is executed at the end of an internal clock pulse.

[0028] The present invention also discloses a static random access memory (SRAM) device, comprising: a virtual power supply circuit configured to generate a virtual power supply voltage; a memory array powered between the virtual power supply voltage and a reference voltage, the memory array comprising memory cells and organized into rows and columns, wherein each row has an associated word line and each column has an associated bit line and a complementary bit line; a row decoder configured to selectively activate the word lines of a desired row; and a column decoder configured to select a desired column; wherein the virtual power supply circuit is configured to respond to an internal clock signal pulse. The current output is reduced to underpower the memory array; and the column drive circuit is configured to drive the bit lines and complementary bit lines of the desired column to the same logic state in response to the activation of the clock pulse and the latched reset signal; wherein the row decoder activates the word lines of each desired row simultaneously in response to the clock pulse and the latched reset signal; and wherein the row decoder deactivates the word lines of each desired row simultaneously in response to the end of the internal clock pulse, thereby placing the memory cells belonging to the desired row and the desired column in a metastable state.

[0029] The virtual power supply circuit may include: at least one first transistor coupled to a power supply voltage and configured to output a virtual power supply voltage when turned on; and at least one second transistor coupled to a power supply voltage and configured to facilitate the output of a virtual power supply voltage when turned on; wherein the at least one second transistor is configured to turn off in response to receiving an internal clock signal pulse, thereby reducing the current output from the virtual power supply circuit to the memory array.

[0030] At least one second transistor can be larger than at least one first transistor.

[0031] The desired number of rows can be less than all rows.

[0032] The desired number of columns can be fewer than all columns.

[0033] The column drive circuit may include: an inverter associated with each different bit line, the output of which is coupled to the bit line; and multiplexing circuitry. The multiplexing circuit may have: different first multiplexers, each associated with a different bit line; and different second multiplexers, each associated with a different complementary bit line; wherein each first multiplexer has a first data input coupled to a latched reset signal, a second data input coupled to a column decoder, a selection input coupled to the latched reset signal, and a clock input coupled to receive an internal clock signal pulse; wherein each second multiplexer has a first data input coupled to the complement of the latched reset signal, a second data input coupled to a column decoder, a selection input coupled to the latched reset signal, and a clock input coupled to receive an internal clock signal pulse; and wherein, in response to the activation of the clocked internal clock signal pulse and the latched reset signal, each first multiplexer and each second multiplexer of each selected column passes its first data input as an output, thereby driving the bit lines and complementary bit lines of the desired column to the same logic state.

[0034] This document also discloses a method for resetting the contents of a memory array, comprising: a) activating a signal at a reset node to cause insufficient current supply to the memory array; b) selecting bit lines and complementary bit lines associated with a desired column of the memory array containing memory cells whose contents are to be corrupted; c) forcing the logic states of the bit lines and complementary bit lines of each desired column to relative logic states; and d) activating each word line associated with a desired row of the memory array containing memory cells whose contents are to be reset simultaneously, and then deactivating these word lines simultaneously, thereby setting the contents of the memory cells whose contents are to be reset to a desired logic value, the desired logic value depending on the relative logic states of their bit lines and their complementary bit lines.

[0035] The method may further include: generating a virtual power supply voltage from the power supply voltage by coupling a power supply voltage node to a virtual power supply voltage node using multiple transistors, thereby generating a virtual power supply voltage at the virtual power supply voltage node; and using the virtual power supply voltage to power the memory array. Enabling a signal at the reset node by turning off one of the multiple transistors used to couple the power supply voltage node to the virtual power supply voltage node can result in insufficient current supply to the memory array.

[0036] One of the transistors that is turned off to insufficiently supply current to the memory array can be the largest transistor among the multiple transistors.

[0037] The relative logical state can be different for different desired columns, so that different desired columns reset their contents to different desired logical values.

[0038] The relative logical state can be used to reset the contents of the desired column to the same desired logical value if the desired column is the same.

[0039] It can be expected that the contents of all memory cells in the memory array will be reset. B) This may include selecting all bit lines and all complementary bit lines. C) This may include, for each column, forcing the logic states of its bit lines and complementary bit lines to relative logic states. D) This may include making each word line active simultaneously, and then making each word line inactive simultaneously.

[0040] C) may include, for each column, forcing the logic state of its bit lines to logic 0 and the logic state of its complementary bit lines to logic 1.

[0041] C) may include, for each column, forcing the logic state of its bit lines to logic 1 and the logic state of its complementary bit lines to logic 0.

[0042] It may be expected that less than all the contents of the memory array will be reset.

[0043] Fewer than all columns may contain storage units whose contents are expected to be reset.

[0044] Fewer than all rows can contain storage units whose contents are expected to be reset.

[0045] The present invention also discloses a static random access memory (SRAM) device, comprising: a virtual power supply circuit configured to generate a virtual power supply voltage; a memory array powered between the virtual power supply voltage and a reference voltage, the memory array comprising memory cells and organized into rows and columns, wherein each row has an associated word line and each column has an associated bit line and a complementary bit line; a row decoder configured to selectively activate the word lines of a desired row; and a column decoder configured to select a desired column; wherein the virtual power supply circuit is configured to respond to an internal clock. The signal pulse reduces its current output to cause insufficient power supply to the memory array; and the column drive circuit is configured to drive the bit lines and complementary bit lines of the desired column to a relative logic state in response to the activation of the clock pulse controlled by the internal clock signal and the latched reset signal; wherein in response to the clock pulse controlled by the internal clock signal and based on the latched reset signal, the row decoder activates the word lines of each desired row simultaneously; and wherein in response to the end of the internal clock signal pulse, the row decoder deactivates the word lines of each desired row simultaneously, thereby resetting the memory cells belonging to the desired row and the desired column.

[0046] The virtual power supply circuit may include: at least one first transistor coupled to a power supply voltage and configured to output a virtual power supply voltage when turned on; and at least one second transistor coupled to a power supply voltage and configured to facilitate the output of the virtual power supply voltage when turned on. The at least one second transistor may be configured to turn off in response to receiving an internal clock signal pulse, thereby reducing the current output from the virtual power supply circuit to the memory array.

[0047] At least one second transistor can be larger than at least one first transistor.

[0048] The desired number of rows can be less than all rows.

[0049] The desired number of columns can be fewer than all columns.

[0050] The column drive circuit may include: an inverter associated with each different bit line, the output of which is coupled to the bit line; and multiplexing circuitry. The multiplexing circuit may have: different first multiplexers, each associated with a different bit line; and different second multiplexers, each associated with a different complementary bit line; wherein each first multiplexer has a first data input coupled to a latched reset signal, a second data input coupled to a column decoder, a selection input coupled to a latched reset signal, and a clock input coupled to receive an internal clock signal pulse; wherein each second multiplexer has a first data input coupled to a latched reset signal, a second data input coupled to a column decoder, a selection input coupled to a latched reset signal, and a clock input coupled to receive an internal clock signal pulse; and wherein, in response to the activation of the clocked internal clock signal pulse and the latched reset signal, each first multiplexer and each second multiplexer of each selected column passes its first data input as an output, thereby driving the bit line and complementary bit line of the desired column to the corresponding logic state. Attached Figure Description

[0051] Figure 1A This is a block diagram of a conventional SRAM device.

[0052] Figure 1B yes Figure 1A A schematic diagram of a single column of a conventional SRAM device.

[0053] Figure 2 This is a schematic block diagram of the SRAM device disclosed herein, which is capable of simultaneously and quickly resetting all rows and all columns of the memory cell to 0 values ​​with low power consumption, and has the ability to limit the current drawn during the reset operation.

[0054] Figure 3 yes Figure 2Timing diagram of an SRAM device when all rows and all columns of a memory cell are reset to the default value of 0.

[0055] Figure 4 This is a schematic block diagram of the SRAM device disclosed herein, which is capable of simultaneously and quickly resetting all rows and all columns of the memory cell to a value of 1 with low power consumption, and has the ability to limit the current drawn during the reset operation.

[0056] Figure 5 yes Figure 4 Timing diagram of an SRAM device when resetting all rows and all columns of a memory cell to the default logic 1.

[0057] Figure 6 This is a schematic block diagram of the SRAM device disclosed herein, which is capable of performing fast corruption of the data stored in all rows and all columns of the memory cell, and has the ability to limit the current drawn during the data corruption operation.

[0058] Figure 7 yes Figure 6 Timing diagram of an SRAM device when the contents of all memory cells of the SRAM device are destroyed simultaneously. Detailed Implementation

[0059] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to embodiments and applications other than those detailed above, without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

[0060] A. Quickly reset the memory cell to logic 0.

[0061] Now, let's refer to... Figure 2 The description pertains to an SRAM device 30, on which a fast memory reset can be performed simultaneously on all memory cells, or simultaneously on all desired rows and desired columns of the memory cells, while limiting the power drawn during the reset to avoid errors caused by a drop in the supply voltage. Such errors may include data loss due to the memory cells not being reset, failure of other components of the SRAM device 30, etc.

[0062] SRAM device 30 includes a power supply voltage generation circuit 35, which generates a virtual power supply voltage from the main power supply voltage node VDD at the virtual power supply voltage node VDDMA, and limits the current supplied to the virtual power supply voltage node VDDMA when the complement of the internal clock signal CKINT, CKINT_B, is active.

[0063] As shown in the figure, the power supply voltage generation circuit 35 includes PMOS transistors P1 and P2, both of which are coupled between the main power supply voltage VDD and the virtual power supply voltage node VDDMA. PMOS transistor P1 can be larger than transistor P2 and can provide a larger amount of current. The gate of PMOS transistor P2 is grounded, so that PMOS transistor P2 is always on when SRAM device 30 is on. The gate of PMOS transistor P1 is configured to receive the complement of the internal clock signal CKINT_B, so that PMOS transistor P1 is on when CKINT_B is not asserted. However, when CKINT_B is asserted, PMOS transistor P1 is off, thereby halving (or more than halving) the total current that can be supplied to the virtual power supply voltage node VDDMA, which has the effect of insufficient power supply to the cells of the memory array 12 that have changed state (i.e., been reset).

[0064] Note that in the example shown, there is one power supply voltage generation circuit 35 for memory array 12. However, in some cases, there may be one power supply voltage generation circuit 35 for each column (where each power supply voltage generation circuit is described above and generates a virtual power supply voltage node VDMA for its corresponding column), or there may be one power supply voltage generation circuit 35 for each block or subarray of array 12. In some cases, even each memory cell may have one power supply voltage generation circuit 35.

[0065] Turning now to other details of the SRAM device 30, which includes a memory array 12. The memory array 12 has a size of m×n, where m is the number of columns and n is the number of rows. At each intersection of a column and a row, there is a memory cell.

[0066] For example, memory cell C[0,0] located at the intersection of bit line 0 and word line 0 in memory array 12 is composed of cross-coupled inverters (the first inverter is a CMOS inverter formed by PMOS MP1 and NMOS MN1, and the second inverter is a CMOS inverter formed by PMOS MP2 and NMOS MN2), wherein the transmission gate NMOS MN3 is coupled between node BLTI[0,0] at the drain of MP1 and MN1 and bit line BL[0], and the transmission gate NMOS MN4 is coupled between node BLFI[0,0] at the drain of MP2 and MN2 and complementary bit line BLN[0]. This memory cell C[0,0] is powered between the virtual power supply voltage node VDDMA and ground GND.

[0067] Similarly, the memory cell C[m-1,0] located at the intersection of the (m-1)th bit line pair and the 0th word line in memory array 12 is composed of cross-coupled inverters (the first inverter is a CMOS inverter formed by PMOS MP3 and NMOS MN5, and the second inverter is a CMOS inverter formed by PMOS MP4 and NMOS MN6), wherein the transmission gate NMOS MN7 is coupled between the node BLTI[m-1,0] at the drain of MP3 and MN5 and the bit line BL[m-1], and the transmission gate NMOS MN8 is coupled between the node BLFI[m-1,0] at the drain of MP2 and MN2 and the complementary bit line BLN[m-1]. This memory cell C[m-1,0] is powered between the virtual power supply voltage node VDDMA and ground GND.

[0068] The memory cell C[0,n-1] located at the intersection of the 0th bit line pair and the (n-1)th word line in memory array 12 is composed of cross-coupled inverters (the first inverter is a CMOS inverter formed by PMOS MP5 and NMOS MN9, and the second inverter is a CMOS inverter formed by PMOS MP6 and NMOS MN10). The transmission gate NMOS MN11 is coupled between the node BLTI[0,n-1] at the drain of MP5 and MN9 and the bit line BL[0], and the transmission gate NMOS MN12 is coupled between the node BLFI[0,n-1] at the drain of MP6 and MN10 and the complementary bit line BLN[0]. This memory cell C[0,n-1] is powered between the virtual power supply voltage node VDDMA and ground GND.

[0069] The memory cell C[m-1, n-1] located at the intersection of the (m-1)th bit line pair and the (n-1)th word line in memory array 12 is composed of cross-coupled inverters (the first inverter is a CMOS inverter formed by PMOS MP7 and NMOS MN13, and the second inverter is a CMOS inverter formed by PMOS MP8 and NMOS MN14). The transmission gate NMOS MN15 is coupled between node BLTI[m-1, n-1] at the drain of MP7 and MN13 and bit line BL[m-1], and the transmission gate NMOS MN16 is coupled between node BLFI[m-1, n-1] at the drain of MP8 and MN14 and complementary bit line BLN[m-1]. This memory cell C[m-1, n-1] is powered between the virtual power supply voltage node VDDMA and ground GND.

[0070] The storage units in each row are controlled by word lines among word lines WL[0],...,WL[n-1]. The selection of one or more rows is accomplished by a row decoder 18b that enables one or more associated word lines among word lines WL[0],...,WL[n-1]. The selection of one or more columns is accomplished by performing the selection by a column decoder 18a.

[0071] The precharge circuit 24 is coupled to each bit line and complementary bit line pair BL[0], BLN[0], ..., BL[m-1], BLN[m-1], and is controlled by the precharge control signal PCH.

[0072] The write driver circuit 22 is coupled between the multiplexing circuit 21 and the precharge circuit 24. The write driver circuit 22 includes an inverter for each bit line BL[0],...,BL[m-1], which has an input coupled to the multiplexing circuit 21 and an output associated with the precharge circuit 24.

[0073] Multiplexing circuit 21 includes a multiplexer (MUX) for each bit line BL[0],...,BL[m-1] and complementary bit line BLN[0],...,BLN[m-1]. The multiplexer (MUX) has a first data input coupled to column decoder 18a, a second data input coupled to a latched version of the reset signal RST, RST_Lat, a selection input coupled to RST_Lat (determining which data input is passed as the output), and a clock input coupled to receive the internal clock signal CKINT. Note that RST_Lat is provided as an input to column decoder 18a to allow selection of the desired column, and RST_Lat is coupled to precharge circuit 24 such that activation of RST_Lat deactivates precharge circuit 24. Also note that RST_Lat is provided as an input to row decoder 18b and is used to allow selection of all rows, or the desired row within a row.

[0074] Now, additional references Figure 3 The operation is described below. To perform a reset of SRAM array 30, as shown at time t0, the reset signal RST (which can be received via pads or pins) is activated. This reset signal RST is latched until time t1 to generate a latched version of the reset signal RST, RST_LAT. At time t2, the internal clock signal CKINT, generated based on the external clock signal CLK, falls to logic low. CKINT falling to logic low means its complement CKINT_B rises to logic high, thereby turning off transistor P1 and limiting the current supply to memory array 12 to the current that can only be provided by transistor P2, thus effectively underpowering the inverters of the cells of the memory array coupled to the virtual power supply voltage node VDDMA.

[0075] This insufficient current operation is crucial for enabling the simultaneous reset (e.g., reset to logic 0) of all desired rows and columns of memory array 12.

[0076] For example, suppose that all memory cells in the desired column of the memory array 12 to be reset store logic 1 and will be reset to logic 0.

[0077] For example, referring to cell C[0,0] of memory array 12, and assuming that cell C[0,0] is storing logic 1, node BLTI[0,0] (the output of the inverter formed by transistors MP1 and MN1) will be logic high, and node BLFI[0,0] (the output of the inverter formed by transistors MP2 and MN2) will be logic low. In order to write logic 0 to cell C[0,0] when word line WL[0] is active, the write driver for bit line BL[0] (e.g., the inverter shown) must draw sufficient current from node BLTI[0,0] to pull node BLTI[0,0] low. Node BLTI[0,0] is pulled low, turning on transistor MP2 and turning off transistor MN2. This causes node BLFI[0,0] to change its state to logic high, which in turn turns off transistor MP1 and turns on transistor MN1, thus holding BLTI[0,0] at logic 0. This allows word line WL[0] to be invalidated to complete the write operation to memory cell C[0,0]. To draw sufficient current from node BLTI[0,0] to pull it low, the write driver for bit line BL[0] must be able to overcome the current originating from node VDDMA.

[0078] When a row is reset, the write driver for bit line BL[0] has sufficient current draw capability to overcome the current from VDDMA (e.g., the write driver can draw more current than the current from VDDMA). However, consider now the case of resetting two rows of memory array 12.

[0079] For this example, suppose we want to reset column 0, and suppose column 0 contains memory cells C[0,0] and C[0,n-1] as shown in the figure, and suppose that both memory cells C[0,0] and C[0,n-1] are storing logic 1 - nodes BLTI[0,0] and BLTI[0,n-1] are logic high, and nodes BLFI[0,0] and BLFI[0,n-1] are logic low. To reset memory cells C[0,0] and C[0,n-1] to logic 0 simultaneously, word lines WL[0] and WL[n-1] are activated simultaneously. The write driver for bit line BL[0] must be able to draw sufficient current from both nodes BLTI[0,0] and BLTI[0,n-1] simultaneously to pull these nodes low - the current draw requirement applied to the write driver for bit line BL[0] is doubled.

[0080] Therefore, it is clear that as the number of rows to be reset simultaneously increases, the current draw requirement applied to the write driver also increases accordingly. For this reason, existing devices cannot reset a large number of memory cell rows simultaneously.

[0081] However, to enable the SRAM device 30 to reset a large number of rows, or even all rows of the memory array 12, a power supply voltage generation circuit 35 is employed. When CKINT drops to logic low at time t2, transistor P1 is turned off, making transistor P2 the sole current provider for the virtual power supply voltage node VDDMA. Therefore, this reduces the total current from the virtual power supply voltage node VDDMA, reducing the current draw requirement on the write driver to reset a given number of memory cells.

[0082] Also at time t2, the precharge is released as CKINT drops to logic low, and the multiplexer of multiplexing circuit 21 is clocked. As a result of the clocking of the multiplexer, the multiplexer selects which data input is passed to its output based on the signal at its selected input. The multiplexer is arranged such that RST_Lat, which is at logic high, selects the data input of the multiplexer coupled to RST_Lat. Therefore, by time t3, the precharge is turned off, and the multiplexer outputs logic high (because RST_Lat is high). Since the inverter is coupled to the multiplexer and associated with the precharge circuit 24 of bit lines BL[0],...,BL[m-1], this causes the signal D_int on bit lines BL[0],...,BL[m-1] to be forced to drop to logic low by time t3, which in turn causes bit lines BL[0],...,BL[m-1] to drop to logic low. Due to the lack of an inverter coupled to the multiplexer and associated with the precharge circuit 24 of bit lines BL[0],...,BL[m-1], the signal D_int_B rises to logic high at time t3, thereby keeping the complementary bit lines BLN[0],...,BLN[m-1] at logic high.

[0083] As CKINT drops to logic low, all word lines WL[0],...,WL[n-1] are activated, thus turning on the transmission gate transistors in each bit cell (e.g., for the bit cells shown in the diagram, MN3, MN4 in C[0,0]; MN7, MN8 in C[m-1,0]; M11, M12 in C[0,n-1]; and M15, M16 in C[m-1,n-1]). Since bit lines BL[0],...,BL[m-1] are at logic low and complementary bit lines BLN[0],...,BLN[m-1] are at logic high, the activated word lines WL[0],...,WL[n-1] cause logic 0 to be written to the bit cell. Therefore, by time t4, nodes BLTI[0,0],...,BLTI[m-1,n-1] drop to logic zero because transistor P1 of the power supply voltage generation circuit 35 is turned off when CKINT goes low, the current draw requirement applied to the write driver 22 decreases, and the write driver 22 is able to draw enough current to overcome the current supplied by transistor P2 to the virtual power supply voltage node VDDMA, thereby quickly pulling BLTI[0,0],...,BLTI[m-1,n-1] low.

[0084] However, it should be noted that, as Figure 3 As shown, the voltage at nodes BLFI[0,0],...,BLFI[m-1,n-1] rises slowly, and by time t5, the voltage reaches only about half of its logic high value. This is because transistor P1 is off, resulting in insufficient current; to charge nodes BLFI[0,0],...,BLFI[m-1,n-1], current is drawn from the virtual power supply voltage node VDDMA, and due to the off state of transistor P1, even less current can be drawn.

[0085] At time t5, the internal clock signal CKINT rises back to logic high, meaning that CKINT_B falls to logic low and transistor P1 is turned on again. Therefore, it should be noted that starting from time t5, nodes BLFI[0,0],...,BLFI[m-1,n-1] are rapidly charged to logic high; this is because starting from t5, more current can be drawn from the virtual power supply voltage node VDDMA.

[0086] As previously stated, at time t5, the internal clock signal CKINT rises back to logic high, releasing the latch of RST, thus causing RST_Lat to fall low. By time t6, all bit cells remain at logic 0, nodes BLTI[0,0],...,BLTI[m-1,n-1] are at logic low, and nodes BLFI[0,0],....,BLFI[m-1,n-1] are at logic high. Word lines WL[0],...,WL[n-1] are released and fall low, and simultaneously, precharge is restored, causing bit lines BL[0],...,BL[m-1] to rise back to logic high. Furthermore, D_int rises back high, and D_int_B falls low.

[0087] Please note that, unlike traditional SRAM where each word in each row is written in one cycle (i.e., clock cycle), only one write cycle is performed in order to reset all columns of row 0,...,n-1.

[0088] Naturally, the above technique can be extended to any number of rows, and therefore, in a memory array 12 of size m×n, all m columns of all n rows can be reset simultaneously, or all m columns of any number of rows can be reset simultaneously, or any number of columns of any number of rows can be reset simultaneously.

[0089] Reference Figure 3 In the example described above, all rows and all columns of memory array 12 are reset to 0. However, all rows and fewer than all columns can be reset, all columns and fewer than all rows can be reset, and fewer than all rows and fewer than all columns can be reset. This is controlled by the RST_Lat signal, which can be observed as being provided as input to both column decoder 18a and row decoder 18b. To achieve this, only the word lines that are expected to be reset are active (as described above, simultaneously), and only the columns that are expected to be reset are selected. For example, column decoder 18a and row decoder 18b may include circuitry that selects certain desired columns and certain desired rows when the active RST_Lat signal is received.

[0090] B. Memory cell is quickly reset to logic 1.

[0091] In the example above, the desired rows and columns of memory array 12 are reset to 0. However, in some applications, the desired rows and columns of memory array 12 can be reset to 1 instead.

[0092] Such an embodiment is in Figure 4 It is shown in the figure and will now be described. Figure 4 SRAM device 30' relative to Figure 2 The difference between the SRAM device 30 and the SRAM device 30 is that, Figure 4 In the SRAM device 30', the data input of the multiplexer MUX in the multiplexing circuit 21' is coupled to the complement of RST_Lat, instead of RST_Lat. This means that, now referring to Figure 5 When the multiplexer is clocked by CKINT, D_int rises to logic high and D_int_B falls to logic low at time t3. This means that the complementary bit lines BLN[0],...,BLN[m-1] fall to logic low, while the bit lines BL[0],...,BL[m-1] remain at logic high.

[0093] Since bit lines BL[0], ..., BL[m-1] are at logic high and complementary bit lines BLN[0], ..., BLN[m-1] are at logic low, when word lines WL[0], ..., WL[n-1] are activated, nodes BLFI[0,0], ..., BLFI[m-1,n-1] drop to logic low. This is because when CKINT goes low, transistor P1 of the power supply voltage generation circuit 35 is turned off, so the current draw requirement applied to the write driver 22 is reduced, and the write driver 22 is able to draw enough current to overcome the current supplied to the virtual power supply voltage node VDDMA through transistor P2, thereby quickly pulling BLFI[0,0], ..., BLFI[m-1,n-1] to logic low.

[0094] However, it should be noted that, as Figure 5 As shown, the voltage at nodes BLTI[0,0],...,BLTI[m-1,n-1] rises slowly, and by time t5, the voltage reaches only about half of the logic high value. This is because transistor P1 is off, resulting in insufficient current; to charge nodes BLTI[0,0],...,BLTI[m-1,n-1], current is drawn from the virtual power supply voltage node VDDMA, and because transistor P1 is off, less current can be drawn.

[0095] At time t5, the internal clock signal CKINT rises back to logic high, meaning that CKINT_B falls to logic low and transistor P1 is turned on again. Therefore, it should be noted that starting from time t5, nodes BLTI[0,0],...,BLTI[m-1,n-1] are rapidly charged to logic high; this is because starting from t5, more current can be drawn from the virtual power supply voltage node VDDMA.

[0096] As previously stated, at time t5, the internal clock signal CKINT rises back to logic high, which releases the latch of RST, causing RST_Lat to fall low. By time t6, all bit cells remain at logic 1, nodes BLFI[0,0],...,BLFI[m-1,n-1] are at logic low, and nodes BLTI[0,0],...,BLFI[m-1,n-1] are at logic high. Word lines WL[0],...,WL[n-1] are released and fall low, and simultaneously, the precharge is restored, causing the complementary bit lines BLN[0],...,BLN[m-1] to rise back to logic high. Furthermore, D_int rises back high, while D_int_B falls low.

[0097] In the example above, the desired rows and columns of memory array 12 are reset to 1. However, in some applications, it may be desirable for the desired rows and columns of memory array 12 to be reset to a pattern. For example, a desired column may be reset to 0, while a desired column may be reset to 1. The variation here refers to columns that are desired to be reset to 1, and the multiplexers associated with the bit lines and complementary bit lines of these columns have... Figure 4 The arrangement shown, however, for columns expected to be reset to 0, has multiplexers associated with those bit lines and complementary bit lines that have Figure 2 The layout shown.

[0098] C. Rapid corruption of memory cells

[0099] Unauthorized attempts to access the contents of memory array 12 can be detected, and it may be expected that some or all of the contents of memory array 12 will be corrupted (i.e., lost, randomized, etc.) so that unauthorized attempts will not retrieve information that has already been stored in memory array 12.

[0100] Now, additional references Figure 6 To describe an example of an SRAM device 30 capable of performing such destruction.

[0101] Figure 6 The SRAM device 30” relative to Figure 2 The difference between the SRAM device 30 and the SRAM device 30 is that, Figure 6 In the SRAM device 30”, the data input of the multiplexer associated with bit lines BL[0],...,BL[m-1] of the multiplexing circuit 21” is coupled to RST_Lat, but the data input of the multiplexer associated with complementary bit lines BLN[0],...,BLN[m-1] of the multiplexing circuit 21” is coupled to the complement of RST_Lat, instead of RST_Lat.

[0102] Now, additional references Figure 7To describe the execution of data corruption.

[0103] This assumes that an unauthorized attempt to access memory array 12 has been detected, and it is desired to corrupt the data stored in all n rows of memory array 12. To perform such data corruption, when the unauthorized attempt is detected, as shown at time t0, the signal RST (from a pin or pad) is activated. This reset signal RST is latched until time t1 to generate a latched version of the reset signal RST, RST_LAT. At time t2, the internal clock signal CKINT, generated based on the external clock signal CLK, falls to logic low. CKINT falling to logic low means that its complement CKINT_B rises to logic high, thereby turning off transistor P1 and limiting the current supply to memory array 12.

[0104] Also at time t2, the precharge is released as CKINT drops to logic low, and the multiplexer of the multiplexing circuit 21” is clocked. As a result of the multiplexer's clocking, the multiplexer selects which data input is passed to its output based on the signal at its selected input. The multiplexers are arranged such that RST_Lat is at logic high, and for those multiplexers associated with bit lines BL[0],...,BL[m-1], those coupled to RST_Lat are selected. The data inputs of the multiplexers are selected, and for those multiplexers associated with complementary bit lines BLN[0],...,BL[m-1], the data inputs of those multiplexers coupled with the two's complement of RST_Lat are chosen. As a result, by time t3, the outputs of the multiplexers associated with bit lines BL[0],...,BL[m-1] have risen to logic high, and the outputs of the multiplexers associated with complementary bit lines BLN[0],...,BLN[m-1] have fallen to logic low.

[0105] Because the inverter is coupled between the multiplexer and the precharge circuit 24 for bit lines BL[0],...,BL[m-1], the signal D_int is forced onto bit lines BL[0],...,BL[m-1], and the signal D_int drops to logic low. Because of the lack of an inverter coupled between the multiplexer and the precharge circuit for complementary bit lines BLN[0],...,BLN[m-1], the signal D_int_B is forced onto complementary bit lines BLN[0],...,BLN[m-1], and the signal D_int_B also drops to logic low.

[0106] Similarly, as CKINT falls to logic low, word lines WL[0],...,WL[n-1] are activated, thereby turning on the transmission gate transistors in each bit cell (e.g., for the bit cells shown, MN3, MN4 in C[0,0]; MN7, MN8 in C[m-1,0]; M11, M12 in C[0,n-1]; and M15, M16 in C[m-1,n-1]). When word lines WL[0],...,WL[n-1] are activated, write driver 22 attempts to pull nodes BLTI[0,0],...,BLTI[m-1,n-1] to logic low.

[0107] In order to pull nodes BLTI[0,0],...,BLTI[m-1,n-1] low, the write driver 22 must have sufficient current draw capability to pull those nodes low simultaneously. In other words, to pull all nodes BLTI[0,0],...,BLTI[m-1,n-1] low simultaneously, the write driver 22 must have sufficient current draw capability to overcome the current sourced from node VDDMA. Here, by utilizing the turn-off of transistor P1, which occurs when the internal clock signal transitions to a low level in the SRAM device 30", the amount of current that can originate from node VDDMA is reduced, thereby reducing the current draw capability of the write driver 22 to pull all nodes BLTI[0,0],...,BLTI[m-1,n-1] low simultaneously. This allows the write driver 22 to pull all nodes BLTI[0,0],...,BLTI[m-1,n-1] low (almost) low, as will be explained below. Therefore, the turn-off of transistor P1 enables the simultaneous destruction of a large number of rows, or even all rows.

[0108] Because the gates of the PMOS transistors whose drains are connected to nodes BLFI[0,0],...,BLFI[m-1,n-1] are connected to nodes BLTI[0,0],...,BLTI[m-1,n-1], current is drawn from nodes BLTI[0,0],...,BLTI[m-1,n-1], resulting in these transistors being turned on, which in turn leads to... Figure 7 As shown, the voltage at nodes BLFI[0,0],...,BLFI[m-1,n-1] rises slightly above ground by time t4. The reason the voltage at nodes BLFI[0,0],...,BLFI[m-1,n-1] rises slightly above ground at this time (instead of rising to logic high) is because the write driver 22 is also attempting to pull nodes BLFI[0,0],...,BLFI[m-1,n-1] low by drawing current from them.

[0109] Also note that the current drawn from nodes BLFI[0,0],...,BLFI[m-1,n-1] causes the gate of the PMOS transistor connected to node BLFI[0,0],...,BLFI[m-1,n-1] to be turned on, and thus... Figure 7 As shown, this results in the voltage at nodes BLTI[0,0],...,BLTI[m-1,n-1] not being fully pulled to ground.

[0110] At time t5, the voltages at the inputs of the inverters for all memory cells C[0,0],...,C[m-1,n-1] are close to (but not at) logic low, and the internal clock signal CKINT rises back to logic high, which releases the latch of RST, so RST_Lat falls low. At time t6, word lines WL[0],...,WL[n-1] are released and fall low, and at the same time, precharge is restored, so bit lines BL[0],...,BL[m-1] rise back to logic high. Additionally, D_int and D_int_B rise back high.

[0111] When word lines WL[0],...,WL[m-1] are released at time t6, memory cells C[0,0],...,C[m-1,n-1] thus enter a metastable state because each memory cell consists of two cross-coupled inverters, and the two cross-coupled inverters cannot both have the same output. This means that one inverter in each metastable memory cell will "win" (i.e., its output will remain unchanged and cause the output of the other inverter to flip), but it is impossible to predict or know which inverter will "win". Therefore, the data state of each affected memory cell becomes randomized, and thus the contents of the corrupted memory cell are randomized, meaning that if an unauthorized attempt continues and succeeds, the data it retrieves will be useless random data.

[0112] Naturally, the above technique can be extended to any number of rows, and therefore, in the case of a memory array 12 of size m×n, all m columns of all n rows can be reset simultaneously.

[0113] Reference Figure 6 In the example described above, all rows and all columns of data in memory array 12 have been corrupted. However, all rows and fewer than all columns of data may have been corrupted, all columns and fewer than all rows of data may have been corrupted, and fewer than all rows and fewer than all columns of data may have been corrupted. This is controlled by the RST_Lat signal, which can be observed as input to both column decoder 18a and row decoder 18b. To achieve this, only word lines containing the data expected to be corrupted are activated (as described above, simultaneously), and only columns containing the data expected to be corrupted are selected.

[0114] Also note that although in the example above, bit lines BL[0],...,BL[m-1] and complementary bit lines BLN[0],...,BL[m-1] are forced to 0 before the desired word lines are activated to perform data corruption, they can alternatively all be forced to 1. As another alternative, the bit lines and complementary bit lines of one column can be forced to 0, while the bit lines and complementary bit lines of another column are forced to 1. In fact, data corruption can be performed on any column where its bit lines and complementary bit lines are forced to the same value before the word lines are activated.

[0115] The above functionality allows for the rapid destruction of desired rows and columns of data within a single write operation (i.e., clock cycle).

[0116] All techniques described in Parts A, B and C of this disclosure above are applicable to both self-timed SRAM memories and non-self-timed SRAM memories.

[0117] Although this disclosure has been described with respect to a limited number of embodiments, those skilled in the art who benefit from this disclosure will understand that other embodiments can be conceived without departing from the scope of this disclosure. Therefore, the scope of this disclosure should be limited only by the appended claims.

Claims

1. A method for corrupting the contents of a memory array, comprising: a) Enabling a signal at the reset node, resulting in insufficient current supply to the memory array; b) Select the bit lines and complementary bit lines associated with the desired column of the memory array containing the memory cells whose contents are to be corrupted; c) For each desired column, force the logic states of its bit lines and complementary bit lines to the same logic state; as well as d) Energize each word line associated with the desired row of the memory array containing the memory cell whose contents are to be corrupted simultaneously, and then deactivate these word lines simultaneously, thereby placing each memory cell whose contents are to be corrupted into a metastable state during a single clock cycle.

2. The method according to claim 1, further comprising: A virtual power supply voltage is generated from the power supply voltage by coupling a power supply voltage node to a virtual power supply voltage node using multiple transistors, thereby generating the virtual power supply voltage at the virtual power supply voltage node; as well as The virtual power supply voltage is used to power the memory array; The signal is activated at the reset node by turning off one of the plurality of transistors that couples the power supply voltage node to the virtual power supply voltage node, resulting in insufficient current supply to the memory array.

3. The method of claim 2, wherein the one transistor among the plurality of transistors that is turned off to insufficiently supply current to the memory array is the largest transistor among the plurality of transistors.

4. The method according to claim 1, It is desired that all storage cells of the memory array have their contents destroyed. b) includes selecting all bit lines and all complementary bit lines. c) includes, for each column, forcing the logic states of its bit lines and complementary bit lines to the same logic state; and Wherein d) includes making each word line active at the same time, and then making each word line inactive at the same time.

5. The method of claim 4, wherein c) comprises, for each column, forcing the logic state of its bit lines and complementary bit lines to a given logic state.

6. The method of claim 1, wherein fewer than all columns contain storage cells intended to corrupt their contents, or fewer than all rows contain storage cells intended to corrupt their contents.

7. The method of claim 1, wherein b), c) and d) are executed in response to an internal clock pulse, wherein the invalidation of the word line is executed at the end of the internal clock pulse.

8. A static random access memory device, comprising: A virtual power supply circuit is configured to generate a virtual power supply voltage. A memory array, powered between the virtual power supply voltage and a reference voltage, the memory array being composed of memory cells and organized into rows and columns, wherein each row has a word line associated with it, and each column has a bit line and a complementary bit line associated with it. The line decoder is configured to selectively activate word lines of the desired line; The column decoder is configured to select the desired column; The virtual power circuit is configured to reduce its current output in response to an internal clock signal pulse, thereby underpowering the memory array. as well as The column drive circuit is configured to drive the bit lines and the complementary bit lines of the desired column to the same logic state in response to the activation of the clock pulse controlled by the internal clock signal and the latched reset signal. In response to a pulse clock controlled by the internal clock signal and based on the latched reset signal, the line decoder enables the word lines of each desired line to be active simultaneously. as well as In response to the end of the internal clock signal pulse, the row decoder simultaneously invalidates the word lines of each desired row, thereby placing the memory cells belonging to the desired row and the desired column in a metastable state.

9. The static random access memory device of claim 8, wherein the virtual power supply circuit comprises: At least one first transistor is coupled to a power supply voltage and configured to output the virtual power supply voltage when turned on; as well as At least one second transistor is coupled to the power supply voltage and configured to facilitate the output of the virtual power supply voltage when turned on; The at least one second transistor is configured to turn off in response to receiving the internal clock signal pulse, thereby reducing the current output from the virtual power circuit to the memory array.

10. The static random access memory device of claim 9, wherein the at least one second transistor is larger than the at least one first transistor.

11. The static random access memory device of claim 9, wherein the column drive circuit comprises: An inverter, associated with each distinct bit line, the output of which is coupled to the bit line; as well as Multiplexing circuit, which includes: Different first multiplexers are associated with each different bit line; and Different second multiplexers are associated with each different complementary bit line; Each of the first multiplexers has a first data input coupled to a latched reset signal, a second data input coupled to the column decoder, a selection input coupled to the latched reset signal, and a clock input coupled to receive pulses of the internal clock signal. Each of the second multiplexers has a first data input coupled to the two's complement of the latched reset signal, a second data input coupled to the column decoder, a selection input coupled to the latched reset signal, and a clock input coupled to receive the internal clock signal pulses; and In response to the activation of the internal clock signal pulse clock and the latched reset signal, each first multiplexer of each selected column passes its first data input as an output, and each second multiplexer of each selected column passes its first data input as an output, thereby driving the bit lines and the complementary bit lines of the desired column to the same logic state.

12. A method for resetting the contents of a memory array, comprising: a) Enabling a signal at the reset node, resulting in insufficient current supply to the memory array; b) Select the bit line and complementary bit line associated with the desired column of the memory array containing the memory cell whose contents are to be corrupted, wherein the signal at the reset node is the complement of the internal clock signal. c) For each desired column, force the logic states of its bit lines and complementary bit lines to the relative logic states; as well as d) Energize each word line associated with the desired row of the memory array containing the memory cell whose contents are to be reset simultaneously, and then deactivate these word lines simultaneously, thereby setting the contents of the memory cell whose contents are to be reset to a desired logical value, the desired logical value depending on the relative logical states of their bit lines and their complementary bit lines.

13. The method of claim 12, further comprising: A virtual power supply voltage is generated from the power supply voltage by coupling a power supply voltage node to a virtual power supply voltage node using multiple transistors, thereby generating the virtual power supply voltage at the virtual power supply voltage node; as well as The memory array is powered using the virtual power supply voltage; The signal is activated at the reset node by turning off one of the plurality of transistors used to couple the power supply voltage node to the virtual power supply voltage node, resulting in insufficient current supply to the memory array.

14. The method of claim 13, wherein the relative logical states are different for different desired columns, such that the contents of different desired columns are reset to different desired logical values, or the relative logical states are the same for the desired columns, such that the contents of all desired columns are reset to the same desired logical value.

15. The method according to claim 13, It is expected that the contents of all storage cells in the memory array will be reset. b) includes selecting all bit lines and all complementary bit lines; c) includes, for each column, forcing the logic states of its bit lines and complementary bit lines to relative logic states; and Wherein d) includes making each word line active at the same time, and then making each word line inactive at the same time.

16. The method of claim 15, wherein c) comprises, for each column, forcing the logic state of its bit lines to a first logic state and forcing the logic state of its complementary bit lines to a second logic state.

17. The method of claim 12, wherein the contents of fewer than all memory cells in the memory array are expected to be reset.

18. A static random access memory device, comprising: A virtual power supply circuit is configured to generate a virtual power supply voltage. A memory array, powered between the virtual power supply voltage and a reference voltage, the memory array being composed of memory cells and organized into rows and columns, wherein each row has a word line associated with it, and each column has a bit line and a complementary bit line associated with it. The line decoder is configured to selectively activate word lines of the desired line; The column decoder is configured to select the desired column; The virtual power supply circuit is configured to reduce its current output in response to an internal clock signal pulse, thereby underpowering the memory array. as well as The column drive circuit is configured to drive the bit lines and the complementary bit lines of the desired column to a relative logic state in response to the activation of the clock pulse controlled by the internal clock signal and the latched reset signal. In response to a pulse clock controlled by the internal clock signal and based on the latched reset signal, the line decoder enables the word lines of each desired line to be active simultaneously. and In response to the end of the internal clock signal pulse, the row decoder simultaneously invalidates the word lines of each desired row, thereby resetting the memory cells belonging to the desired row and the desired column.

19. The static random access memory device of claim 18, wherein the virtual power supply circuit comprises: At least one first transistor is coupled to the power supply voltage and configured to output the virtual power supply voltage when turned on; as well as At least one second transistor is coupled to the power supply voltage and configured to facilitate the output of the virtual power supply voltage when turned on; The at least one second transistor is configured to turn off in response to receiving the internal clock signal pulse, thereby reducing the current output from the virtual power circuit to the memory array.

20. The static random access memory device of claim 18, wherein the column drive circuit comprises: An inverter, associated with each distinct bit line, the output of which is coupled to the bit line; as well as Multiplexing circuit, which includes: Different first multiplexers are associated with each different bit line; and Different second multiplexers are associated with each different complementary bit line; Each of the first multiplexers has a first data input coupled to a latched reset signal, a second data input coupled to the column decoder, a selection input coupled to the latched reset signal, and a clock input coupled to receive pulses of the internal clock signal. Each of the second multiplexers has a first data input coupled to a latched reset signal, a second data input coupled to the column decoder, a selection input coupled to the latched reset signal, and a clock input coupled to receive pulses of the internal clock signal; and In response to the activation of the internal clock signal pulse clock and the latched reset signal, each first multiplexer of each selected column passes its first data input as an output, and each second multiplexer of each selected column passes its first data input as an output, thereby driving the bit lines and the complementary bit lines of the desired column to the relative logic state.

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