Memory device for performing programming operations and operating method thereof

Abstract

The present application relates to memory devices for performing programming operations and methods of operating the same. Provided herein can be memory devices and methods of operating the same. A memory device can include a plurality of memory cells coupled between a common source line and a bit line, a peripheral circuit configured to perform a plurality of programming cycles, each programming cycle including a program voltage application operation of applying a program voltage to the selected memory cells and a verify operation of verifying a program state of the selected memory cells, and control logic configured to control the peripheral circuit, in the program voltage application operation, to apply a pre-charge voltage to the common source line and to vary at least one of a magnitude of the pre-charge voltage and a time of applying the pre-charge voltage in dependence on a magnitude of the program voltage.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to electronic devices, and more specifically, to memory devices for performing programming operations and methods for operating memory devices. Background Technology

[0002] Memory devices are storage devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Memory devices are broadly classified into volatile memory devices and non-volatile memory devices.

[0003] Volatile memory devices are memory devices in which stored data is lost when power is interrupted. Representative examples of volatile memory devices include Static Random Access Memory (SRAM), Dynamic RAM (DRAM), and Synchronous DRAM (SDRAM). Non-volatile memory devices are memory devices in which stored data is retained even when power is interrupted. Representative examples of non-volatile memory devices include Read-Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), Flash Memory, Phase-Change RAM (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), and Ferroelectric RAM (FRAM). Flash Memory is basically classified into NOR and NAND types. Summary of the Invention

[0004] Various embodiments of this disclosure relate to a memory device for performing programming operations that can mitigate disturbances that occur during programming operations, and a method of operating the memory device.

[0005] Embodiments of this disclosure may provide a memory device. The memory device may include: a plurality of memory cells connected between a common source line and a bit line; peripheral circuitry configured to execute a plurality of programming cycles, each programming cycle including a programming voltage application operation of applying a programming voltage to a memory cell selected from the plurality of memory cells and a verification operation of verifying the programming state of the selected memory cell; and control logic configured to control the peripheral circuitry during the programming voltage application operation to: apply a pre-charge voltage to the common source line, and, depending on the magnitude of the programming voltage, change at least one of the amplitude of the pre-charge voltage and the duration of applying the pre-charge voltage to the common source line.

[0006] Embodiments of this disclosure may provide a memory device. The memory device may include: a plurality of memory cell strings, each memory cell string including a plurality of memory cells connected between a common source line and a bit line, and a plurality of dummy memory cells connected between the plurality of memory cells and the common source line; peripheral circuitry configured to execute a plurality of programming cycles, each programming cycle including a programming voltage application operation applying a programming voltage to a memory cell selected from the plurality of memory cells and a verification operation verifying the programming state of the selected memory cell; and control logic configured to control the peripheral circuitry during the programming voltage application operation to: apply a pre-charge voltage to the common source line, apply a dummy voltage to at least one of a plurality of dummy word lines respectively connected to the plurality of dummy memory cells, and change at least one of the amplitude of the dummy voltage and the time of applying the dummy voltage to the at least one dummy word line according to the amplitude of the programming voltage.

[0007] Embodiments of this disclosure provide a method for operating a memory device comprising a plurality of memory cell strings, each memory cell string comprising a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, a drain select line connected between the bit line and the plurality of memory cells, and a plurality of dummy memory cells connected between the plurality of memory cells and the source select line. The method may include: applying a first precharge voltage to the common source line in a first programming cycle of a plurality of programming cycles; applying a first dummy voltage to at least one of a plurality of dummy word lines respectively connected to the plurality of dummy memory cells in the first programming cycle; applying a second precharge voltage higher than the first precharge voltage in a second programming cycle following the first programming cycle of the plurality of programming cycles; and applying a second dummy voltage higher than the first dummy voltage to at least one dummy word line in the second programming cycle.

[0008] Embodiments of this disclosure may provide a memory device. The memory device may include: an array of memory cells in rows and columns, the rows including a first row; and control circuitry configured to execute programming cycles, each programming cycle including applying a pre-charge voltage to a column and applying a programming voltage to a selected row in the first row, wherein each of the pre-charge voltage and the programming voltage increases progressively as the programming cycle proceeds. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0010] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A diagram of the structure of a memory device.

[0011] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 A diagram of a memory cell array.

[0012] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 3 The circuit diagram of storage block BLKa in storage blocks BLK1 to BLKz.

[0013] Figure 5 This illustrates an embodiment according to the present disclosure. Figure 3 A circuit diagram of an example of storage block BLKb in storage blocks BLK1 to BLKz.

[0014] Figure 6 This illustrates an embodiment according to the present disclosure. Figure 3 A circuit diagram of an example of storage block BLKi in storage blocks BLK1 to BLKz.

[0015] Figure 7 This is a diagram used to describe the programming operations of a memory device according to embodiments of the present disclosure.

[0016] Figure 8A This is a diagram illustrating the application of a programming voltage during programming operations of a memory device according to an embodiment of the present disclosure.

[0017] Figure 8B This is a diagram illustrating an example of the application of a programming voltage during programming operations of a memory device according to an embodiment of the present disclosure.

[0018] Figure 9 It is a diagram used to describe the channel potential change during the programming voltage application operation in the programming operation of a memory device according to an embodiment of the present disclosure.

[0019] Figure 10A This is a diagram illustrating the operation of changing the magnitude of the precharge voltage according to the magnitude of the programming voltage during programming operations of a memory device according to an embodiment of the present disclosure.

[0020] Figure 10B This is a diagram illustrating the operation of changing the amplitude of a dummy voltage according to the amplitude of the programming voltage during programming operations of a memory device according to an embodiment of the present disclosure.

[0021] Figure 11A This is a diagram illustrating the operation of changing the time of applying the precharge voltage according to the amplitude of the programming voltage during the programming operation of a memory device according to an embodiment of the present disclosure.

[0022] Figure 11BThis is a diagram illustrating the operation of changing the duration of the applied dummy voltage according to the amplitude of the programming voltage during programming operations of a memory device according to an embodiment of the present disclosure.

[0023] Figure 12 This is a diagram illustrating an operation in which, during programming of a memory device according to an embodiment of the present disclosure, at least one of the following is changed according to the magnitude of the programming voltage, the time for applying the precharge voltage, the magnitude of the dummy voltage, and the time for applying the dummy voltage:

[0024] Figure 13 This is a diagram illustrating the operation of changing the precharge voltage or dummy voltage according to multiple programming cycles in the programming operation of a memory device according to an embodiment of the present disclosure.

[0025] Figure 14 This illustrates an embodiment according to the present disclosure. Figure 2 A diagram of the control logic.

[0026] Figure 15 This is a flowchart illustrating the programming operation of a memory device according to an embodiment of the present disclosure.

[0027] Figure 16 This is a diagram illustrating an erase operation performed on a plurality of memory cells according to an embodiment of the present disclosure.

[0028] Figure 17 It is a diagram used to describe pre-programmed operations according to embodiments of the present disclosure.

[0029] Figure 18 This is a diagram used to describe preprogramming operations including multiple preprogramming loops according to embodiments of the present disclosure.

[0030] Figure 19 This is a flowchart illustrating a pre-programmed operation according to an embodiment of the present disclosure.

[0031] Figure 20 This illustrates an embodiment according to the present disclosure. Figure 1 A diagram of the memory controller.

[0032] Figure 21 This is a block diagram illustrating a memory card system that applies a memory system according to an embodiment of the present disclosure.

[0033] Figure 22 This is a block diagram illustrating a solid-state drive (SSD) system that applies a memory system according to an embodiment of the present disclosure.

[0034] Figure 23 This is a block diagram illustrating a user system that applies a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0035] The specific structural or functional descriptions of embodiments of this disclosure contained herein describe implementations based on the concept of this disclosure. Implementations based on the concept of this disclosure may be implemented in various forms and should not be construed as limited to the implementations described in this specification.

[0036] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0037] Reference Figure 1 The memory system 50 may include a memory device 100 and a memory controller 200. The memory system 50 may be a device for storing data under the control of a host 300, such as a mobile phone, smartphone, MP3 player, laptop, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0038] The memory system 50 can be manufactured as any of various types of storage devices depending on the host interface used for communication with the host 300. For example, the memory system 50 can be implemented as any of the following types of storage devices: solid-state drives (SSDs), multimedia cards (such as MMC, embedded MMC (eMMC), miniaturized MMC (RS-MMC), or micro MMC), secure digital cards (such as SD, mini SD, or micro SD), universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, PCI Express (PCI-e or PCIe) card-type storage devices, compact flash (CF) cards, smart media cards, and memory sticks.

[0039] The memory system 50 can be manufactured in any of the various types of package forms. For example, the memory system 50 can be manufactured in any of the following various types of package forms: package stack (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), or wafer-level stack-up package (WSP).

[0040] The memory device 100 can store data. The memory device 100 can operate in response to the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) that includes a plurality of memory cells for storing data.

[0041] Each memory cell can be implemented as a single-level cell (SLC) capable of storing one bit of data, a multi-level cell (MLC) capable of storing two bits of data, a three-level cell (TLC) capable of storing three bits of data, or a four-level cell (QLC) capable of storing four bits of data.

[0042] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. A single memory block may include multiple pages. In an embodiment, a page may be a unit for storing data in or retrieving data stored in the memory device 100. A memory block may be a unit for erasing data.

[0043] In embodiments, the memory device 100 may be implemented as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Generation 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive RAM (RRAM), Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FRAM), or Spin-Transfer Torque RAM (STT-RAM). In this specification, for ease of description, the memory device 100 will be described as NAND flash memory.

[0044] Memory device 100 can receive commands and addresses from memory controller 200 and can access a region of the memory cell array selected by an address. Memory device 100 can perform operations instructed by commands on the region selected by the address. For example, memory device 100 can perform write operations (i.e., programming operations), read operations, and erase operations. During a write operation, memory device 100 can program data into the region selected by the address. During a read operation, memory device 100 can read data from the region selected by the address. During an erase operation, memory device 100 can erase the data stored in the region selected by the address.

[0045] The memory controller 200 can control the overall operation of the memory system 50.

[0046] When power is supplied to the memory system 50, the memory controller 200 may run firmware (FW). When the memory device 100 is a flash memory device, the firmware (FW) may include a host interface layer (HIL) that controls communication with the host 300, a flash translation layer (FTL) that controls communication between the host 300 and the memory device 100, and a flash interface layer (FIL) that controls communication with the memory device 100.

[0047] In this embodiment, the memory controller 200 can receive data and logical block addresses (LBAs) from the host 300, and can translate the logical block addresses (LBAs) into physical block addresses (PBAs), whereby the PBAs indicate the addresses of memory cells included in the memory device 100 where data is to be stored. In this specification, the terms "logical block address (LBA)" and "logical address" are used interchangeably. Similarly, the terms "physical block address (PBA)" and "physical address" are used interchangeably.

[0048] The memory controller 200 can control the memory device 100 to perform write, read, or erase operations in response to requests received from the host 300. During a write operation, the memory controller 200 can provide the memory device 100 with a write command, a physical block address, and data. During a read operation, the memory controller 200 can provide the memory device 100 with a read command and a physical block address. During an erase operation, the memory controller 200 can provide the memory device 100 with an erase command and a physical block address.

[0049] In this implementation, the memory controller 200 can autonomously generate commands, addresses, and data regardless of whether it receives a request from the host 300, and can send the commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide the memory device 100 with the commands, addresses, and data required for read and write operations involved in performing wear leveling, read recycling, garbage collection, etc.

[0050] In one implementation, the memory controller 200 can control at least two memory devices 100. In this case, the memory controller 200 can control the memory devices 100 according to an interleaving scheme to improve operational performance. The interleaving scheme can be a scheme for controlling the memory devices 100 such that the operations of at least two memory devices 100 overlap with each other.

[0051] The host 300 can communicate with the memory system 50 using at least one of the following communication methods: Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCIe, High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-off DIMM (LRDIMM).

[0052] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A diagram of the structure of a memory device.

[0053] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0054] The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to the address decoder 121 via row lines RL. The memory blocks BLK1 to BLKz are connected to the page buffer group 123 via bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz may include multiple memory cells. In embodiments, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line among the multiple memory cells are defined as a page. That is, the memory cell array 110 may include multiple pages. In embodiments of this disclosure, each of the memory blocks BLK1 to BLKz included in the memory cell array 110 may include multiple dummy cells. For a dummy cell, one or more dummy cells may be connected in series between a drain select transistor and a memory cell, and between a source select transistor and a memory cell.

[0055] Each memory cell of the memory device 100 can be implemented as a single-level cell (SLC) capable of storing one bit of data, a multi-level cell (MLC) capable of storing two bits of data, a three-level cell (TLC) capable of storing three bits of data, or a four-level cell (QLC) capable of storing four bits of data.

[0056] Peripheral circuitry 120 can drive memory cell array 110. In this example, peripheral circuitry 120 can drive memory cell array 110 to perform programming, reading, and erasing operations under the control of control logic 130. In other examples, peripheral circuitry 120 can apply various operating voltages to row lines RL and bit lines BL1 to BLm or discharge the applied voltages under the control of control logic 130.

[0057] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a page buffer group 123, a data input / output circuit 124, and a sensing circuit 125.

[0058] Address decoder 121 is connected to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to embodiments of this disclosure, word lines may include normal word lines and dummy word lines. According to embodiments, row lines RL may also include tubular select lines.

[0059] Address decoder 121 can operate under the control of control logic 130. Address decoder 121 receives address ADDR from control logic 130.

[0060] Address decoder 121 can decode the block address in the received address ADDR. Address decoder 121 can select at least one of the memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 can decode the row address RADD in the received address ADDR. Address decoder 121 can select at least one word line WL of the selected memory block by applying a voltage provided from voltage generator 122 to at least one word line WL according to the decoded row address RADD.

[0061] During programming operations, address decoder 121 may apply a programming voltage to the selected word line and a pass voltage with a level lower than the programming voltage to the unselected word line. During programming verification operations, address decoder 121 may apply a verification voltage to the selected word line and a verification pass voltage with a level higher than the verification voltage to the unselected word line.

[0062] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and a read pass voltage that is higher than the read voltage to the unselected word line.

[0063] Erasure operations on memory device 100 are performed on a block-by-block basis. During the erase operation, the address ADDR input to memory device 100 includes the block address. Address decoder 121 can decode the block address and select a memory block based on the decoded block address. During the erase operation, address decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0064] According to embodiments of this disclosure, address decoder 121 can decode the column address in the received address ADDR. The decoded column address can be transmitted to page buffer set 123. In embodiments, address decoder 121 may include components such as row decoder, column decoder, and address buffer.

[0065] Voltage generator 122 can generate multiple operating voltages Vop using the external power supply voltage provided to memory device 100. Voltage generator 122 can operate under the control of control logic 130.

[0066] In this embodiment, the voltage generator 122 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 can be used as the operating voltage of the memory device 100.

[0067] In this implementation, voltage generator 122 can generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OPSIG. Voltage generator 122 can use either an external or internal power supply voltage to generate multiple operating voltages Vop. Voltage generator 122 can generate various voltages required by the memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0068] The voltage generator 122 may include multiple pump capacitors for receiving an internal power supply voltage to generate multiple operating voltages Vop with various voltage levels, and can generate multiple operating voltages Vop by selectively enabling the multiple pump capacitors under the control of control logic 130.

[0069] The generated operating voltage Vop can be provided to the memory cell array 110 by the address decoder 121.

[0070] Page buffer group 123 includes first page buffer PB1 to m-th page buffer PBm. First page buffer PB1 to m-th page buffer PBm are respectively connected to memory cell array 110 via first bit line BL1 to m-th bit line BLm. First page buffer PB1 to m-th page buffer PBm operate under the control of control logic 130.

[0071] Page buffers PB1 through PBm can send / receive data DATA to / from data input / output circuit 124. During programming operations, page buffers PB1 through PBm receive the data DATA to be stored via data input / output circuit 124 and data line DL.

[0072] During programming operations, page buffers PB1 through PBm can transmit the data DATA to be stored, received via data input / output circuit 124, to the selected memory cell via bit lines BL1 through BLm when a programming pulse is applied to the selected word line. The memory cell in the selected page is programmed based on the received data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification operations, page buffers PB1 through PBm read the data DATA stored in the selected memory cell from the selected memory cell via bit lines BL1 through BLm.

[0073] During a read operation, page buffer group 123 can read data DATA from the memory cell in the selected page via bit lines BL1 to BLm, and can store the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0074] During an erase operation, page buffer group 123 may allow bit lines BL1 to BLm to float. In one embodiment, page buffer group 123 may include column select circuitry.

[0075] In one implementation, when multiple data entries stored in some of the multiple page buffers included in the page buffer group 123 are being programmed into the memory cell array 110, the remaining page buffers can receive new data from the memory controller 200 and then store the new data.

[0076] The data input / output circuit 124 is connected to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. The data input / output circuit 124 operates in response to the control logic 130.

[0077] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 receives the data DATA to be stored from an external controller (not shown). During reading operations, the data input / output circuit 124 outputs the data DATA received from the first page buffer PB1 to the m-th page buffer PBm included in the page buffer group 123 to the external controller.

[0078] During a read or verification operation, the sensing circuit 125 can generate a reference current in response to the enable bit signal VRYBIT generated by the control logic 130, and can output a pass signal or a failure signal to the control logic 130 by comparing the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current.

[0079] Control logic 130 can be connected to address decoder 121, voltage generator 122, page buffer group 123, data input / output circuit 124, and sensing circuit 125. Control logic 130 can control the overall operation of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices.

[0080] Control logic 130 can control peripheral circuit 120 by generating various types of signals in response to command CMD and address ADDR. For example, control logic 130 can generate operation signal OPSIG, row address RADD, page buffer control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, row address RADD to address decoder 121, page buffer control signal PBSIGNALS to page buffer group 123, and enable bit VRYBIT to sensing circuit 125. In addition, control logic 130 can determine whether the verification operation has passed or failed in response to pass signal PASS or failure signal FAIL output from sensing circuit 125.

[0081] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 A diagram of a memory cell array.

[0082] Reference Figure 3 The memory cell array 110 includes multiple memory blocks BLK1 to BLK2. Each memory block may have a three-dimensional (3D) structure. Each memory block may include multiple memory cells stacked on a substrate. The multiple memory cells are arranged in the +X, +Y, and +Z directions. (Refer to the following...) Figure 4 and Figure 5 Describe the structure of each storage block in more detail.

[0083] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 3 The circuit diagram of storage block BLKa in storage blocks BLK1 to BLKz.

[0084] Reference Figure 4 The storage block BLKa comprises multiple cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment, each of the cell strings CS11 to CS1m and CS21 to CS2m can be formed in a "U" shape. In the storage block BLKa, m cell strings are arranged in the row direction (i.e., the positive (+)X direction). Figure 4 In the example, two unit strings are illustrated as arranged in the column direction (i.e., the positive (+) Y direction). However, this illustration is for ease of description and it will be understood that three or more unit strings can be arranged in the column direction.

[0085] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, a tube transistor PT, and at least one drain selection transistor DST.

[0086] The selector transistors SST and DST, and the memory cells MC1 to MCn, can have similar structures. In one embodiment, each of the selector transistors SST and DST, and the memory cells MC1 to MCn, may include a channel layer, a tunnel insulating layer, a charge storage layer, and a barrier insulating layer. In one embodiment, pillars for providing the channel layer may be provided in each cell string. In another embodiment, pillars for providing at least one of the channel layer, tunnel insulating layer, charge storage layer, and barrier insulating layer may be provided in each cell string.

[0087] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCp.

[0088] In one implementation, source-select transistors in cell strings arranged in the same row are connected to source-select lines extending in the row direction, while source-select transistors in cell strings arranged in different rows are connected to different source-select lines. Figure 4 In the first row, the source selection transistors of cell strings CS11 to CS1m are connected to the first source selection line SSL1. In the second row, the source selection transistors of cell strings CS21 to CS2m are connected to the second source selection line SSL2.

[0089] In one implementation, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0090] The first memory cell MC1 to the nth memory cell MCn in each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0091] The first memory cells MC1 to the nth memory cell MCn can be divided into first memory cells MC1 to the pth memory cells MCp and (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first memory cells MC1 to the pth memory cells MCp are arranged sequentially in the direction opposite to the positive (+) Z direction and connected in series between the source selection transistor SST and the transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn are arranged sequentially in the +Z direction and connected in series between the transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cells MCp and the (p+1)th memory cells MCp+1 to the nth memory cells MCn are interconnected with each other via the transistor PT. The gates of the first memory cells MC1 to the nth memory cells MCn in each cell string are respectively connected to the first word line WL1 to the nth word line WLn.

[0092] The gate of the tubular transistor PT in each unit string is connected to the tubular line PL.

[0093] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0094] Cells arranged in the column direction are connected in series to bit lines extending in the column direction. Figure 4 In the first column, the cell strings CS11 and CS21 are connected to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column are connected to the m-th bit line BLm.

[0095] Memory cells connected to the same word line in a cell string arranged in the row direction form a single page. For example, memory cells connected to the first word line WL1 in cell strings CS11 to CS1m in the first row form a single page. Memory cells connected to the first word line WL1 in cell strings CS21 to CS2m in the second row form additional pages. A cell string arranged in the row direction can be selected by selecting one of the drain select lines DSL1 and DSL2. A single page can be selected from the selected cell string by selecting one of the word lines WL1 to WLn.

[0096] In this implementation, instead of the first bit line BL1 to the m-th bit line BLm, even-numbered bit lines and odd-numbered bit lines can be provided. Furthermore, even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the corresponding even-numbered bit lines. Odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the corresponding odd-numbered bit lines.

[0097] In this implementation, one or more of the first memory cells MC1 to the nth memory cell MCn can be used as dummy memory cells. For example, one or more dummy memory cells are provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, one or more dummy memory cells are provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. With more dummy memory cells provided, the operational reliability of the memory block BLKa improves, but the size of the memory block BLKa increases. With fewer memory cells provided, the size of the memory block BLKa decreases, but the operational reliability of the memory block BLKa may deteriorate.

[0098] To effectively control one or more dummy memory cells, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after the erase operation of the memory block BLKa. When an erase operation is performed after programming, the threshold voltage of the dummy memory cells controls the voltage applied to the dummy word lines connected to each dummy memory cell, thus allowing the dummy memory cells to have the desired threshold voltage.

[0099] Figure 5 This illustrates an embodiment according to the present disclosure. Figure 3 A circuit diagram of an example of storage block BLKb in storage blocks BLK1 to BLKz.

[0100] Reference Figure 5 The memory block BLKb may include multiple cell strings CS11′ to CS1m′ and CS21′ to CS2m′. Each of the cell strings CS11′ to CS1m′ and CS21′ to CS2m′ extends in the positive (+) Z direction. Each of the cell strings CS11′ to CS1m′ and CS21′ to CS2m′ includes at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) beneath the memory block BLKb.

[0101] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. The source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings CS11′ to CS1m′ arranged in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21′ to CS2m′ arranged in the second row are connected to the second source select line SSL2. In an embodiment, the source select transistors of cell strings CS11′ to CS1m′ and CS21′ to CS2m′ can be commonly connected to a single source select line.

[0102] The first memory cell MC1 to the nth memory cell MCn in each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0103] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0104] As a result, in addition to excluding the tubular transistor PT from each cell string, Figure 5 The storage block BLKb has the same characteristics as Figure 4 The equivalent circuit of the storage block BLKa is similar to the equivalent circuit.

[0105] In this implementation, instead of the first bit line BL1 to the m-th bit line BLm, even-numbered bit lines and odd-numbered bit lines can be provided. Furthermore, the even-numbered cell strings among the cell strings CS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction can be connected to the corresponding even-numbered bit lines. The odd-numbered cell strings among the cell strings CS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction can be connected to the corresponding odd-numbered bit lines.

[0106] In this implementation, one or more of the first memory cells MC1 to the nth memory cell MCn can be used as dummy memory cells. For example, one or more dummy memory cells are provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, one or more dummy memory cells are provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. As the number of dummy memory cells provided increases, the operational reliability of the memory block BLKb can be improved, while the size of the memory block BLKb can be increased. As the number of dummy memory cells provided decreases, the size of the memory block BLKb can be reduced, while the operational reliability of the memory block BLKb may deteriorate.

[0107] To effectively control one or more dummy memory cells, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation is performed on the memory block BLKb. When an erase operation is performed after programming, the dummy memory cells can have a desired threshold voltage by controlling the voltage applied to the dummy word lines connected to each dummy memory cell.

[0108] Figure 6 This illustrates an embodiment according to the present disclosure. Figure 3A circuit diagram of an example of storage block BLKi in storage blocks BLK1 to BLKz.

[0109] Reference Figure 6 Multiple word lines can be connected in parallel between the first select line and the second select line. Here, the first select line can be the source select line (SSL), and the second select line can be the drain select line (DSL). More specifically, the storage block BLKi can include multiple string STs connected between bit lines BL1 to BLm and the common source line (CSL). Bit lines BL1 to BLm can be connected to individual string STs, while the common source line (CSL) can be connected to all string STs. String STs can be configured in the same way, therefore, the string ST connected to the first bit line BL1 will be described in detail by example.

[0110] A string ST may include a source selection transistor SST connected in series between a common source line CSL and a first bit line BL1, a plurality of memory cells MC1+1 to MCm and a plurality of dummy memory cells D_MC1 to D_MC1 and D_MCm+1 to D_MCn, and a drain selection transistor DST. A string ST may include at least one source selection transistor SST and at least one drain selection transistor DST.

[0111] The source of the source-select transistor SST can be connected to the common source line CSL, while the drain of the drain-select transistor DST can be connected to the first bit line BL1. Memory cells MC1+1 to MCm can be connected in series between the dummy memory cells D_MC1 to D_MC1 adjacent to the source-select transistor SST and the dummy memory cells D_MCm+1 to D_MCn adjacent to the drain-select transistor DST. The dummy memory cells D_MC1 to D_MC1 adjacent to the source-select transistor SST can be connected in series between the memory cells MC1+1 to MCm and the source-select transistor SST. The dummy memory cells D_MCm+1 to D_MCn adjacent to the drain-select transistor DST can be connected in series between the memory cells MC1+1 to MCm and the drain-select transistor DST. The gates of source select transistors (SSTs) included in different string STs can be connected to source select line SSL, and the gates of drain select transistors (DSTs) included in different string STs can be connected to drain select line DSL. The gates of memory cells MC1+1 to MCm can be connected to multiple word lines WL1 to WLm, respectively. Multiple dummy memory cells D_MC1 to D_MC1 and D_MCm+1 to D_MCn can be connected to multiple dummy word lines D_WL1 to D_WL1 and D_WLm+1 to D_WLn, respectively. Among the memory cells included in different string STs, a group of memory cells connected to the same word line can be referred to as a "physical page (PPG)". Therefore, memory block BLKi can include the same number of physical pages (PPGs) as the number of word lines WL1+1 to WLm.

[0112] A memory cell can store one bit of data. This cell is usually called a "single-level cell (SLC)". In this case, a physical page (PPG) can store the data corresponding to a logical page (LPG). The data corresponding to a logical page (LPG) can include the same number of data bits as the number of cells included in a physical page (PPG).

[0113] A memory cell can store two or more bits of data. In this case, a physical page (PPG) can store data corresponding to two or more logical pages (LPGs).

[0114] Figure 7 This is a diagram used to describe the programming operations of a memory device according to embodiments of the present disclosure.

[0115] exist Figure 7In this description, for ease of description, each of the plurality of memory cells is a multi-level cell (MLC) that stores two bits of data. However, the scope of this disclosure is not limited thereto, and each of the plurality of memory cells may be a three-level cell (TLC) that stores three bits of data or a four-level cell (QLC) that stores four bits of data.

[0116] Programming can be an operation that increases the threshold voltage of each memory cell based on the data to be stored in the corresponding memory cell. When performing a programming operation, each memory cell can have a threshold voltage corresponding to one of several programming states. After the programming operation has been performed, the threshold voltage of the memory cell can be determined based on the data to be stored in the memory cell. Each memory cell can have one of several programming states as the target programming state. The target programming state can be determined based on the data to be stored in the corresponding memory cell.

[0117] The programming operation of the memory device 100 may include multiple programming cycles PL1 to PLn. The memory device 100 may perform the programming operation by executing multiple programming cycles PL1 to PLn, such that each selected memory cell has a threshold voltage corresponding to one of multiple programming states. Each of the multiple programming cycles PL1 to PLn may include a programming voltage application operation (PGM step) and a verification operation (verification step).

[0118] The programming voltage application operation (PGM step) can be an operation that applies a programming voltage to a selected word line connected to the selected memory cell. For example, memory device 100 can apply a first programming voltage Vpgm1 to the selected word line connected to the selected memory cell in a first programming cycle PL1. In the programming voltage application operation (PGM step), each selected memory cell can be programmed to a target programming state among multiple programming states.

[0119] A verification operation can be an operation of applying a verification voltage to the selected word line connected to the selected memory cell. A verification operation can be an operation of verifying the programming state of the selected memory cell. More specifically, a verification operation can be an operation of determining whether the selected memory cell has been programmed to a target programming state among multiple programming states. A verification operation can be an operation of applying a verification voltage corresponding to the target programming state of the selected memory cell. For example, when the selected memory cell is read as a cutoff cell using a verification voltage corresponding to the corresponding target programming state of the selected memory cell, the selected memory cell passes the verification operation.

[0120] In this implementation, during the first programming cycle PL1, after applying a first programming voltage Vpgm1 to the selected word line connected to the selected memory cell, the memory device 100 may sequentially apply a first verification voltage V_vfy1 to a third verification voltage V_vfy3 to the selected word line. In this case, a verification operation can be performed by applying the first verification voltage V_vfy1 to a memory cell with a first programming state as the target programming state. A verification operation can be performed by applying a second verification voltage V_vfy2 to a memory cell with a second programming state as the target programming state. A verification operation can be performed by applying a third verification voltage V_vfy3 to a memory cell with a third programming state as the target programming state.

[0121] It can be determined that the memory cell that has undergone verification operations using the respective verification voltages V_vfy1 to V_vfy3 has the target programming state. In the second programming cycle PL2, the memory cell that has passed the verification operation can be disabled for programming. A programming disable voltage can be applied to the bit line connected to the disabled memory cell.

[0122] It can be determined that memory cells for which verification operations using each verification voltage V_vfy1 to V_vfy3 have failed do not have the target programming state. Memory cells for which verification operations have failed can execute the second programming cycle PL2.

[0123] In the second programming cycle PL2, the memory device 100 may apply a voltage higher than the first programming voltage Vpgm1 to the selected word line connected to the selected memory cell. The second programming voltage Vpgm2 is Vpgm. Thereafter, the memory device 100 can perform the verification operation of the second programming cycle PL2 in the same manner as the verification operation of the first programming cycle PL1.

[0124] Subsequently, the memory device 100 can execute the subsequent programming cycle a preset number of times in the same manner as the second programming cycle PL2.

[0125] In this implementation, the programming operation may fail if it is not completed within a preset number of programming loops. The programming operation can succeed if it is completed within the preset number of programming loops. The completion of the programming operation can be determined based on whether all selected memory cells have passed the verification operation. If all selected memory cells have passed the verification operation, subsequent programming loops may not be executed.

[0126] In this implementation, the programming voltage can be determined based on the Incremental Step Pulse Programming (ISPP) method. As programming cycles PL1 to PLn are repeated, the programming voltage level can be gradually increased or decreased (i.e., according to step voltage). The number of times the programming voltage is applied in each programming cycle, the voltage level of the programming voltage, the voltage application time, etc., can be determined in various forms under the control of the memory controller 200.

[0127] Figure 8A This is a diagram illustrating the application of a programming voltage during programming operations of a memory device according to an embodiment of the present disclosure.

[0128] Reference Figure 8A The programming operation of the memory device 100 may include multiple programming cycles PL1 to PLn. Each of the multiple programming cycles PL1 to PLn may include a programming voltage application operation (PGM step) and a verification operation (verification step).

[0129] The programming voltage application operation (PGM step) included in each of the multiple programming cycles PL1 to PLn may include a pre-charge period, a programming pulse (Pgm pulse) period, and a discharge period.

[0130] The period from t1 to t2 can be a pre-charge period. The pre-charge period can be a period during which the common source line CSL is pre-charged. For example, the memory device 100 can apply a pre-charge voltage Vpre to the common source line CSL and an on-state voltage V_on to the source select line SSL during the pre-charge period. Here, the on-state voltage V_on can be a voltage higher than the threshold voltage of the source select transistor connected to the source select line SSL.

[0131] The time period from t2 to t3 can be the programming pulse (Pgm pulse) period. During the programming pulse (Pgm pulse) period, a programmable word line Sel_WL connected to the selected memory cell can be applied. Figure 7 The programming voltages Vpgm1 to Vpgmn are shown in the figure.

[0132] The programming pulse (Pgm pulse) period can be the period during which data is stored in the selected memory cell. For example, during the programming pulse (Pgm pulse) period, the memory device 100 can apply a pass voltage Vpass to the selected word line Sel_WL connected to the selected memory cell for a certain period of time, then apply a programming voltage Vpgm to the selected word line Sel_WL, and can apply a pass voltage Vpass to the unselected word line Unsel_WL. During the programming pulse (Pgm pulse) period, the memory device 100 can apply a ground voltage GND to the source select line SSL and the common source line CSL.

[0133] The period from t3 to t4 can be a discharge period. During the discharge period, the memory device 100 can apply a ground voltage GND to the selected word line Sel_WL and the unselected word line Unsel_WL.

[0134] Figure 8B This is a diagram illustrating an example of the application of a programming voltage during programming operations of a memory device according to an embodiment of the present disclosure.

[0135] In the implementation, Figure 8B It is used to describe the above reference. Figure 8A The diagram illustrates an example of applying a dummy voltage V_dm to the dummy word line D_WL during the pre-charge period of the described programming voltage application operation. Therefore, in Figure 8B In the middle, omission and Figure 8A The component description is the same as the component description in the document.

[0136] Reference Figure 8B The period from t1 to t2 can be a pre-charge period. For example, during the pre-charge period, the memory device 100 can apply a pre-charge voltage Vpre to the common source line CSL and an on-state voltage V_on to the source select line SSL. Furthermore, during the pre-charge period, the memory device 100 can apply a dummy voltage V_dm to the dummy word line D_WL connected to the dummy memory cell.

[0137] Figure 9 It is a diagram used to describe the channel potential change during the programming voltage application operation in the programming operation of a memory device according to an embodiment of the present disclosure.

[0138] exist Figure 9 In the diagram, the horizontal axis represents the location of the transistor connected between the common source line CSL and the bit line BL, while the vertical axis represents the channel potential.

[0139] exist Figure 9 In the text, for ease of description, ten word lines WL1 to WL10 and three dummy word lines D_WL1 to D_WL3 are connected to the memory cell string.

[0140] First of all, Figure 9 The channel potential formed during the programming operation of the memory device 100 by executing one of a plurality of programming cycles will be described.

[0141] The memory device 100 can use a verification voltage in a verification operation included in any of a plurality of programming cycles to verify the programming state of the selected memory cell. Thereafter, the memory device 100 can apply a ground voltage to multiple word lines in a verification operation included in a programming cycle. Here, the voltage of the multiple word lines can be discharged to ground. However, among the multiple word lines, the voltage of the word line connected to the memory cell in the programming state can be discharged to ground first. That is, the channel potential corresponding to the memory cell in the programming state can be disconnected first.

[0142] Subsequently, the charges in the severed channel regions may undergo negative downcoupling, thus all channel potentials connected to the memory cell string can be reduced to a negative state. Furthermore, because the channel potentials corresponding to memory cells in the programming state are severed first, they can be lower than the channel potentials corresponding to memory cells in the erasure state. Therefore, when a subsequent loop is executed after the verification operation included in a programming loop has terminated, the channel potentials connected to the memory cell string can be in a negative state.

[0143] Reference Figure 9 A memory cell string may include multiple memory cells connected in series between a bit line BL and a common source line CSL. These memory cells may be connected to multiple word lines WL1 to WL10. A drain select line DSL may be connected between the multiple memory cells and the bit line BL, while a source select line SSL may be connected between the multiple memory cells and the common source line CSL. Multiple dummy memory cells may be connected between the multiple memory cells and the source select line SSL. These dummy memory cells may be connected to multiple dummy word lines D_WL1 to D_WL3.

[0144] In this implementation, programming operations can be performed in the direction from the first crosshair WL10 adjacent to the drain select line DSL to the first word line WL1 adjacent to the dummy word lines D_WL1 to D_WL3. For example, when programming the sixth word line WL6, the channel potential connected to the memory cell string can be negative after the verification operation included in one of the multiple programming cycles terminates. Thereafter, the memory device 100 can apply a precharge voltage Vpre to the common source line CSL and an on-state voltage V_on to the source select line SSL during the precharge period included in the programming cycle following the first programming cycle.

[0145] Here, the channel potentials of the first word lines WL1 to the sixth word lines WL6 can be increased due to the pre-charge voltage Vpre applied during the pre-charge period. For example, the channel potentials of the first word lines WL1 to the sixth word lines WL6 can rise from a negative state to a positive state. However, the channel potentials of the seventh word lines WL7 to the cross line WL10 can remain in a negative state, unaffected by the pre-charge voltage Vpre. Therefore, a channel potential difference may occur between the channel potentials of the first word lines WL1 to the sixth word lines WL6 and the channel potentials of the seventh word lines WL7 to the cross line WL10. Channel potential). In this case, the charge present in the channel region of the memory cell connected to the sixth word line WL6 can be due to the channel potential difference ( The channel potential (channel potential) has higher energy. Subsequently, a high-energy charge can be injected into the gate of the memory cell connected to the sixth word line WL6. This is called hot carrier injection (HCI). As a result, in the memory cell connected to the sixth word line WL6, a disturbance may occur where the threshold voltage of the memory cell increases due to the hot carrier injection (HCI) phenomenon. Specifically, this phenomenon may be exacerbated when the memory cell is in the erase state. Furthermore, the greater the amplitude of the precharge voltage Vpre applied to the common source line CSL during the precharge period, the greater the channel potential difference (channel potential) becomes. The larger the channel potential, the greater the rise in the threshold voltage of the memory cell connected to the sixth word line WL6 can be due to disturbances.

[0146] However, when the amplitude of the precharge voltage Vpre applied to the common source line CSL during the precharge period is small, the channel potentials of the first word line WL1 to the sixth word line WL6 can still remain negative. For example, if the channel potential of the sixth word line WL6 is negative when the programming voltage is applied, Förnodheim (FN) stress is applied to the memory cell connected to the sixth word line WL6 due to the difference between the amplitude of the programming voltage and the channel potential of the sixth word line WL6, and the threshold voltage of the memory cell connected to the sixth word line WL6 can increase. That is, disturbances caused by FN stress can occur. The greater the difference between the amplitude of the programming voltage applied to the sixth word line WL6 and the channel potential of the sixth word line WL6, the more severe the disturbances caused by FN stress. In other words, the lower the channel potential of the sixth word line WL6, the more severe the disturbances caused by FN stress.

[0147] Furthermore, the thickness (i.e., size) of the letter lines can vary depending on their position. For example, although in Figure 9The example illustrates the case where the selected word line Sel_WL is the sixth word line WL6. However, unlike the case described above, the disturbance caused by hot carrier injection can be reduced as the selected word line Sel_WL, where the programming operation is performed, changes in the direction from the fifth word line WL5 to the first word line WL1. In other words, the closer the selected word line Sel_WL is to the source selection line SSL, the less severe the disturbance caused by hot carrier injection.

[0148] Therefore, embodiments of this disclosure can reduce disturbances caused by hot carrier injection or FN stress by varying the magnitude of the precharge voltage Vpre applied to the common source line CSL during the precharge period according to the magnitude of the programming voltage applied to each of the plurality of programming cycles. Furthermore, in embodiments of this disclosure, the memory device 100 can reduce disturbances caused by hot carrier injection or FN stress by varying at least one of the following during the precharge period: the time of applying the precharge voltage, the magnitude of the dummy voltage applied to the plurality of dummy word lines, and the time of applying the dummy voltage, according to the magnitude of the programming voltage applied to each of the plurality of programming cycles.

[0149] Furthermore, the memory device 100 can reduce disturbances caused by hot carrier injection or FN stress by changing at least one of the following: the magnitude of the precharge voltage Vpre to be applied to the common source line CSL, the duration of the precharge voltage application, the magnitude of the dummy voltage V_dm to be applied to the multiple dummy word lines, and the duration of the dummy voltage application, as the selected word line Sel_WL connected to the selected memory cell gets closer to the source selection line SSL.

[0150] Figure 10A This is a diagram illustrating the operation of changing the magnitude of the precharge voltage according to the magnitude of the programming voltage during programming operations of a memory device according to an embodiment of the present disclosure.

[0151] exist Figure 10A In the graph, the horizontal axis represents time and its vertical axis represents the magnitude of the pre-charge voltage Vpre applied to the common source line.

[0152] Reference Figure 10A The programming operation of the memory device 100 may include multiple programming cycles PL1 to PLn. Each of the multiple programming cycles PL1 to PLn may include a programming voltage application operation (PGM step) and a verification operation (verification step).

[0153] The programming voltage application operation (PGM step) included in each of the multiple programming cycles PL1 to PLn may include a pre-charge period, a programming pulse (Pgm pulse) period, and a discharge period.

[0154] The memory device 100 can apply a precharge voltage Vpre to the common source line during the precharge period of each of the plurality of programming cycles PL1 to PLn. In an embodiment, the memory device 100 can vary the magnitude of the precharge voltage Vpre to be applied to the common source line based on the magnitude of the programming voltage applied in each of the plurality of programming cycles PL1 to PLn. Specifically, the memory device 100 can vary the magnitude of the precharge voltage Vpre to be applied to the common source line based on the magnitude of the programming voltage Vpgm applied during the programming pulse (Pgm pulse) period. As the plurality of programming cycles PL1 to PLn are executed, the magnitude of the programming voltage Vpgm can increase.

[0155] In one implementation, the memory device 100 may apply a pre-charge voltage Vpre to the common source line sequentially, starting from a preset programming cycle, during a plurality of programming cycles PL1 to PLn.

[0156] For example, when the preset programming cycle is the (n-2)th programming cycle PLn-2, ​​the memory device 100 can apply a first pre-charge voltage Vpre1 ​​to the common source line during the pre-charge period of the (n-2)th programming cycle PLn-2. However, compared with Figure 10A The examples shown differ. When the preset programming cycle is the first programming cycle PL1, the memory device 100 may apply a first pre-charge voltage Vpre1 ​​to the common source line during the pre-charge period of the first programming cycle PL1. The memory device 100 may apply a second pre-charge voltage Vpre2, which is higher than the first pre-charge voltage Vpre1, to the common source line during the pre-charge period of the (n-1)th programming cycle PLn-1. The memory device 100 may apply a third pre-charge voltage Vpre3, which is higher than the second pre-charge voltage Vpre2, to the common source line during the pre-charge period of the nth programming cycle PLn.

[0157] In the example, the increment of the precharge voltage Vpre Vpre can be set to any of various values ​​depending on the implementation method.

[0158] For example, the magnitude of the precharge voltage applied during the precharge period of the current programming cycle can be increased by a preset value compared to the magnitude of the precharge voltage applied during the precharge period of a previous programming cycle. In this case, the increment of the precharge voltage Vpre can be constant.

[0159] In other examples, the magnitude of the precharge voltage applied during the precharge period of the current programming cycle can be increased by a preset ratio compared to the magnitude of the precharge voltage applied during the precharge period of a previous programming cycle. In this case, the increment of the magnitude of the precharge voltage Vpre can be increased according to the preset ratio.

[0160] Figure 10B This is a diagram illustrating the operation of changing the amplitude of the dummy voltage according to the amplitude of the programming voltage during the programming operation of a memory device according to an embodiment of the present disclosure.

[0161] exist Figure 10B In the graph, the horizontal axis represents time, and its vertical axis represents the magnitude of the dummy voltage V_dm applied to the dummy word line.

[0162] exist Figure 10B In the middle, omission and Figure 10A The component description is the same as the component description in the document.

[0163] Reference Figure 10B The memory device 100 can apply a dummy voltage V_dm to multiple dummy word lines during the precharge period of each of the multiple programming cycles PL1 to PLn. In an embodiment, the memory device 100 can vary the magnitude of the dummy voltage V_dm to be applied to the multiple dummy word lines based on the magnitude of the programming voltage applied in each of the multiple programming cycles PL1 to PLn.

[0164] In one implementation, the memory device 100 may apply a dummy voltage V_dm sequentially to multiple dummy word lines starting from a preset programming cycle.

[0165] For example, when the preset programming cycle is the (n-2)th programming cycle PLn-2, ​​the memory device 100 can apply a first dummy voltage V_dm1 to multiple dummy word lines during the precharge period of the (n-2)th programming cycle PLn-2. However, compared with Figure 10B The example shown differs. When the preset programming cycle is the first programming cycle PL1, the memory device 100 can apply a first dummy voltage V_dm1 to the multiple dummy word lines during the precharge period of the first programming cycle PL1. The memory device 100 can apply a second dummy voltage V_dm2, which is higher than the first dummy voltage V_dm1, to the multiple dummy word lines during the precharge period of the (n-1)th programming cycle PLn-1. The memory device 100 can apply a third dummy voltage V_dm3, which is higher than the second dummy voltage V_dm2, to the multiple dummy word lines during the precharge period of the nth programming cycle PLn.

[0166] In the example, the increment of the amplitude of the dummy voltage V_dm V_dm can be set to any value from various options depending on the implementation method.

[0167] For example, the magnitude of the dummy voltage applied during the precharge period of the current programming cycle can be increased by a preset value compared to the magnitude of the dummy voltage applied during the precharge period of a previous programming cycle. In this case, the increment of the magnitude of the dummy voltage V_dm can be constant.

[0168] In other examples, the magnitude of the dummy voltage applied during the precharge period of the current programming cycle can be increased by a preset ratio compared to the magnitude of the dummy voltage applied during the precharge period of a previous programming cycle. In this case, the increment of the magnitude of the dummy voltage V_dm can be increased according to the preset ratio.

[0169] In one implementation, the memory device 100 may apply a dummy voltage V_dm to one or more of a plurality of dummy word lines during the precharge period of each of the plurality of programming cycles PL1 to PLn. For example, during the precharge period of each of the plurality of programming cycles PL1 to PLn, the memory device 100 may apply a dummy voltage V_dm to the dummy word line closest to the plurality of memory cells among the plurality of dummy word lines. The number of dummy word lines to which the dummy voltage V_dm is to be applied may be adjusted to any of a variety of values.

[0170] Figure 11A This is a diagram illustrating the operation of changing the time of applying the precharge voltage according to the amplitude of the programming voltage during the programming operation of a memory device according to an embodiment of the present disclosure.

[0171] exist Figure 11A In the graph, the horizontal axis represents time, while its vertical axis represents the magnitude of the pre-charge voltage Vpre applied to the common source line.

[0172] Reference Figure 11A The programming operation of the memory device 100 may include multiple programming cycles PL1 to PLn. Each of the multiple programming cycles PL1 to PLn may include a programming voltage application operation (PGM step) and a verification operation (verification step).

[0173] The programming voltage application operation (PGM step) included in each of the multiple programming cycles PL1 to PLn may include a pre-charge period, a programming pulse (Pgm pulse) period, and a discharge period.

[0174] The memory device 100 can apply a pre-charge voltage Vpre to the common source line for a pre-charge time Pre_T during the pre-charge period of each of the plurality of programming cycles PL1 to PLn. In an embodiment, the memory device 100 can change the time Pre_T for applying the pre-charge voltage to the common source line based on the amplitude of the programming voltage applied in each of the plurality of programming cycles PL1 to PLn. Specifically, the memory device 100 can change the time Pre_T for applying the pre-charge voltage to the common source line based on the amplitude of the programming voltage Vpgm applied during the programming pulse (Pgm pulse) period. As the plurality of programming cycles PL1 to PLn are executed, the amplitude of the programming voltage Vpgm can be increased.

[0175] In one implementation, the memory device 100 may apply a first precharge voltage Vpre1 ​​to the common source line for a first precharge time Pre_T1 during the precharge period of the (n-2)th programming cycle PLn-2. However, compared with Figure 11A Unlike the example shown, the memory device 100 may apply a first precharge voltage Vpre1 ​​to the common source line for a first precharge time Pre_T1 during the precharge period of the first programming cycle PL1. During the precharge period of the (n-1)th programming cycle PLn-1, the memory device 100 may apply a second precharge voltage Vpre2 to the common source line for a second precharge time Pre_T2 that is longer than the first precharge time Pre_T1. During the precharge period of the nth programming cycle PLn, the memory device 100 may apply a third precharge voltage Vpre3 to the common source line for a third precharge time Pre_T3 that is longer than the second precharge time Pre_T2.

[0176] In the example, the increment of the time Pre_T for applying the pre-charge voltage can be set to any value in various implementations.

[0177] For example, the time for applying the precharge voltage during the precharge period of the current programming cycle can be increased by a preset value from the time for applying the precharge voltage during the precharge period of the previous programming cycle. In this case, the increment of the precharge voltage application time Pre_T can be constant.

[0178] In other examples, the time for applying the precharge voltage during the precharge period of the current programming cycle can be increased by a preset ratio compared to the time for applying the precharge voltage during the precharge period of a previous programming cycle. In this case, the increment of the precharge voltage application time Pre_T can be increased according to the preset ratio.

[0179] In one embodiment, the amplitudes of the first pre-charge voltage Vpre1 ​​to the third pre-charge voltage Vpre3 can be equal to each other. In other embodiments, the amplitudes of the first pre-charge voltage Vpre1 ​​to the third pre-charge voltage Vpre3 can be increased according to the amplitude of the programming voltage.

[0180] Figure 11B This is a diagram illustrating the operation of changing the duration of the applied dummy voltage according to the amplitude of the programming voltage during programming operations of a memory device according to an embodiment of the present disclosure.

[0181] exist Figure 11B In the graph, the horizontal axis represents time, and the vertical axis represents the magnitude of the dummy voltage V_dm applied to the dummy word line.

[0182] exist Figure 11B In the middle, omission and Figure 11A The component description is the same as the component description.

[0183] Reference Figure 11B The memory device 100 may apply a dummy voltage V_dm to a plurality of dummy word lines for a precharge time Pre_T during the precharge period of each of the plurality of programming cycles PL1 to PLn. In an embodiment, the memory device 100 may vary the time Pre_T for applying the dummy voltage V_dm to the plurality of dummy word lines based on the magnitude of the programming voltage applied in each of the plurality of programming cycles PL1 to PLn.

[0184] In one implementation, the memory device 100 may apply a first dummy voltage V_dm1 to multiple dummy word lines for a first precharge time Pre_T1 during the precharge period of the (n-2)th programming cycle PLn-2. However, compared with Figure 11B Unlike the example shown, the memory device 100 may apply a first dummy voltage V_dm1 to multiple dummy word lines for a first precharge time Pre_T1 during the precharge period of the first programming cycle PL1. During the precharge period of the (n-1)th programming cycle PLn-1, the memory device 100 may apply a second dummy voltage V_dm2 to the multiple dummy word lines for a second precharge time Pre_T2 that is longer than the first precharge time Pre_T1. During the precharge period of the nth programming cycle PLn, the memory device 100 may apply a third dummy voltage V_dm3 to the multiple dummy word lines for a third precharge time Pre_T3 that is longer than the second precharge time Pre_T2.

[0185] In the implementation, the increment of the time Pre_T for applying the dummy voltage can be set to any of a variety of values, depending on the example.

[0186] For example, the time for applying the dummy voltage during the precharge phase of the current programming cycle can be increased by a preset value compared to the time for applying the dummy voltage during the precharge phase of a previous programming cycle. In this case, the increment of the dummy voltage application time Pre_T can be constant.

[0187] In other examples, the time for which a dummy voltage is applied during the precharge phase of the current programming cycle can be increased by a preset ratio compared to the time for which a dummy voltage is applied during the precharge phase of a previous programming cycle. In this case, the increment of the dummy voltage application time Pre_T can be increased according to the preset ratio.

[0188] In one embodiment, the amplitudes of the first dummy voltage V_dm1 to the third dummy voltage V_dm3 can be equal to each other. In other embodiments, the amplitudes of the first dummy voltage V_dm1 to the third dummy voltage V_dm3 can be increased according to the amplitude of the programming voltage.

[0189] Figure 12 This is a diagram illustrating the operation of changing at least one of the amplitude of the precharge voltage, the time of applying the precharge voltage, the amplitude of the dummy voltage, and the time of applying the dummy voltage according to the amplitude of the programming voltage in a programming operation of a memory device according to an embodiment of the present disclosure.

[0190] exist Figure 12 In the figures, the horizontal axis of each chart represents time. Furthermore, the vertical axis of the charts in the upper part of the figures represents the magnitude of the pre-charge voltage Vpre applied to the common source line, while the vertical axis of the charts in the lower part of the figures represents the magnitude of the dummy voltage V_dm applied to the dummy word line.

[0191] exist Figure 12 In the middle, omission and Figures 10A to 11B The component description is the same as the component description in the document.

[0192] Reference Figure 12 The memory device 100 may apply a first precharge voltage Vpre1 ​​to the common source line for a first precharge time Pre_T1 during the precharge period of the (n-2)th programming cycle PLn-2. The memory device 100 may also apply a first dummy voltage V_dm1 to the dummy word line simultaneously with the first precharge voltage Vpre1 ​​applied to the common source line during the precharge period of the (n-2)th programming cycle PLn-2.

[0193] Subsequently, the memory device 100 may apply a second precharge voltage Vpre2 to the common source line during the precharge period of the (n-1)th programming cycle PLn-1 for a second precharge time Pre_T2 longer than the first precharge time Pre_T1. The memory device 100 may apply a second dummy voltage V_dm2 to the dummy word line simultaneously with the application of the second precharge voltage Vpre2 to the common source line during the precharge period of the (n-1)th programming cycle PLn-1. In one embodiment, the amplitude of the first precharge voltage Vpre1 ​​may be equal to the amplitude of the second precharge voltage Vpre2. In other embodiments, the amplitude of the first dummy voltage V_dm1 may be equal to the amplitude of the second dummy voltage V_dm2.

[0194] Subsequently, the memory device 100 may apply a third precharge voltage Vpre3 to the common source line during the precharge period of the nth programming cycle PLn for a third precharge time Pre_T3 that is longer than the second precharge time Pre_T2. The memory device 100 may also apply a third dummy voltage V_dm3 to the dummy word line simultaneously with the third precharge voltage Vpre3 applied to the common source line during the precharge period of the nth programming cycle PLn.

[0195] In this case, the third pre-charge voltage Vpre3 can be a voltage higher than the second pre-charge voltage Vpre2. Furthermore, the third dummy voltage V_dm3 can be a voltage higher than the second dummy voltage V_dm2. In the example, the increment of the pre-charge voltage amplitude... The increment of the amplitude of Vpre or the dummy voltage. V_dm can be set to any of a variety of values ​​depending on the implementation. In other examples, the increment of the time for applying the pre-charge voltage Vpre or the increment of the time for applying the dummy voltage V_dm can be set to any of a variety of values.

[0196] In this implementation, as the selected word line connected to the selected memory cell gets closer to the source select line or the common source line during the precharge period, the memory device 100 can change at least one of the following: the amplitude of the precharge voltage Vpre to be applied to the common source line, the duration of applying the precharge voltage, the amplitude of the dummy voltage V_dm to be applied to the multiple dummy word lines, and the duration of applying the dummy voltage, depending on the amplitude of the programming voltage. Specifically, as the selected word line connected to the selected memory cell gets closer to the source select line or the common source line during the precharge period, the memory device 100 can increase at least one of the following: the amplitude of the precharge voltage Vpre to be applied to the common source line, the duration of applying the precharge voltage, the amplitude of the dummy voltage V_dm to be applied to the multiple dummy word lines, and the duration of applying the dummy voltage, according to a preset reference value or a preset ratio.

[0197] In addition, not limited to reference Figure 12 In the described implementation, during the precharge period of each of the plurality of programming cycles, the memory device 100 may change at least one of the amplitude of the precharge voltage to be applied to the common source line, the duration of the precharge voltage application, the amplitude of the dummy voltage to be applied to the plurality of dummy word lines, and the duration of the dummy voltage application.

[0198] Figure 13 This is a diagram illustrating the operation of changing the precharge voltage or dummy voltage according to multiple programming cycles in the programming operation of a memory device according to an embodiment of the present disclosure.

[0199] exist Figure 13 For ease of description, during the programming operation of the memory device, the first programming cycle PL1 to the ninth programming cycle PL9 are executed. Furthermore, in... Figure 13 The example only illustrates the precharge periods PL1_P to PL9_P for each of the multiple programming loops.

[0200] Reference Figure 13The multiple programming cycles PL1 to PL9 may include multiple first programming cycles PL1_Group, multiple second programming cycles PL2_Group, and multiple third programming cycles PL3_Group. In an embodiment, the multiple first programming cycles PL1_Group may include pre-charge periods PL1_P to PL3_P from the first programming cycle to the third programming cycle. The multiple second programming cycles PL2_Group may include pre-charge periods PL4_P to PL6_P from the fourth programming cycle to the sixth programming cycle. The multiple third programming cycles PL3_Group may include pre-charge periods PL7_P to PL9_P from the seventh programming cycle to the ninth programming cycle.

[0201] In an implementation, the amplitude of the pre-charge voltage applied to the common source line or the amplitude of the dummy voltage applied to the multiple dummy word lines during the pre-charge period of each of the plurality of first programming cycles PL1_Group can be increased according to a preset reference value or a preset ratio. The amplitude of the pre-charge voltage applied to the common source line or the amplitude of the dummy voltage applied to the multiple dummy word lines during the pre-charge period of each of the plurality of second programming cycles PL2_Group can be constant. In an implementation, the amplitude of the pre-charge voltage applied to the common source line or the amplitude of the dummy voltage applied to the multiple dummy word lines during the pre-charge period of each of the plurality of third programming cycles PL3_Group can be increased according to a preset reference value or a preset ratio.

[0202] In other words, in some programming cycles PL1 through PL9, the magnitude of the pre-charge voltage applied to the common source line or the magnitude of the dummy voltage applied to the multiple dummy word lines can be increased according to a preset reference value or a preset ratio. Unlike this example, in some other programming cycles PL1 through PL9, the magnitude of the pre-charge voltage applied to the common source line or the magnitude of the dummy voltage applied to the multiple dummy word lines can be constant.

[0203] Furthermore, in some programming cycles PL1 through PL9, the time for applying the pre-charge voltage to the common source line or the time for applying the dummy voltage to the multiple dummy word lines can be increased according to a preset reference value or a preset ratio. Unlike this example, in some other programming cycles PL1 through PL9, the time for applying the pre-charge voltage to the common source line or the time for applying the dummy voltage to the multiple dummy word lines can be constant.

[0204] Figure 14 This illustrates an embodiment according to the present disclosure. Figure 2 A diagram illustrating the implementation of the control logic.

[0205] Reference Figure 14 , Figure 2 The memory device 100 may include a memory cell array 110, an address decoder 121, a voltage generator 122, and control logic 1400. The memory cell array 110, address decoder 121, and voltage generator 122 can respectively interact with... Figure 2 The memory cell array 110, address decoder 121, and voltage generator 122 shown are configured and operate in the same manner. Control logic 1400 can be implemented as follows: Figure 2 A component of the control logic 130 shown.

[0206] The control logic 1400 may include a precharge voltage control signal generator 1410, a dummy word line controller 1420, and a common source line controller 1430.

[0207] The precharge voltage control signal generator 1410 can generate programming voltage control signals to indicate the generation of multiple voltages to be used in the programming operation. For example, the precharge voltage control signal generator 1410 can generate a precharge voltage control signal OPSIG_Pre to generate precharge-related voltages at various levels as voltages used during the precharge period, and can provide the generated precharge voltage control signal OPSIG_Pre to the voltage generator 122. The voltage generator 122 can generate various precharge-related voltages Vop to be used during the precharge period in response to the precharge voltage control signal OPSIG_Pre, and can provide the generated precharge-related voltages Vop to the address decoder 121.

[0208] The dummy word line controller 1420 can control the dummy voltage to be applied to multiple dummy word lines. The dummy word line controller 1420 can provide the address decoder 121 with a dummy word line control signal D_WL_Pre for applying dummy voltages to the multiple dummy word lines. The address decoder 121 can, in response to the dummy word line control signal D_WL_Pre, provide the memory cell array 110 with a precharge-related voltage Vop generated by the voltage generator 122.

[0209] The common source line controller 1430 can control the pre-charge voltage to be applied to the common source line. In one embodiment, the common source line controller 1430 can apply a pre-charge voltage CSL_Pre to the common source line of the memory cell array 110.

[0210] Figure 15 This is a flowchart illustrating the programming operation of a memory device according to an embodiment of the present disclosure.

[0211] Reference Figure 15In operation S1501, the memory device 100 can apply a pre-charge voltage to the common source line based on the magnitude of the programming voltage applied to the selected word line. The memory device 100 can change the magnitude of the pre-charge voltage based on the magnitude of the programming voltage applied to the selected word line, and then apply the pre-charge voltage to the common source line. For example, as the magnitude of the programming voltage increases while executing multiple programming cycles, the memory device 100 can increase the magnitude of the pre-charge voltage to be applied to the common source line. Furthermore, as the magnitude of the programming voltage increases, the memory device 100 can increase the time for applying the pre-charge voltage to the common source line.

[0212] In operation S1503, the memory device 100 can apply a dummy voltage to one or more dummy word lines among a plurality of dummy word lines based on the magnitude of the programming voltage. The memory device 100 can change the magnitude of the dummy voltage based on the magnitude of the programming voltage applied to the selected word line, and then apply the dummy voltage to one or more dummy word lines. For example, as the magnitude of the programming voltage increases while executing multiple programming cycles, the memory device 100 can increase the magnitude of the dummy voltage to be applied to one or more dummy word lines. Furthermore, as the magnitude of the programming voltage increases, the memory device 100 can increase the time for applying the dummy voltage to one or more dummy word lines.

[0213] In operation S1505, memory device 100 can apply a programming voltage to the selected memory cell.

[0214] In operation S1507, memory device 100 can verify the programming status of the selected memory cell. For example, memory device 100 can apply a verification voltage to the selected memory cell.

[0215] Figure 16 This is a diagram illustrating an erase operation performed on a plurality of memory cells according to an embodiment of the present disclosure.

[0216] exist Figure 16 In the graph, the horizontal axis represents the threshold voltage Vth of the memory cell, and its vertical axis represents the number of memory cells (cell count).

[0217] Reference Figure 16The threshold voltages of multiple memory cells that have completed programming operations can have a final programming state. The final programming state can include multiple programming states. Multiple programming states can be specified based on the number of data bits stored in a memory cell. For example, when programming data using a three-level cell (TLC) scheme that stores three bits of data in a memory cell, multiple programming states can indicate an initial state E and first programming states PV1 to seventh programming states PV7. After programming operations have been performed, the threshold voltages of multiple memory cells can be determined based on the data to be stored in the memory cells. Each memory cell can have one of multiple programming states as its target programming state based on the data to be stored in the corresponding memory cell. Figure 16 The description will be based on programming multiple memory cells using the TLC scheme.

[0218] Each memory cell that has completed the programming operation can have a threshold voltage corresponding to an initial state E and one of the first programming states PV1 to the seventh programming state PV7. Thereafter, the memory device 100 can perform an erase operation on the plurality of memory cells that have completed the programming operation. The erase operation can be an operation to erase the data stored in the plurality of memory cells. Specifically, the erase operation can be an operation to reduce the threshold voltage of the plurality of memory cells to an erase state ER. For example, during the erase operation, the threshold voltage of each of the plurality of memory cells programmed to have a threshold voltage corresponding to an initial state E and one of the first programming states PV1 to the seventh programming state PV7 can be reduced to the threshold voltage corresponding to the erase state ER.

[0219] Here, because the characteristics of each memory cell are different, the degree to which the threshold voltage of multiple memory cells decreases during the erase operation can differ from one another. For example, during an erase operation on a memory cell having a threshold voltage corresponding to the first programming state PV1, the degree to which the threshold voltage of each memory cell decreases to the threshold voltage corresponding to the erase state ER can differ from one another. That is, because there are memory cells whose threshold voltage decreases significantly during the erase operation on multiple memory cells, the threshold voltage distribution corresponding to the erase state ER can be formed to be relatively wide. Furthermore, a memory cell whose threshold voltage decreases significantly compared to other memory cells during the erase operation on multiple memory cells can be named an "over-erased memory cell". Alternatively, a memory cell whose threshold voltage is lower than the threshold voltage corresponding to the initial state E during the erase operation can be named an "over-erased memory cell".

[0220] Subsequently, the memory device 100 can perform a soft programming operation on the multiple memory cells that have undergone the erase operation. The soft programming operation can be an operation of increasing the threshold voltage of the multiple memory cells. Specifically, the soft programming operation can be an operation of increasing the threshold voltage of the erased memory cells to a threshold voltage corresponding to the initial state E or higher. For example, the memory device 100 can apply a soft programming voltage to the word lines connected to the multiple memory cells during the soft programming operation. Specifically, during the soft programming operation, the threshold voltage of the multiple memory cells corresponding to the erase state ER can be increased to a threshold voltage corresponding to the soft programming state SOC.

[0221] Figure 17 It is a diagram used to describe pre-programmed operations according to embodiments of the present disclosure.

[0222] exist Figure 17 In the graph, the horizontal axis represents the threshold voltage Vth of the dummy memory cell, and its vertical axis represents the number of dummy memory cells (cell count).

[0223] Virtual memory units can be as follows Figure 6 The diagram shows dummy memory cells D_MC1 to D_MC1 connected between memory cells MC1+1 to MCm and the source select line SSL. The dummy memory cells can be as follows: Figure 6 The virtual memory cells D_MCm+1 to D_MCn are connected between memory cells MC1+1 to MCm and drain selection line DSL.

[0224] Reference Figure 17 Before performing programming operations on multiple memory cells, the dummy memory cells may have a threshold voltage corresponding to a first dummy state d_s1. Then, after performing programming, erasing, and soft programming operations on the multiple memory cells, the dummy memory cells may have a threshold voltage corresponding to a second dummy state d_s2. The threshold voltage corresponding to the second dummy state d_s2 may have a wider threshold voltage distribution than the threshold voltage corresponding to the first dummy state d_s1. Specifically, as referenced above... Figure 10B and Figure 11B As described, the threshold voltage distribution of the dummy memory cells can be altered by applying dummy voltages to multiple dummy word lines during the precharge phase of each of the multiple programming cycles. Furthermore, the threshold voltage distribution of the dummy memory cells can be changed after performing erase and soft programming operations on the multiple memory cells. That is, after performing programming, erase, and soft programming operations on the multiple memory cells, the dummy memory cells can have a wider threshold voltage distribution than before the programming operations were performed on the multiple memory cells.

[0225] Furthermore, after the threshold voltage of the dummy memory cell has changed from the threshold voltage distribution in the first dummy state d_s1 to the threshold voltage distribution in the second dummy state d_s2, the memory device 100 can perform programming operations on multiple memory cells. Here, during the precharge period of each of the multiple programming cycles included in the programming operation, a dummy voltage can be applied to the dummy word line connected to the dummy memory cell. However, as the threshold voltage distribution of the dummy memory cell widens, the number of dummy memory cells with threshold voltages lower than the dummy voltage can increase. That is, since the number of dummy memory cells turned on when the dummy voltage is applied decreases, the channel potential may not rise proportionally to the applied dummy voltage.

[0226] Therefore, the memory device 100 can perform a pre-programming operation on dummy memory cells to adjust the threshold voltage distribution of the dummy memory cells. The pre-programming operation may be an operation of identifying the threshold voltage of the dummy memory cells using a pre-verification voltage and performing multiple pre-programming cycles on a first dummy memory cell having a threshold voltage less than or equal to the pre-verification voltage. Each of the multiple pre-programming cycles may include a pre-programming voltage application operation that increases the threshold voltage of the first dummy memory cell and a pre-verification operation that identifies the threshold voltage of the first dummy memory cell.

[0227] The memory device 100 can perform a pre-programming operation on a dummy memory cell and then perform a programming operation on a plurality of memory cells, thereby adjusting the channel potential so that the channel potential increases proportionally to the dummy voltage applied to the dummy word line during pre-charging.

[0228] In one embodiment, the memory device 100 may determine whether to perform a pre-programming operation based on the location of a selected word line connected to a memory cell selected from a plurality of memory cells. Specifically, when the location of the selected word line is the first word line of a memory block including the selected word line, a pre-programming operation is performed on the dummy memory cell, and then a programming operation can be performed on the selected memory cell.

[0229] Reference Figure 17In the central part of the diagram, the memory device 100 can terminate programming, erasing, and soft programming operations performed on multiple memory cells, after which a pre-verification voltage pre_vfy is used to identify the threshold voltage of the dummy memory cells. Specifically, the memory device 100 can perform multiple pre-programming cycles on a first dummy memory cell having a threshold voltage less than or equal to the pre-verification voltage pre_vfy. Furthermore, after multiple pre-programming cycles have been performed, the dummy memory cell can have a threshold voltage greater than the pre-verification voltage pre_vfy. The threshold voltage greater than the pre-verification voltage pre_vfy can have a threshold voltage distribution corresponding to a third dummy state d_s3. By performing multiple pre-programming cycles on the first dummy memory cell, the threshold voltage distribution of the dummy memory cell can change from a second dummy state d_s2 to a third dummy state d_s3. That is, the threshold voltage distribution of the dummy memory cell can be narrowed by performing multiple pre-programming cycles on the first dummy memory cell.

[0230] Figure 18 This is a diagram used to describe preprogramming operations including multiple preprogramming loops according to embodiments of the present disclosure.

[0231] exist Figure 18 In the graph, the horizontal axis represents time, and its vertical axis represents the voltage V applied to the dummy word line.

[0232] Reference Figure 18 The preprogramming operation may include using a pre-verification voltage pre_vfy and multiple preprogramming cycles pre_PL1 to pre_PLn to identify the threshold voltage of the dummy memory cell. Each of the multiple preprogramming cycles pre_PL1 to pre_PLn may include a preprogramming voltage application operation (prePGM) and a pre-verification operation (pre-verification).

[0233] The preprogramming voltage application operation (prePGM) can be an operation that applies a preprogramming voltage pre_p to the dummy word line connected to the dummy memory cell. Specifically, the preprogramming voltage application operation (prePGM) can be an operation that uses the preprogramming voltage pre_p to increase the threshold voltage of the first dummy memory cell. The preverification operation (preverification) can be an operation that applies a preverification voltage pre_vfy to the dummy word line connected to the dummy memory cell. Specifically, the preverification operation (preverification) can be an operation that uses the preverification voltage pre_vfy to identify the threshold voltage of the first dummy memory cell.

[0234] In one implementation, the memory device 100 can identify a first dummy memory cell among the dummy memory cells that has a threshold voltage less than or equal to the pre-verification voltage pre_vfy. Thereafter, the memory device 100 can perform multiple pre-programming loops on the first dummy memory cell.

[0235] In one embodiment, the memory device 100 may apply a first preprogramming voltage pre_p1 to the dummy word line connected to the dummy memory cell during the preprogramming voltage application operation (prePGM) of the first preprogramming cycle pre_PL1. The amplitude of the first preprogramming voltage pre_p1 may be less than Figure 7 The amplitude of the first programming voltage Vpgm1 is shown. Here, the memory device 100 can apply a preprogramming enable voltage to the bit lines connected to the first dummy memory cell. The preprogramming enable voltage can be a ground voltage. The memory device 100 can apply a preprogramming disable voltage to the bit lines connected to the other dummy memory cells besides the first dummy memory cell. The preprogramming disable voltage can be a power supply voltage.

[0236] Subsequently, the memory device 100 may apply a pre-verification voltage pre_Vfy to the dummy word line connected to the dummy memory cell during the pre-verification operation (pre-verification) of the first pre-programming cycle pre_PL1. Here, the pre-programming operation may be terminated when the threshold voltage of the first dummy memory cell is greater than the pre-verification voltage pre_vfy. However, when the first dummy memory cell has a threshold voltage less than or equal to the pre-verification voltage pre_vfy, the second pre-programming cycle pre_PL2 may be executed.

[0237] During the preprogramming voltage application operation (prePGM) of the second preprogramming cycle pre_PL2, the memory device 100 may apply a second preprogramming voltage pre_p2 to the dummy word line connected to the dummy memory cell. The second preprogramming voltage pre_p2 may be a unit pre-voltage increase from the first preprogramming voltage pre_p1. The voltage of pre_p. Unit prevoltage. The magnitude of pre_p can be less than Figure 7 The unit voltage shown The amplitude of Vpgm. Thereafter, the memory device 100 can perform the pre-verification operation (pre-verification) of the second pre-programming loop pre_PL2 in the same manner as the pre-verification operation (pre-verification) of the first pre-programming loop Pre_PL1.

[0238] Subsequently, memory device 100 can execute subsequent preprogramming cycles in the same manner as the second preprogramming cycle pre_PL2. When the threshold voltage of the first dummy memory cell is greater than the pre-verification voltage pre_vfy, memory device 100 can terminate the preprogramming operation and can perform programming operations on multiple memory cells.

[0239] In this implementation, the preprogramming voltage can be determined based on the Incremental Step Pulse Programming (ISPP) method. As multiple preprogramming cycles pre_PL1 to pre_PLn are repeated, the level of the preprogramming voltage can be gradually increased or decreased. Under the control of the memory controller 200, the number of times the preprogramming voltage is applied in each preprogramming cycle, the voltage level of the preprogramming voltage, the voltage application time, etc., can be determined in various ways.

[0240] Figure 19 This is a flowchart illustrating a pre-programmed operation according to an embodiment of the present disclosure.

[0241] Reference Figure 19 During operation S1901, the memory device 100 can perform an erase operation on multiple memory cells. During the erase operation, the threshold voltage of the multiple memory cells can be reduced to the erase state.

[0242] During operation S1903, memory device 100 can perform software programming operations on multiple memory cells.

[0243] In operation S1905, the memory device 100 can use a pre-verification voltage to identify threshold voltages of a plurality of dummy memory cells. In one embodiment, the memory device 100 can identify a first dummy memory cell among the dummy memory cells that has a threshold voltage less than or equal to the pre-verification voltage pre_vfy.

[0244] In operation S1907, the memory device 100 may perform a preprogramming voltage application operation on a first dummy memory cell among a plurality of dummy memory cells that has a threshold voltage less than or equal to the pre-verification voltage. During the preprogramming voltage application operation, the threshold voltage of the first dummy memory cell may be increased.

[0245] In operation S1909, the memory device 100 can identify whether the threshold voltage of the first dummy memory cell is greater than the pre-verification voltage during the pre-verification operation. When the threshold voltage of the first dummy memory cell is greater than the pre-verification voltage, the process can proceed to operation S1911. Conversely, when the threshold voltage of the first dummy memory cell is less than or equal to the pre-verification voltage, the process can proceed to operation S1913.

[0246] In operation S1911, when the threshold voltage of the first dummy memory cell is greater than the pre-verification voltage pre_vfy, the memory device 100 can terminate the pre-programming operation and can perform programming operations on multiple memory cells.

[0247] In operation S1913, when the threshold voltage of the first dummy memory cell is less than or equal to the pre-verification voltage, the memory device 100 may increase the amplitude of the pre-programming voltage by one unit pre-voltage. Thereafter, the memory device 100 may use the pre-programming voltage increased by one unit pre-voltage to perform a pre-programming voltage application operation on the first dummy memory cell.

[0248] Figure 20 This illustrates an embodiment according to the present disclosure. Figure 1 A diagram of the memory controller.

[0249] Figure 20 The memory controller 1600 can be Figure 1 The memory controller 200.

[0250] Reference Figure 20 The memory controller 1600 may include a processor 1610, RAM 1620, error correction circuitry 1630, host interface 1640, ROM 1650, and flash memory interface 1660.

[0251] The processor 1610 can control the overall operation of the memory controller 1600. The RAM 1620 can be used as a buffer memory, cache memory, or working memory of the memory controller 1600.

[0252] Error correction circuit 1630 can perform error correction. Error correction circuit 1630 can perform error correction code (ECC) encoding based on data to be written to memory device 100 via flash interface 1660. ECC-encoded data can be transmitted to memory device 100 via flash interface 1660. Error correction circuit 1630 can perform error correction code decoding (ECC decoding) on ​​data received from memory device 100 via flash interface 1660. In embodiments, error correction circuit 1630 can be included as a component of flash interface 1660 within flash interface 1660.

[0253] ROM 1650 can store various types of information required for the operation of memory controller 1600 in the form of firmware.

[0254] The memory controller 1600 can communicate with external devices (e.g., host 300, application processor, etc.) via host interface 1640.

[0255] The memory controller 1600 can communicate with the memory device 100 via the flash memory interface 1660. The memory controller 1600 can send commands, addresses, control signals, etc., to the memory device 100 and receive data from the memory device 100 via the flash memory interface 1660. In this example, the flash memory interface 1660 may include a NAND interface.

[0256] Figure 21 This is a block diagram illustrating a memory card system that applies a memory system according to an embodiment of the present disclosure.

[0257] Reference Figure 21 The memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

[0258] Memory controller 2100 is coupled to memory device 2200. Memory controller 2100 can access memory device 2200. For example, memory controller 2100 can control read operations, write operations, erase operations, and background operations of memory device 2200. Memory controller 2100 can provide an interface between memory device 2200 and a host computer. Memory controller 2100 can run firmware for controlling memory device 2200. Memory controller 2100 can be configured with the above-mentioned reference... Figure 1 The memory controller 200 described herein is implemented in the same manner. The memory device 2200 can be implemented in the same manner as described above. Figure 1 The memory device 100 described is implemented in the same manner.

[0259] In some implementations, the memory controller 2100 may include components such as RAM, a processor, a host interface, a memory interface, and error correction circuitry.

[0260] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) based on specific communication standards or protocols. In embodiments, the memory controller 2100 can communicate with external devices via at least one of the following communication standards or interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Fast (PCI-e or PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and High Speed ​​Non-Volatile Memory (NVMe). In embodiments, connector 2300 can be defined by at least one of the aforementioned communication standards or interfaces.

[0261] In an implementation, the memory device 2200 may be implemented as any of the following non-volatile memory devices: electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), or spin-transfer torque magnetic RAM (STT-MRAM).

[0262] The memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to configure a memory card. For example, the memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to configure memory cards such as PC cards (Personal Computer Memory Card International Association: PCMCIA), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC or eMMC), SD cards (SD, mini SD, micro SD or SDHC), or universal flash memory (UFS).

[0263] Figure 22 This is a block diagram illustrating a solid-state drive (SSD) system that applies a memory system according to an embodiment of the present disclosure.

[0264] Reference Figure 22The SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 can exchange signals with the host 3100 through a signal connector 3001 and can receive power through a power connector 3002. The SSD 3200 may include an SSD controller 3210, multiple flash memory modules 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0265] According to embodiments of this disclosure, the SSD controller 3210 can perform the above-mentioned... Figure 1 The functions of the memory controller 200 are described.

[0266] SSD controller 3210 can control multiple flash memory modules 3221 to 322n in response to signals received from host 3100. In implementations, these signals can be signals based on the interface between host 3100 and SSD 3200. For example, the signals can be signals defined according to at least one of the following communication standards or interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Fast (PCI-e or PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and High Speed ​​Non-Volatile Memory (NVMe).

[0267] Auxiliary power supply 3230 can be connected to host 3100 via power connector 3002. Auxiliary power supply 3230 can be supplied with power from host 3100 and can be charged. When a stable power supply from host 3100 is not possible, auxiliary power supply 3230 can supply power to SSD 3200. In implementations, auxiliary power supply 3230 can be located inside or outside SSD 3200. For example, auxiliary power supply 3230 can be located within the motherboard and can provide auxiliary power to SSD 3200.

[0268] Buffer memory 3240 serves as a buffer memory for SSD 3200. For example, buffer memory 3240 may temporarily store data received from host 3100 or data received from multiple flash memory modules 3221 to 322n, or it may temporarily store metadata (e.g., a mapping table) of flash memory modules 3221 to 322n. Buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0269] Figure 23 This is a block diagram illustrating a user system that applies a memory system according to an embodiment of the present disclosure.

[0270] Reference Figure 23 The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0271] Application processor 4100 can run components included in user system 4000, operating system (OS), or user programs. In some implementations, application processor 4100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 4000. Application processor 4100 may be provided as a system-on-a-chip (SoC).

[0272] Memory module 4200 can be used as main memory, working memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In embodiments, application processor 4100 and memory module 4200 may be packaged based on a package stack (POP) and then provided as a single semiconductor package.

[0273] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communications such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, or Wi-Fi. In some implementations, network module 4300 may be included in application processor 4100.

[0274] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can send the data stored in storage module 4400 to application processor 4100. In embodiments, storage module 4400 can be implemented as a non-volatile semiconductor memory device, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional (3D) structure. In embodiments, storage module 4400 can be provided as a removable storage medium (i.e., a removable drive) such as a memory card of user system 4000 or an external drive.

[0275] In an implementation, the storage module 4400 may include a plurality of non-volatile memory devices, each of which may be configured as described above. Figure 1 The memory device 100 described herein operates in the same manner. The storage module 4400 can operate in the same manner as described above. Figure 1 The memory system 50 described operates in the same manner.

[0276] User interface 4500 may include an interface for inputting data or instructions to application processor 4100 or outputting data to external devices. In embodiments, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric device. User interface 4500 may also include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active-matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0277] According to this disclosure, a memory device for performing programming operations and a method for operating the memory device are provided, which can improve disturbances that occur during programming operations.

[0278] Exemplary embodiments have been disclosed herein, and although specific terminology has been used, the embodiments are used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, as will be apparent to those skilled in the art at the time of filing this application, unless otherwise specifically stated, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various modifications in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims. Furthermore, embodiments may be combined to form additional embodiments.

[0279] Cross-references to related applications

[0280] This application claims priority to Korean Patent Application No. 10-2021-0091838, filed on July 13, 2021, and Korean Patent Application No. 10-2021-0190111, filed on December 28, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: Multiple memory cells are connected between a common source line and a bit line; The peripheral circuitry executes multiple programming cycles, each programming cycle including a programming voltage application operation that applies a programming voltage to a memory cell selected from the plurality of memory cells and a verification operation that verifies the programming state of the selected memory cell. The programming voltage application operation includes a pre-charge period, a programming pulse period, and a discharge period. as well as Control logic, which controls the peripheral circuitry to: During the pre-charge period, a pre-charge voltage is applied to the common source line, and at least one of the amplitude of the pre-charge voltage and the duration of applying the pre-charge voltage to the common source line is changed according to the amplitude of the programming voltage. During the programming pulse period and the discharge period, a ground voltage is applied to the common source line.

2. The memory device according to claim 1, wherein, The control logic controls the peripheral circuitry to apply the pre-charge voltage to the common source line in a portion of the programming loops, starting from a preset programming loop, among the plurality of programming loops.

3. The memory device according to claim 1, wherein, The peripheral circuit applies programming voltages of different amplitudes in each programming cycle, and The control logic controls the peripheral circuit to increase the magnitude of the programming voltage as the programming cycle proceeds, and to increase at least one of the magnitude of the pre-charge voltage and the duration of applying the pre-charge voltage as the magnitude of the programming voltage increases.

4. The memory device according to claim 3, wherein, The increment of at least one of the amplitude of the pre-charge voltage and the time for applying the pre-charge voltage increases according to a preset reference value or a preset ratio.

5. The memory device according to claim 1, wherein, The control logic controls the peripheral circuitry to increase at least one of the magnitude of the precharge voltage and the duration of the precharge voltage application as the selected memory cell gets closer to the common source line.

6. The memory device according to claim 1, in, Each of the plurality of programming loops includes a plurality of first programming loops and a plurality of second programming loops. The control logic controls the peripheral circuitry to change at least one of the amplitude of the pre-charge voltage and the timing of applying the pre-charge voltage to the common source line during the programming voltage application operation in each of the plurality of first programming cycles. The control logic controls the peripheral circuitry to maintain the amplitude of the precharge voltage and the duration of applying the precharge voltage to the common source line during the programming voltage application operation in each of the plurality of second programming cycles.

7. A memory device comprising: Multiple memory cell strings, each memory cell string including multiple memory cells connected between a common source line and a bit line, and multiple dummy memory cells connected between the multiple memory cells and the common source line; The peripheral circuitry executes multiple programming cycles, each programming cycle including a programming voltage application operation that applies a programming voltage to a memory cell selected from the plurality of memory cells and a verification operation that verifies the programming state of the selected memory cell. The programming voltage application operation includes a pre-charge period, a programming pulse period, and a discharge period. as well as Control logic, which controls the peripheral circuitry to: During the pre-charging period, Apply a pre-charge voltage to the common source line. A dummy voltage is applied to at least one of the dummy word lines connected to the plurality of dummy memory cells, and Based on the amplitude of the programming voltage, at least one of the following is changed: the amplitude of the pre-charge voltage, the duration of applying the pre-charge voltage to the common source line, the amplitude of the dummy voltage, and the duration of applying the dummy voltage to the at least one dummy word line. During the programming pulse period and the discharge period, A ground voltage is applied to the common source line and the at least one dummy word line.

8. The memory device according to claim 7, wherein, The control logic controls the peripheral circuitry to apply the dummy voltage to the at least one dummy word line during a portion of the programming loops, starting from a preset programming loop, within the plurality of programming loops.

9. The memory device according to claim 7, wherein, The peripheral circuit applies programming voltages of different amplitudes in each programming cycle, and The control logic controls the peripheral circuit to increase the magnitude of the programming voltage as the programming cycle progresses, and to increase at least one of the magnitude of the dummy voltage and the duration of applying the dummy voltage as the magnitude of the programming voltage increases.

10. The memory device according to claim 7, wherein, The control logic controls the peripheral circuitry to increase at least one of the magnitude of the dummy voltage and the duration of the dummy voltage application as the selected memory cell approaches the common source line.

11. The memory device according to claim 7, wherein, The virtual memory cell connected to the at least one virtual word line is the one closest to the plurality of virtual memory cells among the plurality of memory cells.

12. The memory device according to claim 7, wherein, The peripheral circuitry also performs an erase operation to erase the data stored in the plurality of memory cells before the programming loop, and The control logic controls the peripheral circuitry after the erase operation to: Prior to the programming loop, a pre-verification voltage is used to identify the threshold voltage of the plurality of dummy memory cells, and Multiple pre-programming loops are executed on the first dummy memory cell among the plurality of dummy memory cells, which has a threshold voltage less than or equal to the pre-verification voltage.

13. The memory device according to claim 12, wherein, Each of the plurality of preprogrammed loops includes: The preprogrammed voltage application operation increases the threshold voltage of the first dummy memory cell using a preprogrammed voltage, and The pre-verification operation uses the pre-verification voltage to identify the threshold voltage of the first dummy memory cell.

14. The memory device according to claim 13, wherein, The control logic controls the peripheral circuitry to execute a subsequent preprogramming loop in one of the plurality of preprogramming loops when a dummy memory cell in the first dummy memory cell has a threshold voltage less than or equal to the pre-verification voltage.

15. The memory device according to claim 14, wherein, The control logic further controls the peripheral circuitry to increase the amplitude of the preprogrammed voltage by a unit pre-voltage as the preprogramming cycle proceeds.

16. The memory device according to claim 14, wherein, The control logic further controls the peripheral circuitry to terminate the pre-programming loop and execute the plurality of programming loops when the threshold voltage of the first dummy memory cell is greater than the pre-verification voltage.

17. The memory device according to claim 7, wherein, Each of the plurality of memory cell strings further includes a second dummy memory cell connected between the plurality of memory cells and the bit line. Specifically, the peripheral circuitry also performs an erase operation to erase the data stored in the plurality of memory cells before the programming loop, and Wherein, the control logic controls the peripheral circuit to: after the erasure operation is terminated. Before the programming loop, a pre-verification voltage is used to identify the threshold voltage of the second dummy memory cell, and Multiple preprogramming loops are performed on the second dummy memory cells that have a threshold voltage less than or equal to the pre-verification voltage.

18. A method of operating a memory device comprising a plurality of memory cell strings, each memory cell string comprising a plurality of memory cells connected between a common source line and a bit line, a source selection transistor connected to a source select line between the common source line and the plurality of memory cells, a drain selection transistor connected to a drain select line between the bit line and the plurality of memory cells, and a plurality of dummy memory cells connected between the plurality of memory cells and the source selection transistor, wherein a plurality of programming cycles of the memory device each comprises a programming voltage application operation and a verification operation, the programming voltage application operation comprising a precharge period, a programming pulse period, and a discharge period, the method comprising the following steps: A first pre-charge voltage is applied to the common source line during the pre-charge period of the first programming cycle in the plurality of programming cycles; During the precharge period in the first programming cycle, a first dummy voltage is applied to at least one of the dummy word lines that are respectively connected to the plurality of dummy memory cells; During the pre-charge period in the second programming cycle following the first programming cycle in the plurality of programming cycles, a second pre-charge voltage higher than the first pre-charge voltage is applied to the common source line; as well as During the precharge period in the second programming cycle, a second dummy voltage higher than the first dummy voltage is applied to the at least one dummy word line. During the programming pulse period and the discharge period, the common source line and the at least one dummy word line are grounded.

19. The method according to claim 18, The method also includes the following steps: The plurality of programming cycles are executed, each programming cycle including applying a programming voltage to a memory cell selected from the plurality of memory cells. The amplitude of the programming voltage increases as the programming cycle proceeds.

20. The method according to claim 19, wherein, The step of applying the second pre-charge voltage includes the following steps: applying the second pre-charge voltage for a longer time than the time for which the first pre-charge voltage is applied to the common source line, and The step of applying the second dummy voltage includes the following steps: applying the second dummy voltage for a longer time than applying the first dummy voltage to the at least one dummy word line.

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