Apparatus, system and method for enforcing error checking and clearing readouts

Abstract

The present application relates to devices, systems, and methods for a forced error check and clean readout. A memory can perform a sequence of ECS operations to read a codeword, detect and correct any errors, and write the corrected codeword back to the memory array. ECS circuitry can count detected errors and set values of one or more ECS registers in a mode register if the count exceeds a threshold filter at the end of an ECS cycle. The memory also includes a forced ECS readout circuit that sets the values in the ECS registers in response to a command, e.g., from a controller.

Description

Technical Field

[0001] This application relates to semiconductor devices, and more specifically, to apparatus, systems, and methods for forcibly checking for errors and clearing readouts. Background Technology

[0002] This disclosure generally relates to semiconductor devices, such as semiconductor memory devices. A semiconductor memory device may include a plurality of memory cells for storing information. The stored information may be encoded as binary data, and each memory cell may store a single bit of information. Information in the memory cell may decay or be altered due to various errors, which may result in one or more incorrect bits of information (e.g., bits having a different state than the originally written bits) being read from the memory device.

[0003] There are numerous applications that can be used to ensure high fidelity of information read from memory. Memory devices may include error correction circuitry that can determine whether information read from a memory cell contains any errors compared to data written into the memory cell, and can correct any errors found. The memory device may periodically use the error correction circuitry to repair errors in the information stored within the memory array by scanning each memory cell of the memory array. The device may present information about the number of errors corrected after scanning each memory cell. However, this process can be time-consuming and dependent on locating a certain number of errors. The ability to generate such information in a controlled manner may be suitable. Summary of the Invention

[0004] In one aspect, this application relates to an apparatus comprising: an error correction code (ECC) circuit configured to detect whether a codeword read from a memory array contains an error; a mode register containing a register value; an error checking and clearing (ECS) circuit configured to change a count value based on the number of times the ECC circuit detects an error and configured to set the register value based on the count value; and a forced ECS readout circuit configured to set the register value based on an external command.

[0005] On the other hand, this application relates to a device comprising: a mode register containing an Error Check and Clear (ECS) register value; and a forced ECS readout circuit configured to receive an external command and set the ECS register value in response to the external command.

[0006] On the other hand, this application relates to a system comprising: a memory including: a mode register containing an Error Check and Clear (ECS) register; and forced ECS readout circuitry configured to set the value of the ECS register based on a command; and a controller including: an ECS test circuitry configured to provide the command; and an ECS check circuitry configured to check the ECS register in the mode register.

[0007] On the other hand, this application relates to an apparatus comprising: an error checking and clearing (ECS) test circuit configured to provide a multipurpose command (MPC) to a memory; and an ECS check circuit configured to read the ECS register of the mode register of the memory.

[0008] In another aspect, this application relates to a method comprising: receiving an Error Check and Clear (ECS) forced read command at a memory; and setting a register in a mode register of the memory based on the ECS forced read command. Attached Figure Description

[0009] Figure 1 This is a block diagram of a semiconductor device according to some embodiments of the present disclosure.

[0010] Figure 2 This is a block diagram of a memory system according to some embodiments of the present disclosure.

[0011] Figure 3 This is a block diagram of an ECS circuit according to some embodiments of the present disclosure.

[0012] Figure 4 This is a block diagram of an example memory storage body according to some embodiments of the present disclosure.

[0013] Figure 5 This is a block diagram of a method according to some embodiments of the present disclosure. Detailed Implementation

[0014] The following description of certain embodiments is exemplary in nature and is in no way intended to limit the scope of this disclosure or its application or use. In the following detailed description of embodiments of the systems and methods of the invention, reference is made to the accompanying drawings, which form a part of this document, and to specific embodiments of the described systems and methods illustrated by way of description. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed systems and methods, and it should be understood that other embodiments may be utilized, and structural and logical changes may be made without departing from the spirit and scope of this disclosure. Furthermore, for clarity, detailed descriptions of certain features will not be elaborated where they would be obvious to those skilled in the art, so as not to obscure the description of embodiments of this disclosure. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of this disclosure is defined only by the appended claims.

[0015] The memory device may include a memory array having multiple memory cells, each memory cell located at the intersection of word lines (rows) and number lines (columns). During a read or write operation, a row may be activated, and data may be read from or written to memory cells along the activated row. Each row may contain a memory cell storing multiple data bits and multiple parity information bits (e.g., data bits and parity bits), which can be used to correct a certain number of errors in the data bits. For example, a row may contain a codeword containing M data bits and K parity bits, which can be used to correct one of the M data bits or one of the K parity bits. During a write operation, the parity bits may be generated by error correction code (ECC) circuitry based on the data written to the memory cells of the row. During a read operation, the error correction code circuitry can use the parity bits to determine whether the read data bits are correct and can correct any errors found in the data as data is provided from the memory device.

[0016] The ECC circuitry can identify errors in the read data and correct it before providing the read data to the data terminals of the memory device. However, errors may remain in the codewords stored in the memory array. The device can perform an Error Checking and Clearing (ECS) operation to address this issue. In an ECS operation, the address of each codeword in the memory array can be accessed one at a time. The codeword at the current address is read, the ECC circuitry corrects for errors (if any), and then the corrected codeword is written back to the memory array. The memory performs an ECS cycle by traversing each codeword address sequence and performing the ECS operation on each codeword in the memory.

[0017] ECS cycles can be performed over relatively long time spans by executing read-correct-write sequences at different addresses at different times (e.g., when memory is idle). For example, an ECS cycle might take 24 hours to complete. While executing an ECS cycle, the ECS circuitry gathers information about the number of corrections being performed. For example, the ECS circuitry might count the total number of codewords with errors or the total number of rows with at least one error as part of an error count (EC), and / or count the row with the highest number of errors as part of an error count per row (EpRC). At the end of the ECS cycle, based on one or more of these counts, the read information can be updated in the mode register. For example, if the EC and / or EpRC counts exceed a threshold filter, the ECS register of the mode register (e.g., the EC and / or EpRC registers) can be updated. If the ECS register indicates that the threshold filter has been exceeded, the memory controller can check the mode register and take action. However, there may be situations where testing the controller's response to the ECS register is not ideal, as the ECS cycle can be relatively long, and therefore updating the ECS register may take a considerable amount of time. Similarly, since the ECS register is only updated when the count exceeds the threshold filter, it is uncertain whether the ECS register is updated in any given ECS cycle.

[0018] This disclosure relates to devices, systems, and methods for forcing error checking and clearing reads. A memory receives a command, such as a multipurpose command (MPC), that forces the ECS mode register to be set to a specified value, regardless of the current state of the ECS cycle. In this way, the system responding to the ECS cycle can be activated quickly and deterministically to report the number of errors exceeding a threshold. For example, as part of a test operation, the controller can provide an MPC, which in turn causes the memory to set the ECS register to indicate that the number of errors occurring exceeds a threshold. The test may involve monitoring the controller's ability to detect and / or respond to the state of the ECS register. Using controller commands allows for relatively fast and deterministic test execution (e.g., without waiting for the entire ECS cycle to execute), because the command sets a reading in the mode register to indicate at least the threshold number of errors, regardless of how many errors actually exist.

[0019] In some embodiments, commands can specify various attributes of the readings set in memory. For example, the EC register can indicate that the total number of erroneous codewords falls within one of several ranges (e.g., threshold to N, N+1 to M, M+1 to 0, etc.), and the controller can specify which range should be indicated by the EC register. In another instance, the EpRC register can indicate the row with the most detected codeword errors, and the number of codeword errors detected in that row. In some embodiments, in addition to commands that set ECS register values, the controller can specify information to be written to the ECS register, such as a specific row address and error count. For example, the controller can write the row address and error count to the mode register, and the MPC can cause the memory to retrieve those values ​​and write them to the EpRC register. In some embodiments, the memory can have predefined values ​​(e.g., EC range, EpRC address, and / or value) that can be set to the ECS register. The use of ECS forced read logic can be enabled by memory settings such as fuse settings and / or mode register settings to prevent the memory from overwriting the ECS register outside the test environment.

[0020] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure. Semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0021] Semiconductor device 100 includes memory array 118. Memory array 118 is shown as including a plurality of memory banks. Figure 1 In one embodiment, the memory array 118 is shown as comprising eight memory banks BANK0-BANK7. In other embodiments, the memory array 118 may contain more or fewer memory banks. Each memory bank includes multiple word lines WL, multiple bit lines BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL. The selection of word lines WL is performed by row decoder 108, and the selection of bit lines BL is performed by column decoder 110. Figure 1In this embodiment, row decoder 108 includes a corresponding row decoder for each memory bank, and column decoder 110 includes a corresponding column decoder for each memory bank. Bit line BL is coupled to a corresponding sense amplifier (SAMP). Read data from bit line BL is amplified by the sense amplifier SAMP and transmitted to read / write amplifier 120 via complementary local data line (LIOT / B), transmission gate (TG), and complementary main data line (MIOT / B) coupled to error correction code (ECC) control circuitry 120. Conversely, write data output from ECC control circuitry 120 is transmitted to the sense amplifier SAMP via complementary main data line MIOT / B, transmission gate TG, and complementary local data line LIOT / B, and written to the memory cell MC coupled to bit line BL.

[0022] The semiconductor device 100 may employ multiple external terminals, including: a command and address (C / A) terminal coupled to the command and address bus to receive commands and addresses; a CS signal clock terminal for receiving clock CK and / or CK; a data terminal DQ for providing data; and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0023] An external clock CK and / or CK is supplied to the clock terminals, and this external clock is provided to input circuitry 112. The external clocks can be complementary. Input circuitry 112 generates an internal clock ICLK based on the CK and / or CK clocks. The ICLK clock is provided to command decoder 106 and internal clock generator 114. Internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. An internal data clock LCLK is provided to input / output circuitry 122 to time the operation of circuits contained within input / output circuitry 122, for example, to a data receiver to time the reception of written data.

[0024] A memory address can be supplied to the C / A terminal. The memory address supplied to the C / A terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 can also supply a decoded bank address BADD, which can indicate the bank of memory in the memory array 118 containing the decoded row address XADD and column address YADD. Commands can be supplied to the C / A terminal. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as read commands for performing read operations and write commands for performing write operations, as well as other commands and operations. Access commands can be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD indicating the memory cell to be accessed.

[0025] Commands can be provided as internal command signals to command decoder 106 via command / address input circuitry 102. Command decoder 106 includes circuitry for decoding the internal command signals to generate various internal signals and commands for performing operations. For example, command decoder 106 can provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0026] Device 100 can receive access commands as read commands. When a read command is received and read commands are supplied in a timely manner for the bank address, row address, and column address, a codeword containing read data and read parity bits is read from the memory cell in the memory array 118 corresponding to the row address and the column address. The read command is received by command decoder 106, which provides an internal command to provide the read data from the memory array 118 to ECC control circuitry 120. ECC control circuitry 120 can use the parity bits in the codeword to determine whether the codeword contains any errors, and if any errors are detected, they can be corrected to generate a corrected codeword (e.g., by changing the state of the identified erroneous bits). The corrected codeword is output from the data terminal DQ to the outside of device 100 via input / output circuitry 122.

[0027] Device 100 can receive access commands as write commands. When a write command is received and, as part of a write operation, a write command is supplied in a timely manner for the bank address, row address, and column address, write data is supplied to ECC control circuit 120 via the DQ terminal. The write data supplied to the data terminal DQ is written into the memory cells in memory array 118 corresponding to the row and column addresses. The write command is received via command decoder 106, which provides an internal command to receive the write data via the data receiver in input / output circuit 122. A write clock can also be provided to an external clock terminal to time the reception of the write data via the data receiver in input / output circuit 122. The write data is supplied to ECC control circuit 120 via input / output circuit 122. ECC control circuit 120 can generate multiple parity bits based on the write data and can provide the write data and parity bits as a codeword to memory array 118 for writing into memory cell MC.

[0028] ECC control circuit 120 can be used to ensure the fidelity of data read from a specific group of memory cells to data written to said group of memory cells. Device 100 may include multiple different ECC control circuits 120, each responsible for a different portion of the memory cells MC of memory array 118. For example, one or more ECC control circuits 120 may be present for each bank of memory in memory array 118.

[0029] Each ECC control circuit 120 can receive a codeword containing a number of data bits and a number of parity bits (e.g., 128 data bits and 8 parity bits). Depending on whether it is a read or write operation, the data bits can be provided from the I / O circuit 122 or the memory array 118, and the ECC control circuit 120 uses the parity bits to locate and correct potential errors in the codeword. For example, as part of a write operation, the ECC control circuit 120 can receive 128 data bits from the I / O circuit 122 and can generate 8 parity bits based on the 128 data bits to form a codeword of 136 bits in total. The codeword can be written to the memory array 118. As part of an example read operation, the ECC control circuit 120 can receive a codeword with 128 data bits and 8 parity bits from the memory cell array 118. The ECC control circuit 120 can generate new parity bits from the 128 data bits and then compare the new parity bits with the read parity bits in the codeword to generate a correction sub-bit. The correction bits can be used to locate errors in the codeword and ECC control circuitry 120, and can correct any errors found before the data bits are supplied to the I / O circuitry 122. While various embodiments can be discussed with reference to ECC circuitry using codewords, where eight parity bits are used to look for an error in 128 data bits, it should be understood that these are for illustrative purposes only, and other numbers of data bits, error bits, and parity bits may be used in other exemplary embodiments.

[0030] During a read operation, ECC control circuitry 120 checks the codeword and locates and corrects any errors before providing the corrected codeword to I / O circuitry 122. Therefore, if an error exists, it can be retained in the codeword stored in memory array 118 because correction has been performed between memory array 118 and I / O circuitry 122. Memory device 100 includes error checking and clearing (ECS) logic 130 for correcting errors stored within memory array 118. ECS circuitry 130 generates an address sequence covering all memory cells in memory array 118. For each address in the sequence, ECS circuitry 130 operates address decoder 104 and command decoder 106 to perform a read operation on the memory cell at that address, and then writes the corrected codeword back to memory array 118, instead of providing the corrected codeword from device 100 as in a normal read. By looping through the address sequence containing all memory cells, ECS circuitry 130 can perform an ECS loop to correct errors in memory cell array 118.

[0031] ECS circuit 130 can execute ECS cycles based on manual or automatic modes. In manual mode, ECS circuit 130 can receive commands (e.g., MPC) and can execute ECS operations in response to said commands. In automatic mode, ECS circuit 130 can use internal logic and timing to execute ECS operations. For example, ECS circuit 130 can execute ECS operations during a refresh operation. ECS circuit 130 can have a specified time to complete an address sequence (e.g., execute an ECS cycle). For example, memory device 100 can specify 12, 24, or 48 hours to complete a sequence of ECS operations containing all memory cells in memory array 118. ECS circuit 130 can perform read, correct, and write ECS operations for each address in the sequence, such that the sequence is completed within the specified time period. Therefore, the timing between individual ECS operations can be specified by the total number of codewords in memory array 118 and the length of time for which an ECS cycle should be executed.

[0032] ECS circuit 130 collects information about located errors. This information can be stored in mode register 132, allowing the controller of memory device 100 to retrieve read information about errors in memory device 100. For example, each time a codeword with an error is detected, ECS circuit 130 can change (e.g., increment) the error count (EC) value. In some embodiments, the error count (EC) can be changed in response to each row containing one or more codeword errors. Whether the EC value represents the total number of codewords or rows with at least one codeword error can be a setting of memory 100 (e.g., based on a setting in mode register 132) and can change between ECS cycles. When all addresses in the sequence have been addressed, ECS circuit 130 can write this count value to mode register 132. In some embodiments, if the EC count value exceeds a threshold filter, ECS circuit 130 can only write the count value to mode register 132. In some embodiments, the EC register of mode register 132 may not store an exact EC count value, but rather a range of EC count values ​​can be specified. For example, the first state of the EC register can indicate that the EC count value is below a threshold, the second state of the EC register can indicate that the EC count value is between the threshold and the second threshold, and the third state can indicate that the EC count value is within the range of the second threshold and the third threshold, and so on.

[0033] Another instance of reading that the ECS circuit 130 may generate is the per-row error count (EpRC). This reading can be generated as an alternative to or supplement to the EC reading. As the ECS circuit continues, it can generate row addresses and then cycle through the column addresses of those rows, where each column address specifies one of a plurality of codewords along the row. The ECS circuit 130 may have an EpRC counter that tracks the maximum number of codewords with errors at a single row address and the row address of the row with the maximum number of errors. Once the address sequence is complete, if the EpRC count is greater than the threshold filter, the ECS circuit 130 can write the error count and row address into the ECS register of the mode register 132.

[0034] The threshold filter of the EpRC register may differ from the threshold filter of the EC register. In some embodiments, the filter may be a memory setting.

[0035] Memory device 100 includes forced ECS read circuitry 134. In response to a command, forced ECS read circuitry 134 can update mode register 132, such as when one or more of the ECS count values ​​exceed a threshold at the end of an ECS cycle, regardless of the current state of the counter or the position of the ECS circuitry within the cycle. The command can be a multipurpose command (MPC) received from outside memory device 100 (e.g., via command address input circuitry 102 and / or command decoder 104). In some embodiments, memory device 100 may include preset values ​​to be written to the ECS register in response to an MPC. For example, the mode register may include other registers storing preset ECS values. These values ​​can be written to the ECS register in response to an MPC command. In some embodiments, the controller may specify additional details that should be written to mode register 132. For example, the controller may specify the count (or range) of the EC registers to be written to mode register 132, and / or specify the row address and / or EpRC count value to be written to the EpRC register of mode register 132 by writing these values ​​to the registers of mode register 132. In response to the MPC command, the ECS readout circuit 134 is forced to read the value of the controller write mode register and set it as the ECS register.

[0036] In some embodiments, the forced ECS read logic 134 can only be enabled by settings of the memory device 100, such as fuses and / or mode register settings. For example, under normal circumstances, the only way to update the ECS portion of the mode register 132 is via the ECS circuit 130 at the end of an ECS cycle. However, when forced ECS read is enabled, the aforementioned portion of the mode register 130 can also be updated by the forced ECS read logic in response to a command. This helps to limit the use of the command to situations where the memory device 100 is used for testing.

[0037] The device 100 may also receive commands that cause it to perform one or more refresh operations as part of a self-refresh mode. In some embodiments, the self-refresh mode command may be externally issued to the memory device 100. In some embodiments, the self-refresh mode command may be generated periodically by components of the device. In some embodiments, a refresh signal AREF may also be activated when an external signal indicates a self-refresh enters a command. The refresh signal AREF may be a pulse signal that is activated when the command decoder 106 receives a signal indicating entry into the self-refresh mode. The refresh signal AREF may be activated immediately after the command input and may thereafter be activated cyclically according to desired internal timing. The refresh signal AREF may be used to control the timing of refresh operations during the self-refresh mode. Thus, refresh operations may continue automatically. A self-refresh exit command may stop the automatic activation of the refresh signal AREF and return it to an idle state. The refresh signal AREF is supplied to the refresh control circuitry 116. The refresh control circuitry 116 supplies a refresh row address RXADD to a row decoder 108, which may refresh one or more word lines WL indicated by the refresh row address RXADD.

[0038] Power supply potentials VDD and VSS are supplied to the power supply terminals. These potentials VDD and VSS are then supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power supply potentials VDD and VSS supplied to the power supply terminals. Internal potential VPP is primarily used in the line decoder 108, internal potentials VOD and VARY are primarily used in the sense amplifier SAMP included in the memory array 118, and internal potential VPERI is used in many peripheral circuit blocks.

[0039] Power potentials VDDQ and VSSQ are also supplied to the power terminals. These power potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In some embodiments of this disclosure, the power potentials VDDQ and VSSQ supplied to the power terminals may be the same potentials as the power potentials VDD and VSS supplied to the power terminals. In another embodiment of this disclosure, the power potentials VDDQ and VSSQ supplied to the power terminals may be different potentials from the power potentials VDD and VSS supplied to the power terminals. The power potentials VDDQ and VSSQ supplied to the power terminals are used in the input / output circuit 122 so that power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0040] Figure 2 This is a block diagram of a memory system according to some embodiments of the present disclosure. System 200 includes a controller 202 and a memory 204. In some embodiments, the memory may be implemented Figure 1The memory device 100. The memory system 200 shows components that can be used in instance operation, wherein the controller 202 tests its ability to detect and / or respond to different ECS-related reads (e.g., stored in one or more ECS registers) in the mode register 218. To avoid having to wait until the ECS mode register 218 is updated (e.g., at the end of the ECS sequence, and only when one or more counts exceed a threshold), the controller 202 can use the ECS test circuit 206 to provide a command, such as MPC, to the forced ECS read circuit 220 of the memory 204. The forced ECS read circuit 220 updates one or more of the ECS registers in the mode register 218 based on the command. The ECS check circuit 208 of the controller 202 can then identify the update information in the mode register 218 and respond to it.

[0041] Controller 202 includes ECS test circuitry 206, which can be used to perform tests on the ECS system of memory 204. Controller 206 also includes ECS check circuitry 208, which monitors ECS-related registers in mode register 218 of memory 204. For example, controller 206 can periodically perform mode register read operations on memory 204, and ECS check circuitry 208 can receive ECS-related values ​​from memory 204. In some embodiments, ECS check circuitry 208 can represent normal operation of controller 202, while ECS test circuitry 206 can be used solely for testing purposes. As part of the test operation, ECS test circuitry 206 can provide commands, such as MPC, to memory 204, and then monitor the response of ECS check circuitry 208. ECS check circuitry 208 can periodically receive updated values ​​(e.g., EC and / or EpRC values) from the ECS portion of mode register 218. If these values ​​indicate an error count higher than a threshold, ECS check circuitry can cause controller 202 to take various actions. For example, controller 202 can flag memory 204 for having too many errors and can take various corrective actions, etc. After a command is given to memory 204, as part of the test operation, ECS test circuit 206 can monitor the response of ECS check circuit 208 (and / or other components of controller 202) to ensure a proper response to a number of errors greater than a threshold detected in mode register 218.

[0042] ECS test circuitry 206 may provide, along with a command, information specifying which values ​​should be set to the ECS registers (e.g., EC and / or EpRC registers) in mode register 218. In some embodiments, ECS test circuitry 206 may provide this information as part of a command. In some embodiments, ECS test circuitry 206 may write specified values ​​to memory (e.g., to mode register 218) along with or separately from a command. A command (e.g., MPC) causes ECS forced read circuitry 220 to write values ​​provided by the controller to the ECS registers. For example, if the EC register has a set of values ​​representing different ranges, ECS test circuitry 206 may send values ​​(e.g., count ranges) to mode register 218. Similarly, in an instance of MPC pointing to the EpRC register, ECS test circuitry 206 may have written a count value and / or row address to mode register 218, which should be set to the EpRC register by ECS forced read circuitry 220. In some embodiments, values ​​may be preset in memory 204 instead of being provided by controller 202.

[0043] ECS check circuit 208 enables controller 202 to take one or more actions based on values ​​read from the ECS register in mode register 218. For example, if the EC register indicates that more than a threshold number of errors were counted in the most recent ECS cycle, controller 202 can identify memory 204 as defective. Memory 204 can be flagged by controller 202, which can then notify the user that repair or further testing is required. For example, controller 202 can also transfer critical information to memory modules that have not been identified as defective. If the EpRC register indicates that more than a threshold number of errors exist on an identified row (e.g., based on the row address stored in the EpRC register), controller 202 can identify that row as defective. EpRC can take various steps to mitigate the damage, such as by removing data from the defective row, by performing post-packet repair operations, etc.

[0044] Memory 204 includes ECS circuitry 214, which generates addresses from an address sequence as part of an ECS loop. For example, ECS circuitry 214 may provide row and column addresses, then update (e.g., increment) the column addresses, and continue until all column addresses are provided. Then, ECS circuitry 214 may update (e.g., increment) the row addresses and repeat the process. Once all address combinations for a given memory bank are provided (e.g., the final row and column addresses are provided), the memory bank address can be updated (e.g., incremented). The ECS circuitry may continue generating addresses until addresses associated with all memory cells are provided during the ECS loop. The current address may be provided along with a command (not shown) to row and column decoder 212 such that, for each address, the codeword associated with the current address is read out to ECC circuitry 216, corrected (if necessary), and the corrected codeword is written back to the location specified by the current address. The address can then be updated.

[0045] ECC circuit 216 can provide ECS circuit 214 with a signal ErrDet indicating that an error has been detected. The ErrDet signal can be active whenever ECC circuit 216 detects an error in a codeword read from memory array 210. The ECS circuit includes one or more counters that are updated (e.g., incremented) in response to the ErrDet signal. For example, the EC counter can be updated based on each time the ErrDet signal is active, while the EpRC counter can also take into account the current address provided by ECS circuit 214 to calculate the maximum number of errors per row. If the counters exceed a threshold at the end of the ECS cycle, ECS circuit 214 can write information to mode register 218 based on the count value. Different values ​​tracked by ECS circuit 214 can have different thresholds (e.g., EC threshold and EpRC threshold). The thresholds can be memory settings (e.g., fuse settings and / or mode register settings) and can be set based on customer requirements.

[0046] Mode register 218 can store various values ​​related to ECS operation. For example, this disclosure describes the EC register and the EpRC register, but different, more, or fewer registers may exist in other instances. Each register can store various values ​​associated with a corresponding counter in ECS circuitry 214. For example, the EC register can represent the number of erroneous codewords detected in the previous ECS cycle. The EC register can represent the initial count value or the range in which the count value decreases. For example, the first value of the EC register can represent that the count is below a threshold, the second value of the EC register can represent that the count is between the threshold and the first count value, the third value of the EC register can represent that the count is between the first count value and the second count value, and so on. The EpRC register can store the count value and the row address associated with the row containing the most codeword errors.

[0047] Figure 3 This is a block diagram of an ECS circuit according to some embodiments of the present disclosure. Figure 3 The ECS circuit 300 and other components, such as the ECC circuit 301 (e.g., Figure 1 120 and / or Figure 2 216) and ECS forced read logic 330 (e.g., Figure 1 134 and / or Figure 2 (220). In some embodiments, the ECS circuit 300 may be included in Figure 1 ECS circuit 130 and / or Figure 2 Of 214.

[0048] ECS circuit 300 includes ECS address counter 302. ECS address counter 302 generates a current address ADD, which may include row address XADD, column address YADD, and / or memory address BADD. The current address can be provided to the address decoder (e.g., via multiplexer 326) Figure 1The decoder (of 104, 108, and / or 110) can then read the codeword specified by address ADD to ECC circuit 301. The ECC circuit can determine if the codeword contains an error, correct the error, and write the corrected codeword back to the memory array. If an error is detected, ECC circuit 301 provides the signal ErrDet at an active level. ECS address counter 302 can then update address ADD in response to the next ECS operation. ECS circuit 300 includes EC error counter 310 and EpRC error counter 318, each of which can increment in response to the active ErrDet signal. Various logic circuits (e.g., 304-308, 316, and 322-324) can control the behavior of how counters 310 and 318 are updated, as described in more detail herein. When the ECS cycle completes, EC register loading logic circuit 312 can determine if the count value stored in EC error counter 310 exceeds a threshold. Based on this comparison, EC register loading logic circuit 312 can update the mode register (e.g., Figure 2 The value of the EC register in (218). Similarly, the EpRC register load circuit 314 can compare the count from the EpRC error counter 318 with a threshold and can update the value of the EpRC register accordingly. The ECS forced read logic 330 can receive the command MPC and can instruct one (or both) of the register load circuits 312 and 314 to update their respective registers accordingly.

[0049] ECS address counter 302 contains a set of counters used to determine the current value of address ADD. For example, ECS address counter 302 may include a row address counter, a column address counter, and a bank address counter, each of which determines the value of the row address, column address, and bank address in the current address ADD. A reset signal (Reset) or a mode register command (stored in mode register 14MR14 in this example) resets the address counters to their initial values. When the ECS command signal ECSCMD is active (indicating ECS ​​mode) and the write signal CAS Write is active (indicating that a previous ECS operation has just completed), ECS address counter 302 updates the value of address ADD by changing one or more of its internal counters. The value of the address counters may be reset when the maximum value is reached. When a counter feeds to a newline, it may cause another counter to change (e.g., increment), or it may cause a newline signal to be provided.

[0050] For example, in response to an update, ECS address counter 302 can update the column address while keeping the row address and bank address the same. When a column address reaches its maximum value (e.g., all columns in the current row have performed ECS operations), the column counter can be reset (to the initial column address), a column wrap signal ColWrap can be provided, and the row address value can be updated (e.g., incremented). When a row address reaches its maximum value, the row address can wrap to its initial value, and the bank address can be updated. When the bank address wraps, a bank address wrap signal BWrap is provided to indicate that the ECS cycle has completed. Figure 4 Examples of address updates and line breaks are described in more detail.

[0051] Multiplexer 326 provides an address ADD or an external address generated by ECS address counter 302. Multiplexer 326 can be controlled (via a signal not shown) to determine whether to provide an ADD address, used as part of ECS operation, to the decoder, or whether to provide an external address (e.g., as part of an access operation, refresh operation, etc.).

[0052] In the EC path, latch 306 holds the EC update signal. A set terminal is coupled to the error detection signal ErrDet. When ErrDet is active (e.g., when ECC circuit 301 detects an error in the current codeword), the value of the EC update signal is set to 1. The reset terminal of latch 306 is coupled to selector circuit 304. Selector circuit 304 determines the mode of the EC counter. In a first mode, the EC counter can represent the total number of codeword errors, and the signal BWrap is passed to the reset terminal of latch 306, causing its value to be reset each time an ECS cycle completes. In a second mode, the EC counter can represent the total number of rows containing at least one error, and selector 304 can pass the signal ColWrap to the reset terminal of latch 306. Therefore, latch 306 can be reset each time the row address is changed.

[0053] Counter 308 receives an update signal from latch 306 and increments the counter each time the value of the EC update signal becomes 1. Counter 308 is reset by the signal BWrap to ensure that the overall value of EC is determined on an ECS cycle basis. The value from counter 308 is provided to EC counter 310, which controls the EC count value. The EC count value increments each time counter 308 increments. Therefore, in the first mode, the EC count value is incremented each time ErrDet is active. In the second mode, the EC count value is incremented once per row if any address along each row (e.g., any value of the column address given the row and memory address) causes the ErrDet signal to be active.

[0054] EC counter 310 provides the EC count value to EC mode register loading logic 312. EC mode register loading logic 312 has a loading terminal coupled to signal BWrap. When signal BWrap is active (e.g., indicating the end of an ECS cycle), the EC mode register loading logic compares the EC count value with a threshold and writes the value to the mode register based on the comparison.

[0055] In the EpRC path, latch 316 has a set terminal coupled to ErrDet. When ErrDet is active, the EpRC update signal becomes active and provides activation to EpRC counter 318. Latch 316 has a reset terminal coupled to the signal ColWrap. Therefore, when a column address is row-fed (e.g., when a given row is completed), the value in latch 316 is reset to an inactive level (e.g., 0). In this way, latch 316 provides an active signal each time ErrDet is active, but resets after each row is completed. Each time latch 316 provides activation (e.g., each time ErrDet is active on a given row), EpRC counter 318 increments the EpRC count value. EpRC counter circuit 318 has a reset terminal coupled to the signal ColWrap, such that the EpRC count value is reset whenever an ECS operation on a given row is completed.

[0056] The EpRC count value is provided to comparator 320, which compares the current EpRC count value with the EpRC count value stored in register 322. If the current EpRC count is larger, it is written to the stored EpRC count value and stored in register 322. When a new value is stored in register 322 as the stored EpRC count value, the row and column address portions of ADD are also stored in register 324. Registers 322 and 324 are reset by the signal BWrap, indicating that the ECS loop has completed.

[0057] The EpRC mode register load logic 314 has a load terminal coupled to BWrap. In response to BWrap being active, the load logic 314 reads values ​​from registers 322 and 324. The EpRC mode register 314 compares these values ​​with a threshold and writes the EpRC count value, along with the row and column addresses stored at addresses 322 and 324, to the EpRC mode register. In some embodiments, the EpRC load logic 314 may also check the EC load logic 312 to determine if the EC count value exceeds a threshold, and if the EC count value exceeds the threshold, only the EpRC count value (and address) may be loaded.

[0058] Figure 4This is a block diagram of an example memory storage unit according to some embodiments of the present disclosure. In some embodiments, the memory storage unit 400 may be included in... Figure 1 memory array 118 and / or Figure 2 In the memory array 210.

[0059] The memory bank 400 is divided into multiple memory pads, each containing multiple memory cells organized at the intersection of word lines WL and bit lines. The bit lines are grouped together in column select CS lines, each column select CS line containing a certain number of bit lines (e.g., 2, 4, 8, 16, etc.) accessed by a common column select address. For illustration, eight column select groups (represented as column select lines (labeled 0 to 7)) and two word lines WL0 and WL1 are shown for each memory pad, but more or fewer may be used in other exemplary embodiments.

[0060] During ECS ​​operation, the memory bank address, row address, and column address are provided for memory bank 400. For example, during the first ECS operation, the row address can be specified as WL0, and the column address can be specified as CS0. Bits are read from CS0 in each of the memory pads to form a codeword. In the next ECS operation, the column address is updated to CS1, and bits are read from the intersection of each CS1 and WL1 in each pad. When the ECS address counter reaches WL0 and CS7, in the next ECS operation, the column address is pushed back to CS0, and the row address is updated to WL0.

[0061] Figure 5 This is a block diagram of a method according to some embodiments of the present disclosure. In some embodiments, method 500 may be performed by... Figure 1-4 The method 500 may be implemented by one or more of the devices and / or systems described herein. Method 500 may include a controller (e.g., Figure 2 The steps performed in section 202 are shown in the dashed box. The steps in the solid box can be executed by memory.

[0062] Method 500 includes an optional block 501 that describes the generation of an ECS forced read command. The ECS forced read command can be generated by the controller's ECS test circuitry (e.g., Figure 2 The ECS forced read command (206) is generated. In some embodiments, the ECS forced read command may be an MPC. The ECS forced read command may be generated as part of a test operation. In some embodiments, method 500 may include writing ECS ​​register values ​​to memory (e.g., writing to a non-ECS register). Subsequently, in response to the ECS forced read command, these values ​​may be loaded into the ECS register. These values ​​may be provided with the command or separately.

[0063] Method 500 includes block 510, which describes receiving an ECS forced read command. The ECS forced read command can be executed on the ECS forced read circuitry (e.g., Figure 1-3 Received at 134, 220, and / or 330). Method 500 includes block 515, which describes setting a value in the mode register. The value in the mode register can be set in response to a received ECS forced read command. For example, method 500 may include setting a value in the EC register based on an EC count (or value) specified in a register of the mode register. The value may be a preset value or specified by the controller. Method 500 may include setting a value in the EpRC register based on an EpRC count (or value) and a row address specified in the mode register. The value and row address may be preset values ​​or specified by the controller.

[0064] Method 500 includes optional block 502, which describes a response to a value in the mode register. For example, the controller's ECS check circuitry (e.g., 208) can read ECS register values, such as values ​​in the EC and / or EpRC registers. Based on the result, the controller can take one or more actions. For example, if the EC register value indicates a number of errors greater than a threshold, the ECS check circuitry can instruct the controller to identify the memory as defective. The controller can take various corrective actions, such as transferring data to another memory module. For example, if the EpRC register value indicates a row has a number of errors greater than a threshold, the controller can identify the row address stored in the EpRC register as defective. The controller can take various corrective actions, such as removing data from the row and / or performing repair operations, such as post-packet repair operations.

[0065] Method 500 may optionally include blocks 520 to 540 describing ECS ​​cycle steps. Method 500 may include putting the memory into automatic ECS mode, wherein the memory periodically performs an ECS cycle over a selected time span (e.g., within 24 hours). Block 520 describes address generation. Addresses may be generated by an ECS address counter (e.g., Figure 3 The address is generated using a 302 (or similar) method. The address can come from an address sequence and can contain row addresses, column addresses, and bank addresses. Each time an address is generated (e.g., each time box 520 is repeated), the column address can be changed (e.g., incremented) until a newline character is generated, at which point the row address can be changed (e.g., incremented). When the row address gives a newline character, the bank address can be changed (e.g., incremented). When the bank address gives a newline character, the ECS loop is complete.

[0066] Box 525 describes performing an ECS operation on a codeword associated with an address. The ECS operation involves reading the codeword from memory to the ECC circuitry, correcting errors (if any), and writing the corrected codeword back to the memory array (at the address specified).

[0067] Box 530 describes changing the count value in the event of a codeword inclusion error. For example, the EC count value can be updated (e.g., incremented) each time a codeword inclusion error is detected, or each time a line contains an erroneous codeword. Box 530 may include updating the EpRC count value each time a codeword inclusion error is detected along a line. Box 530 may include comparing the EpRC count value with a stored EpRC value, and replacing the stored EpRC value with the EpRC count value if the EpRC count value is greater than the stored EpRC value.

[0068] Box 535 describes determining whether the address is the final address of the ECS sequence. For example, a memory address line feed signal can indicate whether the current address is the final address. If not, the ECS loop can return to box 520. If so, the ECS loop can continue to box 540. Box 540 describes comparing the count value (or the stored EpRC value) with a threshold filter. If the count value is greater than the threshold, the value of the ECS register in the mode register can be set using box 515 (as previously described).

[0069] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with or separated from one or more other examples, embodiments, and / or processes and / or performed in a separate device or device portion of a system, apparatus, or method according to the present invention.

[0070] Finally, the foregoing discussion is intended to illustrate the system of the invention only and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, while the system of the invention has been described in detail with reference to exemplary embodiments, it should be understood that numerous modifications and alternative embodiments can be devised by those skilled in the art without departing from the broader and established spirit and scope of the system of the invention as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. An apparatus comprising: Error correction code (ECC) circuitry is configured to detect whether a codeword read from a memory array contains an error; The mode register contains error checking and clearing of the ECS register; An error checking and clearing ECS ​​circuit is configured to change a counter value based on the number of times the ECC circuit detects an error and is further configured to set the value of the ECS register in the mode register based on the counter value; as well as A forced ECS readout circuit is configured to set the value of the ECS register based on an external command. The ECS register includes a per-row error count EpRC register, wherein the ECS circuitry is configured to increment the count value whenever the ECC circuitry detects an error along the current row, compare the incremented count value with a stored count value, and replace the stored count value with the incremented count value in response to the count value being greater than the stored count value, and wherein the ECS circuitry is configured to set the value of the EpRC register based on the stored count value exceeding a threshold.

2. The device of claim 1, wherein the ECS register further includes an error count EC register, wherein the ECS circuitry is configured to increment the count value each time the ECC circuitry detects the error, and wherein the ECS circuitry is configured to set the value of the EC register based on the count value exceeding a threshold.

3. The device of claim 2, wherein the external command includes a command count value, and wherein in response to the external command, the forced ECS readout circuitry sets the value of the EC register based on the command count value.

4. The device of claim 1, wherein the mode register includes a command count value and a row address, and wherein, in response to the external command, the forced ECS readout circuitry sets the EpRC register based on the command count value and the row address.

5. The device according to claim 1, wherein the external command is received from the controller.

6. The device of claim 1, wherein the forced ECS readout circuit is enabled by a fuse setting.

7. An apparatus comprising: The mode register contains error checking and clearing of the ECS register; An ECS circuit is configured to perform an ECS operation as part of an ECS loop, wherein the ECS circuit is configured to set the value of the ECS register based on the ECS operation at the end of the ECS loop. as well as A forced ECS readout circuit is configured to receive an external command and, in response to the external command, set the value of the ECS register. The ECS register includes an EpRC register for per-line error counting, wherein the ECS circuitry is configured to increment a count value whenever the ECC circuitry detects an error along the current line, compare the incremented count value with a stored count value, and replace the stored count value with the incremented count value in response to the count value being greater than the stored count value, and wherein the ECS circuitry is configured to set the value of the EpRC register based on the stored count value exceeding a threshold.

8. The device of claim 7, wherein the ECS register further includes an error count EC register, and wherein the value of the EC register represents a range of values ​​to which the error count value belongs.

9. The device of claim 8, wherein the mode register contains a value specifying the range of values ​​to be set in the EC register.

10. The device of claim 7, wherein the EpRC register is configured to store a count value and a row address.

11. A system comprising: The memory includes: The mode register contains error checking and clearing of the ECS register; The ECS circuitry is configured to set the value of the ECS register based on the count of detected errors; A forced ECS readout circuit, configured to set the value of the ECS register based on a command; and An error correction code (ECC) circuit, configured to determine whether each of a plurality of codewords contains an error; and The controller includes: ECS test circuitry, configured to provide the command; and An ECS check circuit is configured to check the ECS register in the mode register. The ECS register includes a per-row error count EpRC register, wherein the ECS circuitry is configured to increment a count value whenever the ECC circuitry detects an error along the current row, compare the incremented count value with a stored count value, and replace the stored count value with the incremented count value in response to the count value being greater than the stored count value, and wherein the ECS circuitry is configured to set the value of the EpRC register based on the stored count value exceeding a threshold.

12. The system of claim 11, wherein the ECS circuit is configured to count the number of times the plurality of codewords containing errors occur, wherein the ECS circuit is configured to set the value of the ECS register based on the count of the plurality of codewords containing errors.

13. The system of claim 11, wherein the ECS register includes an error count EC value, a per-row error count EpRC value, a row address, or a combination thereof.

14. The system of claim 11, wherein the controller further provides a value, a row address, or a combination thereof.

15. The system of claim 11, wherein the command is a multipurpose command (MPC).

16. A method comprising: As part of the error checking and clearing ECS ​​loop, the number of errors in memory is counted; At the end of the ECS cycle, the value of the ECS register in the mode register of the memory is set; Receives an ECS forced read command at the memory location; as well as The value of the ECS register is set based on the ECS forced read command. The ECS register includes an EpRC register for per-row error counts, and the method further includes: The counter value is incremented whenever the ECC circuit detects an error along the current line. The incrementing count value is compared with the stored count value; In response to a count value greater than a stored count value, the stored count value is replaced with the incrementing count value; and The value of the EpRC register is set based on the stored count value exceeding the threshold.

17. The method of claim 16, wherein the register further comprises an error counter EC register, and the method further comprises receiving a value to be set into the EC register.

18. The method of claim 16, further comprising receiving a value to be set into the EpRC register and a row address.

19. The method of claim 16, further comprising: The ECS forced read command is provided by the controller of the memory; as well as The controller responds to the register in the mode register.

20. The method of claim 16, further comprising: Generate addresses from address sequences; Perform an ECS operation on the codeword stored at the location in the memory array specified by the address; If the codeword contains an error, the count value is changed; In response to the fact that the address is the final address in the address sequence, determine whether the count value is greater than a threshold; as well as In response to the count value being greater than the threshold at the end of the ECS cycle, the value of the ECS register in the mode register is set.

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