Packaging method and packaging structure

Abstract

A packaging method and a packaging structure, the packaging method comprises: providing a first device wafer, the first device wafer comprises a first substrate and a first dielectric layer on the first substrate, the first device wafer comprises a mark area; in the mark area, a groove is formed in the first dielectric layer; a first mark layer is formed in the groove, the material of the first mark layer is a metal element-containing material; providing a second device wafer, the second device wafer comprises a second substrate and a second dielectric layer on the second substrate, the second dielectric layer is provided with a second mark layer in the surface opposite to the first substrate, the material of the second mark layer is a metal element-containing material; the second dielectric layer is arranged opposite to the first dielectric layer, and the second mark layer is aligned with the first mark layer, and the bonding of the second dielectric layer and the first dielectric layer is realized through a bonding process. The accurate alignment of the first mark layer and the second mark layer can be realized, so as to further improve the packaging yield.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a packaging method and packaging structure. Background Technology

[0002] With the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink, and the requirements for integrated circuit packaging technology are also constantly increasing. Existing packaging technologies include ball grid array (BGA), chip scale package (CSP), wafer level package (WLP), 3D packaging, and system in package (SiP).

[0003] Currently, in order to meet the goals of lower cost, higher reliability, faster speed and higher density of integrated circuit packaging, advanced packaging methods mainly adopt wafer-level package system in package (WLPSiP). Compared with traditional system packaging, wafer-level package system in package completes the packaging integration process on the wafer, which has advantages such as significantly reducing the area of ​​the package structure, reducing manufacturing costs, optimizing electrical performance, and batch manufacturing, and can significantly reduce workload and equipment requirements.

[0004] Wafer-level system packaging mainly includes two important processes: physical connection and electrical connection. Physical connection between the device wafer and the chip to be integrated is usually achieved by bonding, while electrical connection between semiconductor devices is achieved by through-hole etching (e.g., silicon through-hole etching) and electroplating technology. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a packaging method and packaging structure, which is beneficial to further improve the packaging yield.

[0006] To address the aforementioned problems, the present invention provides a packaging structure comprising: a first device wafer, the first device wafer including a first substrate and a first dielectric layer located on the first substrate, the first device wafer including a marking region; a groove located in the marking region and in the surface of the first dielectric layer facing away from the first substrate; a first marking layer located in the groove, the first marking layer being made of a material containing a metal element; and a second device wafer bonded to the first device wafer, the second device wafer including a second substrate and a second dielectric layer located on the second substrate, a second marking layer formed in the surface of the second dielectric layer facing away from the second substrate, the second marking layer being made of a material containing a metal element, the second dielectric layer being disposed opposite to and bonded to the first dielectric layer, and the second marking layer being aligned with the first marking layer.

[0007] Accordingly, embodiments of the present invention also provide a packaging method, comprising: providing a first device wafer, the first device wafer including a first substrate and a first dielectric layer located on the first substrate, the first device wafer including a marking region; forming a groove in the first dielectric layer in the marking region; forming a first marking layer in the groove, the first marking layer being made of a material containing a metal element; providing a second device wafer, the second device wafer including a second substrate and a second dielectric layer located on the second substrate, a second marking layer being formed on the side of the second dielectric layer facing away from the second substrate, the second marking layer being made of a material containing a metal element; disposing the second dielectric layer opposite to the first dielectric layer, aligning the second marking layer with the first marking layer, and bonding the second dielectric layer with the first dielectric layer through a bonding process.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] This invention provides a packaging method in which a groove is formed in a first dielectric layer in a marking area; a first marking layer is formed in the groove, the first marking layer being made of a material containing a metal element; a second device wafer is provided, the second device wafer including a second substrate and a second dielectric layer located on the second substrate, the second marking layer being formed on the side of the second dielectric layer facing away from the second substrate, the second marking layer being made of a material containing a metal element; the second dielectric layer and the first dielectric layer are disposed opposite to each other, and the second marking layer and the first marking layer are aligned with each other, and bonding of the second dielectric layer and the first dielectric layer is achieved through a bonding process. Compared with the current scheme where the first dielectric layer exposed in the groove is used as the first marking layer, this invention forms a first marking layer at the bottom and sidewalls of the groove after forming the groove in the first dielectric layer, and the material of the first marking layer is a material containing a metal element. Since the material containing a metal element has a strong reflectivity, the process equipment can accurately identify the first marking layer and the second marking layer during the bonding process, thereby achieving precise alignment of the first marking layer and the second marking layer, and further improving the packaging yield. Attached Figure Description

[0010] Figures 1 to 2 This is a structural diagram showing the steps in an encapsulation method.

[0011] Figure 3 This is a schematic diagram of an embodiment of the packaging structure of the present invention;

[0012] Figures 4 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the packaging method of the present invention. Detailed Implementation

[0013] The yield rate of current packaging structures needs improvement. This paper analyzes the reasons for this need to improve the yield rate using a specific packaging structure formation method as an example.

[0014] Figures 1 to 2 This is a structural diagram showing the steps in an encapsulation method.

[0015] refer to Figure 1 A first device wafer is provided, the first device wafer including a first substrate 10 and a first dielectric layer 11 located on the first substrate 10, the first device wafer including a marking region 10A; a groove 12 is formed in the first dielectric layer 11 in the marking region 10A.

[0016] The portion of the first dielectric layer 11 exposed in the groove 12 serves as the first marking layer.

[0017] refer to Figure 2The second device wafer is provided, the second device wafer includes a second substrate 20 and a second dielectric layer 21 located on the second substrate 20, a second marking layer 22 is formed in the surface of the second dielectric layer 21 facing away from the second substrate 20, and the material of the second marking layer 22 is a material containing metal elements.

[0018] Continue to refer to Figure 2 The second dielectric layer 21 is disposed opposite to the first dielectric layer 11, and the second marking layer 22 and the groove 12 are aligned with each other. The bonding process is used to bond the second dielectric layer 21 to the first dielectric layer 11.

[0019] Research revealed that the exposed portion of the first dielectric layer 11 in the groove 12 serves as the first marking layer, and the material of the first marking layer is a dielectric material. However, the material of the second marking layer 22 is a material containing metallic elements. Therefore, in the bonding process between the second dielectric layer 21 and the first dielectric layer 11, because the reflectivity of the material containing metallic elements is higher than that of the dielectric material, the bonding machine cannot accurately identify the first marking layer during the bonding process. Consequently, the groove 12 and the second marking layer 22 cannot achieve precise alignment (e.g., ...). Figure 2 (As shown by the dashed coil in the middle), thereby reducing the package yield.

[0020] To address the technical problem, embodiments of the present invention provide a packaging structure, comprising: providing a first device wafer, the first device wafer including a first substrate and a first dielectric layer located on the first substrate, the first device wafer including a marking region; forming a groove in the first dielectric layer in the marking region; forming a first marking layer in the groove, the first marking layer being made of a material containing a metal element; providing a second device wafer, the second device wafer including a second substrate and a second dielectric layer located on the second substrate, a second marking layer being formed on the side of the second dielectric layer facing away from the first substrate, the second marking layer being made of a material containing a metal element; arranging the second dielectric layer opposite to the first dielectric layer and aligning the second marking layer with the first marking layer, and bonding the second dielectric layer with the first dielectric layer through a bonding process.

[0021] Compared with the current approach of using the first dielectric layer exposed in the groove as the first marking layer, the present invention forms a first marking layer at the bottom and sidewalls of the groove after forming a groove in the first dielectric layer. The material of the first marking layer is a material containing metal elements. Since the material containing metal elements has a strong reflectivity, the process equipment can accurately identify the first marking layer and the second marking layer during the bonding process, thereby achieving precise alignment between the first marking layer and the second marking layer, and further improving the packaging yield.

[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Figure 3 This is a schematic diagram of an embodiment of the packaging structure of the present invention.

[0024] The packaging structure includes: a first device wafer 60, the first device wafer including a first substrate (not shown) and a first dielectric layer 201 located on the first substrate, the first device wafer 60 including a marking region 200A; a groove 202 located in the marking region 200A and in the surface of the first dielectric layer 201 facing away from the first substrate; a first marking layer 208 located in the groove 202, and the material of the first marking layer 208 is a material containing a metal element; and a second device wafer 61 bonded to the first device wafer 60, the second device wafer 61 including a second substrate (not shown) and a second dielectric layer 210 located on the second substrate, a second marking layer 212 formed in the surface of the second dielectric layer 210 facing away from the second substrate, the material of the second marking layer 212 being a material containing a metal element, the second dielectric layer 210 being disposed opposite to and bonded to the first dielectric layer 201, and the second marking layer 212 being aligned with the first marking layer 201.

[0025] In this embodiment, a first marking layer 208 is provided in the groove 202, and the material of the first marking layer 208 is a material containing metal elements. Since the material containing metal elements has a strong reflectivity, the process equipment can accurately identify the first marking layer 208 and the second marking layer 212, thereby achieving precise alignment between the first marking layer 208 and the second marking layer 212, and further improving the packaging yield.

[0026] In this embodiment, the packaging structure is a wafer-level packaging structure, thereby improving the packaging efficiency and reliability of obtaining the packaging structure.

[0027] The first device wafer 60 is a wafer for completing device fabrication, and the first device wafer 60 can be fabricated using integrated circuit fabrication technology.

[0028] In this embodiment, the first substrate includes a first substrate 200, NMOS devices and PMOS devices formed on the first substrate 200 by processes such as deposition and etching, and structures such as dielectric layers and metal interconnects formed on the devices.

[0029] It should be noted that, for ease of illustration, in this embodiment, only the first substrate 200 is shown, and the devices formed on the first substrate 200 are not shown.

[0030] In this embodiment, the first device wafer 60 includes a marking region 200A.

[0031] The marking area 200A is the region where the first device wafer 60 and the second device wafer 61 can be aligned.

[0032] It should be noted that, for ease of illustration, this embodiment uses a single marking region 200A in the first device wafer 60 as an example. In other embodiments, the number of marking regions in the first device wafer 60 is not limited to one.

[0033] In this embodiment, the first substrate 200 of the first device wafer 60 is a silicon substrate. In other embodiments, the material of the first substrate may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc. The first substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. The material of the first substrate may be a material suitable for process requirements or easy to integrate.

[0034] In this embodiment, the first substrate has a first front side (not shown) and a first back side (not shown). The first front side refers to the side of the first substrate that faces away from the first substrate 200; the first back side refers to the bottom surface of the first substrate 200, that is, the exposed surface of the first substrate 200.

[0035] The first dielectric layer 201 serves as one of the bonding layers for bonding the first device wafer 60 and the second device wafer 61. The first dielectric layer 201 also provides a process basis for the groove 202.

[0036] The first dielectric layer 201 is made of a dielectric material. Therefore, the first device wafer 60 and the second device wafer 61 are bonded together by fusion bonding.

[0037] In this embodiment, the material of the first dielectric layer 201 includes one or more of SiO2, SiN and SiON.

[0038] In this embodiment, in the first device wafer 60, the first dielectric layer 201 is located on the first back side.

[0039] In this embodiment, the groove is located in the marking area 200A and is located in the surface of the first dielectric layer 201 facing away from the first substrate.

[0040] The groove 202 provides a spatial location for the formation of the first marking layer 208.

[0041] It should be noted that the depth of the groove 202 should not be too large or too small. If the depth of the groove 202 is too large, the etching process during the semiconductor structure formation process can easily damage the device at the bottom of the groove 202 and the first substrate 200, thereby affecting the performance of the semiconductor structure. If the depth of the groove 202 is too small, the etching process of the first marking layer 208 in the groove 202 during the semiconductor structure formation process is difficult to control, thereby affecting the alignment effect of the first marking layer 208 and the second marking layer 212. Therefore, in this embodiment, the depth of the groove 202 is 2000 angstroms to 5000 angstroms. For example, the depth of the groove 202 is 2500 angstroms, 3000 angstroms, or 4000 angstroms.

[0042] In this embodiment, the first marking layer 208 is located in the groove. Therefore, the first marking layer 208 is exposed on the side of the first dielectric layer 201 facing away from the first substrate, so that the bonding process equipment can accurately identify the first marking layer 208 during the bonding process of the first device wafer 60 and the second device wafer 61.

[0043] Moreover, the material of the first marking layer 208 is a material containing metal elements. Since the material containing metal elements has a strong reflectivity, during the bonding process of the first device wafer 60, the bonding process equipment can accurately identify the first marking layer 208 and the second marking layer 212, so as to achieve precise alignment between the first marking layer 208 and the second marking layer 212, thereby further improving the packaging yield.

[0044] It should be noted that, since materials containing metallic elements have strong reflectivity, it is sufficient for the first marking layer 208 to be formed in the groove 202. In the formation process of the first marking layer 208, to reduce material consumption and lower costs, in this embodiment, the first marking layer 208 is located at the bottom and sidewalls of the groove 202. In other embodiments, the first marking layer may also fill the groove.

[0045] In this embodiment, the material of the first marking layer 208 includes one or more of TiN, Ti, TaN, and Ta.

[0046] TiN, Ti, TaN and Ta materials are all materials containing metal elements. Since materials containing metal elements have a strong reflectivity, it is beneficial to accurately identify the first marking layer 208 and the second marking layer 212, thereby improving the alignment accuracy of the first marking layer 208 and the second marking layer 212.

[0047] It should be noted that the thickness of the first marking layer 208 should not be too large or too small. If the thickness of the first marking layer 208 is too large, gaps may easily form between the first marking layer 208 and the sidewall of the groove 202, thereby affecting the reflectivity of the first marking layer 208 and thus preventing the second marking layer 212 from achieving precise alignment with the first marking layer 208. If the thickness of the first marking layer 208 is too small, it may also affect the reflectivity of the first marking layer 208, thus preventing the second marking layer 212 from achieving precise alignment with the first marking layer 208. Therefore, in this embodiment, the thickness of the first marking layer 208 is 50 angstroms to 200 angstroms.

[0048] In this embodiment, the first marking layer 208 is located at the bottom and sidewall of the groove 202. Therefore, the thickness of the first marking layer 208 refers to the dimension of the first marking layer 208 located at the bottom of the groove 202 along the depth direction of the groove 202, or the dimension of the first marking layer 208 located on the sidewall of the groove 202 along the direction perpendicular to the sidewall of the groove 202.

[0049] In this embodiment, the semiconductor structure further includes a protective layer 205, located in the groove 202, and covering the bottom and sidewalls of the first marking layer 208.

[0050] In the formation process of the first marking layer 208, the protective layer 205 protects the top of the first marking layer 208, reduces the probability of the first marking layer 208 being contaminated, and thus improves the metal reflectivity of the first marking layer 208.

[0051] In this embodiment, the material of the protective layer 205 includes one or more of SiO2, SiN and SiON.

[0052] The SiO2, SiN and SiON materials have good insulation properties, which can reduce the probability of the first marking layer 208 being contaminated.

[0053] It should be noted that the thickness of the protective layer 205 should not be too large or too small. If the thickness of the protective layer 205 is too large, the difficulty of removing the exposed protective layer 205 on both sides of the marking area 200A during the formation process of the first marking layer 208 will increase; if the thickness of the protective layer 205 is too small, the protective effect of the protective layer 205 on the first marking layer 208 will decrease, increasing the probability of the first marking layer 208 being contaminated. Therefore, in this embodiment, the thickness of the protective layer 205 is 50 angstroms to 500 angstroms.

[0054] The second device wafer 61 is a wafer for completing device fabrication, and the second device wafer 61 can be fabricated using integrated circuit fabrication technology.

[0055] In this embodiment, the second substrate includes a second substrate 211, NMOS devices and PMOS devices formed on the second substrate 211 by processes such as deposition and etching, and structures such as dielectric layers and metal interconnects formed on the devices.

[0056] It should be noted that, for ease of illustration, in this embodiment, only the second substrate 211 is shown as the second substrate, and the devices formed on the second substrate 211 are not shown.

[0057] In this embodiment, the second substrate 211 of the second device wafer 61 is a silicon substrate. In other embodiments, the material of the second substrate may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc. The second substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. The material of the second substrate may be a material suitable for process requirements or easy to integrate.

[0058] In this embodiment, the second substrate has a second front side (not shown) and a second back side (not shown). The second front side refers to the side of the second substrate that faces away from the second substrate 211; the second back side refers to the bottom surface of the second substrate 211, that is, the exposed surface of the second substrate 211.

[0059] In this embodiment, a second dielectric layer 210 is formed on the top of the second substrate. The second dielectric layer 210 serves as one of the bonding layers for bonding the first device wafer 60 and the second device wafer 61, and also provides a process basis for the second marking layer 212.

[0060] The material of the second dielectric layer 210 is a dielectric material. Therefore, the first device wafer 60 and the first device wafer 60 are bonded together by fusion bonding.

[0061] In this embodiment, the material of the second dielectric layer 210 includes one or more of SiO2, SiN and SiON.

[0062] In this embodiment, the second dielectric layer 210 is located on the second front side.

[0063] In this embodiment, the second marking layer 212 is exposed on the side of the second dielectric layer 210 facing away from the second substrate, so that the process equipment can accurately identify the second marking layer 212 during the bonding process.

[0064] The material of the second marking layer 212 is a material containing metal elements. Since the material containing metal elements has a strong reflectivity, during the bonding process of the first device wafer 60 and the second device wafer 61, the bonding process equipment can accurately identify the second marking layer 212, thereby achieving precise alignment between the first marking layer 208 and the second marking layer 212.

[0065] Since both the first marking layer 208 and the second marking layer 212 have strong reflectivity, the process equipment can accurately identify the positions of the first marking layer 208 and the second marking layer 212, thereby enabling the first marking layer 208 and the second marking layer 212 to achieve precise alignment.

[0066] In this embodiment, the material of the second marking layer 212 includes one or both of Cu and Al.

[0067] It should be noted that, since the second marking layer 212 and the first marking layer 208 can be aligned with each other, the bonding between the second dielectric layer 210 and the first dielectric layer 201 is higher, thereby further improving the packaging yield.

[0068] Figures 4 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the packaging structure of the present invention.

[0069] refer to Figure 4 A first device wafer 50 is provided, the first device wafer 50 includes a first substrate and a first dielectric layer 101 located on the first substrate, and the first device wafer 50 includes a marking region 100A.

[0070] In this embodiment, the packaging method is used to achieve wafer-level packaging, and the first device wafer 50 is used to bond with the second device wafer in subsequent processes.

[0071] The first device wafer 50 is a wafer for completing device fabrication, and the first device wafer 50 can be fabricated using integrated circuit fabrication technology.

[0072] In this embodiment, the first substrate includes a first substrate 100, NMOS devices and PMOS devices formed on the first substrate 200 by processes such as deposition and etching, and structures such as dielectric layers and metal interconnects formed on the devices.

[0073] It should be noted that, for ease of illustration, in this embodiment, only the first substrate 100 is shown, and the devices formed on the first substrate 100 are not shown.

[0074] In this embodiment, the first device wafer 50 includes a marking region 100A.

[0075] The marking area 100A is the region where the first device wafer 50 and the second device wafer can achieve self-alignment.

[0076] It should be noted that, for ease of illustration, this embodiment uses a single marking region 100A in the first device wafer 50 as an example. In other embodiments, the number of marking regions in the first device wafer 50 is not limited to one.

[0077] In this embodiment, the first substrate 100 of the first device wafer 50 is a silicon substrate. In other embodiments, the material of the first substrate may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc. The first substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. The material of the first substrate may be a material suitable for process requirements or easy to integrate.

[0078] In this embodiment, the first substrate has a first front side (not shown) and a first back side (not shown). The first front side refers to the side of the first substrate that faces away from the first substrate 100; the first back side refers to the bottom surface of the first substrate 100, that is, the exposed surface of the first substrate 100.

[0079] In this embodiment, a first dielectric layer 101 is formed on the top of the first substrate. The first dielectric layer 101 serves as one of the bonding layers for bonding the first device wafer and the subsequently provided second device wafer, and the first dielectric layer 101 also provides a process basis for the subsequent formation of grooves in the marking region 100A.

[0080] The first dielectric layer 201 is made of a dielectric material. Therefore, the first device wafer 50 and the subsequently provided second device wafer are bonded together by fusion bonding.

[0081] In this embodiment, the material of the first dielectric layer 101 includes one or more of SiO2, SiN and SiON.

[0082] In this embodiment, in the first device wafer 50, the first dielectric layer 101 is located on the first back side.

[0083] refer to Figure 5 In the marking area 100A, a groove 102 is formed in the first dielectric layer 101.

[0084] The groove 102 provides space for the subsequent formation of the first marking layer.

[0085] It should be noted that the depth of the groove 102 should not be too large or too small. If the depth of the groove 102 is too large, the etching process during the formation of the groove 102 may easily damage the device and the first substrate 100 at the bottom of the groove 102, thereby affecting the performance of the semiconductor structure. If the depth of the groove 102 is too small, the filling effect of the first marking layer in the groove 102 will be poor during the subsequent formation of the first marking layer, thereby affecting the alignment effect between the subsequent first marking layer and the second marking layer. Therefore, in this embodiment, the depth of the groove 102 is 2000 angstroms to 5000 angstroms. For example, the depth of the groove 102 is 2500 angstroms, 3000 angstroms, or 4000 angstroms.

[0086] In this embodiment, the process of forming the groove 102 in the first dielectric layer 101 includes a dry etching process.

[0087] It should be noted that the dry etching process includes anisotropic dry etching process. Anisotropic dry etching process has the characteristics of anisotropic etching, that is, the longitudinal etching rate is greater than the transverse etching rate. It can ensure the morphology quality of the sidewalls of the groove 102 during the formation of the groove 102 in the first dielectric layer 101.

[0088] refer to Figures 6 to 10 A first marking layer 108 is formed in the groove 102, and the material of the first marking layer 108 is a material containing metal elements.

[0089] In this embodiment, after forming a groove 102 in the first dielectric layer 101, a first marking layer 108 is formed at the bottom and sidewalls of the groove 102. Therefore, the first marking layer 108 is exposed on the side of the first dielectric layer 110 facing away from the first substrate, so that the bonding process equipment can accurately identify the first marking layer 108 during the bonding process of the first device wafer 50 and the subsequently provided second device wafer.

[0090] Moreover, the material of the first marking layer 108 is a material containing metal elements. Since the material containing metal elements has a strong reflectivity, in the subsequent bonding process of the first device wafer 50 and the second device wafer, the bonding process equipment can accurately identify the first marking layer 108 and the second marking layer, so as to achieve precise alignment between the first marking layer 108 and the second marking layer, thereby further improving the packaging yield.

[0091] It should be noted that, since materials containing metallic elements have strong reflectivity, it is sufficient for the first marking layer 108 to be formed in the groove 102. To reduce material consumption and lower costs in forming the first marking layer 108, in this embodiment, the first marking layer 108 is located at the bottom and sidewalls of the groove 102. In other embodiments, the first marking layer may also fill the groove.

[0092] In this embodiment, the step of forming a first marking layer 108 at the bottom and sidewall of the groove 102 includes: forming a first marking material layer 103 at the bottom and sidewall of the groove 102 and at the top of the first dielectric layer 101; removing the first marking material layer 103 located at the top of the first dielectric layer 101, and retaining the first marking material layer 103 located at the bottom and sidewall of the groove 102 as the first marking layer 108.

[0093] The process of forming the first marking layer 108 at the bottom and sidewalls of the groove 102 includes one or both of physical vapor deposition and chemical vapor deposition processes.

[0094] As an example, the process of forming the first marking layer 108 at the bottom and sidewalls of the groove 102 is a physical vapor deposition process. The physical vapor deposition process is simple to operate, has low process cost, produces a uniform and dense film, and has strong adhesion to the first dielectric layer 101.

[0095] It should be noted that the first marking material layer 103 located on top of the first dielectric layer 101 is removed to expose the top of the first dielectric layer 101, thereby providing a process basis for the subsequent bonding of the first device wafer 50 and the second device wafer.

[0096] In this embodiment, the material of the first marking layer 108 includes one or more of TiN, Ti, TaN, and Ta.

[0097] TiN, Ti, TaN and Ta materials are all materials containing metal elements. Since materials containing metal elements have a strong reflectivity, it is beneficial to accurately identify the first marking layer 108 and the second marking layer, thereby improving the alignment accuracy between the first marking layer 108 and the second marking layer.

[0098] refer to Figure 7 After the first marking material 103 is formed, before removing the first marking material layer 103 located on top of the first dielectric layer 101, the method further includes: forming a protective layer 105 in the groove 102, the protective layer 105 covering the bottom and sidewalls of the first marking material layer 103, and also extending to cover the first marking material layer 103 located on top of the first dielectric layer 101.

[0099] The protective layer 105 protects the top of the first marking material 103, reduces the probability of the first marking material 103 coming into contact with the subsequently formed mask layer, reduces the probability of the first marking material 103 being contaminated, and thereby improves the metallic reflectivity of the first marking material 103.

[0100] In this embodiment, the process of forming the protective layer 105 in the groove 102 includes chemical vapor deposition.

[0101] Chemical vapor deposition (CVD) is characterized by its simple operation, high efficiency, and good coverage, which enables the protective layer 105 to cover the bottom and sidewalls of the first marking material layer 103.

[0102] In this embodiment, the material of the protective layer 105 includes one or more of SiO2, SiN and SiON.

[0103] The SiO2, SiN and SiON materials have good insulation properties, which can reduce the probability of the first marking layer 208 being contaminated.

[0104] It should be noted that the thickness of the protective layer 105 should not be too large or too small. If the thickness of the protective layer 105 is too large, the difficulty of removing the exposed protective layer 105 on both sides of the marking area 100A during the formation process of the first marking layer 108 will increase; if the thickness of the protective layer 105 is too small, the protective effect of the protective layer 105 on the first marking layer 108 will decrease, increasing the probability of the first marking layer 108 being contaminated. Therefore, in this embodiment, the thickness of the protective layer 105 is 50 angstroms to 500 angstroms.

[0105] In this embodiment, the step of removing the first marker material layer 103 located on top of the first dielectric layer 101 includes: as follows Figure 8 As shown, a mask layer 106 is formed over a first marking material layer 103 in the groove 102, and the mask layer 106 also extends to cover a portion of the top of the first marking material layer 103 outside the groove 102; as Figure 9 As shown, patterning is performed using the mask layer 106 as a mask, and the first marker material layer 103 exposed by the mask layer 106 is removed; after removing the first marker material layer 103 exposed by the mask layer 106, the mask layer 106 is removed; as shown Figure 10 As shown, after removing the mask layer 106, the remaining first marking material layer 103 located on top of the first dielectric layer 101 is planarized, with the top of the first dielectric layer 101 as the stopping position.

[0106] In this embodiment, the material of the mask layer 106 includes organic materials. Specifically, the material of the mask layer 106 includes BARC (bottom anti-reflective coating) material.

[0107] In this embodiment, in the step of forming the mask layer 106, the mask layer 106 is formed on the protective layer 105.

[0108] In order to avoid the mask layer 106 from coming into contact with the first marking material layer 103 and reduce the probability of the mask layer 106 contaminating the first marking material layer 103, the mask layer 106 is formed on the protective layer 105.

[0109] In this embodiment, during the patterning process using the mask layer 106 as a mask, the protective layer 105 exposed by the mask layer 106 is also removed.

[0110] In the same step, removing the protective layer 105 and the first marking material layer 103 exposed by the mask layer 106 can reduce the number of process steps and lower the process cost.

[0111] In this embodiment, the patterning process using the mask layer 106 as a mask includes a wet etching process.

[0112] The wet etching process is isotropic, which can reduce damage to the first dielectric layer 101 while removing the protective layer 105 and the first marking material layer 103 exposed by the mask layer 106, so that the first dielectric layer 101 can be preserved.

[0113] In this embodiment, during the planarization process of the remaining first marking material layer 103 located on top of the first dielectric layer 101, the remaining protective layer 105 located on top of the first dielectric layer 101 is also planarized, while retaining the remaining protective layer 105 located in the groove 102.

[0114] In this embodiment, the process of planarizing the remaining first marking material layer 103 located on top of the first dielectric layer 101 includes a chemical mechanical polishing process.

[0115] refer to Figure 11 A second device wafer 51 is provided, the second device wafer 51 includes a second substrate and a second dielectric layer 110 located on the second substrate, a second marking layer 112 is formed in the side of the second dielectric layer 110 facing away from the second substrate, and the material of the second marking layer 112 is a material containing metal elements.

[0116] The second device wafer 51 is a wafer for completing device fabrication, and the second device wafer 51 can be fabricated using integrated circuit fabrication technology.

[0117] In this embodiment, the second substrate includes a second substrate 111, devices such as NMOS devices and PMOS devices formed on the second substrate 111 by processes such as deposition and etching, and structures such as dielectric layers and metal interconnects formed on the devices.

[0118] It should be noted that, for ease of illustration, in this embodiment, only the second substrate 111 is shown as the second substrate, and the devices formed on the second substrate 111 are not shown.

[0119] In this embodiment, the second substrate 111 of the second device wafer 51 is a silicon substrate. In other embodiments, the material of the second substrate may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc. The second substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. The material of the second substrate may be a material suitable for process requirements or easy to integrate.

[0120] In this embodiment, the second substrate has a second front side (not shown) and a second back side (not shown). The second front side refers to the side of the second substrate that faces away from the second substrate 111; the second back side refers to the bottom surface of the second substrate 111, that is, the exposed surface of the second substrate 111.

[0121] In this embodiment, a second dielectric layer 110 is formed on the top of the second substrate. The second dielectric layer 110 serves as one of the bonding layers for bonding the first device wafer 50 and the second device wafer 51, and also provides a process basis for the formation of the second marking layer 112.

[0122] The material of the second dielectric layer 110 is a dielectric material. Therefore, the first device wafer 50 and the first device wafer 51 are bonded together by fusion bonding.

[0123] In this embodiment, the material of the second dielectric layer 110 includes one or more of SiO2, SiN and SiON.

[0124] In this embodiment, the second dielectric layer 110 is located on the second front side.

[0125] In this embodiment, the second marking layer 112 is exposed on the side of the second dielectric layer 110 facing away from the second substrate, so that the process equipment can accurately identify the second marking layer 112 during the bonding process.

[0126] In this embodiment, the material of the second marking layer 112 includes one or both of Cu and Al.

[0127] Specifically, the material of the second marking layer 112 is a material containing metal elements. Since the material containing metal elements has a strong reflectivity, during the bonding process of the first device wafer 50 and the second device wafer 51, the bonding process equipment can accurately identify the second marking layer 112, thereby achieving precise alignment between the first marking layer 108 and the second marking layer 112.

[0128] Continue to refer to Figure 11 The second dielectric layer 110 is disposed opposite to the first dielectric layer 101, and the second marking layer 112 is aligned with the first marking layer 108. The second dielectric layer 110 and the first dielectric layer 101 are bonded together by a bonding process.

[0129] Since both the first marking layer 108 and the second marking layer 112 have strong reflectivity, the process equipment can accurately identify the positions of the first marking layer 108 and the second marking layer 112, thereby enabling the first marking layer 108 and the second marking layer 112 to achieve precise alignment.

[0130] It should be noted that, since the second marking layer 112 and the first marking layer 108 can be aligned with each other, the bonding degree between the second dielectric layer 110 and the first dielectric layer 101 is higher, thereby further improving the packaging yield.

[0131] In this embodiment, both the second dielectric layer 110 and the first dielectric layer 101 are dielectric materials. Therefore, the bonding between the second dielectric layer 110 and the first dielectric layer 101 is achieved by fusion bonding.

[0132] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A packaging method, characterized in that, include: A first device wafer is provided, the first device wafer including a first substrate and a first dielectric layer located on the first substrate, the first device wafer including a marking region; In the marking area, a groove is formed in the first dielectric layer; A first marking layer is formed in the groove. The material of the first marking layer is a material containing a metal element. The material containing the metal element provides enhanced reflectivity for optical detection in the bonding process, so as to ensure that the first marking layer can be accurately identified by the process equipment. A protective layer is formed on the first marking layer in the groove; A second device wafer is provided, the second device wafer including a second substrate and a second dielectric layer located on the second substrate, a second marking layer is formed in the side of the second dielectric layer facing away from the second substrate, and the material of the second marking layer is a material containing metal elements; The second dielectric layer is positioned opposite to the first dielectric layer, and the second marking layer is aligned with the first marking layer. The second dielectric layer and the first dielectric layer are then bonded together using a melt bonding process. In the step of forming the first marking layer in the groove, the first marking layer is located at the bottom and sidewall of the groove; The step of forming a first marking layer at the bottom and sidewalls of the groove includes: forming a first marking material layer at the bottom and sidewalls of the groove and at the top of the first dielectric layer; removing the first marking material layer at the top of the first dielectric layer, and retaining the first marking material layer at the bottom and sidewalls of the groove as the first marking layer; The step of removing the first marking material layer located on top of the first dielectric layer includes: forming a mask layer above the first marking material layer in the groove, the mask layer further extending to cover a portion of the top of the first marking material layer outside the groove; performing patterning processing using the mask layer as a mask to remove the first marking material layer exposed by the mask layer; after removing the first marking material layer exposed by the mask layer, planarizing the remaining first marking material layer located on top of the first dielectric layer with the top of the first dielectric layer as the stop position; and removing the mask layer after the planarization process. In the step of forming the mask layer, the mask layer is formed on the protective layer; During the patterning process using the mask layer as a mask, the protective layer exposed by the mask layer is also removed.

2. The packaging method as described in claim 1, characterized in that, In the step of providing the first device wafer, the first substrate has a first front side and a first back side opposite to each other, and the first dielectric layer is located on the first back side.

3. The packaging method as described in claim 1, characterized in that, In the step of providing the second device wafer, the second substrate has a second front side and a second back side opposite to each other, and the second dielectric layer is located on the second front side.

4. The packaging method as described in claim 1, characterized in that, In the step of forming a first marking layer in the groove, the first marking layer is located at the bottom and sidewalls of the groove, or the first marking layer fills the groove.

5. The packaging method as described in claim 1, characterized in that, The protective layer also covers the bottom and sidewalls of the first marking material layer, and extends to cover the first marking material layer located on top of the first dielectric layer; During the planarization process of the remaining first marking material layer located on top of the first dielectric layer, the remaining protective layer located on top of the first dielectric layer is also planarized, while retaining the remaining protective layer located in the groove.

6. The packaging method as described in claim 1, characterized in that, The process of forming the first marker layer at the bottom and sidewalls of the groove includes one or both of physical vapor deposition and chemical vapor deposition processes.

7. The packaging method as described in claim 1, characterized in that, The material of the first labeling layer includes one or more of TiN, Ti, TaN, and Ta.

8. The packaging method as described in claim 1, characterized in that, The process for forming a protective layer in the groove includes chemical vapor deposition.

9. The packaging method as described in claim 1, characterized in that, The material of the second marking layer includes one or both of Cu and Al.

10. The packaging method as described in claim 1, characterized in that, The material of the protective layer includes one or more of SiO2, SiN and SiON.

11. The packaging method as described in claim 1, characterized in that, In the step of patterning using the mask layer as a mask, the patterning process includes a wet etching process.

12. A packaging structure formed by the packaging method according to any one of claims 1 to 11, characterized in that, include: A first device wafer, the first device wafer including a first substrate and a first dielectric layer located on the first substrate, the first device wafer including a marking region; The groove is located in the marking area and in the surface of the first dielectric layer facing away from the first substrate; A first marking layer is located in the groove, and the material of the first marking layer is a material containing metal elements. The material containing metal elements provides enhanced reflectivity for optical detection in the bonding process, so as to ensure that the first marking layer can be accurately identified by the process equipment. A protective layer is located in the groove and covers the first marking layer; A second device wafer bonded to the first device wafer, the second device wafer including a second substrate and a second dielectric layer on the second substrate, a second marking layer formed on the side of the second dielectric layer facing away from the second substrate, the material of the second marking layer being a material containing a metal element, the second dielectric layer being disposed opposite to the first dielectric layer and bonded by fusion bonding, and the second marking layer being aligned with the first marking layer.

13. The packaging structure as described in claim 12, characterized in that, In the first device wafer, the first substrate has a first front side and a first back side opposite to each other, and the first dielectric layer is located on the first back side.

14. The packaging structure as described in claim 12, characterized in that, In the second device wafer, the second substrate has a second front side and a second back side facing each other, and the second dielectric layer is located on the second front side.

15. The packaging structure as described in claim 12, characterized in that, The first marking layer is located at the bottom and sidewalls of the groove, or the first marking layer fills the groove.

16. The packaging structure as described in claim 12, characterized in that, The depth of the groove is 2000 angstroms to 5000 angstroms.

17. The packaging structure as described in claim 12, characterized in that, The material of the first labeling layer includes one or more of TiN, Ti, TaN, and Ta.

18. The packaging structure as described in claim 12 or 13, characterized in that, The thickness of the first marking layer is 50 angstroms to 200 angstroms.

19. The packaging structure as described in claim 12, characterized in that, The thickness of the protective layer is 50 angstroms to 500 angstroms.

20. The packaging structure as described in claim 12, characterized in that, The material of the protective layer includes one or more of SiO2, SiN and SiON.

21. The packaging structure as described in claim 12, characterized in that, The material of the second marking layer includes one or both of Cu and Al.

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