Semiconductor structure and methods for forming semiconductor structures

Abstract

This disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The method includes: providing a substrate, the substrate including an initial fin-shaped active region and a first isolation structure located between adjacent initial fin-shaped active regions; etching the initial fin-shaped active regions and the first isolation structure to form a fin-shaped active region and a second isolation structure located between adjacent fin-shaped active regions, the top surface of the fin-shaped active region and the top surface of the second isolation structure being within a preset height range; etching the second isolation structure using a wet etching process to form a fin while forming a third isolation structure and a gate trench located between adjacent fin-shaped active regions.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, a semiconductor structure and a method for forming a semiconductor structure. Background Technology

[0002] When forming a FinFET structure, the gate structure and gate oxide layer need to be embedded in the substrate by etching a gate trench. However, the sidewalls of the gate trench are easily damaged during the etching process, which affects the gate oxide interface state of the FinFET structure and leads to device reliability failure. Summary of the Invention

[0003] This disclosure provides a semiconductor structure and a method for forming a semiconductor structure.

[0004] On one hand, embodiments of this disclosure provide a method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate including an initial fin-shaped active region and a first isolation structure located between adjacent initial fin-shaped active regions; etching the initial fin-shaped active regions and the first isolation structure to form a fin-shaped active region and a second isolation structure located between adjacent fin-shaped active regions, the top surface of the fin-shaped active region and the top surface of the second isolation structure being within a preset height range; etching the second isolation structure using a wet etching process to form a fin portion while forming a third isolation structure and a gate trench located between adjacent fin-shaped active regions.

[0005] In some embodiments, the height of the fin-shaped active region is less than the height of the initial fin-shaped active region.

[0006] In some embodiments, etching the initial fin-shaped active region and the first isolation structure forms a fin-shaped active region and a second isolation structure located between adjacent fin-shaped active regions. The top surface of the fin-shaped active region and the top surface of the second isolation structure are within a preset height range. This includes: controlling the etching selectivity ratio to 1:1, and using a dry etching process to etch the initial fin-shaped active region and the first isolation structure to form the fin-shaped active region and the second isolation structure located between adjacent fin-shaped active regions; wherein the top surface of the fin-shaped active region and the top surface of the second isolation structure are at the same height.

[0007] In some embodiments, the etching gases used in the dry etching process include CHF3, CF4, HBr, and Cl2.

[0008] In some embodiments, the etching solution used in the wet etching process includes a diluted hydrofluoric acid solution, wherein the volume ratio of hydrogen fluoride to deionized water in the diluted hydrofluoric acid solution is 1:150 to 1:250.

[0009] In some embodiments, the method further includes: using ions of a preset type to perform ion implantation on two adjacent initial fin-shaped active regions to form a source and a drain located in the two adjacent initial fin-shaped active regions respectively; wherein the preset type of ions includes at least one of the following: phosphorus ions, antimony ions, arsenic ions, and boron ions.

[0010] In some embodiments, the method further includes: forming a gate oxide layer in the gate trench; and forming a gate structure in the gate trench where the gate oxide layer is formed to form a fin field-effect transistor.

[0011] In some embodiments, forming a gate structure in a gate trench where the gate oxide layer is formed includes: sequentially forming a metal barrier layer, a conductive metal layer, and a protective layer in the gate trench where the gate oxide layer is formed to form the gate structure.

[0012] In some embodiments, the initial fin-shaped active region and the first isolation structure are formed by the following steps: providing an initial substrate; etching the initial substrate to form the substrate and the initial fin-shaped active region located on the substrate; wherein the initial fin-shaped active regions are arranged in a matrix, with a first direction as the row direction of the matrix and a second direction as the column direction of the matrix; the initial fin-shaped active regions extend in a third direction; a first contact hole with a first size or a second contact hole with a second size is included between two adjacent initial fin-shaped active regions along the first direction, the second size being larger than the first size; a first sub-isolation structure and a second sub-isolation structure are formed in the first contact hole and the second contact hole, respectively, the first sub-isolation structure and the second sub-isolation structure constituting the first isolation structure.

[0013] In some embodiments, the first isolation structure further includes an isolation layer, and the step of forming the first isolation structure further includes: forming the isolation layer covering the initial fin-shaped active region, the first sub-isolation structure, and the second sub-isolation structure.

[0014] In some embodiments, the first sub-isolation structure includes an initial first silicon oxide layer, and the second sub-isolation structure includes an initial second silicon oxide layer and an initial silicon nitride layer; forming the first sub-isolation structure and the second sub-isolation structure in the first contact hole and the second contact hole respectively includes: depositing silicon oxide material in the first contact hole to form the initial first silicon oxide layer; depositing silicon oxide material in the second contact hole to form the initial second silicon oxide layer; and depositing silicon nitride material in the second contact hole where the initial second silicon oxide layer is formed to form the initial silicon nitride layer.

[0015] In some embodiments, etching the initial fin-shaped active region and the first isolation structure to form a fin-shaped active region and a second isolation structure located between adjacent fin-shaped active regions includes: etching away the isolation layer; etching portions of the initial fin-shaped active region, the first sub-isolation structure, and the second sub-isolation structure to form a fin-shaped active region, a third sub-isolation structure, and a fourth sub-isolation structure, respectively; wherein the third sub-isolation structure and the fourth sub-isolation structure constitute the second isolation structure.

[0016] In some embodiments, the second isolation structure is etched using a wet etching process to form a fin while simultaneously forming a third isolation structure and a gate trench located between adjacent fin-shaped active regions. This includes: etching the remaining initial first silicon oxide layer and the remaining initial second silicon oxide layer using a wet etching process to form the fin while simultaneously forming the third isolation structure and the gate trench; wherein the third isolation structure includes a first silicon oxide layer, a second silicon oxide layer, and a silicon nitride layer; the gate trench includes a first gate sub-trench and a second gate sub-trench, the first gate sub-trench being located on the first silicon oxide layer, and the second gate trench being located between the silicon nitride layer and the adjacent fin; the depth of the first gate sub-trench is greater than the depth of the second gate trench.

[0017] In some embodiments, the method further includes: forming a bit line structure connected to one of the source / drain terminals; and forming a capacitor structure connected to the other source / drain terminal.

[0018] On the other hand, this disclosure provides a semiconductor structure formed using the method in any of the above embodiments, the structure comprising: a substrate; a fin-shaped active region located on the substrate; a third isolation structure located between adjacent fin-shaped active regions; wherein at least a portion of the top surface of the third isolation structure is lower than the top surface of the fin-shaped active region, and the exposed fin-shaped active region serves as a fin.

[0019] In some embodiments, the semiconductor structure includes at least a transistor structure, the transistor structure including a source and a drain located in two adjacent fins, and a gate located between adjacent fins.

[0020] In this embodiment, firstly, a substrate is provided, on which an initial fin-shaped active region and a first isolation structure located between adjacent initial fin-shaped active regions are provided, such that the first isolation structure can isolate adjacent initial fin-shaped active regions. Secondly, the initial fin-shaped active regions and the first isolation structure are etched to form a fin-shaped active region and a second isolation structure located between adjacent fin-shaped active regions. The top surface of the fin-shaped active region and the top surface of the second isolation structure are within a preset height range, thus providing a relatively flat surface for subsequent etching to form fins and gate trenches. Finally, the second isolation structure is etched using a wet etching process, forming a third isolation structure and a gate trench located between adjacent fin-shaped active regions while simultaneously forming fins. This eliminates the need for forming gate trenches through plasma and physical bombardment, thereby effectively reducing lattice damage to the sidewalls of the gate trenches, thereby reducing the impact on the performance and reliability of semiconductor devices, while also improving the uniformity of fin height and reducing the differences between transistors. Attached Figure Description

[0021] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0022] Figure 1 A schematic diagram illustrating the implementation flow of a method for forming a semiconductor structure according to an embodiment of this disclosure;

[0023] Figures 2 to 8 This is a schematic diagram of the process of forming a semiconductor structure provided in an embodiment of this disclosure. Detailed Implementation

[0024] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0025] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0026] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0027] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0029] To reduce costs, the Dynamic Random Access Memory (DRAM) market is producing more chips on a single wafer to improve efficiency. Simultaneously, the market demand for portable mobile electronic devices requires smaller, more portable, and faster devices, making the continuous increase in DRAM storage capacity a necessity. To meet market demands and maximize profits, researchers are constantly reducing the effective size of planar structures and shrinking linewidths. After reaching the limits of electrical performance, to pursue ultimate performance and maximize profits, researchers have proposed a three-dimensional (3D) structure, burying the critical gate and gate oxide layer within the silicon substrate, thus forming the FinField-Effect Transistor (FinETF) structure.

[0030] In related technologies, dry etching is generally used to form gate trenches. The characteristic of dry etching is anisotropy. Due to plasma and physical bombardment, the sidewalls of the gate trenches etched anisotropically have poor interface roughness, which damages the silicon crystal structure and affects the gate oxide interface states of the FinFET structure, leading to device reliability failure.

[0031] Since the gate trench and the active area (AA) are different, the lattice damage caused by ion implantation in the AA can be repaired by subsequent high-temperature processing. However, if high-temperature repair is used after the gate trench is formed by dry etching, it will affect the previously implanted ion distribution again. Therefore, high-temperature repair is not an effective solution for the lattice damage caused by dry etching when forming the gate trench.

[0032] Before introducing the embodiments of this disclosure, let's define three directions that may be used in the following embodiments to describe the three-dimensional structure. Taking a Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis, and Z-axis. Ignoring the flatness of the top and bottom surfaces, in the directions of the top and bottom surfaces of the substrate (i.e., the plane on which the substrate lies), two intersecting (e.g., perpendicular) directions are defined as the first direction and the second direction. For example, the arrangement direction of the initial finned active regions can be defined as the first direction and the second direction, and the extension direction of the initial active regions can be defined as the third direction. Based on the first and second directions, the planar orientation of the substrate can be determined. In this embodiment of the disclosure, the first direction and the second direction are perpendicular to each other, and the third direction is located between the first and second directions. In this embodiment of the disclosure, the first direction is defined as the X-axis, the second direction as the Y-axis, and the third direction as the Z-axis.

[0033] This disclosure provides a method for forming a semiconductor structure, with reference to... Figure 1 The method includes steps S101 to S103, wherein:

[0034] Step S101: Provide a substrate, on which an initial fin-shaped active region is provided and a first isolation structure is located between adjacent initial fin-shaped active regions;

[0035] Here, the substrate may include a silicon substrate, which may also include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0036] The initial finned active regions are formed by etching the initial substrate. In some embodiments, multiple arrayed finned active regions can be formed in the substrate, and adjacent finned active regions are used to form a transistor, which serves as a transistor in a memory cell. In implementation, the arrangement of the finned active regions can be set according to the distribution of the memory cells of the specific memory, and is not limited here.

[0037] The first isolation structure can be a shallow trench isolation (STI) structure located between adjacent initial fin-shaped active regions. That is, the first isolation structure surrounds the initial fin-shaped active regions and is used to isolate adjacent initial fin-shaped active regions. In implementation, the material of the first isolation structure can be at least one of silicon oxide, silicon nitride, silicon oxynitride, borosilicate glass, or other suitable isolation materials. For example, the first isolation structure may include silicon oxide and silicon nitride; the process of forming the first isolation structure may involve first filling a trench with silicon oxide, and then filling the trench containing silicon oxide with silicon nitride, thereby forming the first isolation structure.

[0038] Step S102: Etch the initial fin-shaped active region and the first isolation structure to form the fin-shaped active region and the second isolation structure located between adjacent fin-shaped active regions. The top surface of the fin-shaped active region and the top surface of the second isolation structure are within a preset height range.

[0039] Here, the preset height range can be set according to the height of the initial fin-shaped active area and the etching precision. Step S102 is to reduce the height of the initial fin-shaped active area on the substrate and make the top surface of the fin-shaped active area and the top surface of the second isolation structure within the preset height range, providing a relatively flat plane for the subsequent wet etching process to form the fin. The remaining first isolation structure after etching forms the second isolation structure, and the remaining initial fin-shaped active area after etching forms the fin-shaped active area.

[0040] In some embodiments, the height of the fin-shaped active region is less than the height of the initial fin-shaped active region.

[0041] In some embodiments, the etching selectivity ratio between the initial finned active region and the first isolation structure can be controlled to 1:1. A dry etching process is used to etch the initial finned active region and the first isolation structure to form the finned active region and a second isolation structure located between adjacent finned active regions. In practice, the etching selectivity ratio between the initial finned active region and the first isolation structure can be made 1:1 by selecting the type and proportion of the etching gas, thereby ensuring that the top surface of the second isolation structure and the top surface of the finned active region are at the same height after etching. That is, the surface of the etched structure is flat. The etching gases used in the dry etching process may include trifluoromethane (CHF3), carbon tetrafluoride (CF4), hydrogen bromide (HBr), and chlorine (Cl2). In other embodiments, the etching gas may also include one or more of other fluorocarbon gases, such as difluoromethane (CH2F2), octafluoropropane (C3F8), perfluorobutadiene (C4F6), octafluorocyclobutane (C4F8), and octafluorocyclopentene (C5F8).

[0042] It should be noted that when the initial fin-shaped active region is made of silicon and the first isolation structure includes silicon oxide and silicon nitride, the etching selectivity ratio of silicon, silicon oxide and silicon nitride needs to be controlled to be 1:1:1. This allows silicon, silicon oxide and silicon nitride to be etched to the same horizontal height, meaning that the top surfaces of the formed fin-shaped active region and the second isolation structure are at the same horizontal height.

[0043] In some embodiments, when etching silicon oxide and / or silicon nitride, CHF3 at 120 standard milliliters per minute (sccm) to 180 sccm and CF4 at 30 sccm to 50 sccm can be used; when etching silicon, CHF3 at 80 sccm to 120 sccm, CF4 at 110 sccm to 150 sccm, HBr at 50 sccm to 70 sccm and Cl2 at 10 sccm to 25 sccm can be used.

[0044] In step S103, the second isolation structure is etched using a wet etching process, and the fins are formed simultaneously with the formation of the third isolation structure and the gate trench located between the adjacent fin-shaped active regions.

[0045] Here, the remaining second isolation structure after etching is the third isolation structure. Since part of the second isolation structure has been etched, at least part of the top surface of the third isolation structure will be lower than the top surface of the fin active region. In this way, gate trenches will be formed on the third isolation structure between adjacent fin active regions, and the sidewalls of part of the fin active region will be exposed. The fin active regions with exposed sidewalls can form fins.

[0046] In some embodiments, the etching solution used in the wet etching process may include a diluted hydrofluoric acid solution, wherein the volume ratio of hydrogen fluoride to deionized water in the diluted hydrofluoric acid solution is 1:150 to 1:250, for example, 1:200. In this embodiment, by controlling the volume ratio of hydrogen fluoride to deionized water in the diluted hydrofluoric acid solution, the fin-shaped active region can be avoided during the etching of the second isolation structure, resulting in a higher fin and thus improving the operating speed of the semiconductor device.

[0047] In some embodiments, the etching time of the second isolation structure can also be controlled so that the depth of the formed gate trench meets a preset depth.

[0048] In this embodiment, firstly, a substrate is provided, on which an initial fin-shaped active region and a first isolation structure located between adjacent initial fin-shaped active regions are provided, such that the first isolation structure can isolate adjacent initial fin-shaped active regions. Secondly, the initial fin-shaped active regions and the first isolation structure are etched to form a fin-shaped active region and a second isolation structure located between adjacent fin-shaped active regions. The top surface of the fin-shaped active region and the top surface of the second isolation structure are within a preset height range, thus providing a relatively flat surface for subsequent etching to form fins and gate trenches. Finally, the second isolation structure is etched using a wet etching process, forming a third isolation structure and a gate trench located between adjacent fin-shaped active regions while simultaneously forming fins. This eliminates the need for forming gate trenches through plasma and physical bombardment, thereby effectively reducing lattice damage to the sidewalls of the gate trenches, thereby reducing the impact on the performance and reliability of semiconductor devices, while also improving the uniformity of fin height and reducing the differences between transistors.

[0049] The following will refer to Figures 2 to 8 The process of forming a semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0050] First, refer to Figure 2 and Figure 3Step S101 is executed, providing a substrate 11, which includes an initial fin-shaped active region 12a and a first isolation structure 13 located between adjacent initial fin-shaped active regions 12a. Figure 2 and Figure 3 The right image in the diagram is a cross-sectional view along the AA' direction in the left image.

[0051] In some embodiments, the initial fin-shaped active region and the first isolation structure can be formed through steps S1011 to S1013, wherein:

[0052] Step S1011: Provide an initial substrate;

[0053] Step S1012: Etch the initial substrate to form a substrate and an initial fin-shaped active region located on the substrate; wherein, the initial fin-shaped active regions are arranged in a matrix, with the first direction as the row direction of the matrix and the second direction as the column direction of the matrix; the initial fin-shaped active regions extend in the third direction; between two adjacent initial fin-shaped active regions along the first direction, there is a first contact hole with a first size or a second contact hole with a second size, the second size being larger than the first size;

[0054] In step S1013, a first sub-isolation structure and a second sub-isolation structure are formed in the first contact hole and the second contact hole, respectively, and the first sub-isolation structure and the second sub-isolation structure constitute the first isolation structure.

[0055] Here, the initial substrate and the initial fin-shaped active region on the substrate can be formed by etching the initial substrate using wet etching processes (e.g., etching with strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid) or dry etching processes (e.g., plasma etching, reactive ion etching, or ion milling).

[0056] In some embodiments, the first sub-isolation structure and the second sub-isolation structure may be made of the same material, such as silicon oxide; the first sub-isolation structure and the second sub-isolation structure may also be made of different materials, for example, the first sub-isolation structure may be made of silicon oxide, and the second sub-isolation structure may be made of silicon oxide and silicon nitride.

[0057] refer to Figure 2 The initial substrate is etched to form a substrate 11 and an initial fin-shaped active region 12a located on the substrate 11. From Figure 2As shown in the left figure, the initial fin-shaped active regions 12a are arranged in a matrix, with the X-axis as the row direction and the Y-axis as the column direction. The initial fin-shaped active regions 12a extend along the Z-axis. The angle θ between the Z-axis and X-axis can be greater than 0 degrees (°) and less than 90°. Adjacent initial fin-shaped active regions 12a along the X-axis are separated by either a first contact hole 102 with a first size d1 or a second contact hole 103 with a second size d2, where the second size d2 is larger than the first size d1. This means the spacing between the initial fin-shaped active regions 12a along the X-axis is different. Due to the load effect, the depths of the first contact hole 102 and the second contact hole 103 are different, with the second contact hole 103 being deeper than the first contact hole 102. In other words, the depth of the contact holes in areas with dense initial fin-shaped active regions is less than the depth of the contact holes in areas with sparse initial fin-shaped active regions. In addition, in the X-axis direction, the first contact hole 102 and the second contact hole 103 are alternately arranged on both sides of the initial fin-shaped active region.

[0058] refer to Figure 2 and Figure 3 A first sub-isolation structure 131 and a second sub-isolation structure 132 are formed in the first contact hole 102 and the second contact hole 103, respectively, and the first sub-isolation structure 131 and the second sub-isolation structure 132 constitute the first isolation structure 13. Figure 3 As can be seen, the depth of the second sub-isolation structure 132 is greater than the depth of the first sub-isolation structure 131.

[0059] In some embodiments, the first isolation structure further includes an isolation layer, and the step of forming the first isolation structure further includes: step S1014, forming an isolation layer covering the initial fin-shaped active region, the first sub-isolation structure, and the second sub-isolation structure.

[0060] Continue to refer to Figure 3 An isolation layer 133 is formed on the initial fin-shaped active region 12a, the first sub-isolation structure 131, and the second sub-isolation structure 132. Thus, the first isolation structure 13 includes the first sub-isolation structure 131, the second sub-isolation structure 132, and the isolation layer 133.

[0061] In some embodiments, the first sub-isolation structure includes an initial first silicon oxide layer, and the second sub-isolation structure includes an initial second silicon oxide layer and an initial silicon nitride layer;

[0062] The implementation of step S1013 may include steps S1131 to S1133, wherein:

[0063] Step S1131: Deposit silicon oxide material into the first contact hole to form an initial first silicon oxide layer;

[0064] Step S1132: Deposit silicon oxide material in the second contact hole to form an initial second silicon oxide layer;

[0065] Step S1133: Deposit silicon nitride material into the second contact hole where the initial second silicon oxide layer is formed to form an initial silicon nitride layer.

[0066] Here, because the size of the first contact hole is smaller than the size of the second contact hole and the depth of the first contact hole is smaller than the depth of the second contact hole in the first direction, under the same deposition process and deposition conditions, when the first contact hole is filled with silicon oxide material, the second contact hole is not yet filled with silicon oxide material, leaving gaps. Silicon nitride material is continued to be deposited in the second contact hole where the initial second silicon oxide layer has been formed until the second contact hole is filled. This forms a second sub-isolation structure including the initial second silicon oxide layer and the initial silicon nitride layer, thereby improving the isolation effect of the first isolation structure. In other embodiments, silicon oxide material can also be deposited in the gaps, so that the isolation material in both the first and second sub-isolation structures is silicon oxide.

[0067] Continue to refer to Figure 2 and Figure 3 Silicon oxide material is deposited in the first contact hole 102 to form an initial first silicon oxide layer; silicon oxide material is deposited in the second contact hole 103 to form an initial second silicon oxide layer 1321; silicon nitride material is deposited in the second contact hole 103 where the initial second silicon oxide layer 1321 is formed to form an initial silicon nitride layer 1322. Thus, the second sub-isolation structure 132 includes the initial second silicon oxide layer 1321 and the initial silicon nitride layer 1322.

[0068] In practice, silicon oxide and silicon nitride materials can be deposited and an isolation layer can be formed using any of the following deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0069] The following is for reference. Figure 3 and Figure 4 In step S102, the initial fin-shaped active region 12a and the first isolation structure 13 are etched to form the fin-shaped active region 12 and the second isolation structure 14 located between adjacent fin-shaped active regions 12. The top surface of the fin-shaped active region 12 and the top surface of the second isolation structure 14 are within a preset height range.

[0070] In some embodiments, the implementation of step S102 may include steps S1021 and S1022, wherein:

[0071] Step S1021: Etch to remove the isolation layer;

[0072] Step S1022: Etch the initial fin-shaped active region, the first sub-isolation structure, and the second sub-isolation structure to form the fin-shaped active region, the third sub-isolation structure, and the fourth sub-isolation structure, respectively.

[0073] The third and fourth sub-isolation structures constitute the second isolation structure.

[0074] Here, after the first sub-isolation structure is etched, a third sub-isolation structure will be formed, and after the second sub-isolation structure is etched, a fourth sub-isolation structure will be formed. A dry etching process can be used to etch away the isolation layer and partially etch the initial fin-shaped active region, the first sub-isolation structure, and the second sub-isolation structure. This allows the top surface of the fin-shaped active region 12 and the top surface of the second isolation structure 14 to be at the same height.

[0075] refer to Figure 3 The isolation layer 133 is etched away, thereby exposing the top surface of the initial fin-shaped active region 12a, the top surface of the first sub-isolation structure 131, and the top surface of the second sub-isolation structure 132; portions of the initial fin-shaped active region 12a, the first sub-isolation structure 131, and the second sub-isolation structure 132 are etched to form, respectively, the top surfaces of the initial fin-shaped active region 12a, the first sub-isolation structure 131, and the second sub-isolation structure 132. Figure 4 The diagram shows the fin-shaped active region 12, the third sub-isolation structure 141, and the fourth sub-isolation structure 142. The third sub-isolation structure 141 and the fourth sub-isolation structure 142 constitute the second isolation structure 14. The third sub-isolation structure 141 may include the remaining initial first silicon oxide layer, and the fourth sub-isolation structure 142 includes the remaining initial second silicon oxide layer and the remaining initial silicon nitride layer.

[0076] It is understandable that, in order to provide a flat surface for the wet etching process, the initial fin-shaped active region, the first sub-isolation structure, and the second sub-isolation structure can be etched by a dry etching process, thereby reducing the height of the initial fin-shaped active region, the first sub-isolation structure, and the second sub-isolation structure, and making the top surfaces of the three structures at the same height.

[0077] The following will refer to Figures 4 to 6 In step S103, the second isolation structure 14 is etched using a wet etching process, and the fin 17 is formed simultaneously with the formation of the third isolation structure 15 and the gate trench 16 located between the adjacent fin-shaped active regions 12.

[0078] When the isolation materials in the first and second sub-isolation structures of the second isolation structure are the same, after etching the second isolation structure using a wet etching process, a structure like this will be formed. Figure 5 The third isolation structure 15 shown and the gate trench 16 located between adjacent fin-shaped active regions 12 also form fins 17. Due to the loading effect, the etching depth of the first sub-isolation structure is deeper than that of the second sub-isolation structure. Therefore, the top surface of the fifth sub-isolation structure 151 in the third isolation structure 15 is lower than the top surface of the sixth sub-isolation structure 152. It can also be seen that the side surfaces of the fins 17 have different heights, that is, the fins 17 have a height difference, which can improve the operating speed of the semiconductor device.

[0079] In some embodiments, the implementation of step S103, "etching the second isolation structure using a wet etching process, and forming fins while forming the third isolation structure and the gate trench located between adjacent fin-shaped active regions", may include step S1031, etching the remaining initial first silicon oxide layer and the remaining initial second silicon oxide layer using a wet etching process, and forming fins while forming the third isolation structure and the gate trench.

[0080] The third isolation structure includes a first silicon oxide layer, a second silicon oxide layer, and a silicon nitride layer; the gate trench includes a first gate sub-trench and a second gate sub-trench, the first gate sub-trench is located on the first silicon oxide layer, and the second gate sub-trench is located between the silicon nitride layer (i.e., the remaining initial silicon nitride layer) and the adjacent fin; the depth of the first gate sub-trench is greater than the depth of the second gate sub-trench.

[0081] Here, by selecting process parameters such as the type, concentration, and temperature of the etching solution in the wet etching process, it is possible to etch only silicon oxide material without etching silicon nitride material during the etching process.

[0082] refer to Figure 4 and Figure 6The remaining initial first silicon oxide layer and the remaining initial second silicon oxide layer are etched using a wet etching process to form a fifth sub-isolation structure 151, a sixth sub-isolation structure 152, a first gate trench 161 located on the fifth sub-isolation structure 151, and a second gate trench 162 located on the sixth sub-isolation structure 152. Simultaneously, fin-shaped active regions 12 on the side surfaces are exposed to form fins 17. The fifth sub-isolation structure 151 includes a first silicon oxide layer, and the sixth sub-isolation structure 152 includes a second silicon oxide layer 1521 and a silicon nitride layer 1522 in contact with the side surface of the second silicon oxide layer 1521. Therefore, the third isolation structure 15 includes a first silicon oxide layer (i.e., the fifth sub-isolation structure 151), a second silicon oxide layer 1521, and a silicon nitride layer 1522. The gate trench 16 includes a first gate sub-trench 161 and a second gate sub-trench 162; wherein, the second gate sub-trench 162 is located between the silicon nitride layer 1522 and the adjacent fin 17, that is, on the second silicon oxide layer 1521, and the depth of the first gate sub-trench 161 is greater than the depth of the second gate sub-trench 162.

[0083] In some embodiments, the method of forming a semiconductor structure further includes: implanting ions of a predetermined type into two adjacent initial fin-shaped active regions to form a source and a drain located in the two adjacent initial fin-shaped active regions, respectively; wherein the predetermined type of ions includes at least one of the following: phosphorus ions, antimony ions, and arsenic ions. In other embodiments, the predetermined type of ions may also include at least one of the following: boron ions, gallium ions, and indium ions.

[0084] In some embodiments, the method for forming a semiconductor structure further includes steps S104 and S105, wherein:

[0085] Step S104: Form a gate oxide layer in the gate trench;

[0086] Step S105: A gate structure is formed in a gate trench with a gate oxide layer to form a fin field-effect transistor.

[0087] Here, the material of the gate oxide layer can include silicon oxide, silicon oxynitride, etc. Since the damage to the sidewalls of the gate trench is smaller, this improves the interface states of the gate oxide layer formed in the gate trench, thereby improving the reliability of the semiconductor device.

[0088] refer to Figure 7 In the gate trench (see reference) Figure 5 A gate oxide layer 18 is formed in the gate trench 16 and the finned active region 12; a gate structure 19 is formed in the gate trench and the finned active region 12 to form a fin field-effect transistor.

[0089] refer to Figure 8 , Figure 8 The right image in the diagram is a cross-sectional view along the AA' direction in the left image, showing the first and second gate trenches (see reference). Figure 6 A gate oxide layer 18 is formed on the first gate sub-trench 161 and the second gate sub-trench 162, as well as the fin active region 12. A gate structure 19 is then formed on the gate oxide layer 18 to form a fin field-effect transistor.

[0090] In some embodiments, the gate may include a gate oxide layer, a metal barrier layer, a conductive metal layer, and a protective layer, and the implementation of step S105 may include:

[0091] A metal barrier layer, a conductive metal layer, and a protective layer are sequentially formed in a gate trench where a gate oxide layer is formed to form a gate structure.

[0092] The metal barrier layer not only regulates the threshold voltage of the semiconductor structure but also acts as a barrier layer to prevent metal contamination of the gate oxide layer from the conductive metal layer. Furthermore, the metal barrier layer can also serve as an adhesion layer, improving the adhesion between the conductive metal layer and the gate oxide layer, thereby allowing the conductive metal layer and the gate oxide layer to grow together more effectively. In implementation, the material of the metal barrier layer can be at least one of the following: titanium nitride (TiN), lanthanum oxide (La2O3), zirconium silicide (ZrSi2), molybdenum silicide (MoSi2), tantalum silicide (TaSi2), nickel silicide (NiSi2), tantalum aluminum nitride (TaAl), aluminum tantalum carbide (TaAlC), aluminum tantalum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), or tantalum silicon nitride (TaSiN).

[0093] The conductive metal layer can be used as the conductive electrode of the gate structure. The material of the conductive metal layer can be any material with good conductivity, such as any one of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu).

[0094] The protective layer can cover the conductive metal layer, thus protecting the conductive metal layer. The protective layer can be silicon nitride or other suitable materials.

[0095] During implementation, any of the following deposition processes can be used to form the gate oxide layer, metal barrier layer, conductive metal layer, and protective layer: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes.

[0096] When forming the gate structure, firstly, a gate oxide layer (which can be silicon oxide), a metal barrier layer, and an initial conductive metal layer (which can be tungsten) are sequentially deposited in the gate trench. After CMP, part of the initial conductive metal layer is etched so that the top surface of the initial conductive metal layer is lower than the top surface of the fin-shaped active region to form a conductive metal layer. Then, silicon nitride is filled on the conductive metal layer to form a protective layer. The gate structure thus formed includes a gate oxide layer, a metal barrier layer, a conductive metal layer, and a protective layer.

[0097] In this embodiment, the gate structure is located in the substrate, thus it is a buried gate structure, which improves the integration density of the semiconductor device and enables miniaturization. Furthermore, in the first direction, the gate structure sequentially includes a conductive metal layer, a metal barrier layer, and a gate oxide layer from the inside out. This reduces the leakage current problem caused by miniaturization, thereby reducing the power consumption of the semiconductor device and improving its reliability.

[0098] In some embodiments, the method for forming a semiconductor structure further includes steps S106 and S107, wherein:

[0099] Step S106: Form a bit line structure connected to a source / drain.

[0100] Step S107: A capacitor structure is formed that is connected to another source / drain.

[0101] Here, bit lines are used to read or write the saved state of the memory cell; the bit line structure can include metallic materials, such as tungsten, aluminum, cobalt, etc. The capacitor structure can store data, and the capacitor structure can include a first electrode layer, a dielectric layer, and a second electrode layer stacked sequentially.

[0102] In this embodiment, the materials of the first electrode layer and the second electrode layer may include metal nitrides or metal silicides, such as titanium nitride. The material of the dielectric layer may include a high-k dielectric material, such as lanthanum oxide (La₂O₃), aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), hafnium oxynitride (HfON), or hafnium silicate (HfSiO₂). x One or any combination of zirconium oxide (ZrO2) or zirconium oxide (ZrO2).

[0103] This disclosure also provides a semiconductor structure formed using any of the methods described in the foregoing embodiments, with reference to... Figure 5 or Figure 6 The semiconductor structure includes:

[0104] Base 11;

[0105] Fin-shaped active region 12 located on base 11;

[0106] A third isolation structure 15 is located between adjacent fin-shaped active regions 12;

[0107] In this configuration, at least a portion of the top surface of the third isolation structure 15 is lower than the top surface of the fin-shaped active region 12, and the exposed fin-shaped active region 12 serves as the fin portion 17.

[0108] In some embodiments, reference Figure 7 The third isolation structure 15 includes a fifth sub-isolation structure 151 and a sixth sub-isolation structure 152, wherein the top surface of the fifth sub-isolation structure 151 is lower than the top surface of the sixth sub-isolation structure 152. The materials of the fifth sub-isolation structure 151 and the sixth sub-isolation structure 152 can both be silicon oxide.

[0109] In some embodiments, the materials of the fifth sub-isolation structure 151 and the sixth sub-isolation structure 152 may be different. For example, refer to Figure 8 The fifth sub-isolation structure 151 may include a first silicon oxide layer, and the sixth sub-isolation structure 152 may include a second silicon oxide layer 1521 and a silicon nitride layer 1522 in contact with the side surface of the second silicon oxide layer 1521.

[0110] In some embodiments, reference Figure 7 or Figure 8 The semiconductor structure may also include:

[0111] The gate oxide layer 18 and the gate structure 19 located on the third isolation structure 15 together constitute the gate and are located between adjacent fins 17.

[0112] In some embodiments, in a first direction, the gate structure includes, from the inside out, a conductive metal layer and a metal barrier layer; a protective layer is located on the conductive metal layer.

[0113] In some embodiments, the semiconductor structure includes at least a transistor structure, the transistor structure including a source and a drain located in two adjacent fins, and a gate located between the adjacent fins.

[0114] In some embodiments, the semiconductor structure may further include: a bit line structure connected to one source / drain; and a capacitor structure connected to the other source / drain.

[0115] In some embodiments, the method for forming a semiconductor structure provided in this disclosure is used to form the semiconductor structure described in the above embodiments, and the semiconductor structure has similar beneficial effects to the method embodiments.

[0116] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled or directly coupled to each other.

[0117] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0118] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0119] The above descriptions are merely some embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this disclosure should be included within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A substrate is provided, the substrate including initial fin-shaped active regions and a first isolation structure located between adjacent initial fin-shaped active regions, the initial fin-shaped active regions being arranged in a matrix, and a first contact hole having a first size or a second contact hole having a second size, the second size being larger than the first size, being located between two adjacent initial fin-shaped active regions along a first direction; a first sub-isolation structure having an initial first silicon oxide layer and a second sub-isolation structure including an initial second silicon oxide layer and an initial silicon nitride layer are formed in the first contact hole and the second contact hole, respectively, including: depositing silicon oxide material in the first contact hole to form the initial first silicon oxide layer; depositing silicon oxide material in the second contact hole to form the initial second silicon oxide layer; and depositing silicon nitride material in the second contact hole where the initial second silicon oxide layer is formed to form the initial silicon nitride layer; the first sub-isolation structure and the second sub-isolation structure constitute the first isolation structure; The etching selectivity ratio is controlled at 1:1, and the initial fin-shaped active region, the initial first silicon oxide layer, the initial second silicon oxide layer and the initial silicon nitride layer are etched using a dry etching process to form the fin-shaped active region and the second isolation structure located between adjacent fin-shaped active regions. The top surface of the fin-shaped active region and the top surface of the second isolation structure are at the same height. The second isolation structure is etched using a wet etching process with an etching solution including a diluted hydrofluoric acid solution, wherein the volume ratio of hydrogen fluoride to deionized water in the diluted hydrofluoric acid solution is 1:150 to 1:

250. The fins are formed simultaneously with the formation of the third isolation structure and the gate trench located between adjacent fin-shaped active regions. The third isolation structure includes a fifth sub-isolation structure and a sixth sub-isolation structure located on two side surfaces of the fin that are disposed opposite to each other along the first direction. The top surface of the fifth sub-isolation structure is lower than the top surface of the sixth sub-isolation structure.

2. The method according to claim 1, characterized in that, The height of the fin-shaped active region is less than the height of the initial fin-shaped active region.

3. The method according to claim 1, characterized in that, The etching gases used in the dry etching process include CHF3, CF4, HBr, and Cl2.

4. The method according to claim 1, characterized in that, The method further includes: Using ions of a preset type, ion implantation is performed on two adjacent initial fin-shaped active regions to form source and drain electrodes located in the two adjacent initial fin-shaped active regions respectively; The ions of the preset type include at least one of the following: phosphorus ions, antimony ions, arsenic ions, and boron ions.

5. The method according to claim 4, characterized in that, The method further includes: A gate oxide layer is formed in the gate trench; A gate structure is formed in a gate trench where the gate oxide layer is formed to form a fin field-effect transistor.

6. The method according to claim 5, characterized in that, Forming a gate structure in a gate trench where the gate oxide layer is formed includes: A metal barrier layer, a conductive metal layer, and a protective layer are sequentially formed in the gate trench where the gate oxide layer is formed to form the gate structure.

7. The method according to claim 1, characterized in that, The initial fin-shaped active region and the first isolation structure are formed through the following steps: Provide the initial base; The initial substrate is etched to form the substrate and the initial fin-shaped active region located on the substrate; wherein the initial fin-shaped active regions are arranged in a matrix, with a first direction as the row direction of the matrix and a second direction as the column direction of the matrix; the initial fin-shaped active regions extend in a third direction.

8. The method according to claim 7, characterized in that, The first isolation structure further includes an isolation layer, and the step of forming the first isolation structure further includes: An isolation layer is formed covering the initial fin-shaped active region, the first sub-isolation structure, and the second sub-isolation structure.

9. The method according to claim 8, characterized in that, Etching the initial fin-shaped active region and the first isolation structure to form a fin-shaped active region and a second isolation structure located between adjacent fin-shaped active regions includes: The isolation layer is removed by etching; The initial fin-shaped active region, the first sub-isolation structure, and the second sub-isolation structure described in the etching portion respectively form the fin-shaped active region, the third sub-isolation structure, and the fourth sub-isolation structure; The third sub-isolation structure and the fourth sub-isolation structure constitute the second isolation structure.

10. The method according to claim 9, characterized in that, The second isolation structure is etched using a wet etching process, and fins are formed simultaneously with the formation of the third isolation structure and the gate trench located between adjacent fin-shaped active regions, including: The remaining initial first silicon oxide layer and the remaining initial second silicon oxide layer are etched using a wet etching process, and the fins are formed simultaneously with the formation of the third isolation structure and the gate trench. The third isolation structure includes a first silicon oxide layer, a second silicon oxide layer, and a silicon nitride layer; the gate trench includes a first gate sub-trench and a second gate sub-trench, the first gate sub-trench is located on the first silicon oxide layer, and the second gate sub-trench is located between the silicon nitride layer and the adjacent fin; the depth of the first gate sub-trench is greater than the depth of the second gate sub-trench.

11. The method according to claim 5, characterized in that, The method further includes: Forming a bit line structure connected to one of the source / drain electrodes; A capacitor structure is formed that is connected to another source / drain electrode.

12. A semiconductor structure, characterized in that, The structure is formed using the method described in any one of claims 1 to 11, and includes: Base; Fin-shaped active regions located on the substrate; A third isolation structure located between adjacent fin-shaped active regions; In this configuration, at least a portion of the top surface of the third isolation structure is lower than the top surface of the fin-shaped active region, and the exposed fin-shaped active region serves as a fin.

13. The semiconductor structure according to claim 12, characterized in that, The semiconductor structure includes at least a transistor structure, the transistor structure including: a source and a drain located in two adjacent fins, and a gate located between adjacent fins.

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