Semiconductor integrated circuit chip / die and wiring structure

Abstract

The present application discloses a semiconductor integrated circuit wafer / die and its wiring structure. The wiring structure comprises at least an intermediate conductive wiring layer, which comprises a first type of mesh conductor layer and a second type of mesh conductor layer electrically isolated from each other, and the first type of mesh conductor layer and the second type of mesh conductor layer have a plurality of first type of protrusions and a plurality of second type of protrusions respectively. Each first type of protrusion fuses at least one of a plurality of first type of conductive islands, the second type of mesh conductor layer envelopes the plurality of first type of conductive islands which are not fused, and is isolated from each first type of conductive island which is not fused. Each second type of protrusion fuses at least one of a plurality of second type of conductive islands, the first type of mesh conductor layer envelopes the plurality of second type of conductive islands which are not fused, and is isolated from each second type of conductive island which is not fused. The wiring structure can at least reduce the wiring resistance, increase the current collection and processing capacity, and effectively improve the integration of the semiconductor integrated circuit wafer / die.

Description

Technical Field

[0001] Embodiments of this disclosure relate to integrated circuits, and more particularly to wiring structures for semiconductor integrated circuit wafers / dies. Background Technology

[0002] Integrating more integrated circuit chips and circuit components into smaller sizes on integrated circuit products or system circuit boards (i.e., increasing integration density) has become an important trend in integrated circuit development. Integrated circuit wafers / dies are typically packaged into forms that can be soldered / mounted / plugged onto system circuit boards. Packaged integrated circuit chips have input / output (I / O) pins or solder bumps to allow electrical connections and signal exchange with external circuits. However, with the continuous improvement of the integration density of integrated circuits that can be fabricated on semiconductor substrates through optimizations in semiconductor manufacturing processes, existing packaging and wiring schemes have become a significant factor limiting further increases in integration density and further reductions in chip size. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor integrated circuit wafer / die, comprising a semiconductor substrate and a wiring structure located on the semiconductor substrate. Embodiments of this disclosure also provide a wiring structure for a semiconductor integrated circuit wafer / die.

[0004] In one example, the semiconductor integrated circuit wafer / die can be divided into a defined first region and a defined second region. The wiring structure includes at least an intermediate conductive wiring layer, which may include a first type mesh conductor layer and a second type mesh conductor layer, respectively located in the defined second region and the defined first region and electrically isolated from each other. The first type mesh conductor layer and the second type mesh conductor layer have a boundary region. The first type mesh conductor layer has a plurality of first type protrusions in the boundary region, extending from the first type mesh conductor layer and towards the second type mesh conductor layer. The second type mesh conductor layer has a plurality of second type protrusions in the boundary region, extending from the second type mesh conductor layer and towards the first type mesh conductor layer.

[0005] In one example, the intermediate conductive wiring layer further includes a plurality of first-type conductive islands distributed in the defined first region, wherein each of the plurality of first-type protrusions fuses with at least one of the plurality of first-type conductive islands, and those first-type conductive islands not fused by the plurality of first-type protrusions are referred to as unfused plurality of first-type conductive islands. A second-type mesh conductor layer encloses the unfused plurality of first-type conductive islands and is isolated from each of the unfused plurality of first-type conductive islands.

[0006] In one example, the intermediate conductive wiring layer further includes a plurality of second-type conductive islands distributed in the defined second region, wherein each of the plurality of second-type protrusions fuses with at least one of the plurality of second-type conductive islands, and those second-type conductive islands not fused by the plurality of second-type protrusions are referred to as unfused plurality of second-type conductive islands. The first-type mesh conductor layer encloses the unfused plurality of second-type conductive islands and is isolated from each of the unfused plurality of second-type conductive islands.

[0007] In one example, the first type of mesh conductor layer has a plurality of mesh openings corresponding one-to-one with the plurality of unfused second type conductive islands, each of the plurality of unfused second type conductive islands being located within a corresponding mesh opening.

[0008] In one example, the second type of mesh conductor layer has a plurality of mesh openings corresponding one-to-one with the plurality of unfused first type conductive islands, each of the plurality of unfused first type conductive islands being located within a corresponding mesh opening.

[0009] In one example, adjacent rows of first-type conductive islands are staggered along the width of the semiconductor substrate (or the semiconductor integrated circuit wafer / die), and adjacent rows of second-type conductive islands are staggered along the width of the semiconductor substrate (or the semiconductor integrated circuit wafer / die).

[0010] In one example, the plurality of first-type conductive islands are arranged in a quincunx pattern, and the plurality of second-type conductive islands are also arranged in a quincunx pattern.

[0011] In one example, the wiring structure further includes: a lower conductive wiring layer located below the intermediate conductive wiring layer, comprising multiple first-type conductive traces and multiple second-type conductive traces, which are parallel to each other, do not contact each other, and are arranged alternately; and a first interlayer dielectric layer located between the lower conductive wiring layer and the intermediate conductive wiring layer; the first-type mesh conductor layer and the multiple first-type conductive islands are coupled to the multiple first-type conductive traces through multiple first-type vias formed in the first interlayer dielectric layer; and the second-type mesh conductor layer and the multiple second-type conductive islands are coupled to the multiple second-type conductive traces through multiple second-type vias formed in the first interlayer dielectric layer.

[0012] In one example, the first-type conductive islands located directly above every two adjacent first-type conductive traces are staggered along the width of the semiconductor substrate, and the second-type conductive islands located directly above every two adjacent second-type conductive traces are staggered along the width of the semiconductor substrate.

[0013] In one example, the plurality of first-type conductive islands are located directly above the plurality of first-type conductive traces and are arranged in a quincunx pattern, and the plurality of second-type conductive islands are located directly above the plurality of second-type conductive traces and are also arranged in a quincunx pattern.

[0014] In one example, the plurality of first-type vias are fabricated in the portion of the first interlayer dielectric layer directly above the plurality of first-type conductive traces, and the plurality of second-type vias are fabricated in the portion of the first interlayer dielectric layer directly above the plurality of second-type conductive traces.

[0015] In one example, for the portion of the first interlayer dielectric layer located in the first defined region, one or more first-type vias corresponding to each first-type conductive island are made only at a position directly below each first-type conductive island and overlapping directly above a first-type conductive trace, while no first-type vias are made at positions other than directly below each first-type conductive island.

[0016] In one example, for the portion of the first interlayer dielectric layer located in the second defined region, one or more second-type vias corresponding to each second-type conductive island are made only at a location directly below each second-type conductive island and overlapping directly above a second-type conductive trace, while no second-type vias are made at locations other than directly below each second-type conductive island.

[0017] In one example, the defined first region and the defined second region have equal areas.

[0018] In one example, the defined first region and the defined second region are divided along the diagonal of the semiconductor integrated circuit wafer / die.

[0019] In one example, the plurality of first-type teeth and the plurality of second-type teeth are arranged alternately, and adjacent first-type teeth and second-type teeth are spaced apart from each other.

[0020] In one example, the wiring structure further includes: an upper conductive wiring layer located above the intermediate conductive wiring layer, comprising a third type conductor layer and a fourth type conductor layer electrically isolated from each other, the third type conductor layer and the fourth type conductor layer being respectively disposed in the designated first region and the designated second region; and a second interlayer dielectric layer located between the upper conductive wiring layer and the intermediate conductive wiring layer; the third type conductor layer being coupled to the plurality of first type conductive islands through a plurality of third type vias formed in the second interlayer dielectric layer; and the fourth type conductor layer being coupled to the plurality of second type conductive islands through a plurality of fourth type vias formed in the second interlayer dielectric layer.

[0021] In one example, the plurality of third-type vias correspond one-to-one with the plurality of first-type conductive islands.

[0022] In one example, the plurality of fourth-type vias correspond one-to-one with the plurality of second-type conductive islands.

[0023] In one example, the thickness of the upper conductive wiring layer is greater than the thickness of the middle conductive wiring layer.

[0024] In one example, the thickness of the intermediate conductive wiring layer is greater than or equal to the thickness of the lower conductive wiring layer.

[0025] In one example, the semiconductor integrated circuit wafer / die may further include a plurality of double-diffused metal-oxide-semiconductor field-effect transistor (DMOS) cells fabricated in the semiconductor substrate, wherein each DMOS cell may include a source region and a drain region, the source region of each DMOS cell being electrically coupled to one of the plurality of first-type conductive traces, and the drain region of each DMOS cell being electrically coupled to one of the plurality of second-type conductive traces. In one example, each DMOS cell further includes a gate region that wraps around a corresponding first-type conductive trace when viewed from a planar top view.

[0026] The semiconductor integrated circuit wafer / die and the wiring structure for the semiconductor integrated circuit wafer / die according to the embodiments of this disclosure can more effectively utilize the area of ​​the wafer / die and the area of ​​each conductive wiring layer, at least reducing wiring resistance and increasing current collection and current handling capabilities. Furthermore, employing the unfused plurality of second-type conductive islands and the unfused plurality of first-type conductive islands respectively dispersed in the first-type mesh conductor layer and the second-type mesh conductor layer can help to further effectively utilize the area of ​​the intermediate conductive wiring layer, improve the balanced distribution of current paths, increase current collection capabilities, and reduce wiring resistance on the current paths. It also allows for the fabrication of higher-density integrated circuit cells, modules, or elements to be electrically interconnected or electrically led out through the wiring structure in the substrate of the semiconductor integrated circuit wafer / die, thereby improving the integration density of integrated circuit cells, modules, or elements within the semiconductor integrated circuit wafer / die. Attached Figure Description

[0027] The accompanying drawings below will help to better understand the following description of embodiments of this disclosure. For simplicity, the same or similar components or structures in different drawings are referred to by the same reference numerals.

[0028] Figure 1 A plan perspective view of a semiconductor integrated circuit wafer / die 100 according to an embodiment of the present disclosure is shown.

[0029] Figure 2A and Figure 2B A plan view of the first conductive wiring layer 102 of a semiconductor integrated circuit wafer / die 100 according to an embodiment of the present disclosure is shown in the XY plane.

[0030] Figure 3A and Figure 3B This diagram illustrates a partial longitudinal section of the semiconductor integrated circuit wafer / die 100 cut along the Z-axis direction from the AA' and BB' sections on the YZ plane.

[0031] Figure 4A and Figure 4B They respectively indicated Figure 2A A magnified planar schematic diagram of a portion of the first defined region and a portion of the second defined region.

[0032] Figure 5 A plan view of the second conductive wiring layer 103 of a semiconductor integrated circuit wafer / die 100 according to an embodiment of the present disclosure is shown in the XY plane.

[0033] Figure 6 It indicates Figure 5A partial planar enlarged schematic diagram of the second conductive wiring layer 103 in the boundary region 505.

[0034] Figure 7 This diagram illustrates a partial longitudinal section of a semiconductor integrated circuit wafer / die 100 cut along the CC' section line in the YZ plane from the Z-axis direction.

[0035] Figure 8A It indicates Figure 5 A partial planar enlarged schematic diagram of the second conductive wiring layer 103 in the designated second region.

[0036] Figure 8B It indicates Figure 5 A partial planar enlarged schematic diagram of the second conductive wiring layer 103 in the designated first region.

[0037] Figure 9 The diagram illustrates a plan view of the third conductive wiring layer 104 of a semiconductor integrated circuit wafer / die 100 according to an embodiment of the present disclosure in the XY plane.

[0038] Figure 10A , Figure 10B and Figure 10C This illustration shows a partial longitudinal cross-sectional view of a semiconductor integrated circuit wafer / die 200 according to an embodiment of the present disclosure, cut along the Z-axis direction along the AA', BB' and CC' sections respectively on the YZ plane.

[0039] Figure 11A , Figure 11B and Figure 11C This illustration shows a partial longitudinal cross-sectional view of a semiconductor integrated circuit wafer / die 300 according to an embodiment of the present disclosure, cut along the Z-axis direction along the AA', BB' and CC' sections respectively on the YZ plane. Detailed Implementation

[0040] In the following detailed description of this disclosure, numerous specific details of circuits, components, methods, etc., are described to better understand the embodiments of this disclosure. Those skilled in the art will understand that this disclosure can be practiced even with the absence of some details. For the sake of clarity, some details well-known to those skilled in the art are not repeated here.

[0041] In the specification and claims of this invention, the use of terms such as "left," "right," "inner," "outer," "front," "back," "upper," "lower," "top," "above," "bottom," and "below" is merely for descriptive convenience and does not indicate the necessary or permanent relative position of components / structures. Those skilled in the art should understand that such terms can be interchanged where appropriate, for example, so that embodiments of the invention can still operate in orientations different from those described in this specification. Furthermore, the term "coupled" means a direct or indirect electrical or non-electrical connection. When an element is referred to as "directly connected," "directly coupled," or "directly in contact" with another element, it means there are no intermediate elements. Terms such as "first," "second," and "third" are used only as prepositions to distinguish different circuits, elements, or structures and are not intended to indicate sequence, nor are they necessarily mentioned / cited in order.

[0042] Figure 1 A plan perspective view of a semiconductor integrated circuit wafer / die 100 according to an embodiment of the present disclosure is shown. Figure 1 This can be viewed as a perspective view of the semiconductor integrated circuit wafer / die 100 in the XY plane, illustrated in a vertical coordinate system defined by mutually perpendicular X, Y, and Z axes. The semiconductor integrated circuit wafer / die 100 may contain integrated circuit cells, modules, or elements fabricated therein. For example, in one exemplary embodiment, the semiconductor integrated circuit wafer / die 100 may contain a high-power switching cell, such as a double-diffused metal-oxide-semiconductor field-effect transistor (DMOS). In another exemplary embodiment, the semiconductor integrated circuit wafer / die 100 may further include a driving unit for driving the high-power switching cell, which can provide a driving voltage or driving current to, for example, a control terminal of the high-power switching cell. In another exemplary embodiment, the semiconductor integrated circuit wafer / die 100 may further include a control unit for controlling the high-power switching cell to switch on and off. Those skilled in the art should understand that, depending on the actual application and design requirements, integrated circuit cells, modules, or elements with other functions can be fabricated in the semiconductor integrated circuit wafer / die 100, and this disclosure is not intended to limit this.

[0043] Continue to refer to Figure 1For example, the semiconductor integrated circuit wafer / die 100 may include a wiring structure on a substrate 101, which includes at least one conductive wiring layer for electrically interconnecting or leading out nodes / terminals (including active regions, such as source / emitter, drain / absorber, gate / base, etc. of transistors) of integrated circuit cells, modules, or elements fabricated on the substrate 101, thereby allowing the integrated circuit cells, modules, or elements fabricated on the substrate 101 to be electrically coupled or exchange signals with other external circuits. Those skilled in the art will understand that the substrate 101 may include semiconductor materials such as silicon (Si) and germanium (Ge), compound semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), and silicon germanium (SiGe), or other forms of substrates such as silicon-on-insulator (SOI). In one embodiment, the at least one conductive wiring layer may be part of a metal layer on the substrate 101. Figure 1 The example illustrates that at least one conductive wiring layer may include a first conductive wiring layer 102, a second conductive wiring layer 103, and a third conductive wiring layer 104. Those skilled in the art should understand that the number of these at least one conductive wiring layers can be reasonably selected according to electrical connection and wiring requirements, and this application does not limit this. An interlayer dielectric layer is formed between each adjacent (here referring to adjacent in the Z-axis direction) conductive wiring layer. Those skilled in the art should understand that in... Figure 1 The planar perspective view does not show the interlayer dielectric layers in order to better illustrate the perspective of each conductive wiring layer; however, it can be further combined with... Figure 3A , Figure 3B and Figure 7 The longitudinal cross-sectional diagram shown is used for understanding.

[0044] Figure 2A This diagram illustrates a plan view of a first conductive wiring layer 102 of a semiconductor integrated circuit wafer / die 100 according to an embodiment of the present disclosure. The first conductive wiring layer 102 may include a plurality of first-type conductive traces 201 and a plurality of second-type conductive traces 202, which are parallel to each other, do not contact each other, and are arranged alternately to form, for example... Figure 2A The diagram illustrates a pattern of repeating "first type conductive trace 201, second type conductive trace 202, first type conductive trace 201, second type conductive trace 202..." from top to bottom (i.e., along the width W direction / Y-axis direction of the substrate 101). In one embodiment, each first type conductive trace 201 substantially spans the entire length L of the substrate 101 (e.g., ...). Figure 1The length L of the substrate 101 is shown as the dimension in the X-axis direction. Each second-type conductive trace 202 also substantially spans the entire length L of the substrate 101. In one embodiment, the plurality of first-type conductive traces 201 and the plurality of second-type conductive traces 202 are arranged in parallel repeating units of "first-type conductive trace 201, second-type conductive trace 202" in the width W / Y-axis direction of the substrate 101 until they substantially fill the entire width W of the substrate 101 (e.g., ...). Figure 1 The width W of the substrate 101 is shown as its dimension in the Y-axis direction. Figure 2A For ease of understanding, the plurality of first-type conductive traces 201 and the plurality of second-type conductive traces 202 are illustrated with parallel thick black lines. For clarity, a row of comb-shaped left-pointing arrows indicates and labels the plurality of first-type conductive traces 201, and a row of comb-shaped right-pointing arrows indicates and labels the plurality of second-type conductive traces 202. In one embodiment, when the semiconductor integrated circuit wafer / die 100 is used to build an actual application system, the plurality of first-type conductive traces 201 can be used to couple / transmit a first potential, and the plurality of second-type conductive traces 202 can be used to couple / transmit a second potential. The first potential and the second potential are not equal relative to the same reference ground potential, that is, there is a potential difference between the first potential and the second potential.

[0045] For example, taking a semiconductor integrated circuit wafer / die 100 containing a high-power switching unit (e.g., a DMOS) therein, in practical applications, the plurality of first-type conductive traces 201 can be used to couple / transmit the source potential of the DMOS, and the plurality of second-type conductive traces 202 can be used to couple / transmit the drain potential of the DMOS. In one embodiment, the width of each second-type conductive trace 202 can be greater than the width of each first-type conductive trace 201. In one embodiment, a gate conductive layer (e.g., a gate polysilicon layer) can be fabricated in / on the substrate 101, and the gate conductive layer can be patterned, for example, to include a plurality of gate conductive structures 105. In one embodiment (see reference) Figure 2B (A schematic planar perspective view), the plurality of gate conductive structures 105 can correspond one-to-one with the plurality of first-type conductive traces 201. For example, in one embodiment, each gate conductive structure 105 in Figure 2BThe planar perspective view shows a first-type conductive trace 201 encircling the corresponding trace. Those skilled in the art should understand that the gate conductive layer (or the plurality of gate conductive structures 105) and the first conductive wiring layer 102 (or the layer that may include multiple first-type conductive traces 201 and multiple second-type conductive traces 202) are not located on the same plane; that is, they may have a certain distance / spacing in the Z-axis direction (see...). Figure 3A and Figure 3B (Schematic cross-sectional view).

[0046] According to an exemplary embodiment of the present disclosure, a first interlayer dielectric layer 300 is formed on the first conductive wiring layer 102, with reference to... Figure 3A and Figure 3B . Figure 3A and Figure 3B This can be viewed as a schematic diagram of a partial longitudinal section of a semiconductor integrated circuit wafer / die 100 cut along the Z-axis direction from the AA' and BB' sections, respectively, on the YZ plane. Combined with... Figure 2A , Figure 3A and Figure 3B The diagram illustrates that the first interlayer dielectric layer 300 contains a plurality of first-type vias 301 and a plurality of second-type vias 302, each of which extends longitudinally (along the Z-axis) through the first interlayer dielectric layer 300. In an exemplary embodiment, the plurality of first-type vias 301 are formed in the portion of the first interlayer dielectric layer 300 directly above the plurality of first-type conductive traces 201, and the plurality of second-type vias 302 are formed in the portion of the first interlayer dielectric layer 300 directly above the plurality of second-type conductive traces 202. The plurality of first-type vias 301 are used to electrically connect the plurality of first-type conductive traces 201. Each first-type via 301 extends longitudinally through the first interlayer dielectric layer 300 from its upper surface 300T until it reaches and at least touches (i.e., physically directly contacts) one of the plurality of first-type conductive traces 201. The plurality of second-type vias 302 are used to electrically connect the plurality of second-type conductive traces 202. Each second-type via 302 extends longitudinally through the first interlayer dielectric layer 300 from its upper surface 300T until it reaches and at least touches (i.e., physically directly contacts) one of the plurality of second-type conductive traces 202. In one embodiment, each of the plurality of first-type vias 301 and the plurality of second-type vias 302 is filled with conductive material (e.g., tungsten, cobalt, nickel, copper, or combinations thereof or alloys thereof).

[0047] According to an exemplary embodiment of this disclosure, still referring to Figure 2A and Figure 2B To illustrate, the semiconductor integrated circuit wafer / die 100 (including the substrate 101 and each layer fabricated on the substrate 101 along the Z-axis) can be divided into a defined first region and a defined second region on the XY plane. Figure 2A and Figure 2B The dashed line 203 in the image indicates the approximate boundary between the first and second regions of this design. For example... Figure 2A and Figure 2B In the example, the area to the right of the dividing line 203 can be referred to as the first area of ​​the setting, and the area to the left of the dividing line 203 can be referred to as the second area of ​​the setting.

[0048] To help with better understanding, Figure 4A and Figure 4B They respectively indicated Figure 2A A magnified planar schematic diagram of a portion located in the first defined region and a portion located in the second defined region. Figure 4A and Figure 4B In the partially enlarged schematic diagram, each small, unfilled square with a cross represents a cross-sectional view or a projection view on the upper surface 102T of the first wiring layer for a single first-type via 301 or a single second-type via 302. Those skilled in the art should understand that although the diagram... Figure 4A and Figure 4B The cross-sectional shape or projected shape of each first type through hole 301 and each second type through hole 302 on the XY plane is represented by small squares. However, this is only for providing an example to aid understanding. The cross-sectional shape or projected shape of each first type through hole 301 and each second type through hole 302 on the XY plane can be other defined geometric shapes, such as including but not limited to circles, rectangles or other polygons adapted to the manufacturing process. This disclosure does not limit the geometric shape.

[0049] In one exemplary embodiment, the designated first region and the designated second region may have substantially equal (theoretically or ideally, they can be referred to as equal) areas (here referring to the areas measured from the XY plane). This allows for a more balanced distribution and smoother flow of current through the plurality of first-type vias 301 and the plurality of second-type vias 302. In one exemplary embodiment, the designated first region and the designated second region substantially each occupy approximately half the area (L*W) of the semiconductor integrated circuit wafer / die 100 (theoretically or ideally, they can be referred to as each occupying half the area of ​​the semiconductor integrated circuit wafer / die 100). Those skilled in the art should understand that the terms "substantially" and "substantially approximately" as used herein take into account deviations within a tolerance range that are permissible in actual products due to manufacturing processes, etc., and this disclosure should be understood to cover both theoretical / ideal cases and cases where deviations exist within a tolerance range in actual products.

[0050] In one exemplary embodiment, the defined first region and the defined second region may be approximately along the diagonal of the semiconductor integrated circuit wafer / die 100 (e.g., Figure 2A and Figure 2B The example illustrates a general boundary line 203, where the portion to the right of boundary line 203 can be referred to as the first region, and the portion to the left of boundary line 203 can be referred to as the second region. This maximizes the longitudinal (Z-axis direction) interface between the first and second regions, thereby increasing the partition utilization of the wiring structure on substrate 101 and effectively reducing wiring resistance. However, those skilled in the art should understand that... Figure 2A and Figure 2B This is merely an example to aid understanding and is not intended to limit the division method of the defined first and second regions. The defined first and second regions can be adapted to different methods depending on the actual application and design requirements. Figure 2A and Figure 2BAny other division method illustrated. For example, in one variant embodiment, the dividing line 203 can be set as more than one dividing line parallel to the diagonal of the semiconductor integrated circuit wafer / die 100 (this can be understood as dividing the semiconductor integrated circuit wafer / die 100 into more sub-regions on the XY plane, or as the set first region or the set second region can include separate sub-regions); in another variant embodiment, the dividing line 203 can be set as the midline along the long or wide side of the semiconductor integrated circuit wafer / die 100; in yet another variant embodiment, the dividing line 203 can be set as a square frame, rectangular frame, circular frame, etc., located within the projection shape of the semiconductor integrated circuit wafer / die 100 on the XY plane. It is impossible to enumerate all the different division methods here, but these variations of the division methods do not exceed the protection scope of this application.

[0051] Figure 5 This diagram illustrates a plan view of a second conductive wiring layer 103 of a semiconductor integrated circuit wafer / die 100 according to an embodiment of the present disclosure in the XY plane. The second conductive wiring layer 103 can be fabricated on the first interlayer dielectric layer 300 and may include a plurality of first-type conductive islands 401. These plurality of first-type conductive islands 401 are distributed in the defined first region, and adjacent rows (where "row" can refer to the direction along the length L of the substrate 101 or...) are also shown. Figure 2A and Figure 5 (Illustrated X-axis direction) The first type of conductive island 401 is in the width W direction along the semiconductor substrate 101 (i.e. Figure 2A and Figure 5 (Illustrated along the Y-axis) staggered arrangement. For example, those first-type conductive islands 401 located directly above every two adjacent first-type conductive traces 201 are arranged along the width W direction of the substrate 101 (i.e., Figure 2A and Figure 5 (Illustrated along the Y-axis) staggered arrangement. That is, those first-type conductive islands 401 located directly above every two adjacent first-type conductive traces 201 are arranged along the width W direction of the substrate 101 (i.e., Figure 2A and Figure 5 (Illustrated along the Y-axis) The elements are not aligned, but rather alternately staggered. Figure 5 In the plan view, each grid-filled small square represents a single first-type conductive island 401. Each first-type conductive island 401 can be coupled to one of the plurality of first-type conductive traces 201 via one or more of the plurality of first-type vias 301 (and the conductive material therein). For aid of understanding, in Figure 2AThe planar top-view perspective view also illustrates the distribution pattern of the plurality of first-type conductive islands 401 on the XY plane, with each grid-filled square representing a projection of a single first-type conductive island 401 onto the upper surface 102T of the first wiring layer (or on the XY plane). Further reference... Figure 2A and Figure 4A Plan view and Figure 3A A longitudinal cross-sectional diagram can help to better understand Figure 5 The distribution pattern of the plurality of first-type conductive islands 401 on the XY plane, their relative positions and interconnections with the plurality of first-type through holes 301 and the plurality of first-type conductive traces 201.

[0052] Continue to refer to Figure 5 As illustrated, according to one embodiment of this disclosure, the second conductive wiring layer 103 may further include a plurality of second-type conductive islands 402. These plurality of second-type conductive islands 402 are distributed in the defined second region, and every two adjacent rows (where "row" can refer to the direction along the length L of the substrate 101 or...) are... Figure 2A and Figure 5 (Illustrated X-axis direction) The second type of conductive island 402 is in the width W direction along the semiconductor substrate 101 (i.e. Figure 2A and Figure 5 (Illustrated along the Y-axis) staggered arrangement. For example, those second-type conductive islands 402 located directly above every two adjacent second-type conductive traces 202 are arranged along the width W direction of the substrate 101 (i.e., Figure 2A and Figure 5 (Illustrated along the Y-axis) staggered arrangement. That is, those second-type conductive islands 402 located directly above every two adjacent second-type conductive traces 202 are arranged along the width W direction of the substrate 101 (i.e. Figure 2A and Figure 5 (Illustrated along the Y-axis) They are not aligned, but rather alternately staggered. Figure 5 In the top plan view, each dot-filled small square represents a single Type II conductive island 402. Each Type II conductive island 402 can be electrically coupled to one of the plurality of Type II conductive traces 202 via one or more of the plurality of Type II vias 302 (and the conductive material therein). For aid of understanding, in Figure 2A The planar top-view perspective view also illustrates the distribution pattern of the plurality of second-type conductive islands 402 on the XY plane, with each dot-filled square representing a projection of a single second-type conductive island 402 onto the upper surface 102T of the first wiring layer (or on the XY plane). Further reference... Figure 2A and Figure 4B Plan view and Figure 3B A longitudinal cross-sectional diagram can help to better understand Figure 5 The distribution pattern of the plurality of second-type conductive islands 402 on the XY plane, their relative positions and interconnections with the plurality of second-type vias 302 and the plurality of second-type conductive traces 202.

[0053] This allows for a smaller spacing between adjacent first-type conductive traces 201 and second-type conductive traces 202, where the spacing refers to the spacing along the width W direction of the substrate 101 (i.e., Figure 2A (Illustrated Y-axis direction) The shortest distance between adjacent first-type conductive traces 201 and second-type conductive traces 202. Therefore, on a limited area of ​​the semiconductor integrated circuit wafer / die 100 (or substrate 101) in the XY plane, a higher density of conductive traces 201 and 202 can be arranged (meaning that a higher density of integrated circuit cells, modules, or elements to be electrically interconnected or led out through the at least one conductive wiring layer can be fabricated in the substrate 101), thereby improving the integration density of integrated circuit cells, modules, or elements within the semiconductor integrated circuit wafer / die 100.

[0054] In one exemplary embodiment, the plurality of first-type conductive islands 401 located directly above the plurality of first-type conductive traces 201 can be arranged in a quincunx pattern, and the plurality of second-type conductive islands 402 located directly above the plurality of second-type conductive traces 202 can also be arranged in a quincunx pattern. Those skilled in the art should understand that, with reference to... Figures 2A to 5 The description of the plurality of first-type conductive islands 401 and the plurality of second-type conductive islands 402 and their arrangement / distribution pattern is merely exemplary and not intended to limit this disclosure. In other embodiments, other staggered arrangements may be used. Although Figure 5 and Figure 2A The cross-sectional shape or projected shape of each first type conductive island 401 and each second type conductive island 402 in the XY plane is represented by a small square. However, this is only for providing an example to aid understanding. The cross-sectional shape or projected shape of each first type conductive island 401 and each second type conductive island 402 in the XY plane can be other defined geometric shapes, such as including but not limited to circles, rectangles or other polygons adapted to the manufacturing process. This disclosure does not limit the geometric shape.

[0055] In an exemplary embodiment, for the portion of the first interlayer dielectric layer 300 located in the first defined region, one or more first-type vias 301 corresponding to each first-type conductive island 401 may be formed only at a location directly below each first-type conductive island 401 and overlapping directly above the first-type conductive trace 201, while no first-type vias 301 are formed at locations other than directly below each first-type conductive island 401. (See also...) Figure 4A For the portion of the first interlayer dielectric layer 300 located in the second designated area, multiple first-type conductive vias 301 can still be fabricated directly above each first-type conductive trace 201.

[0056] In an exemplary embodiment, for the portion of the first interlayer dielectric layer 300 located in the second defined region, one or more second-type vias 302 corresponding to each second-type conductive island 402 may be formed only at a location directly below each second-type conductive island 402 and overlapping directly above the second-type conductive trace 202, while no second-type vias 302 are formed at locations other than directly below each second-type conductive island 402. (See reference...) Figure 4B For the portion of the first interlayer dielectric layer 300 located in the first designated area, multiple second-type conductive vias 302 can still be fabricated directly above each second-type conductive trace 202.

[0057] Continue to refer to Figure 5 As illustrated, according to one embodiment of this disclosure, the second conductive wiring layer 103 may further include a first type mesh conductor layer 501 and a second type mesh conductor layer 502, electrically isolated from each other, and respectively located (e.g., laid in) the defined second region (e.g. Figure 5 In the example, the area to the left of the dividing line 203) and the first area set (e.g.) Figure 5 In the example, the area to the right of boundary line 203 (within the region). Figure 5 In the top plan view, the first type of mesh conductor layer 501 is represented by a whole mesh filled with a grid pattern, and the second type of mesh conductor layer 502 is represented by a whole mesh filled with dots. The first type of mesh conductor layer 501 and the second type of mesh conductor layer 502 have a boundary region 505. Figure 5The approximate extent of the boundary region is indicated by a dashed box (also labeled 505 for simplicity). The first-type mesh conductor layer 501 has multiple first-type protrusions 503 in the boundary region 505, extending from the first-type mesh conductor layer 501 and towards the second-type mesh conductor layer 502, thus giving the first-type mesh conductor layer 501 an uneven edge in the boundary region 505. The second-type mesh conductor layer 502 has multiple second-type protrusions 504 in the boundary region 505, extending from the second-type mesh conductor layer 502 and towards the first-type mesh conductor layer 501, thus also giving the second-type mesh conductor layer 502 an uneven edge in the boundary region 505. The plurality of first-type protrusions 503 and the plurality of second-type protrusions 504 are arranged alternately and interlock with each other to form a zipper-like or interdigitated arrangement, and the adjacent first-type protrusions 503 and second-type protrusions 504 are separated from each other (e.g., electrically isolated from each other).

[0058] To help with better understanding, Figure 6 It indicates Figure 5 A partial planar enlarged schematic diagram of the second conductive wiring layer 103 in the boundary region 505. Figure 7 This diagram illustrates a partial longitudinal section of a semiconductor integrated circuit wafer / die 100 cut along the CC' section line in the YZ plane from the Z-axis direction.

[0059] Figure 8A It indicates Figure 5 A partial planar enlarged schematic diagram of the second conductive wiring layer 103 in the designated second region. Figure 8B It indicates Figure 5 A partial planar enlarged schematic diagram of the second conductive wiring layer 103 in the designated first region.

[0060] exist Figure 5 and Figure 6In the schematic diagram example, each first type tooth 503 and each second type tooth 504 is shown as a sword-shaped tooth. However, those skilled in the art should understand that this is merely exemplary and not intended to limit the scope of this disclosure. In other variant embodiments, each first type tooth 503 and each second type tooth 504 can be designed as any other suitable shape (e.g., rectangular tooth, rhomboid tooth, finger-shaped tooth with rounded tips, petal-shaped tooth, etc.). These shape transformations cannot be enumerated here and do not exceed the scope of protection of this disclosure. The use of the aforementioned zipper-like or interdigitated edge arrangement at the junction region 505 of the first type mesh conductor layer 501 and the second type mesh conductor layer 502 can help reduce the electric field intensity density at the junction region 505 caused by the difference in potential coupled to the first type mesh conductor layer 501 and the second type mesh conductor layer 502 in practical applications, and make the current collection of the first type mesh conductor layer 501 and the second type mesh conductor layer 502 smoother.

[0061] According to an exemplary embodiment of this disclosure, continued reference Figure 5 and Figure 6 As illustrated, each of the plurality of first-type protrusions 503 can fuse with at least one of the plurality of first-type conductive islands 401 (i.e., each first-type protrusion 503 and at least one of the plurality of first-type conductive islands 401 are a seamless integral with each other). Therefore, it can also be considered that those first-type conductive islands 401 fused by the plurality of first-type protrusions 503 are in fact fused with the first-type mesh conductor layer 501 (since the plurality of first-type protrusions 503 are part of the first-type mesh conductor layer 501). Further reference Figure 7 A partial longitudinal cross-sectional diagram can be better understood. Figure 7 The dashed box on the cross-section of the first type protrusion 503 indicates at least one first type conductive island 401 fused by the first type protrusion 503. Therefore, it can also be considered that the at least one first type conductive island 401 fused by each first type protrusion 503 is virtually divided from the first type protrusion 503, and is actually a part of the first type protrusion 503. This part (i.e., the fused at least one first type conductive island 401) is in contact / connected to at least one corresponding first type via 301 (and the conductive material therein) in the underlying first interlayer dielectric layer 300. Thus, each first type protrusion 503 is in contact / connected to at least one corresponding first type via 301 (and the conductive material therein) in the Z-axis direction, and can be electrically coupled to at least one of the plurality of first type conductive traces 201. Figure 5 , Figure 6 and Figure 7The example illustrates a scenario where each first-type protrusion 503 is integrated with one of the plurality of first-type conductive islands 401. However, those skilled in the art should understand that this is merely exemplary. In other embodiments, each first-type protrusion 503 may be integrated with more than one of the plurality of first-type conductive islands 401 (e.g., two or three, etc.), which can be adjusted according to actual application and design requirements.

[0062] According to an exemplary embodiment of this disclosure, continued reference Figure 5 and Figure 6 As illustrated, each of the plurality of second-type protrusions 504 is integrated with at least one of the plurality of second-type conductive islands 402, meaning that each second-type protrusion 504 and at least one of the plurality of second-type conductive islands 402 are a seamless integral unit. Therefore, it can also be considered that those second-type conductive islands 402 integrated by the plurality of second-type protrusions 504 are in fact integrated with the second-type mesh conductor layer 502 (since the plurality of second-type protrusions 504 are part of the second-type mesh conductor layer 502). Further reference... Figure 7 A partial longitudinal cross-sectional diagram can be better understood. Figure 7 The dashed box on the cross-section of the second-type protrusion 504 illustrates at least one second-type conductive island 402 fused to the second-type protrusion 504. Therefore, it can also be considered that the at least one second-type conductive island 402 fused to each second-type protrusion 504 is virtually partitioned from the second-type protrusion 504, and is actually a part of the second-type protrusion 504. This part (i.e., the fused at least one second-type conductive island 402) is in contact / connected to at least one corresponding second-type via 302 (and the conductive material therein) in the underlying first interlayer dielectric layer 300. Thus, each second-type protrusion 504 is in contact / connected to at least one corresponding second-type via 302 (and the conductive material therein) in the Z-axis direction, thereby being electrically coupled to at least one of the plurality of second-type conductive traces 202. Figure 5 , Figure 6 and Figure 7 The example illustrates a scenario where each second-type protrusion 504 is integrated with one of the plurality of second-type conductive islands 402. However, those skilled in the art should understand that this is merely exemplary. In other embodiments, each second-type protrusion 504 may be integrated with more than one of the plurality of second-type conductive islands 402 (e.g., two or three, etc.), which can be adjusted according to actual application and design requirements.

[0063] According to an exemplary embodiment of this disclosure, continued reference Figure 5The first type of mesh conductor layer 501 encloses those second-type conductive islands 402 that are not fused with the plurality of second-type protrusions 504 (or the second type of mesh conductor layer 502). Hereinafter, "those second-type conductive islands 402 that are not fused with the plurality of second-type protrusions 504 (or the second type of mesh conductor layer 502)" will be referred to as "the remaining plurality of second-type conductive islands" or "the unfused plurality of second-type conductive islands". The first type of mesh conductor layer 501 is separated / isolated from each of the remaining plurality of second-type conductive islands 402, for example, there are gaps between the first type of mesh conductor layer 501 and each of the remaining plurality of second-type conductive islands 402, and these gaps can be filled with dielectric / electrical isolation material. In other words, the first type of mesh conductor layer 501 has a plurality of mesh openings 506 corresponding one-to-one with the remaining plurality of second type conductive islands 402 (or the plurality of unfused second type conductive islands 402), each of the remaining plurality of second type conductive islands 402 being located within a corresponding mesh opening 506, like a small island independent from the first type of mesh conductor layer 501. In one embodiment, each mesh opening 506 may be conformal to its corresponding second type conductive island 402 (i.e., having the same geometry in the XY plane, but the size of the mesh opening 506 is larger than the size of the second type conductive island 402), see further. Figure 8A A magnified view of a local plane can be better understood.

[0064] According to an exemplary embodiment of this disclosure, reference is made to Figure 5 and Figure 3BAs illustrated, the first type of mesh conductor layer 501 as a whole can be electrically coupled to the plurality of first type conductive traces 201 in the first wiring layer 102 in the Z-axis direction through the first type of vias 301 (and the conductive material therein) located in the second defined region. The plurality of second type conductive islands 402 (or the plurality of unfused second type conductive islands 402) dispersed in the plurality of meshes 506 of the first type of mesh conductor layer 501 can be electrically coupled to the plurality of second type traces 202 in the Z-axis direction through corresponding second type vias 302 (and the conductive material therein). Therefore, in practical applications, the first type of mesh conductor layer 501 and the remaining multiple second type conductive islands 402 (or the multiple unfused second type conductive islands 402) dispersed in its multiple mesh openings 506 can be used to couple / transmit different potentials. For example, in the application example where "the multiple first type conductive traces 201 are used to couple / transmit the first potential and the multiple second type conductive traces 202 are used to couple / transmit the second potential", the first type of mesh conductor layer 501 is essentially used to couple / transmit the first potential, while the remaining multiple second type conductive islands 402 (or the multiple unfused second type conductive islands 402) dispersed in its multiple mesh openings 506 are essentially used to couple / transmit the second potential. For example, in a semiconductor integrated circuit wafer / die 100 containing a high-power switching unit (e.g., a DMOS) therein, in practical applications, the first type of mesh conductor layer 501 is essentially used to couple / transmit the source potential of the DMOS, while the remaining plurality of second type conductive islands 402 dispersed in its plurality of meshes 506 are essentially used to couple / transmit the drain potential of the DMOS.

[0065] According to an exemplary embodiment of this disclosure, continued reference Figure 5The second type of mesh conductor layer 502 encloses those first type conductive islands 401 that are not fused with the plurality of first type protrusions 503. Hereinafter, "those first type conductive islands 401 that are not fused with the plurality of first type protrusions 503" will be referred to as "the remaining plurality of first type conductive islands" or "the unfused plurality of first type conductive islands". The second type of mesh conductor layer 502 is separated / isolated from each of the remaining plurality of first type conductive islands 401, for example, there are gaps between the second type of mesh conductor layer 502 and each of the remaining plurality of first type conductive islands 401, and these gaps can be filled with dielectric / electrical isolation material. In other words, the second type of mesh conductor layer 502 has a plurality of mesh openings 507 corresponding one-to-one with the remaining plurality of first type conductive islands 401 (or the plurality of unfused first type conductive islands 401), each of the remaining plurality of first type conductive islands 401 being located within a corresponding mesh opening 507, like a small island separated from the second type of mesh conductor layer 502. In one embodiment, each mesh opening 507 may be conformal to its corresponding first type conductive island 401 (i.e., having the same geometry in the XY plane, but the size of the mesh opening 507 is larger than the size of the first type conductive island 401), see further. Figure 8A A magnified view of a local plane can be better understood.

[0066] According to an exemplary embodiment of this disclosure, reference is made to Figure 5 and Figure 3AAs illustrated, the second-type mesh conductor layer 502 as a whole can be electrically coupled to the plurality of second-type conductive traces 202 in the first wiring layer 102 in the Z-axis direction through the second-type vias 302 (and conductive material therein) located in the first defined region. The plurality of first-type conductive islands 401 dispersed in the plurality of meshes 507 of the second-type mesh conductor layer 502 can be electrically coupled to the plurality of first-type traces 201 in the Z-axis direction through corresponding first-type vias 301 (and conductive material therein). Therefore, in practical applications, the second type of mesh conductor layer 502 and the remaining multiple first type conductive islands 401 (or the unfused multiple first type conductive islands 401) dispersed in its multiple meshes 507 can be used to couple / transmit different potentials. For example, in the application example where "the multiple first type conductive traces 201 are used to couple / transmit the first potential and the multiple second type conductive traces 202 are used to couple / transmit the second potential", the second type of mesh conductor layer 502 is essentially used to couple / transmit the second potential, while the remaining multiple first type conductive islands 401 (or the unfused multiple first type conductive islands 401) dispersed in its multiple meshes 507 are essentially used to couple / transmit the first potential. For example, in a semiconductor integrated circuit wafer / die 100 containing a high-power switching unit (e.g., a DMOS) therein, in practical applications, the second type of mesh conductor layer 502 is essentially used to couple / transmit the drain potential of the DMOS, while the remaining plurality of first type conductive islands 401 dispersed in its plurality of meshes 507 are essentially used to couple / transmit the source potential of the DMOS.

[0067] The use of the first type of mesh conductor layer 501 and the second type of mesh conductor layer 502 in the semiconductor integrated circuit wafer / die 100 according to the embodiments of this disclosure can help to more effectively utilize the area of ​​the second conductive wiring layer 103, reduce the wiring resistance on the path for transmitting the first potential and the second potential (which can also be considered as the path for transmitting the current corresponding to the first potential and the second potential), and increase the current collection and current processing capabilities. Furthermore, the use of the unfused plurality of second type conductive islands 402 and the unfused plurality of first type conductive islands 401, respectively dispersed in the first type of mesh conductor layer 501 and the second type of mesh conductor layer 502, can further help to effectively utilize the area of ​​the second conductive wiring layer 103, improve the balanced distribution of the current path, increase the current collection capability, and reduce the wiring resistance on the current path.

[0068] According to an exemplary embodiment of this disclosure, a second interlayer dielectric layer 600 may be fabricated on the second conductive wiring layer 103, and the third conductive wiring layer 104 may be fabricated on the second interlayer dielectric layer 600. (Refer to...) Figure 9 , Figure 3A , Figure 3B and Figure 7 An exemplary illustration. Figure 9 A plan view of the third conductive wiring layer 104 of a semiconductor integrated circuit wafer / die 100 according to an embodiment of the present disclosure is shown. Figure 9 , Figure 3A , Figure 3B and Figure 7 The second interlayer dielectric layer 600 is illustrated with a plurality of third-type vias 601 and a plurality of fourth-type vias 602. Each of the plurality of third-type vias 601 and the plurality of fourth-type vias 602 extends longitudinally (along the Z-axis direction) through the second interlayer dielectric layer 600, providing an electrical coupling / connection path between the second conductive wiring layer 103 and the third conductive wiring layer 104. In one embodiment, each of the plurality of third-type vias 601 and the plurality of fourth-type vias 602 is filled with conductive material (e.g., tungsten, cobalt, Co / nickel, copper, or combinations thereof or alloys thereof). The third conductive wiring layer 104 may include a third-type conductor layer 701 and a fourth-type conductor layer 702, electrically isolated from each other, and respectively located (e.g., laid in) the defined first region (e.g., Figure 9 The area to the right of the dividing line 203 in the schematic diagram) and the designated second area (e.g. Figure 9 (In the schematic diagram, the area to the left of boundary line 203). In one embodiment, the third type conductor layer 701 may be a single layer of conductive material laid in the designated first area, and the fourth type conductor layer 702 may be a single layer of conductive material laid in the designated second area. In one embodiment, the third type conductor layer 701 and each third type via 601 (and the conductive material therein) are in direct contact and connection at the upper surface 600T of the second interlayer dielectric layer 600, and the fourth type conductor layer 702 and each fourth type via 602 (and the conductive material therein) are in direct contact and connection at the upper surface 600T of the second interlayer dielectric layer 600.

[0069] In one embodiment, the plurality of third-type vias 601 correspond one-to-one with the plurality of first-type conductive islands 401 in the second conductive wiring layer 103 (including those first-type conductive islands 401 fused with the plurality of first-type protrusions 503 / first-type mesh conductor layers 501 and those first-type conductive islands 401 not fused with the plurality of first-type protrusions 503 / first-type mesh conductor layers 501), that is, a corresponding third-type via 601 is formed in the second interlayer dielectric layer 600 for each first-type conductive island 401. Figure 9 In the plan view, each grid-filled small square illustrates a cross-sectional view or a projection on the XY plane of a single third-type via 601 on the lower surface 104B of the third wiring layer / the upper surface 600T of the second interlayer dielectric layer. In an exemplary embodiment, the "one-to-one correspondence" here may include: the positions / coordinates of each first-type conductive island 401 and its corresponding third-type conductive via 601 on the lower surface 600B of the second interlayer dielectric layer 600 overlap, so that each third-type via 601 (and the conductive material therein) can directly contact and connect with its corresponding first-type conductive island 401, that is: each third-type via 601 starts from the upper surface 600T of the second interlayer dielectric layer 600 (or the lower surface of the third-type conductor layer 701) and longitudinally traverses the second interlayer dielectric layer 600 until it reaches and at least touches (i.e., physically directly contacts) its corresponding first-type conductive island 401 in the second conductive wiring layer 103. In an exemplary embodiment, the "one-to-one correspondence" here may further include: the cross-sectional shape or projected shape of each third-type conductive via 601 and its corresponding first-type conductive island 401 on the upper surface 103T of the second conductive wiring layer 103 or the lower surface 600B of the second interlayer dielectric layer 600 is matched, for example, they may have the same geometry, and further combined Figure 5 , Figure 3A , Figure 3B and Figure 7The illustration can be used to better understand this. Each first-type conductive island 401 can be electrically coupled to the third-type conductor layer 701 through its corresponding third-type via 601 (and the conductive material therein). Therefore, the plurality of third-type vias 601 can electrically couple the third-type conductor layer 701 to the plurality of first-type conductive islands 401 in the second conductive wiring layer 103 (including those first-type conductive islands 401 not fused with the first-type mesh conductor layer 501 and those first-type conductive islands 401 fused with the first-type mesh conductor layer 501), and further electrically coupled to the plurality of first-type conductive traces 201 through the plurality of first-type vias 301 (and the conductive material therein).

[0070] In one embodiment, the plurality of fourth-type vias 602 correspond one-to-one with the plurality of second-type conductive islands 402 in the second conductive wiring layer 103 (including those second-type conductive islands 402 fused with the plurality of second-type protrusions 504 / second-type mesh conductor layers 502 and those second-type conductive islands 402 not fused with the plurality of second-type protrusions 504 / second-type mesh conductor layers 502), that is, a corresponding fourth-type via 602 is formed in the second interlayer dielectric layer 600 for each second-type conductive island 402. Figure 9In the plan view, small squares filled with dots indicate a cross-sectional view or a projection on the XY plane of a single fourth-type via 602 on the lower surface 104B of the third wiring layer / the upper surface 600T of the second interlayer dielectric layer. In an exemplary embodiment, the "one-to-one correspondence" here may also include: the positions / coordinates of each second-type conductive island 402 and its corresponding third-type conductive via 602 on the lower surface 600B of the second interlayer dielectric layer 600 overlap, so that each fourth-type via 602 (and the conductive material therein) can directly contact and connect with its corresponding second-type conductive island 402, that is: each fourth-type via 602 starts from the upper surface 600T of the second interlayer dielectric layer 600 (or the lower surface of the fourth-type conductor layer 702) and longitudinally traverses the second interlayer dielectric layer 600 until it reaches and at least touches (i.e., physically directly contacts) its corresponding second-type conductive island 402 in the second conductive wiring layer 103. In an exemplary embodiment, the "one-to-one correspondence" here may further include: the cross-sectional shape or projected shape of each fourth-type conductive via 602 and its corresponding second-type conductive island 402 on the lower surface 600B of the second interlayer dielectric layer 600 is matched, for example, they may have the same geometry. Each second-type conductive island 402 can be electrically coupled to the fourth-type conductor layer 702 through its corresponding fourth-type via 602 (and the conductive material therein). Thus, the plurality of fourth-type vias 602 can electrically couple the fourth-type conductor layer 702 to the plurality of second-type conductive islands 402 in the second conductive wiring layer 103 (including those second-type conductive islands 402 not fused with the second-type mesh conductor layer 502 and those second-type conductive islands 402 fused with the second-type mesh conductor layer 502), and then can be electrically coupled to the plurality of second-type conductive traces 202 through the plurality of second-type vias 302 (and the conductive material therein).

[0071] Therefore, in practical applications, the third type conductor layer 701 and the fourth type conductor layer 702 can be used to couple / transmit different potentials. For example, in the application example where "the plurality of first type conductive traces 201 are used to couple / transmit a first potential, and the plurality of second type conductive traces 202 are used to couple / transmit a second potential," the third type conductor layer 701 is essentially used to couple / transmit the first potential, while the fourth type conductor layer 702 is essentially used to couple / transmit the second potential. For example, taking a semiconductor integrated circuit wafer / die 100 containing a high-power switching unit (e.g., a DMOS) fabricated therein, in practical applications, the third type conductor layer 701 is essentially used to couple / transmit the source potential of the DMOS, while the fourth type conductor layer 702 is essentially used to couple / transmit the drain potential of the DMOS.

[0072] In one embodiment, the thickness T3 of the third conductive wiring layer 104 (including the third type conductor layer 701 and the fourth type conductor layer 702) is greater than the thickness T2 of the second conductive wiring layer 103 (including the first type mesh conductor layer 501, the second type mesh conductor layer 502, the plurality of first type conductive islands 401 and the plurality of second type conductive islands 402), i.e., T3 > T2. In an exemplary embodiment, the thickness T3 of the third conductive wiring layer 104 can be 1.5 to 8 times the thickness T2 of the second conductive wiring layer 103. In one embodiment, the thickness T2 of the second conductive wiring layer 103 is greater than or equal to the thickness T1 of the first conductive wiring layer 102 (including the plurality of first type traces 201 and the plurality of second type traces 202), i.e., T2 ≥ T1. In an exemplary embodiment, the third conductive wiring layer 104 (including the third type conductor layer 701 and the fourth type conductor layer 702) can include aluminum, and its thickness T3 can be in the range of 0.8 μm to 4 μm. In one exemplary embodiment, the third conductive wiring layer 104 (including a third type conductor layer 701 and a fourth type conductor layer 702) may include copper, and its thickness T3 may be in the range of 2 μm to 3 μm. In one exemplary embodiment, the second conductive wiring layer 103 (including a first type mesh conductor layer 501, a second type mesh conductor layer 502, the plurality of first type conductive islands 401 and the plurality of second type conductive islands 402) may include aluminum, and its thickness T2 may be in the range of 0.4 μm to 0.8 μm. In one exemplary embodiment, the second conductive wiring layer 103 (including a first type mesh conductor layer 501, a second type mesh conductor layer 502, the plurality of first type conductive islands 401 and the plurality of second type conductive islands 402) may include copper, and its thickness T2 may be in the range of 0.2 μm to 0.4 μm. In one exemplary embodiment, the first conductive wiring layer 102 (including the plurality of first-type traces 201 and the plurality of second-type traces 202) may include aluminum, and its thickness T1 may be in the range of 0.4 μm to 0.5 μm. In one exemplary embodiment, the first conductive wiring layer 102 (including the plurality of first-type traces 201 and the plurality of second-type traces 202) may include copper, and its thickness T1 may be in the range of 0.2 μm to 0.3 μm. The term "thickness" mentioned above refers to the dimension in the Z-axis direction. Those skilled in the art should understand that the at least one conductive wiring layer (e.g., including the first conductive wiring layer 102, the second conductive wiring layer 103, the third conductive wiring layer 104, etc.) may include other metals or other conductive materials with better conductivity than aluminum or copper, and this disclosure does not limit this.

[0073] According to an exemplary embodiment of this disclosure, continued reference Figure 9 As illustrated, the semiconductor integrated circuit wafer / die 100 may further include a plurality of conductive bumps fabricated on the third conductive wiring layer 104. For example, it may include at least one first-type conductive bump 901 located on and in direct contact with / electrically connected to the third-type conductor layer 701, and at least one second-type conductive bump 902 located on and in direct contact with / electrically connected to the fourth-type conductor layer 702. Figure 9 In the example, the plurality of conductive bumps are indicated by circles filled with diagonal lines, such as two first-type conductive bumps 901 and two second-type conductive bumps 902. Those skilled in the art should understand that this is merely exemplary and not intended to limit the scope of this disclosure. The plurality of conductive bumps can be used to electrically couple the third conductive wiring layer 104 to the lead frame or other wire-wound substrate or printed circuit board of the semiconductor integrated circuit wafer / die 100, etc., to allow the semiconductor integrated circuit wafer / die 100 to be electrically coupled or exchange signals with other circuits.

[0074] The following is a brief description using a semiconductor integrated circuit wafer / die 100 containing a high-power switching unit (e.g., a DMOS) fabricated therein, to further aid in understanding the embodiments of this disclosure. See also Figure 3A , Figure 3B and Figure 7 A partial longitudinal cross-sectional view shows that multiple DMOS cells can be fabricated in the semiconductor substrate 101, for example, forming a DMOS cell array. Each DMOS cell may include a source region 106, a drain region 107, and a gate region 108, wherein the gate region 108 may include the gate conductive structure 105 and a gate dielectric structure 109 located between the gate conductive structure 105 and the semiconductor substrate 101. Therefore, in a planar top view (on the XY plane), the gate region 108 of each DMOS cell surrounds a corresponding first-type conductive trace 201. The source region 106 and the drain region 107 may have the same conductivity type (or doping type), for example, a first doping type ( Figure 3A and Figure 3B (Exemplarily illustrated as N-type). The semiconductor substrate 101 may also have the first doping type, with a doping concentration lower than that of the source region 106 and the drain region 107. Each DMOS cell may further include a body region 110 surrounding the source region 106, which has a conductivity type (or doping type) opposite to that of the source region 106, such as a second doping type (e.g., N-type). Figure 3A and Figure 3B(Exemplarily illustrated as P-type), the body region 110 separates the source region 106 from the semiconductor substrate 101. Each DMOS cell may further include a body contact region 111 having the same conductivity type (or doping type) as the body region 110, such as a second doping type. Figure 3A and Figure 3B The substrate 101 is exemplarily represented as P-type and has a higher doping concentration than the extracted 110 to reduce the ohmic contact resistance of the body region 110 to the wiring structure. An interlayer dielectric layer 112 (e.g., referred to as a third interlayer dielectric layer 112 to distinguish it from the first interlayer dielectric layer 300 and the second interlayer dielectric layer 600) is formed between the first conductive wiring layer 102 and the semiconductor substrate 101. The source region 106 of each DMOS cell can be electrically coupled to one of the plurality of first-type conductive traces 201 through a source contact via 113 formed in the interlayer dielectric layer 112 and a conductive material filling the source contact via. The drain region 107 of each DMOS cell can be electrically coupled to one of the plurality of second-type conductive traces 202 through a drain contact via 114 formed in the interlayer dielectric layer 112 and a conductive material filling the drain contact via. Thus, the source regions 106 of all DMOS cells in the semiconductor substrate 101 can be bonded via the above method. Figures 2A to 9 The wiring structure / at least one conductive wiring layer (e.g., first conductive wiring layer 102, second conductive wiring layer 103, and third conductive wiring layer 104) fabricated on the semiconductor substrate 101 as described in the example is ultimately electrically coupled to the third type conductor layer 701 and the first type conductive bump 901 thereon, and the drain regions 107 of all DMOS cells can be connected via the above combination. Figures 2A to 9 The wiring structure / at least one conductive wiring layer (e.g., the first conductive wiring layer 102, the second conductive wiring layer 103, and the third conductive wiring layer 104) fabricated on the semiconductor substrate 101 as described in the example is ultimately electrically coupled to the fourth type conductor layer 702 and the second type conductive bump 902 thereon.

[0075] In practical applications, the first potential (or source potential) and the second potential (or drain potential) can be electrically coupled / transmitted to all source regions 106 and all drain regions 107 of the high-power switching unit (e.g., DMOS) through the wiring structure / at least one conductive wiring layer on the semiconductor substrate 101. When the high-power switching unit (taking an N-channel DMOS as an example) is turned on, that is, when the gate-source potential difference between the gate region 108 and the source region 106 of the N-channel DMOS is greater than the turn-on threshold voltage of the N-channel DMOS, since the drain region 107 and the source region 106 of each DMOS cell are coupled to the second potential and the first potential respectively (for the example of N-channel DMOS, the second potential is greater than the first potential), current will flow from the drain region 107 of each DMOS cell through the channel of the DMOS cell to its source region 106 (hereinafter referred to as DMOS cell current).

[0076] In one embodiment, corresponding to the transmission path of the second potential (or drain potential), the DMOS cell current flowing through each DMOS cell is coupled / transmitted via the drain region 107 to the plurality of second-type conductive traces 202, and then collected in the designated second region via, for example, a plurality of second-type vias 302 to the second-type mesh conductor layer 502, and simultaneously collected in the designated first region via, for example, a plurality of second-type vias 302 to the plurality of second-type conductive islands 402. In one embodiment, the current collected to the second-type mesh conductor layer 502 can be further coupled / transmitted to the fourth-type conductor layer 702 via those fourth-type vias 602 (i.e., those fourth-type vias 602 corresponding to those second-type conductive islands 402 fused by the plurality of second-type protrusions 504) above the second-type mesh conductor layer 502. In one embodiment, the current collected to the plurality of second-type conductive islands 402 can be further coupled / transmitted to the fourth-type conductor layer 702 through a fourth-type via 602 corresponding to each second-type conductive island 402.

[0077] Similarly, corresponding to the transmission path of the first potential (or source potential), the DMOS cell current flowing through each DMOS cell is coupled / transmitted to the plurality of first-type conductive traces 201 via the source region 106, and then collected in the designated first region via, for example, a plurality of first-type vias 301 to the first-type mesh conductor layer 501, and simultaneously collected in the designated second region via, for example, a plurality of first-type vias 301 to the plurality of first-type conductive islands 401. In one embodiment, the current collected to the first-type mesh conductor layer 501 can be further coupled / transmitted to the third-type conductor layer 701 via those third-type vias 601 (i.e., those third-type vias 601 corresponding to those first-type conductive islands 401 fused by the plurality of first-type protrusions 503) above the first-type mesh conductor layer 501. In one embodiment, the current collected to the plurality of first-type conductive islands 401 can be further coupled / transmitted to the fourth-type conductor layer 702 through a third-type via 601 corresponding to each first-type conductive island 401.

[0078] Those skilled in the art should understand that the above descriptions of the semiconductor integrated circuit wafer / die 100 and the wiring structure for the semiconductor integrated circuit wafer / die 100 according to the embodiments of this disclosure are exemplary. In one example, the wiring structure may include an intermediate conductive wiring layer (e.g., the second conductive wiring layer 103). In one example, the wiring structure may further include a lower conductive wiring layer (e.g., the first conductive wiring layer 102) and / or a higher conductive wiring layer (e.g., the third conductive wiring layer 104). Those skilled in the art should understand that the number of conductive wiring layers included in the wiring structure for the semiconductor integrated circuit wafer / die according to the embodiments of this disclosure can be reasonably selected according to electrical connection requirements and wiring requirements, and this application does not limit this. For example, in other variant embodiments, depending on the actual application requirements, the wiring structure for a semiconductor integrated circuit wafer / die may include any selection or combination of the intermediate conductive wiring layer (e.g., the second conductive wiring layer 103), the lower conductive wiring layer (e.g., the first conductive wiring layer 102), and the upper conductive wiring layer (e.g., the third conductive wiring layer 104), and the number of lower, intermediate, or upper conductive wiring layers can be reasonably selected. For example, in one example, it may include multiple (e.g., two or three) lower conductive wiring layers or multiple (e.g., two or three) intermediate conductive wiring layers. In the wiring structure, an interlayer dielectric layer is formed between each adjacent (here referring to adjacent in the Z-axis direction) conductive wiring layer, and adjacent conductive wiring layers can be electrically coupled through vias formed in the interlayer dielectric layer between them.

[0079] Figure 10A , Figure 10B and Figure 10C This illustration shows a partial longitudinal cross-sectional view of a semiconductor integrated circuit wafer / die 200 according to an embodiment of the present disclosure, cut along the AA', BB', and CC' sections in the YZ plane from the Z-axis direction. The semiconductor integrated circuit wafer / die 200 differs from the integrated circuit wafer / die 100 in that it may include more than one lower conductive wiring layer. The wiring structure of the semiconductor integrated circuit wafer / die 200 exemplarily includes two adjacent lower conductive wiring layers (i.e., two layers of the first conductive wiring layer 102) in the Z-axis direction. An interlayer dielectric layer 117 (e.g., referred to as the fourth interlayer dielectric layer 117 to distinguish it from other interlayer dielectric layers 300, 600, and 112) is formed between the two lower conductive wiring layers 102. This interlayer dielectric layer 117 is electrically coupled via a plurality of fifth-type vias 115 and a plurality of sixth-type vias 116 formed therein (here, the fifth and sixth types are only used to decorate vias 115 and 116 to distinguish them from the aforementioned plurality of first-type vias 301, plurality of second-type vias 302, plurality of third-type vias 601, and plurality of fourth-type vias 602). For example, corresponding first-type traces 201 in the two lower conductive wiring layers 102 can be electrically coupled via a plurality of fifth-type vias 115, and corresponding second-type traces 202 can be electrically coupled via a plurality of sixth-type vias 116. Those skilled in the art should understand that, apart from this, the above references... Figures 1 to 9 Description of the integrated circuit wafer / die 100 and its wiring structure, especially the structure, pattern, shape, arrangement, etc. of the intermediate conductive wiring layer (e.g., the second conductive wiring layer 103), the lower conductive wiring layer (e.g., the first conductive wiring layer 102), and the upper conductive wiring layer (e.g., the third conductive wiring layer 104) in the XY plane, and the description of the intermediate conductive wiring layer 103 and the lower conductive wiring layer 102 (applicable to...). Figure 10A , Figure 10B and Figure 10C The illustrative example can be understood as a description of the electrical coupling relationship and coupling method between the lower conductive wiring layer 102 (adjacent to the middle conductive wiring layer 103) or the middle conductive wiring layer 103 and the upper conductive wiring layer 104 in the Z-axis direction. It is also applicable to... Figure 10A , Figure 10B and Figure 10C The example shows a semiconductor integrated circuit wafer / die 200. Even though the semiconductor integrated circuit wafer / die 200 is not described in as much detail here as the semiconductor integrated circuit wafer / die 100, those skilled in the art can understand it by referring to... Figures 1 to 9 Description of the integrated circuit wafer / die 100 and its wiring structure, and appendix Figure 10A , Figure 10B and Figure 10C The meaning is self-evident and needs no further explanation here.

[0080] Figure 11A , Figure 11B and Figure 11C This illustration shows a partial longitudinal cross-sectional view of a semiconductor integrated circuit wafer / die 300 according to an embodiment of the present disclosure, cut along the AA', BB', and CC' sections in the YZ plane from the Z-axis direction. The semiconductor integrated circuit wafer / die 300 differs from the integrated circuit wafer / die 100 in that it may include more than one intermediate conductive wiring layer. The wiring structure of the semiconductor integrated circuit wafer / die 300 exemplarily includes two adjacent intermediate conductive wiring layers (i.e., two layers of the second conductive wiring layer 103) in the Z-axis direction. An interlayer dielectric layer 118 (e.g., referred to as the fifth interlayer dielectric layer 118 to distinguish it from other interlayer dielectric layers 300, 600, 112, and 117) is formed between the two intermediate conductive wiring layers 103. This interlayer dielectric layer 118 is electrically coupled through multiple seventh-type vias 119 and multiple eighth-type vias 120 (here, the eighth and ninth types are only used to decorate vias 119 and 120 to distinguish them from the aforementioned multiple first-type vias 301, multiple second-type vias 302, multiple third-type vias 601, multiple fourth-type vias 602, multiple fifth-type vias 115, and multiple sixth-type vias 116). For example, corresponding first-type traces 201 in the two lower conductive wiring layers 102 can be electrically coupled through multiple fifth-type vias 115, and corresponding second-type traces 202 can be electrically coupled through multiple sixth-type vias 116. Those skilled in the art should understand that, apart from this, the above references... Figures 1 to 9 Description of the integrated circuit wafer / die 100 and its wiring structure, especially the structure, pattern, shape, arrangement, etc. of the intermediate conductive wiring layer (e.g., the second conductive wiring layer 103), the lower conductive wiring layer (e.g., the first conductive wiring layer 102), and the upper conductive wiring layer (e.g., the third conductive wiring layer 104) in the XY plane, and the description of the intermediate conductive wiring layer 103 (suitable for...). Figure 11A , Figure 11B and Figure 11C In the illustrative example, it can be understood as the intermediate conductive wiring layer 103 (adjacent to the lower conductive wiring layer 102) and the lower conductive wiring layer 102 or the intermediate conductive wiring layer 103 (applicable to...). Figure 11A , Figure 11B and Figure 11CThe illustrative example can be understood as a description of the electrical coupling relationship and coupling method between the intermediate conductive wiring layer 103 (adjacent to the upper conductive wiring layer 104) and the upper conductive wiring layer 104 in the Z-axis direction. This also applies to... Figure 11A , Figure 11B and Figure 11C The example shows a semiconductor integrated circuit wafer / die 300. Even though the semiconductor integrated circuit wafer / die 300 is not described in as much detail here as the semiconductor integrated circuit wafer / die 100, those skilled in the art can obtain its meaning by referring to... Figures 1 to 9 Description of the integrated circuit wafer / die 100 and its wiring structure, and appendix Figure 11A , Figure 11B and Figure 11C The meaning is self-evident and needs no further explanation here.

[0081] Such as Figures 10A-10C and Figure 11A-11C The illustrative examples and variations thereof are not exhaustive, but all are within the spirit and scope of the invention. This disclosure provides a semiconductor integrated circuit wafer / die and a wiring structure for it. While some embodiments of this disclosure are described in detail, it should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Other possible alternative embodiments can be understood by those skilled in the art through reading this disclosure.

Claims

1. A semiconductor integrated circuit wafer / die, comprising: Semiconductor substrate; and Wiring structure located on the semiconductor substrate; in The semiconductor integrated circuit wafer / die is divided into a defined first region and a defined second region; The wiring structure includes at least an intermediate conductive wiring layer, which includes a first type mesh conductor layer and a second type mesh conductor layer, located in the defined second region and the defined first region respectively and electrically isolated from each other. The first type mesh conductor layer and the second type mesh conductor layer have a boundary region. The first type mesh conductor layer has a plurality of first type protrusions in the boundary region, extending from the first type mesh conductor layer and towards the second type mesh conductor layer. The second type mesh conductor layer has a plurality of second type protrusions in the boundary region, extending from the second type mesh conductor layer and towards the first type mesh conductor layer. The intermediate conductive wiring layer further includes a plurality of first-type conductive islands distributed in the defined first region, wherein each of the plurality of first-type protrusions fuses with at least one of the plurality of first-type conductive islands, and those first-type conductive islands not fused by the plurality of first-type protrusions are referred to as the plurality of unfused first-type conductive islands. The intermediate conductive wiring layer further includes a plurality of second-type conductive islands distributed in the defined second region, wherein each of the plurality of second-type protrusions fuses with at least one of the plurality of second-type conductive islands, and those second-type conductive islands not fused by the plurality of second-type protrusions are referred to as the plurality of unfused second-type conductive islands. The first type of mesh conductor layer encloses the plurality of unfused second type conductive islands and is isolated from each of the plurality of unfused second type conductive islands; The second type of mesh conductor layer encloses the plurality of unfused first type conductive islands and is isolated from each of the plurality of unfused first type conductive islands.

2. The semiconductor integrated circuit wafer / die as described in claim 1, wherein, The first type of mesh conductor layer has a plurality of mesh openings corresponding one-to-one with the plurality of unfused second type conductive islands, each of the plurality of unfused second type conductive islands being located within a corresponding mesh opening.

3. The semiconductor integrated circuit wafer / die as described in claim 1, wherein, The second type of mesh conductor layer has a plurality of mesh openings corresponding one-to-one with the plurality of unfused first type conductive islands, each of the plurality of unfused first type conductive islands being located within a corresponding mesh opening.

4. The semiconductor integrated circuit wafer / die as described in claim 1, wherein, The adjacent rows of first-type conductive islands are staggered along the width of the semiconductor substrate, and the adjacent rows of second-type conductive islands are staggered along the width of the semiconductor substrate.

5. The semiconductor integrated circuit wafer / die as described in claim 1, wherein, The plurality of first-type conductive islands are arranged in a quincunx pattern, and the plurality of second-type conductive islands are also arranged in a quincunx pattern.

6. The semiconductor integrated circuit wafer / die of claim 1, wherein the wiring structure further comprises: The lower conductive wiring layer is located below the intermediate conductive wiring layer and includes multiple first-type conductive traces and multiple second-type conductive traces, which are parallel to each other, do not contact each other, and are arranged alternately. as well as The first interlayer dielectric layer is located between the lower conductive wiring layer and the intermediate conductive wiring layer; The first type of mesh conductor layer and the plurality of first type of conductive islands are coupled to the plurality of first type of conductive traces through a plurality of first type of vias fabricated in the first interlayer dielectric layer; and The second type of mesh conductor layer and the plurality of second type of conductive islands are coupled to the plurality of second type of conductive traces through a plurality of second type vias fabricated in the first interlayer dielectric layer.

7. The semiconductor integrated circuit wafer / die of claim 6, wherein the first type conductive islands located directly above every two adjacent first type conductive traces are staggered along the width direction of the semiconductor substrate, and the second type conductive islands located directly above every two adjacent second type conductive traces are staggered along the width direction of the semiconductor substrate.

8. The semiconductor integrated circuit wafer / die as claimed in claim 6, wherein the plurality of first-type conductive islands are located directly above the plurality of first-type conductive traces and are arranged in a quincunx pattern, and the plurality of second-type conductive islands are located directly above the plurality of second-type conductive traces and are also arranged in a quincunx pattern.

9. The semiconductor integrated circuit wafer / die of claim 6, wherein the plurality of first-type vias are formed in the portion of the first interlayer dielectric layer directly above the plurality of first-type conductive traces, and the plurality of second-type vias are formed in the portion of the first interlayer dielectric layer directly above the plurality of second-type conductive traces.

10. The semiconductor integrated circuit wafer / die as claimed in claim 9, wherein for the portion of the first interlayer dielectric layer located in the defined first region, one or more first-type vias corresponding to each first-type conductive island are made only at a position directly below each first-type conductive island and overlapping directly above a first-type conductive trace, while no first-type vias are made at positions other than directly below each first-type conductive island; For the portion of the first interlayer dielectric layer located in the defined second region, one or more second-type vias corresponding to each second-type conductive island are made only at the position directly below each second-type conductive island and overlapping with the position directly above each second-type conductive trace, while no second-type vias are made at the position outside the position directly below each second-type conductive island.

11. The semiconductor integrated circuit wafer / die of claim 1, wherein the defined first region and the defined second region have equal areas.

12. The semiconductor integrated circuit wafer / die as claimed in claim 1, wherein the defined first region and the defined second region are divided along the diagonal of the semiconductor integrated circuit wafer / die.

13. The semiconductor integrated circuit wafer / die of claim 1, wherein the plurality of first-type protrusions and the plurality of second-type protrusions are arranged alternately, and adjacent first-type protrusions and second-type protrusions are spaced apart from each other.

14. The semiconductor integrated circuit wafer / die as claimed in claim 1 or 6, wherein the wiring structure further comprises: The upper conductive wiring layer, located above the intermediate conductive wiring layer, includes a third type conductor layer and a fourth type conductor layer that are electrically isolated from each other. The third type conductor layer and the fourth type conductor layer are respectively laid in the designated first region and the designated second region. as well as A second interlayer dielectric layer located between the upper conductive wiring layer and the middle conductive wiring layer; The third type conductor layer is coupled to the plurality of first type conductive islands through a plurality of third type vias fabricated in the second interlayer dielectric layer; and The fourth type conductor layer is coupled to the plurality of second type conductive islands through a plurality of fourth type vias fabricated in the second interlayer dielectric layer.

15. The semiconductor integrated circuit wafer / die of claim 14, wherein the plurality of third-type vias correspond one-to-one with the plurality of first-type conductive islands.

16. The semiconductor integrated circuit wafer / die of claim 14, wherein the plurality of fourth type vias correspond one-to-one with the plurality of second type conductive islands.

17. The semiconductor integrated circuit wafer / die of claim 14, wherein the thickness of the upper conductive wiring layer is greater than the thickness of the middle conductive wiring layer.

18. The semiconductor integrated circuit wafer / die of claim 6, wherein the thickness of the intermediate conductive wiring layer is greater than or equal to the thickness of the lower conductive wiring layer.

19. The semiconductor integrated circuit wafer / die of claim 6, further comprising a plurality of double-diffused metal-oxide-semiconductor field-effect transistor (DMOS) cells fabricated in the semiconductor substrate, wherein each DMOS cell includes a source region and a drain region, the source region of each DMOS cell is electrically coupled to one of the plurality of first-type conductive traces, and the drain region of each DMOS cell is electrically coupled to one of the plurality of second-type conductive traces.

20. The semiconductor integrated circuit wafer / die of claim 19, wherein each DMOS cell further includes a gate region that, when viewed from a planar top view, wraps around a corresponding first-type conductive trace.

21. A wiring structure for semiconductor integrated circuit wafers / dies, comprising: An intermediate conductive wiring layer includes a first type mesh conductor layer and a second type mesh conductor layer, which are respectively located in a designated second region and a designated first region of the semiconductor integrated circuit wafer / die and are electrically isolated from each other. The first type mesh conductor layer and the second type mesh conductor layer have an interface region. The first type mesh conductor layer has a plurality of first type protrusions in the interface region, which extend from the first type mesh conductor layer and toward the second type mesh conductor layer. The second type mesh conductor layer has a plurality of second type protrusions in the interface region, which extend from the second type mesh conductor layer and toward the first type mesh conductor layer. The intermediate conductive wiring layer further includes a plurality of first-type conductive islands distributed in the defined first region, wherein each of the plurality of first-type protrusions fuses with at least one of the plurality of first-type conductive islands, and those first-type conductive islands not fused by the plurality of first-type protrusions are referred to as the plurality of unfused first-type conductive islands. The intermediate conductive wiring layer further includes a plurality of second-type conductive islands distributed in the defined second region, wherein each of the plurality of second-type protrusions fuses with at least one of the plurality of second-type conductive islands, and those second-type conductive islands not fused by the plurality of second-type protrusions are referred to as the plurality of unfused second-type conductive islands. The first type of mesh conductor layer encloses the plurality of unfused second type conductive islands and is isolated from each of the plurality of unfused second type conductive islands; The second type of mesh conductor layer encloses the plurality of unfused first type conductive islands and is isolated from each of the plurality of unfused first type conductive islands.

22. The wiring structure as described in claim 21, wherein, The first type of mesh conductor layer has a plurality of mesh openings corresponding one-to-one with the plurality of unfused second type conductive islands, each of the plurality of unfused second type conductive islands being located within a corresponding mesh opening.

23. The wiring structure as described in claim 21, wherein, The second type of mesh conductor layer has a plurality of mesh openings corresponding one-to-one with the plurality of unfused first type conductive islands, each of the plurality of unfused first type conductive islands being located within a corresponding mesh opening.

24. The wiring structure as described in claim 21, wherein, Adjacent rows of first-type conductive islands are staggered along the width of the semiconductor integrated circuit wafer / die, and adjacent rows of second-type conductive islands are staggered along the width of the semiconductor integrated circuit wafer / die.

25. The semiconductor integrated circuit wafer / die of claim 21, wherein the plurality of first-type conductive islands are arranged in a quincunx pattern, and the plurality of second-type conductive islands are also arranged in a quincunx pattern.

26. The wiring structure of claim 21, further comprising: The lower conductive wiring layer is located below the intermediate conductive wiring layer and includes multiple first-type conductive traces and multiple second-type conductive traces, which are parallel to each other, do not contact each other, and are arranged alternately. as well as The first interlayer dielectric layer is located between the lower conductive wiring layer and the intermediate conductive wiring layer; The first type of mesh conductor layer and the plurality of first type of conductive islands are coupled to the plurality of first type of conductive traces through a plurality of first type of vias fabricated in the first interlayer dielectric layer; and The second type of mesh conductor layer and the plurality of second type of conductive islands are coupled to the plurality of second type of conductive traces through a plurality of second type vias fabricated in the first interlayer dielectric layer.

27. The wiring structure of claim 26, wherein the first type conductive islands located directly above every two adjacent first type conductive traces are staggered along the width direction of the semiconductor integrated circuit wafer / die, and the second type conductive islands located directly above every two adjacent second type conductive traces are staggered along the width direction of the semiconductor integrated circuit wafer / die.

28. The wiring structure of claim 26, wherein the plurality of first-type conductive islands are located directly above the plurality of first-type conductive traces and are arranged in a quincunx pattern, and the plurality of second-type conductive islands are located directly above the plurality of second-type conductive traces and are also arranged in a quincunx pattern.

29. The wiring structure of claim 26, wherein the plurality of first-type vias are formed in the portion of the first interlayer dielectric layer directly above the plurality of first-type conductive traces, and the plurality of second-type vias are formed in the portion of the first interlayer dielectric layer directly above the plurality of second-type conductive traces.

30. The wiring structure of claim 29, wherein for the portion of the first interlayer dielectric layer located in the defined first region, one or more first-type vias corresponding to each first-type conductive island are made only at a position directly below each first-type conductive island and overlapping directly above a first-type conductive trace, while no first-type vias are made at positions other than directly below each first-type conductive island; For the portion of the first interlayer dielectric layer located in the defined second region, one or more second-type vias corresponding to each second-type conductive island are made only at the position directly below each second-type conductive island and overlapping with the position directly above each second-type conductive trace, while no second-type vias are made at the position outside the position directly below each second-type conductive island.

31. The wiring structure of claim 21, wherein the designated first region and the designated second region have equal areas.

32. The wiring structure of claim 21, wherein the defined first region and the defined second region are divided along the diagonal of the semiconductor integrated circuit wafer / die.

33. The wiring structure of claim 21, wherein the plurality of first type teeth and the plurality of second type teeth are arranged alternately, and adjacent first type teeth and second type teeth are spaced apart from each other.

34. The wiring structure as described in claim 21 or 26, further comprising: The upper conductive wiring layer, located above the intermediate conductive wiring layer, includes a third type conductor layer and a fourth type conductor layer that are electrically isolated from each other. The third type conductor layer and the fourth type conductor layer are respectively laid in the designated first region and the designated second region. as well as A second interlayer dielectric layer located between the upper conductive wiring layer and the middle conductive wiring layer; The third type conductor layer is coupled to the plurality of first type conductive islands through a plurality of third type vias fabricated in the second interlayer dielectric layer; and The fourth type conductor layer is coupled to the plurality of second type conductive islands through a plurality of fourth type vias fabricated in the second interlayer dielectric layer.

35. The wiring structure of claim 34, wherein the plurality of third-type vias correspond one-to-one with the plurality of first-type conductive islands.

36. The wiring structure of claim 34, wherein the plurality of fourth type vias correspond one-to-one with the plurality of second type conductive islands.

37. The wiring structure of claim 34, wherein the thickness of the upper conductive wiring layer is greater than the thickness of the middle conductive wiring layer.

38. The wiring structure of claim 26, wherein the thickness of the intermediate conductive wiring layer is greater than or equal to the thickness of the lower conductive wiring layer.

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