Semiconductor element with air gap under landing pad and method of making same

Abstract

One embodiment of this disclosure provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a first lower plug and a second lower plug disposed on a semiconductor substrate. The semiconductor device also includes a first landing pad disposed on an upper surface and upper sidewalls of the first lower plug; and a first upper plug disposed on the first landing pad and electrically connected to the first lower plug. The width of the first lower plug is greater than the width of the first upper plug. The semiconductor device further includes a dielectric layer disposed on the semiconductor substrate. The first lower plug, the second lower plug, the first landing pad, and the first upper plug are disposed within the dielectric layer, and the dielectric layer includes an air gap disposed between the first lower plug and the second lower plug.

Description

[0001] Cross-referencing

[0002] This application claims priority and benefits from U.S. Official Application No. 17 / 374,343, filed July 13, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor element and a method for fabricating the same. In particular, it relates to a semiconductor element having an air gap beneath a landing pad and a method for fabricating the same. Background Technology

[0004] Semiconductor components are indispensable for many modern applications. With advancements in electronic technology, semiconductor components have become increasingly smaller, while simultaneously offering superior functionality and incorporating a greater number of integrated circuits. Due to the miniaturization of semiconductor components, different forms and sizes of semiconductor components realizing different functions are integrated and packaged into a single module. Furthermore, numerous manufacturing steps are performed on the integration of various types of semiconductor devices.

[0005] However, the fabrication and integration of these semiconductor devices involve many complex steps and operations. Integration within these semiconductor devices becomes increasingly complex. This increased complexity in the fabrication and integration of these semiconductor devices can lead to several defects, such as poor electrical interconnection caused by misalignment between multiple upper conductive features and multiple lower conductive features. Therefore, there is a need for continuous improvement of the fabrication process of these semiconductor devices to address these defects and enhance their performance.

[0006] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0007] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a first lower plug and a second lower plug disposed on a semiconductor substrate. The semiconductor device also includes a first landing pad disposed on an upper surface and upper sidewalls of the first lower plug; and a first upper plug disposed on the first landing pad and electrically connected to the first lower plug. The width of the first lower plug is greater than the width of the first upper plug. The semiconductor device further includes a dielectric layer disposed on the semiconductor substrate. The first lower plug, the second lower plug, the first landing pad, and the first upper plug are disposed within the dielectric layer, and the dielectric layer includes an air gap disposed between the first lower plug and the second lower plug.

[0008] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a first gate stack and a second gate stack disposed on a semiconductor substrate. One of the first gate stack and the second gate stack includes a plurality of gate layers, and an air gap is provided between the first gate stack and the second gate stack. The semiconductor device also includes a first gate structure and a second gate structure disposed on the first gate stack and the second gate stack, respectively; and a first dielectric layer surrounding each lower sidewall of the first gate structure and each lower sidewall of the second gate structure. The semiconductor device further includes a first landing pad disposed on an upper surface and each upper sidewall of the first gate structure; and a first plug disposed on the first landing pad and electrically connected to the first gate structure. A width of the first gate structure is greater than a width of the first plug. Furthermore, the semiconductor device includes a second dielectric layer disposed on the first dielectric layer. The first landing pad and the first plug are surrounded by the second dielectric layer.

[0009] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a first lower plug and a second lower plug on a semiconductor substrate; and forming a first dielectric layer surrounding the first lower plug and the second lower plug. An upper surface and upper sidewalls of the first lower plug and an upper surface and upper sidewalls of the second lower plug protrude from the first dielectric layer. The method also includes performing a heat treatment process to form a first landing pad on the upper surface and upper sidewalls of the first lower plug, and to form a second landing pad on the upper surface and upper sidewalls of the second lower plug; and after the heat treatment process, removing the first dielectric layer to form an opening between the first lower plug and the second lower plug. The preparation method further includes depositing a second dielectric layer in the opening and on the first and second landing pads to form an air gap in the opening and surrounded by the second dielectric layer; and forming a first upper plug in the second dielectric layer and on the first landing pad. The width of the first lower plug is greater than the width of the first upper plug.

[0010] One embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a first gate stack and a second gate stack on a semiconductor substrate. One of the first gate stack and the second gate stack includes a plurality of gate layers, and an air gap exists between the first gate stack and the second gate stack. The method also includes forming a first gate structure and a second gate structure on the first gate stack and the second gate stack, respectively; and forming a first dielectric layer surrounding the first gate structure and the second gate structure. An upper surface and upper sidewalls of the first gate structure and an upper surface and upper sidewalls of the second gate structure protrude from the first dielectric layer. The method further includes performing a thermal processing step to form a first landing pad on the upper surface and upper sidewalls of the first gate structure, and to form a second landing pad on the upper surface and upper sidewalls of the second gate structure. Furthermore, the method includes forming a second dielectric layer to cover the first landing pad and the second landing pad; and forming a first plug in the second dielectric layer and on the first landing pad. The width of the first gate structure is greater than the width of the first plug.

[0011] This disclosure provides some embodiments of a semiconductor device and a method for fabricating the same. In some embodiments, the semiconductor device has a plurality of lower plugs disposed on a semiconductor substrate (or, when the semiconductor device is a gate-all-around (GAA) transistor, a plurality of gate structures disposed on a plurality of gate stacks); a landing pad disposed on an upper surface and an upper sidewall of one of the lower plugs; and an upper plug disposed on the landing pad. The landing pad provides an increased landing area for the upper plug to land on. Therefore, multiple misalignment problems between the upper plug and the lower plugs can be avoided or reduced. In some embodiments, an air gap is formed below the landing pad and between the plurality of lower plugs (or, when the semiconductor device is a GAA transistor, between the plurality of gate stacks). Therefore, parasitic capacitance between the plurality of lower plugs (or the plurality of gate stacks) can be reduced. Therefore, the yield of the semiconductor device can be improved, and the overall device performance can be improved.

[0012] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0013] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0014] Figure 1 This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0015] Figure 2 This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0016] Figure 3 This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0017] Figure 4 This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0018] Figure 5 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0019] Figure 6 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of multiple lower emboli during semiconductor device formation, according to some embodiments of the present disclosure.

[0020] Figure 7 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure of forming a first dielectric layer during the formation of a semiconductor element to surround the intermediate stage of the plurality of lower plugs.

[0021] Figure 8 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in which multiple landing pads are formed during the intermediate stage of the multiple lower embolizations during the formation of semiconductor elements.

[0022] Figure 9 This is a top view schematic diagram illustrating an intermediate stage during the formation of a semiconductor device in some embodiments of the present disclosure, where a first dielectric layer is removed.

[0023] Figure 10 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in which a second dielectric layer is deposited during the formation of a semiconductor element to create an air gap in the intermediate stage between the plurality of lower plugs.

[0024] Figure 11 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0025] Figure 12 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of multiple gate structures on multiple gate stacks during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0026] Figure 13 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure during the formation of a first dielectric layer to surround the plurality of gate structures.

[0027] Figure 14 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of multiple landing pads on multiple gate structures during the formation of semiconductor devices, according to some embodiments of the present disclosure.

[0028] Figure 15 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0029] Figure 16 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure of a stage in which a sacrificial dielectric layer is formed during the formation of a semiconductor device and the sacrificial layer has a plurality of openings exposing a semiconductor substrate.

[0030] Figure 17 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of multiple barrier layers and multiple lower plugs in the multiple openings during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0031] Figure 18 This is a cross-sectional schematic diagram illustrating an intermediate stage in the removal of the sacrificial dielectric layer during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0032] Figure 19 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure of forming a first dielectric layer during the formation of a semiconductor device to surround the intermediate stage between the plurality of lower plugs and the plurality of barrier layers.

[0033] Figure 20 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure during the formation of a plurality of landing pads on the plurality of lower emboli and the plurality of barrier layers.

[0034] Figure 21 This is a cross-sectional schematic diagram illustrating an intermediate stage in the removal of the first dielectric layer during the formation of a semiconductor device according to some embodiments of the present disclosure.

[0035] Figure 22 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0036] Figure 23 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in which a second dielectric layer is deposited during the formation of a semiconductor element to create an air gap in the intermediate stage between the plurality of lower plugs.

[0037] Figure 24This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure where a sacrificial dielectric layer is formed during the formation of a semiconductor device, and the sacrificial dielectric layer has an intermediate stage in which multiple openings are exposed to expose multiple gate stacks.

[0038] Figure 25 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of multiple barrier layers and multiple lower plugs in the multiple openings during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0039] Figure 26 This is a cross-sectional schematic diagram illustrating an intermediate stage in the removal of the sacrificial dielectric layer during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0040] Figure 27 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure of forming a first dielectric layer during the formation of a semiconductor device to surround the intermediate stage between the plurality of gate structures and the plurality of barrier layers.

[0041] Figure 28 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure during the formation of a plurality of landing pads on the plurality of gate structures and the plurality of barrier layers.

[0042] Explanation of reference numerals in the attached figures:

[0043] 30: Preparation method

[0044] 50: Preparation method

[0045] 70: Preparation method

[0046] 100: Semiconductor components

[0047] 101: Semiconductor substrate

[0048] 133: Lower embolization

[0049] 133LS: Lower sidewall

[0050] 133T: Upper surface

[0051] 133US: Upper sidewall

[0052] 135: Dielectric layer

[0053] 137: Landing mat

[0054] 140: Opening

[0055] 143: Dielectric layer

[0056] 150: Air gap

[0057] 150T: Surface

[0058] 153: Upper embolization

[0059] 200: Semiconductor components

[0060] 201: Semiconductor substrate

[0061] 203: Gate layer

[0062] 205a: Gate stack

[0063] 205b: Gate Stack

[0064] 207: Internal insulation structure

[0065] 209: Internal spacer

[0066] 211: External insulation structure

[0067] 213: Semiconductor Materials

[0068] 220: Air gap

[0069] 233: Gate structure

[0070] 233LS: Lower sidewall

[0071] 233T: Upper surface

[0072] 233US: Upper sidewall

[0073] 235: Dielectric layer

[0074] 237: Landing mat

[0075] 243: Dielectric layer

[0076] 253: Embolism

[0077] 300: Semiconductor components

[0078] 301: Semiconductor substrate

[0079] 323: Sacrificial Dielectric Layer

[0080] 330: Opening

[0081] 331: Barrier Layer

[0082] 331LS: Lower sidewall

[0083] 331T: Upper surface

[0084] 331US: Upper sidewall

[0085] 333: Subcutaneous embolization

[0086] 333LS: Lower sidewall

[0087] 333T: Upper surface

[0088] 333US: Upper sidewall

[0089] 335: Dielectric layer

[0090] 337: Landing mat

[0091] 337a: Internal

[0092] 337b: External

[0093] 340: Opening

[0094] 343: Dielectric layer

[0095] 350: Air gap

[0096] 353: Upper embolization

[0097] 400: Semiconductor Components

[0098] 401: Semiconductor substrate

[0099] 403: Gate layer

[0100] 405a: Gate Stack

[0101] 405b: Gate Stack

[0102] 407: Internal insulation structure

[0103] 411: External insulation structure

[0104] 413: Semiconductor Materials

[0105] 420: Air gap

[0106] 431: Barrier Layer

[0107] 433: Gate structure

[0108] 435: Dielectric layer

[0109] 437: Landing mat

[0110] 437a: Internal

[0111] 437b: external

[0112] 443: Dielectric layer

[0113] 453: Embolism

[0114] D1: Distance

[0115] D2: Distance

[0116] D3: Distance

[0117] D4: Distance

[0118] D5: Distance

[0119] D6: Distance

[0120] D7: Distance

[0121] D8: Distance

[0122] S11: Steps

[0123] S13: Steps

[0124] S15: Steps

[0125] S17: Steps

[0126] S19: Steps

[0127] S21: Steps

[0128] S31: Steps

[0129] S33: Steps

[0130] S35: Steps

[0131] S37: Steps

[0132] S39: Steps

[0133] S41: Steps

[0134] S51: Steps

[0135] S53: Steps

[0136] S55: Steps

[0137] S57: Steps

[0138] S59: Steps

[0139] S61: Steps

[0140] S63: Steps

[0141] S65: Steps

[0142] S67: Steps

[0143] W1: Width

[0144] W2: Width

[0145] W3: Width

[0146] W4: Width

[0147] W5: Width

[0148] W6: Width

[0149] W7: Width

[0150] W8: Width

[0151] W9: Width

[0152] W10: Width Detailed Implementation

[0153] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0154] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0155] Figure 1 This is a cross-sectional schematic diagram illustrating a semiconductor element 100 according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 100 includes a semiconductor substrate 101; a plurality of lower plugs 133 disposed on the semiconductor substrate 101; a plurality of landing pads 137 disposed on the plurality of lower plugs 133; and a plurality of upper plugs 153 disposed on the plurality of landing pads 137. In some embodiments, the plurality of upper plugs 153 are electrically connected to the plurality of lower plugs 133 via the plurality of landing pads 137. Furthermore, the semiconductor element 100 includes a dielectric layer 143 (also represented as an interlayer metal dielectric (IMD) layer) disposed on the semiconductor substrate 101.

[0156] In some embodiments, the plurality of lower thrombees 133, the plurality of landing pads 137, and the plurality of lower thrombees 153 are disposed within a dielectric layer 143. In other words, the plurality of lower thrombees 133, the plurality of landing pads 137, and the plurality of upper thrombees 153 are surrounded by the dielectric layer 143. Furthermore, the dielectric layer 143 includes an air gap 150 disposed between adjacent lower thrombees 133. In some embodiments, the air gap 150 is surrounded by the dielectric layer 143. Additionally, it should be understood that in some embodiments, the plurality of landing pads 137 are disposed on each of the upper surfaces and upper sidewalls of the plurality of lower thrombees 133. In some embodiments, each of the upper surfaces and upper sidewalls of the plurality of lower thrombees 133 is covered by and in direct contact with the plurality of landing pads 137.

[0157] Figure 2 This is a cross-sectional schematic diagram illustrating a semiconductor element 200 according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 200 includes a semiconductor substrate 201 that has been patterned to form a plurality of gate stacks 205a, 205b. At least one of the plurality of gate stacks 205a, 205b has a plurality of interleaved stacked semiconductor layers (semiconductor substrate 201) and a gate layer 203.

[0158] In some embodiments, the semiconductor element 200 also includes an inner insulating structure 207 disposed between the gate stacks 205a and 205b; and a plurality of outer insulating structures 211 disposed on each side of the plurality of gate stacks 205a and 205b, opposite to each sidewall of the inner insulating structure 207. In some embodiments, the semiconductor element 200 further includes a semiconductor material 213 disposed on the inner insulating structure 207 and the outer insulating structures 211, and the portion of the semiconductor material 213 between the plurality of gate stacks 205a and 205b includes an air gap 220. In some embodiments, the air gap 220 is surrounded by the semiconductor material 213.

[0159] In some embodiments, the upper surface of the semiconductor material 213 is substantially flush with the upper surface of the semiconductor substrate 201 (e.g., the upper surfaces of the plurality of gate stacks 205a, 205b). In this disclosure, the term "substantially" means preferably 90%, more preferably 95%, even more preferably 98%, and most preferably 99%. Furthermore, the semiconductor element 200 also includes a plurality of internal spacers 209 stacked between the plurality of semiconductor layers (semiconductor substrate 201) of the plurality of gate stacks 205a, 205b, and adjacent to opposite sides of the plurality of gate layers 203.

[0160] Please refer to the following: Figure 2According to some embodiments, the semiconductor element 200 includes a plurality of gate structures 233 disposed on at least one of the plurality of gate stacks 205a, 205b; and a dielectric layer 235 (also referred to as an IMD layer) disposed on the gate stacks 205a, 205b and the semiconductor material 213, and surrounding the plurality of gate structures 233. It should be understood that the upper portion of each of the plurality of gate structures 233 protrudes from the dielectric layer 235. In some embodiments, the upper surfaces and upper sidewalls of each of the plurality of gate structures 233 protrude from (or are not covered by) the dielectric layer 235.

[0161] In some embodiments, the semiconductor element 200 includes a plurality of landing pads 237 disposed on the plurality of gate structures 233; and a plurality of plugs 253 (also referred to as a plurality of upper plugs) disposed on the plurality of landing pads 237. In some embodiments, the plurality of plugs 253 are electrically connected to the plurality of gate structures 233 via the landing pads 237. Furthermore, the semiconductor element 200 includes a dielectric layer 243 (also referred to as an IMD layer) disposed on the dielectric layer 235. In some embodiments, the plurality of gate structures 233, the plurality of landing pads 237, and the plurality of plugs 253 are disposed within the dielectric layer 243. In other words, the plurality of gate structures 233, the plurality of landing pads 237, and the plurality of plugs 253 are surrounded by the dielectric layer 243.

[0162] Figure 3 This is a cross-sectional schematic diagram illustrating a semiconductor element 300 according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 300 includes a semiconductor substrate 301; a plurality of lower plugs 333 and a plurality of barrier layers 331 disposed on the semiconductor substrate 301; a plurality of landing pads 337 disposed on the plurality of lower plugs 333 and the plurality of barrier layers 331; and a plurality of upper plugs 353 disposed on the plurality of landing pads 337. In some embodiments, the plurality of upper plugs 353 are electrically connected to the plurality of lower plugs 333 via the landing pads 337. Furthermore, the semiconductor element 300 includes a dielectric layer 343 (also referred to as an IMD layer) disposed on the semiconductor substrate 301.

[0163] In some embodiments, the plurality of lower plugs 333 are disposed on the plurality of barrier layers 331, and at least one of the barrier layers 331 extends to surround the corresponding lower plug 333. In other words, the plurality of barrier layers 331 cover each lower surface and each sidewall of the plurality of lower plugs 333. Furthermore, at least one of the plurality of landing pads 337 includes a plurality of outer surfaces 337b and an inner surface 337a, with the inner surface 337a disposed between the plurality of outer surfaces 337b. It should be understood that each inner surface 337a of the plurality of landing pads 337 is disposed on the plurality of lower plugs 333, and each outer surface 337b of the plurality of landing pads 337 is disposed on the plurality of barrier layers 331. In some embodiments, the plurality of inner surfaces 337a directly contact each upper surface of the plurality of plugs 333, and the plurality of outer surfaces 337b directly contact each upper surface and each upper sidewall of the plurality of barrier layers 331.

[0164] In some embodiments, the plurality of lower thrombi 333, the plurality of landing pads 337, and the plurality of upper thrombi 353 are disposed within a dielectric layer 343. In other words, the plurality of lower thrombi 333, the plurality of landing pads 337, and the plurality of upper thrombi 353 are surrounded by a dielectric layer 343. Furthermore, the dielectric layer 343 includes an air gap 353 disposed between adjacent lower thrombi 333 (e.g., adjacent barrier layers 331). In some embodiments, the air gap 353 is surrounded by the dielectric layer 343. In some embodiments, the plurality of upper thrombi 353 are separated from the plurality of outer surfaces 337b of the plurality of landing pads 337 by a portion of the dielectric layer 343. However, in some embodiments, the plurality of upper thrombi 353 directly contact the plurality of outer surfaces 337b of the plurality of landing pads 337.

[0165] Figure 4 This is a cross-sectional schematic diagram illustrating a semiconductor element 400 according to some embodiments of the present disclosure. Similar to... Figure 2 The semiconductor element 200 and semiconductor element 400 include a semiconductor substrate 401, which has been patterned to form a plurality of gate stacks 405a, 405b. At least one of the plurality of gate stacks 405a, 405b has a plurality of interleaved stacked semiconductor layers (semiconductor substrate 401) and a gate layer 403.

[0166] In some embodiments, the semiconductor element 400 also includes an inner insulating structure 407 disposed between the plurality of gate stacks 405a, 405b; and a plurality of outer insulating structures 411 disposed on each side of the plurality of gate stacks 405a, 405b, opposite to each side of the inner insulating structure 407. In some embodiments, the semiconductor element 400 further includes a semiconductor material 413 disposed on the inner insulating structure 407 and the plurality of outer insulating structures 411, and the portion of the semiconductor material 413 between the plurality of gate stacks 405a, 405b includes an air gap 420. In some embodiments, the air gap 420 is surrounded by the semiconductor material 413.

[0167] In some embodiments, the upper surface of the semiconductor material 413 is substantially flush with the upper surface of the semiconductor substrate 401 (e.g., the upper surfaces of the plurality of gate stacks 405a, 405b). Furthermore, the semiconductor element 400 also includes a plurality of internal spacers 409 stacked between the plurality of semiconductor layers (semiconductor substrate 401) of the plurality of gate stacks 405a, 405b, and adjacent to the opposite side of the plurality of gate layers 403.

[0168] Please refer to the following: Figure 4 According to some embodiments, a semiconductor device 400 includes a plurality of gate structures 433 and a plurality of barrier layers 431 disposed on at least one of the plurality of gate stacks 405a, 405b; and a dielectric layer 435 (also referred to as an IMD layer) disposed on the plurality of gate stacks 405a, 405b and semiconductor material 413 and surrounding the plurality of gate structures 433. In some embodiments, the plurality of gate structures 433 are disposed on the plurality of barrier layers 431, and at least one of the plurality of barrier layers 431 extends to surround the corresponding gate structure 433. In other words, the plurality of barrier layers 431 cover each lower surface and each sidewall of the plurality of gate structures 433. Furthermore, it should be understood that each upper portion of the plurality of gate structures 433 and barrier layers 431 protrudes from the dielectric layer 435. In some embodiments, the upper surfaces and upper sidewalls of the plurality of gate structures 433 and the upper surfaces and upper sidewalls of the plurality of barrier layers 431 protrude from the dielectric layer 435 (or are not covered).

[0169] In some embodiments, the semiconductor element 400 includes a plurality of landing pads 437 disposed on the plurality of gate structures 433 and the plurality of barrier layers 431; and a plurality of plugs 453 (also represented as a plurality of upper plugs) disposed on the plurality of landing pads 437. In some embodiments, the plurality of plugs 453 are electrically connected to the plurality of gate structures 433 via the plurality of landing pads 437. In some embodiments, at least one of the plurality of landing pads 437 includes a plurality of outer surfaces 437b and an inner surface 437a, with the inner surface 437a disposed between the plurality of outer surfaces 437b. It should be understood that each inner surface 437a of the plurality of landing pads 437 is disposed on the plurality of gate structures 433, and each outer surface 437b of the plurality of landing pads 437 is disposed on the plurality of barrier layers 431. In some embodiments, the plurality of inner surfaces 437a directly contact the upper surfaces of the plurality of gate structures 433, and the plurality of outer surfaces 437b directly contact the upper surfaces and upper sidewalls of the plurality of barrier layers 431.

[0170] Furthermore, the semiconductor element 400 includes a dielectric layer 443 (also referred to as an IMD layer) disposed on the dielectric layer 435. In some embodiments, the plurality of gate structures 433, the plurality of landing pads 437, and the plurality of plugs 453 are disposed within the dielectric layer 443. In other words, the plurality of gate structures 433, the plurality of landing pads 437, and the plurality of plugs 453 are surrounded by the dielectric layer 443. In some embodiments, the plurality of plugs 543 are separated from the plurality of outer surfaces 437b of the plurality of landing pads 437 by a portion of the dielectric layer 443. However, in some embodiments, the plurality of plugs 453 directly contact the plurality of outer surfaces 437b of the plurality of landing pads 437.

[0171] Figure 5 This is a flowchart illustrating semiconductor elements (e.g., according to some embodiments of this disclosure) Figure 1 The method 10 for preparing a semiconductor element 100 includes steps S11, S13, S15, S17, S19 and S21. Figure 5 Steps S11 to S21 will be described in detail with reference to the following figures.

[0172] Figures 6 to 10 This is a cross-sectional view illustrating the intermediate processes during the formation of semiconductor device 100. For example... Figure 6As shown, the semiconductor substrate 101 may be part of an integrated circuit (IC) chip, which includes various passive and active electronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), side-diffused MOS (LSMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC components, or combinations thereof.

[0173] Depending on the IC manufacturing stage, the semiconductor substrate 101 may include various material layers (e.g., dielectric layers, semiconductor layers, and / or conductive layers) configured to form IC features (e.g., doped regions, insulating features, gate features, source / drain features, interconnect features, other features, or combinations thereof). For clarity, the semiconductor substrate 101 has been simplified. It should be understood that additional features may be added to the semiconductor substrate 101, and in other embodiments, some features as described below may be replaced, modified, or removed.

[0174] like Figure 6 As shown, according to some embodiments, the plurality of lower plugs 133 are formed on the semiconductor substrate 101. The corresponding steps are described in the following... Figure 5 Step S11 of the fabrication method 10 shown. In some embodiments, the plurality of lower plugs 133 comprise a conductive material, such as copper. In some embodiments, at least one of the plurality of lower plugs 133 has a lower width W1 and an upper width W2, wherein the lower width W1 is greater than the upper width W2. In some embodiments, there is a distance D1 between the upper portions of adjacent lower plugs 133. In some embodiments, the plurality of lower plugs 133 have a tapered profile that tapers gradually from the semiconductor substrate 101.

[0175] Next, as Figure 7 As shown, according to some embodiments, a dielectric layer 135 is formed to surround the lower portions of each of the plurality of lower plugs 133 and expose the upper portions of each of the plurality of lower plugs 133. The corresponding steps are described in the following... Figure 5Step S13 of the fabrication method 10 shown. In some embodiments, the dielectric layer 135 comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon oxynitride, silicon carbonitride, silicon oxycarbonitride, or the like. The fabrication technique of the dielectric layer 135 may include depositing a dielectric material (not shown) on the semiconductor substrate 101 and the plurality of lower plugs 133 by a deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a physical vapor deposition (PVD) process; and removing the upper portion of the dielectric layer 135 by a chemical mechanical polishing (CMP) process or an etch-back process.

[0176] After the upper portion of dielectric layer 135 is removed, the upper portions of each of the plurality of lower plugs 133 protrude from dielectric layer 135. In some embodiments, according to certain examples, the upper surfaces 133T and upper sidewalls 133US of each of the plurality of lower plugs 133 protrude and are exposed, while the lower sidewalls 133LS of each of the plurality of lower plugs 133 are covered by dielectric layer 135.

[0177] Next, as Figure 8 As shown, according to some embodiments, a heat treatment process is performed to form a plurality of landing pads 137 on each of the upper surfaces 133T and upper sidewalls 133US of the plurality of lower plugs 133. The corresponding steps are described in... Figure 5 Step S15 of the preparation method 10 shown. In some embodiments, during a heat treatment process, a silicon-containing gas is used to selectively form the plurality of landing pads 137 on the plurality of exposed upper surfaces 133T and the plurality of exposed upper sidewalls 133US of the plurality of lower plugs 133. In some embodiments, the plurality of landing pads 137 comprise copper germanide (Cu3Ge). Because the plurality of landing pads 137 provide an increased landing area for the plurality of upper plugs subsequently formed thereon, misalignment problems between the plurality of upper plugs and lower plugs 133 subsequently formed can be avoided or reduced.

[0178] like Figure 9 As shown, according to some embodiments, after the plurality of landing pads 137 are formed, the dielectric layer 135 is removed to form an opening 140 between adjacent lower plugs 137. The corresponding steps are described in the following... Figure 5 Step S17 of the preparation method 10 shown. In some embodiments, the dielectric layer 135 is removed by a stripping process (e.g., a wet stripping process) and / or an ashing process (e.g., a plasma ashing process). Once the dielectric layer 135 is removed, the lower sidewalls 133LS of the plurality of lower plugs 133 are exposed.

[0179] Next, as Figure 10 As shown, according to some embodiments, dielectric layer 143 is deposited on Figure 9 Structurally, and due to an overhang effect, an air gap 150 is formed in an opening 140 between adjacent lower plugs 133. In some embodiments, a dielectric layer 143 is deposited on the semiconductor substrate 101, the plurality of lower plugs 133, and the plurality of landing pads 137, and the opening 140 (see reference) Figure 9 The dielectric layer 143 is partially filled. The corresponding steps are explained in the following... Figure 5 Step S19 of the preparation method 10 shown. In some embodiments, the plurality of exposed lower sidewalls 133LS of the plurality of lower plugs 133 are covered by a dielectric layer 143.

[0180] Furthermore, in some embodiments, an air gap 150 is formed beneath the plurality of landing pads 137 and surrounded by a dielectric layer 143. In some embodiments, the upper surfaces 133T of each of the plurality of lower plugs 133 are higher than the uppermost surface 150T of the air gap 150. Some materials and processes used to form the dielectric layer 143 are similar to or the same as those used to form the dielectric layer 135, and will not be described in detail again herein. Because of the air gap 150 between the plurality of lower plugs 133, the parasitic capacitance between the plurality of lower plugs 133 can be reduced.

[0181] Please refer back to this page. Figure 1 According to some embodiments, after the dielectric layer 143 is formed, a plurality of upper plugs 153 are formed in the dielectric layer 143 and on the plurality of landing pads 137. The corresponding steps are described in... Figure 5 Step S21 in the preparation method 10 shown. In some embodiments, the plurality of upper plugs 153 comprise a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, gold, silver, or a combination thereof.

[0182] Furthermore, the fabrication technique for the plurality of upper plugs 153 may include etching the dielectric layer 143 to form a plurality of openings (not shown) to expose the corresponding landing pads 137; depositing a conductive material (not shown) in the plurality of openings and on the dielectric layer 143; and planarizing the conductive material so that the remaining upper surfaces of the conductive material (e.g., the plurality of upper plugs 153) are substantially flush with the upper surface of the dielectric layer 143. After the plurality of upper plugs 153 are formed, a semiconductor device 100 is obtained. Please refer to... Figure 1 and Figure 6 At least one of the widths W1 and W2 of the lower plug 133 is greater than the width W3 of the upper plug 153, and the distance D2 between adjacent upper plugs 153 is greater than the distance between adjacent lower plugs 133.

[0183] Figure 11 This is a flowchart illustrating semiconductor elements (e.g., according to some embodiments of this disclosure) Figure 2 The method 30 for preparing a semiconductor element 200 includes steps S31, S33, S35, S37, S39 and S41. Figure 11 Steps S31 to S41 are described in detail with reference to the following figures.

[0184] Figures 12 to 14 This is a cross-sectional view illustrating the intermediate processes during the formation of semiconductor device 200. For example... Figure 12 As shown, according to some embodiments, a patterned semiconductor substrate 201 is used to form gate stacks 205a and 205b, and the plurality of gate structures 233 are formed on the gate stacks 205a and 205b.

[0185] The semiconductor substrate 201 may be a semiconductor wafer, such as a silicon wafer. Additionally, the semiconductor substrate 201 may comprise elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and gallium arsenide phosphide (GaInAsP).

[0186] In some embodiments, the semiconductor substrate 201 includes an epitaxial layer. For example, the semiconductor substrate 201 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 201 is a semiconductor-on-insulator (SOI) substrate, which may include a substrate, a buried oxide layer, and a semiconductor layer, wherein the buried oxide layer is located on the substrate, the semiconductor layer is located on the buried oxide layer, and the SOI substrate is, for example, a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SOI substrate can be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other applicable methods.

[0187] The plurality of semiconductor layers (semiconductor substrates 201) and the plurality of gate layers 203 are stacked alternately in gate stacks 205a and 205b, and a plurality of internal spacers 209 are formed on opposite sides of the plurality of gate layers 203 and sandwiched between the plurality of semiconductor layers (semiconductor substrates 201) in gate stacks 205a and 205b. In some embodiments, the plurality of internal spacers 209 comprise silicon oxide, silicon nitride, or other applicable dielectric materials. The fabrication technique of the plurality of internal spacers 209 may include laterally recessing the plurality of gate layers 203 to form a plurality of air gaps between the plurality of semiconductor layers (semiconductor substrates 201) in gate stacks 205a and 205b; depositing a dielectric material in the plurality of air gaps; and removing excess portions of the dielectric material outside the plurality of air gaps.

[0188] Some of the materials and processes used to form the inner insulating structure 207 and the plurality of outer insulating structures 211 are similar to those used to form the plurality of inner spacers 209, and their detailed description will not be repeated herein. Furthermore, due to the high aspect ratio of the aperture between the gate stacks 205a and 205b, semiconductor material 213 is formed on the inner insulating structure 207 and the plurality of outer insulating structures 211, and an air gap 220 is formed on the inner insulating structure 207. In some embodiments, the air gap 220 is surrounded by semiconductor material 213.

[0189] Semiconductor material 213 can be any suitable material, including, but not limited to, silicon (Si) or silicon germanium (SiGe). The fabrication technique for semiconductor material 213 may include a deposition process, such as a CVD process, an ALD process, or a PVD process. The fabrication technique for semiconductor material 213 may include a deposition process followed by a planarization process (e.g., a CMP process). After semiconductor material 213 is formed, the plurality of gate structures 233 are formed on gate stacks 205a and 205b. The corresponding steps are described in the following... Figure 11 Steps S31 and S33 in the preparation method 30 shown.

[0190] In some embodiments, the plurality of gate structures 233 comprises a conductive material, such as copper. In some embodiments, at least one of the plurality of gate structures 233 has a width W4. In some embodiments, there is a distance D3 between the upper portions of adjacent gate structures 233. It should be understood that the parasitic capacitance between the gate stacks 205a and 205b can be reduced due to the air gap 220 between the gate stacks 205a and 205b.

[0191] Next, as Figure 13 As shown, according to some embodiments, a dielectric layer 235 is formed to surround and expose the upper portions of each of the plurality of gate structures 233. The corresponding steps are described in the following... Figure 11 Step S35 of the fabrication method 30 shown. In some embodiments, the dielectric layer 235 comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon oxynitride, silicon oxynitride, or the like. The fabrication technique of the dielectric layer 235 may include depositing a dielectric material (not shown) on the semiconductor material 213, the gate stacks 205a, 205b, and the plurality of gate structures 233 by a deposition process, such as a CVD process, an ALD process, or a PVD process; and removing the top portion of the dielectric layer 235 by a CMP process or an etch-back process.

[0192] After the upper portion of the dielectric layer 235 is removed, the upper portions of each of the plurality of gate structures 233 protrude from the dielectric layer 235. In some embodiments, according to certain examples, the upper surfaces 233T and upper sidewalls 233US of each of the plurality of gate structures 233 protrude and are exposed, while the lower sidewalls 233LS of each of the plurality of gate structures 233 are covered by the dielectric layer 235.

[0193] Next, as Figure 14 As shown, according to some embodiments, a heat treatment process is performed to form a plurality of landing pads 237 on each of the upper surfaces 233T and upper sidewalls 233US of the plurality of gate structures 233. The corresponding steps are described in... Figure 11Step S37 of the fabrication method 30 shown. In some embodiments, during a heat treatment process, a silicon-containing gas is used to selectively form the plurality of landing pads 237 on the plurality of exposed upper surfaces 233T and the plurality of exposed upper sidewalls 233US of the plurality of gate structures 233. In some embodiments, the plurality of landing pads 237 comprise copper germanide (Cu3Ge). Because the plurality of landing pads 237 provide an increased landing area for the plurality of upper plugs subsequently formed thereon, misalignment problems between the plurality of plugs subsequently formed and the plurality of gate structures 233 can be avoided or reduced.

[0194] Please refer back to this page. Figure 2 According to some embodiments, a dielectric layer 243 is formed on a dielectric layer 235 and covers the plurality of landing pads 237, and the plurality of plugs 253 are formed in the dielectric layer 243 and on the plurality of landing pads 237. The corresponding steps are described in the following... Figure 11 Steps S39 and S41 in the preparation method 30 shown. Some materials and processes used to form dielectric layer 243 are similar to or the same as those used to form dielectric layer 235, and their detailed descriptions will not be repeated herein. In some embodiments, the plurality of plugs 253 comprise a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, gold, silver, or a combination thereof.

[0195] Furthermore, the fabrication technique for the plurality of plugs 253 may include etching the dielectric layer 243 to form a plurality of openings (not shown) to expose the corresponding landing pads 237; depositing a conductive material (not shown) in the plurality of openings and on the dielectric layer 243; and planarizing the conductive material so that the remaining conductive material (e.g., the plurality of plugs 253) is substantially flush with the upper surface of the dielectric layer 243. After the plurality of plugs 253 are formed, a semiconductor device 200 is obtained. Please refer to... Figure 2 and Figure 12 The width W4 of the gate structure 233 is greater than the width W5 of the plug 253, and the distance D4 between adjacent plugs 253 is greater than the distance D3 between adjacent gate stacks 205a and 205b.

[0196] Figure 15 This is a flowchart illustrating semiconductor elements (e.g., according to some embodiments of this disclosure) Figure 3 The method 50 for preparing a semiconductor element 300 includes steps S51, S53, S55, S57, S59, S61, S63, S65 and S67. Figure 15 Steps S51 to S67 are described in detail with reference to the following figures.

[0197] Figures 16 to 22 This is a cross-sectional view illustrating the intermediate processes during the formation of semiconductor device 300. For example... Figure 16 As shown, according to some embodiments, a sacrificial dielectric layer 323 having a plurality of openings 330 is formed on a semiconductor substrate 301. In some embodiments, the semiconductor substrate 301 is partially exposed through at least one of the plurality of openings 330. The corresponding steps are described in the following... Figure 15 Step S51 in the preparation method 50 shown.

[0198] Semiconductor substrate 301 may be similar to semiconductor substrate 101 as described above, and will not be described again herein. Sacrificial dielectric layer 323 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon oxynitride, silicon oxynitride, or the like. In some embodiments, the fabrication technique of sacrificial dielectric layer 323 includes depositing a dielectric material (not shown) on semiconductor substrate 301; and etching the dielectric material using an anisotropic etching process to form the plurality of openings 330, such that the plurality of openings 330 have a tapered profile that gradually tapers away from semiconductor substrate 301.

[0199] In some other embodiments, the fabrication technique of the sacrificial dielectric layer 323 includes forming a plurality of sacrificial patterns (not shown) on a semiconductor substrate 301; forming a sacrificial dielectric material (not shown) to surround the plurality of sacrificial patterns; planarizing the sacrificial dielectric material so that the upper surface of the remaining sacrificial dielectric material (e.g., the sacrificial dielectric layer 323) is substantially flush with the upper surfaces of the plurality of sacrificial patterns; and removing the plurality of sacrificial patterns.

[0200] Next, the plurality of barrier layers 331 are formed to line the lower surfaces and sidewalls of the plurality of openings 330, and the plurality of lower plugs 333 are formed on and surrounded by the plurality of barrier layers 331. The corresponding steps are described in the following... Figure 15 Steps S53 and S55 of the fabrication method 50 are shown. In some embodiments, the plurality of barrier layers 331 comprise a titanium-containing material, such as titanium or titanium nitride, and the plurality of lower plugs 333 comprise copper. The fabrication techniques for the plurality of barrier layers 331 and the plurality of lower plugs 333 may include multiple deposition processes, such as CVD, ALD, PVD, sputtering, or plating. After the plurality of deposition processes, a planarization process (e.g., a CMP process) may be performed to make the upper surfaces of the plurality of barrier layers 331 and the upper surfaces of the plurality of lower plugs 333 substantially flush with the upper surface of the sacrificial dielectric layer 323.

[0201] In some embodiments, at least one of the plurality of lower plugs 333 and the corresponding barrier layer 331 share a lower width W6 and an upper width W7, with the lower width W6 being greater than the upper width W7. That is, according to some embodiments, at least one of the plurality of lower plugs 333 and the corresponding barrier layer 331 share a tapered profile that tapers gradually from the direction away from the semiconductor substrate 101. Since the thickness of the plurality of barrier layers 331 is too small relative to the thickness of the plurality of lower plugs 333, the lower width of at least one of the plurality of lower plugs 333 may be approximately the same as the width W6, and the upper width of at least one of the plurality of lower plugs 333 may be approximately the same as the width W7. In other words, each lower width of the plurality of lower plugs 333 is greater than each upper width of the plurality of lower plugs 333, and at least one of the plurality of lower plugs 333 has a tapered profile that tapers gradually from the direction away from the semiconductor substrate 101.

[0202] Furthermore, in some embodiments, there is a distance D5 between the upper portions of adjacent barrier layers 331. Since the thickness of the plurality of barrier layers 331 is too small compared to the thickness of the plurality of lower plugs 333, the distance between adjacent lower plugs 333 is approximately the same as the distance D5.

[0203] like Figure 18 As shown, according to some embodiments, after the plurality of barrier layers 331 and the plurality of lower plugs 333 are formed, the sacrificial dielectric layer 323 is removed. The corresponding steps are described in the following... Figure 15 Step S57 in the preparation method 50 shown. In some embodiments, the sacrificial dielectric layer 323 is removed by a stripping process (e.g., a wet stripping process) and / or an ashing process (e.g., a plasma ashing process).

[0204] Next, as Figure 19 As shown, according to some embodiments, a dielectric layer 335 is formed to surround the lower portions of the plurality of lower plugs 333 and the plurality of barrier layers 331, and to expose the upper portions of the plurality of lower plugs 333 and the plurality of barrier layers 331. The corresponding steps are described in the following... Figure 15 Step S59 of the fabrication method 50 shown. Some materials and processes used to form the dielectric layer 335 are similar to or the same as those used to form the sacrificial dielectric layer 323, and their detailed descriptions will not be repeated here. The fabrication technique of the dielectric layer 335 includes depositing a dielectric material (not shown) on the semiconductor substrate 301, the plurality of lower plugs 333, and the plurality of barrier layers 331 by a deposition process, such as a CVD process, an ALD process, or a PVD process; and removing the upper part of the dielectric layer 335 by a CMP process or an etch-back process.

[0205] After the upper portion of dielectric layer 335 is removed, the upper portions of the plurality of lower plugs 333 and the upper portions of the plurality of barrier layers 331 protrude from dielectric layer 335. In some embodiments, according to some examples, the upper surfaces 333T and upper sidewalls 333US of the plurality of lower plugs 333 and the upper sidewalls 331US of the plurality of barrier layers 331 protrude (and / or are exposed), while the lower sidewalls 333LS of the plurality of lower plugs 333 and the lower sidewalls 331LS of the plurality of barrier layers 331 are covered by dielectric layer 335.

[0206] In some embodiments, the formation of dielectric layer 335 is omitted. In these examples, the sacrificial dielectric layer 323 is partially removed so that the lower portion of the remaining sacrificial dielectric layer 323 covers the lower sidewalls 331LS of the plurality of barrier layers 331 and the lower sidewalls 333LS of the plurality of lower plugs 333.

[0207] Then, as Figure 20 As shown, according to some embodiments, a heat treatment process is performed to form the plurality of landing pads 337 on the upper surfaces 333T and upper sidewalls 333US of the plurality of lower emboli 333 and on the upper surfaces 331T and upper sidewalls 331US of the plurality of barrier layers 331. The corresponding steps are described in the following... Figure 15 Step S61 in the preparation method 50 shown. In some embodiments, at least one of the plurality of landing pads 337 includes a plurality of outer surfaces 337b and an inner surface 337a, with the inner surface 337a disposed between the plurality of outer surfaces 337b.

[0208] In some embodiments, during a heat treatment process, a silicon-containing gas is used to selectively form the interiors 337a of the plurality of landing pads 337 on the plurality of exposed upper surfaces 333T of the plurality of lower emboli 333, and together form the exteriors 337b of the plurality of landing pads 337 on the plurality of exposed upper surfaces 331T and the plurality of upper sidewalls 331US of the plurality of barrier layers 331. In some embodiments, the plurality of interiors 337a and the plurality of exteriors 337b comprise different materials, but their simultaneous fabrication technique includes a heat treatment process. In some embodiments, the plurality of interiors 337a comprise tungsten silicide, while the plurality of exteriors 337b comprise titanium silicide. Because the plurality of landing pads 337 provide an increased landing area for the plurality of upper emboli subsequently formed thereon, misalignment problems between the plurality of upper emboli and lower emboli 333 subsequently formed can be avoided or reduced.

[0209] like Figure 21As shown, after the plurality of landing pads 337 are formed, the dielectric layer 335 is removed to form an opening 340 between adjacent lower plugs 337 (or between adjacent barrier layers 331 surrounding the plurality of lower plugs 337). The corresponding steps are described in the following... Figure 15 Step S63 of the fabrication method 50 shown. In some embodiments, the sacrificial dielectric layer 335 is removed by a stripping process (e.g., a wet stripping process) and / or an ashing process (e.g., a plasma ashing process). Once the dielectric layer 335 is removed, the lower sidewalls 331LS of the plurality of barrier layers 331 are exposed.

[0210] Next, as Figure 22 As shown, according to some embodiments, dielectric layer 343 is deposited on Figure 21 Structurally, and due to an overhang effect, an air gap 350 is formed in an opening 340 between adjacent lower plugs 333 (or between adjacent barrier layers 311). In some embodiments, a dielectric layer 343 is deposited on the semiconductor substrate 301, the plurality of lower plugs 333, the plurality of barrier layers 331, and the plurality of landing pads 337, and the opening 340 (see reference) Figure 21 The dielectric layer 343 partially fills the area. The corresponding steps are explained in the following... Figure 15 Step S65 of the fabrication method 50 shown. In some embodiments, the plurality of exposed lower sidewalls 331LS of the plurality of barrier layers 331 are covered by a dielectric layer 343.

[0211] Furthermore, in some embodiments, an air gap 350 is formed beneath the plurality of landing pads 337 and is surrounded by a dielectric layer 343. In some embodiments, the upper surfaces 333T of each of the plurality of lower plugs 333 are higher than the uppermost surface of the air gap 350. Some materials and processes used to form the dielectric layer 343 are similar to or the same as those used to form the dielectric layer 335, and their detailed descriptions will not be repeated herein. Because of the air gap 350 between the plurality of lower plugs 333, the parasitic capacitance between the plurality of lower plugs 333 can be reduced.

[0212] Please refer to Figure 3 According to some embodiments, after the dielectric layer 343 is formed, the plurality of upper plugs 353 are formed in the dielectric layer 343 and on the plurality of landing pads 337. The corresponding steps are described in... Figure 15 Step S67 of the preparation method 50 shown. In some embodiments, the plurality of upper plugs 353 comprise a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, gold, silver, or a combination thereof.

[0213] Furthermore, the fabrication technique for the plurality of upper plugs 353 may include etching the dielectric layer 343 to form a plurality of openings (not shown) to expose the corresponding landing pads 337; depositing a conductive material (not shown) in the plurality of openings and on the dielectric layer 343; and planarizing the conductive material so that the remaining upper surfaces of the conductive material (e.g., the plurality of upper plugs 353) are substantially flush with the upper surface of the dielectric layer 343. After the plurality of upper surfaces 353 are formed, a semiconductor device 300 is obtained. Please refer to... Figure 3 and Figure 17 The widths W6 and W7, at least one of which is greater than the width W8, and the distance from D6 is greater than the distance from D5.

[0214] Figure 23 This is a flowchart illustrating semiconductor elements (e.g., according to some embodiments of this disclosure) Figure 4 The semiconductor device 400) is prepared by a method 70, and the preparation method 70 includes steps S71, S73, S75, S77, S79, S81, S83, S85 and S87. Figure 23 Steps S71 to S87 are described in detail with reference to the following figures.

[0215] Figures 24 to 28 This is a cross-sectional view illustrating the intermediate processes during the formation of semiconductor device 400. For example... Figure 24 As shown, the semiconductor substrate 401, gate stacks 405a and 405b, the plurality of gate layers 403, the plurality of internal spacers 409, the internal insulating structure 407, the external insulating structure 411, and the semiconductor material 413 can be similar to the semiconductor substrate 201, gate stacks 205a and 205b, the plurality of gate layers 203, the plurality of internal spacers 209, the internal insulating structure 207, the external insulating structure 211, and the semiconductor material 213 of the semiconductor element 200, and their descriptions will not be repeated in the text.

[0216] Furthermore, in some embodiments, an air gap 420 is formed on the inner insulating structure 407 due to the high aspect ratio of the aperture between the gate stacks 405a and 405b. In some embodiments, the air gap 420 is surrounded by a semiconductor material 413. It should be understood that the presence of the air gap 420 between the gate stacks 405a and 405b reduces the parasitic capacitance between them.

[0217] like Figure 24 As shown, according to some embodiments, a sacrificial dielectric layer 423 having a plurality of openings 430 is formed on the semiconductor material 413 and the gate stacks 405a, 405b. In some embodiments, at least one of the gate stacks 405a, 405b is partially exposed through a corresponding opening 430. The corresponding steps are described in the following... Figure 23Steps S71 and S73 in the preparation method 70 shown.

[0218] The sacrificial dielectric layer 423 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon oxynitride, silicon oxynitride, or the like. In some embodiments, the fabrication technique of the sacrificial dielectric layer 423 includes depositing a dielectric material (not shown) on the semiconductor material 413 and the gate stacks 405a, 405b; and etching the dielectric material to form the plurality of openings 430. In some other embodiments, the fabrication technique of the sacrificial dielectric layer 423 includes forming a plurality of sacrificial patterns (not shown) on the semiconductor material 413 and the gate stacks 405a, 405b; forming a sacrificial dielectric material (not shown) around the plurality of sacrificial patterns; planarizing the sacrificial dielectric material so that the upper surface of the remaining sacrificial dielectric material (e.g., sacrificial dielectric layer 323) is substantially flush with the upper surfaces of the plurality of sacrificial patterns; and removing the plurality of sacrificial patterns.

[0219] Next, the plurality of barrier layers 431 are formed to line the lower surfaces and sidewalls of the plurality of openings 430, and the plurality of gate structures 433 are formed on and surrounded by the plurality of barrier layers 431. The corresponding steps are described in the following... Figure 23 Steps S75 and S77 of the fabrication method 70 are shown. In some embodiments, the plurality of barrier layers 431 comprise a titanium-containing material, such as titanium or titanium nitride, and the plurality of gate structures 433 comprise copper. The fabrication techniques for the plurality of barrier layers 431 and the plurality of gate structures 433 may include multiple deposition processes, such as CVD, ALD, PVD, sputtering, or plating. After the multiple deposition processes, a planarization process (e.g., a CMP process) may be performed to make the upper surfaces of the plurality of barrier layers 331 and the upper surfaces of the plurality of gate structures 433 substantially flush with the upper surface of the sacrificial dielectric layer 423.

[0220] In some embodiments, at least one of the plurality of gate structures 433 and the corresponding barrier layer 431 together have a width W9. Since the thickness of the plurality of barrier layers 431 is too small relative to the thickness of the plurality of gate structures 433, the width of at least one of the plurality of gate structures 433 may be approximately the same as the width W9. Furthermore, in some embodiments, there is a distance D7 between the upper portions of adjacent barrier layers 431. Since the thickness of the plurality of barrier layers 431 is too small relative to the thickness of the plurality of gate structures 433, the distance between adjacent gate structures 433 is approximately the same as the distance D7.

[0221] like Figure 26 As shown, according to some embodiments, after the plurality of barrier layers 431 and the plurality of gate structures 433 are formed, the sacrificial dielectric layer 423 is removed. The corresponding steps are described in the following... Figure 23Step S79 in the preparation method 70 shown. In some embodiments, the sacrificial dielectric layer 423 is removed by a stripping process (e.g., a wet stripping process) and / or an ashing process (e.g., a plasma ashing process).

[0222] Next, as Figure 27 As shown, according to some embodiments, a dielectric layer 435 is formed to surround the lower portions of each of the plurality of gate structures 433 and the plurality of barrier layers 431 and expose the upper portions of each of the plurality of gate structures 433 and the plurality of barrier layers 431. The corresponding steps are described in the following... Figure 23 Step S81 of the fabrication method 70 shown. Some materials and processes used to form the dielectric layer 435 are similar to or the same as those used to form the sacrificial dielectric layer 423, and their detailed descriptions will not be repeated here. The fabrication technique of the dielectric layer 435 includes depositing a dielectric material (not shown) on the semiconductor material 413 and the gate stacks 405a, 405b, on the plurality of gate structures 433 and the plurality of barrier layers 431 by a deposition process, such as a CVD process, an ALD process or a PVD process; and removing the top of the dielectric layer 435 by a CMP process or an etch-back process.

[0223] After the upper portion of the dielectric layer 435 is removed, the upper portions of each of the plurality of gate structures 433 and the upper portions of each of the plurality of barrier layers 431 protrude from the dielectric layer 435. In some embodiments, according to certain examples, the upper surfaces 433T and upper sidewalls 433US of each of the plurality of gate structures 433 and the upper surfaces 431T and upper sidewalls 431US of each of the plurality of barrier layers 431 protrude (and / or are exposed), while the lower sidewalls 433LS of each of the plurality of gate structures 433 and the lower sidewalls 431LS of each of the plurality of barrier layers 431 are covered by the dielectric layer 435.

[0224] In some embodiments, the formation of dielectric layer 435 is omitted. In these examples, the sacrificial dielectric layer 423 is partially removed so that the upper portion of the sacrificial dielectric layer 423 remains to cover the lower sidewalls 431LS of the plurality of barrier layers 431 and the lower sidewalls 433LS of the plurality of gate structures 433.

[0225] Then, as Figure 28 As shown, according to some embodiments, a heat treatment process is performed to form the plurality of landing pads 437 on each upper surface 433T and each upper sidewall 433US of the plurality of gate structures 433, and on each upper surface 431T and each upper sidewall 431US of the plurality of barrier layers 431. The corresponding steps are described in the following... Figure 23Step S83 in the preparation method 70 shown. In some embodiments, at least one of the plurality of landing pads 437 includes a plurality of outer surfaces 437b and an inner surface 437a, with the inner surface 437a disposed between the plurality of outer surfaces 437b.

[0226] In some embodiments, during a heat treatment process, a silicon-containing gas is used to selectively form the interiors 437a of the plurality of landing pads 437 on the plurality of exposed upper surfaces 433T of the plurality of gate structures 433, and together form the exteriors 437b of the plurality of landing pads 437 on the plurality of exposed upper surfaces 431T and the plurality of upper sidewalls 431US of the plurality of barrier layers 431. In some embodiments, the plurality of interiors 437a and the plurality of exteriors 437b comprise different materials, but their simultaneous fabrication techniques include a heat treatment process. In some embodiments, the plurality of interiors 437a comprise tungsten silicide, while the plurality of exteriors 437b comprise titanium silicide. Because the plurality of landing pads 437 provide an increased landing area for the plurality of upper plugs subsequently formed thereon, misalignment problems between the plurality of upper plugs and lower plugs 433 subsequently formed can be avoided or reduced.

[0227] Please refer back to this page. Figure 4 According to some embodiments, a dielectric layer 443 is formed on a dielectric layer 435 and covers the plurality of landing pads 437, while the plurality of plugs 453 are formed in the dielectric layer 443 and on the plurality of landing pads 437. The corresponding steps are described in... Figure 23 Steps S85 and S87 in the preparation method 70 shown. Some materials and processes used to form dielectric layer 443 are similar to or the same as those used to form dielectric layer 435, and their detailed descriptions will not be repeated herein. In some embodiments, the plurality of plugs 453 comprise a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, gold, silver, or a combination thereof.

[0228] Furthermore, the fabrication technique for the plurality of plugs 453 may include etching the dielectric layer 443 to form a plurality of openings (not shown) to expose the corresponding landing pads 437; depositing a conductive material (not shown) in the plurality of openings and on the dielectric layer 443; and planarizing the conductive material so that the remaining upper surfaces of the conductive material (e.g., the plurality of plugs 453) are substantially flush with the upper surface of the dielectric layer 443. After the plurality of plugs 453 are formed, a semiconductor device 400 is obtained. Please refer to... Figure 4 and Figure 25 Width W9 is greater than width W10, while distance D8 is greater than distance D7.

[0229] This disclosure provides several embodiments of semiconductor elements 100, 200, 300, 400 and methods for their fabrication. In some embodiments, at least one of the semiconductor elements 100, 200, 300, and 400 includes a plurality of conductive features (e.g., the plurality of lower plugs 133 of semiconductor element 100, the plurality of gate structures 233 of semiconductor element 200, the plurality of lower plugs 333 of semiconductor element 300, and the plurality of gate structures 433 of semiconductor element 400); a plurality of landing pads (e.g., the plurality of landing pads 137 of semiconductor element 100, the landing pads 237 of semiconductor element 200, the plurality of landing pads 337 of semiconductor element 300, and the landing pads 437 of semiconductor element 400) disposed on each upper surface and each upper sidewall of the plurality of conductive features; and a plurality of upper plugs (e.g., the plurality of upper plugs 153 of semiconductor element 100, the plurality of plugs 253 of semiconductor element 200, the plurality of lower plugs 353 of semiconductor element 300, and the plurality of plugs 453 of semiconductor element 400) disposed on the plurality of landing pads. The landing pad provides multiple increased landing areas for the multiple upper plugs to land on. Therefore, multiple misalignment problems between the upper plugs and the multiple conductive features can be avoided or reduced, and contact resistance can be reduced.

[0230] Furthermore, multiple air gaps are formed under the multiple landing pads and between the multiple conductive features (or between the multiple gate stacks under the multiple conductive features). For example, air gap 150 of semiconductor element 100 is formed between the multiple lower plugs 133, air gap 220 of semiconductor element 200 is formed between gate stacks 205a and 205b, air gap 350 of semiconductor element 300 is formed between the multiple lower plugs 333, and air gap 420 of semiconductor element 400 is formed between gate stacks 405a and 405b. Therefore, the parasitic capacitance between the multiple conductive features or the multiple gate stacks can be reduced. Therefore, the yield of semiconductor elements 100, 200, 300, and 400 can be improved, and the overall device performance can be improved.

[0231] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a first lower plug and a second lower plug disposed on a semiconductor substrate. The semiconductor device also includes a first landing pad disposed on an upper surface and upper sidewalls of the first lower plug; and a first upper plug disposed on the first landing pad and electrically connected to the first lower plug. The width of the first lower plug is greater than the width of the first upper plug. The semiconductor device further includes a dielectric layer disposed on the semiconductor substrate. The first lower plug, the second lower plug, the first landing pad, and the first upper plug are disposed within the dielectric layer, and the dielectric layer includes an air gap disposed between the first lower plug and the second lower plug.

[0232] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a first gate stack and a second gate stack disposed on a semiconductor substrate. One of the first gate stack and the second gate stack includes a plurality of gate layers, and an air gap is provided between the first gate stack and the second gate stack. The semiconductor device also includes a first gate structure and a second gate structure disposed on the first gate stack and the second gate stack, respectively; and a first dielectric layer surrounding each lower sidewall of the first gate structure and each lower sidewall of the second gate structure. The semiconductor device further includes a first landing pad disposed on an upper surface and each upper sidewall of the first gate structure; and a first plug disposed on the first landing pad and electrically connected to the first gate structure. A width of the first gate structure is greater than a width of the first plug. Furthermore, the semiconductor device includes a second dielectric layer disposed on the first dielectric layer. The first landing pad and the first plug are surrounded by the second dielectric layer.

[0233] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a first lower plug and a second lower plug on a semiconductor substrate; and forming a first dielectric layer surrounding the first lower plug and the second lower plug. An upper surface and upper sidewalls of the first lower plug and an upper surface and upper sidewalls of the second lower plug protrude from the first dielectric layer. The method also includes performing a heat treatment process to form a first landing pad on the upper surface and upper sidewalls of the first lower plug, and to form a second landing pad on the upper surface and upper sidewalls of the second lower plug; and after the heat treatment process, removing the first dielectric layer to form an opening between the first lower plug and the second lower plug. The preparation method further includes depositing a second dielectric layer in the opening and on the first and second landing pads to form an air gap in the opening and surrounded by the second dielectric layer; and forming a first upper plug in the second dielectric layer and on the first landing pad. The width of the first lower plug is greater than the width of the first upper plug.

[0234] One embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a first gate stack and a second gate stack on a semiconductor substrate. One of the first gate stack and the second gate stack includes a plurality of gate layers, and an air gap exists between the first gate stack and the second gate stack. The method also includes forming a first gate structure and a second gate structure on the first gate stack and the second gate stack, respectively; and forming a first dielectric layer surrounding the first gate structure and the second gate structure. An upper surface and upper sidewalls of the first gate structure and an upper surface and upper sidewalls of the second gate structure protrude from the first dielectric layer. The method further includes performing a thermal processing step to form a first landing pad on the upper surface and upper sidewalls of the first gate structure, and to form a second landing pad on the upper surface and upper sidewalls of the second gate structure. Furthermore, the method includes forming a second dielectric layer to cover the first landing pad and the second landing pad; and forming a first plug in the second dielectric layer and on the first landing pad. The width of the first gate structure is greater than the width of the first plug.

[0235] The various embodiments disclosed herein have several advantageous features. By forming a landing pad between a lower plug and an upper plug (or a gate structure and a plug in the gate structure), multiple misalignment problems can be avoided or reduced, thereby reducing contact resistance. Furthermore, by forming an air gap under the landing pad and between adjacent lower plugs (or between adjacent gate stacks), parasitic capacitance can be reduced. Therefore, the yield of the semiconductor device can be improved, and the overall device performance can be enhanced.

[0236] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0237] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A first lower plug and a second lower plug are disposed on a semiconductor substrate; A first landing pad is disposed on an upper surface and each upper sidewall of the first lower plug; A first upper embolism is disposed on the first landing pad and electrically connected to the first lower embolism, wherein a width of the first lower embolism is greater than a width of the first upper embolism; A dielectric layer is disposed on the semiconductor substrate, wherein the first lower embolism, the second lower embolism, the first landing pad, and the first upper embolism are disposed in the dielectric layer, wherein the dielectric layer includes an air gap disposed between the first lower embolism and the second lower embolism; and A first barrier layer covers a lower surface, each lower sidewall, and each upper sidewall of the first lower plug, wherein a portion of the first barrier layer is sandwiched between the first landing pad and the first lower plug. The first landing pad includes: An interior that covers the upper surface of the first lower plug; as well as Multiple exteriors cover the upper surfaces and upper sidewalls of the first barrier layer, wherein the interior and the multiple exteriors contain different materials.

2. The semiconductor device of claim 1, further comprising: A second landing pad is disposed on an upper surface and each upper sidewall of the second lower plug; as well as A second upper embolism is disposed on the second landing pad and electrically connected to the second lower embolism, wherein a distance between the first upper embolism and the second upper embolism is greater than a distance between the first lower embolism and the second lower embolism.

3. The semiconductor element of claim 1, wherein the lower width of the first lower plug is greater than the upper width of the first lower plug, and the upper width of the first lower plug is greater than the width of the first upper plug.

4. The semiconductor element of claim 1, wherein an upper surface of the first lower plug is higher than an uppermost surface of the air gap.

5. The semiconductor element of claim 1, wherein the first landing pad comprises copper germanide.

6. The semiconductor element of claim 1, wherein each of the plurality of outer upper surfaces of the first landing pad is higher than an inner upper surface of the first landing pad.

7. The semiconductor element of claim 1, wherein the interior of the first landing pad comprises tungsten silicide, and the plurality of exteriors of the first landing pad comprise titanium silicide.

8. A method for fabricating a semiconductor element, comprising: A first lower plug and a second lower plug are formed on a semiconductor substrate; A first dielectric layer is formed to surround the first lower plug and the second lower plug, wherein an upper surface and each upper sidewall of the first lower plug and an upper surface and each upper sidewall of the second lower plug protrude from the first dielectric layer; Perform a heat treatment process to form a first landing pad on the upper surface and each of the upper sidewalls of the first lower plug, and to form a second landing pad on the upper surface and each of the upper sidewalls of the second lower plug; After the heat treatment process, the first dielectric layer is removed to form an opening between the first lower plug and the second lower plug; A second dielectric layer is deposited in the opening and on the first and second landing pads to form an air gap in the opening and surrounded by the second dielectric layer; and A first upper plug is formed in the second dielectric layer and on the first landing pad, wherein the width of the first lower plug is greater than the width of the first upper plug.

9. The method for fabricating a semiconductor element as claimed in claim 8, further comprising forming a second upper plug in the second dielectric layer and on the second landing pad, wherein a distance between the first upper plug and the second upper plug is greater than a distance between the first lower plug and the second lower plug.

10. The method for fabricating a semiconductor element as claimed in claim 8, wherein a silicon-containing gas is used during the heat treatment process.

11. The method for preparing a semiconductor device as described in claim 8, further comprising: A sacrificial dielectric layer having a first opening and a second opening is formed on a semiconductor substrate; A first barrier layer and a second barrier layer are formed to respectively line the first opening and the second opening; The first lower embolism and the second lower embolism are respectively formed on the first barrier layer and the second barrier layer; and After the first and second lower plugs are formed, the sacrificial dielectric layer is removed.

12. The method for fabricating a semiconductor element as claimed in claim 11, wherein the first opening and the second opening have a tapered profile that gradually tapers away from the semiconductor substrate.

13. The method for fabricating a semiconductor element as claimed in claim 11, wherein the first landing pad comprises: A first interior that covers the upper surface of the first lower plug; as well as Multiple exteriors cover each upper surface and each upper sidewall of the first barrier layer, wherein each upper surface of the multiple exteriors is higher than one upper surface of the interior, and wherein the interior and the multiple exteriors are formed simultaneously through the heat treatment process.

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