A capacitor and chip

Abstract

This application provides a capacitor and a chip, relating to the field of chip design. The capacitor includes a substrate, a well region, a first polysilicon region, a second polysilicon region, an active region, and a capacitor body. The substrate is doped with a first type of ion. The well region is formed on the surface of the substrate and extends from the surface into the interior of the substrate, and is doped with a second type of ion. The first and second type ions have opposite polarities. The first and second polysilicon regions are deposited in portions above the well region, and the active region is implanted between two adjacent second polysilicon regions. The capacitor body is disposed above the first polysilicon region. Applying this capacitor to a chip can increase the density of the active region and polysilicon in the chip, thereby improving the chip's reliability.

Description

Technical Field

[0001] This application relates to the field of chip design, specifically to a capacitor and a chip. Background Technology

[0002] In semiconductor manufacturing, MIM capacitors are widely used in various integrated circuits because they can provide better frequency and temperature-dependent characteristics, reducing the difficulty and complexity of integration with CMOS front-end processes.

[0003] In the prior art, MIM capacitors mainly include a top metal layer, a first electrode plate, and a second electrode plate. The second electrode plate is disposed between the first electrode plate and the top metal layer, and is also connected to the top metal layer through a through-hole.

[0004] However, the application of such MIM capacitors in chips can affect the reliability of the chips. Summary of the Invention

[0005] In view of the above problems, embodiments of this application provide a capacitor and a chip that overcome or at least partially solve the problem that the application of MIM capacitors in chips affects the reliability of the chips.

[0006] According to a first aspect of the embodiments of this application, a capacitor is provided, comprising: a substrate, a well region, a first polysilicon region, a second polysilicon region, an active region, and a capacitor body. The substrate is doped with ions of a first type, and the well region is formed on the surface of the substrate and extends from the surface to the interior of the substrate. The well region is doped with ions of a second type, wherein the polarities of the first type ions and the second type ions are opposite. The first polysilicon region and the second polysilicon region are deposited in portions above the well region, and the active region is implanted between two adjacent second polysilicon regions. The capacitor body is disposed in the region above the first polysilicon region.

[0007] In this embodiment, the capacitor includes: a substrate, a well region, a first polysilicon region, a second polysilicon region, an active region, and a capacitor body. Applying this capacitor to a chip can increase the density of the active region and the density of polysilicon in the chip, thereby improving the chip's reliability.

[0008] In one alternative embodiment, the capacitor body includes a first plate, a second plate, and a top metal layer. The second plate is disposed between the first plate and the top metal layer, and the top metal layer is electrically connected to the second plate.

[0009] In one alternative embodiment, the capacitor further includes an isolation structure, which is a hollow structure, and the capacitor body is housed within the isolation structure.

[0010] In this embodiment, by setting an isolation structure, the etching accuracy of the capacitor can be improved, and unnecessary parasitic capacitance between the surrounding devices and the capacitor body can be reduced.

[0011] In one alternative embodiment, the isolation structure includes a first metal layer, a second polysilicon region connected to the first metal layer via a first contact hole, and an active region connected to the first metal layer via a second contact hole.

[0012] The active region and the polysilicon can be connected together through the first contact hole and the second contact hole, which reduces the trap resistance.

[0013] In one alternative approach, the sum of the areas of the first polycrystalline silicon region and the second polycrystalline silicon region is equal to the area of ​​the active region.

[0014] By using this capacitor in a chip, the area of ​​polysilicon in the region where the capacitor is located can be equal to the area of ​​the active region, thus making the ratio of polysilicon to active region in the chip more balanced and improving the chip's performance.

[0015] In one alternative approach, shallow trench isolation regions are formed below both the first polysilicon region and the second polysilicon region.

[0016] In one alternative embodiment, the isolation structure further includes a second metal layer, wherein the first metal layer in the isolation structure is connected to the second metal layer through a first via. The first metal layer and the first electrode plate are formed based on the same photomask, and the second metal layer and the top metal layer are formed based on the same photomask.

[0017] The first and second metal layers are formed on the sides of the capacitor body, which can surround the capacitor body from the side and enhance the overall noise immunity of the capacitor. Moreover, the first metal layer and the first electrode plate are formed on the same mask, and the second metal layer and the top metal layer are formed on the same mask, which can improve the etching accuracy of the capacitor and reduce the production cost of the capacitor.

[0018] In one alternative embodiment, the isolation structure further includes a second metal layer and a third metal layer. The first metal layer in the isolation structure is connected to the second metal layer through a first via, and the second metal layer is connected to the third metal layer through a second via. The second metal layer and the first electrode plate are formed based on the same photomask, and the third metal layer and the top metal layer are formed based on the same photomask.

[0019] The first, second, and third metal layers are all formed on the side of the capacitor body, which can surround the capacitor body from the side and enhance the overall noise immunity of the capacitor. Moreover, the second metal layer and the first electrode are formed on the same mask, and the third metal layer and the top metal layer are formed on the same mask. This not only improves the etching accuracy of the capacitor, but also allows the first electrode of the capacitor body to be farther away from the substrate below, reducing the parasitic capacitance generated between the first electrode and the substrate below.

[0020] In one alternative embodiment, the isolation structure further includes a fourth metal layer, the third metal layer being connected to the fourth metal layer via a third via, the fourth metal layer being higher than the top metal layer.

[0021] By placing the fourth metal layer above the top metal layer, the parasitic capacitance between other devices adjacent to the capacitor and the top metal layer can be reduced, as can the parasitic capacitance between other devices above the capacitor body and the top metal layer, thereby further enhancing the overall noise immunity of the capacitor.

[0022] In one alternative approach, the projection area of ​​the third metal layer onto the plane of the substrate is located within the projection area of ​​the fourth metal layer onto the plane of the substrate, and the area of ​​the projection area of ​​the fourth metal layer onto the plane of the substrate is greater than the area of ​​the projection area of ​​the third metal layer onto the plane of the substrate.

[0023] This allows the fourth metal layer to better surround the capacitor body, thereby enhancing the overall noise immunity of the capacitor.

[0024] In one alternative approach, the projection of the fourth metal layer onto the plane of the substrate and the projection of the capacitor body onto the plane of the substrate do not overlap.

[0025] In this way, the fourth metal layer will not be located directly above the capacitor body, which enhances the overall noise immunity of the capacitor and greatly reduces the parasitic capacitance between the top metal layer and the fourth metal layer.

[0026] In one alternative approach, the first type is P-type and the second type is N-type.

[0027] In one alternative approach, the first type is N-type and the second type is P-type.

[0028] A second aspect of this application also provides a chip, including the capacitor provided in the first aspect of this application.

[0029] The chip provided in this application increases the density of the active region and the density of polysilicon in the area where the capacitor is located, thereby improving the chip's reliability.

[0030] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of a polysilicon and active region disposed below the capacitor body, provided in an embodiment of this application.

[0033] Figure 2 This is a cross-sectional schematic diagram of a capacitor provided in an embodiment of this application.

[0034] Explanation of reference numerals in the attached figures:

[0035] 01. Substrate; 02. Well region; 03. First polysilicon region; 04. Second polysilicon region; 05. Active region; 06. First metal layer; 07. Second contact hole; 08. Shallow trench isolation region; 09. First electrode plate; 10. Top metal layer; 11. Second electrode plate; 12. Metal via; 13. Second metal layer; 14. First via; 15. Third metal layer; 16. Second via; 17. Fourth metal layer; 18. Third via. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0038] The terms "comprising" and "having," and any variations thereof, used in the specification, claims, and drawings of this application are intended to cover without excluding other meanings. The words "a" or "an" do not exclude the presence of multiples.

[0039] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0040] The directional terms appearing in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of the capacitor and chip of this application. For example, in the description of this application, terms such as "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the figures. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0041] Furthermore, the descriptions of directions such as the X direction, Y direction, and Z direction used to explain the operation and construction of the components of a capacitor and chip in this embodiment are not absolute but relative. Although these directions are appropriate when the components of the capacitor and chip are in the positions shown in the figure, they should be interpreted differently when these positions change to correspond to the changes.

[0042] Furthermore, the terms "first," "second," etc., in the specification and claims of this application or in the aforementioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0043] In the description of this application, unless otherwise stated, "multiple" means two or more (including two), and similarly, "multiple groups" means two or more (including two groups).

[0044] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, "connection" or "linkage" in mechanical structures can refer to a physical connection, such as a fixed connection, for example, a connection fixed by fasteners, such as a connection fixed by screws, bolts, or other fasteners; a physical connection can also be a detachable connection, such as a snap-fit ​​or interlocking connection; a physical connection can also be an integral connection, such as a connection formed by welding, bonding, or integral molding. In circuit structures, "connection" or "linkage" can refer not only to a physical connection but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is connected; it can also refer to the internal connection of two components. Signal connection can refer not only to signal connection through a circuit but also to signal connection through a media, such as radio waves. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0045] In the prior art, with the development of the semiconductor industry, capacitors are widely used in various integrated circuits. The inventors discovered that during chip manufacturing, it is necessary not only to achieve a certain ratio between the active region density and the polysilicon density throughout the entire chip, but also to achieve a certain ratio between the active region density and the polysilicon density in each specific area of ​​the chip. However, in areas where capacitors are located within the chip, the relatively large size of the capacitors results in lower active region density and polysilicon density in these areas, affecting the chip's reliability.

[0046] Therefore, some embodiments of this application provide a capacitor that, when applied in a chip, can improve the chip's reliability. Please refer to [reference needed] for details. Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of a polysilicon and active region disposed below the capacitor body, provided in an embodiment of this application. Figure 2 This is a cross-sectional schematic diagram of a capacitor provided in an embodiment of this application. The capacitor provided in this embodiment includes: a substrate 01, a well region 02, a first polysilicon region 03, a second polysilicon region 04, an active region 05, and a capacitor body. The substrate 01 is doped with a first type of ions. The well region 02 is formed on the surface of the substrate 01 and extends from the surface of the substrate 02 into the interior of the substrate 01. The well region 02 is doped with a second type of ions, the first type of ions having opposite polarities to the second type of ions. The first polysilicon region 03 and the second polysilicon region 04 are deposited in portions above the well region 02. The active region 05 is implanted between two adjacent second polysilicon regions 04. The capacitor body is disposed above the first polysilicon region 03.

[0047] For example, such as Figure 1 As shown, the active region 05 comprises four rectangular regions of the same shape, and the second polysilicon region 04 comprises four square regions of the same shape, smaller than the first polysilicon region 03. The internal region enclosed by the second polysilicon region 04 and the active region 05 is the first polysilicon region 03. Thus, both the polysilicon region below the capacitor and the region filled with the active region 05 are regularly shaped regions, facilitating the manufacturing process.

[0048] In practical applications, the first type of ions can be P-type ions, such as boron, gallium, and indium, or N-type ions, such as phosphorus and arsenic. The second type of ions can be either N-type or P-type ions. Specifically, if the first type is P-type ions, then substrate 01 is a P-type substrate; correspondingly, if the second type of ions is N-type ions, then well region 02 is an N-type well region. If the first type is N-type ions, then substrate 01 is an N-type substrate; correspondingly, if the second type of ions is P-type ions, then well region 02 is a P-type well region.

[0049] refer to Figure 2 The capacitor body includes a first electrode plate 09, a second electrode plate 11, and a top metal plate 10. The second electrode plate 11 is disposed between the first electrode plate 09 and the top metal plate 10. The top metal plate 10, the first electrode plate 09, and the second electrode plate 11 are all arranged parallel to each other, and the top metal plate 10 is electrically connected to the second electrode plate 11. For example, the top metal plate 10 is electrically connected to the second electrode plate 11 through a metal through-hole 12, and there can be multiple metal through-holes 12.

[0050] In this embodiment, the capacitor includes: a substrate 01, a well region 02, a first polysilicon region 03, a second polysilicon region 04, an active region 05, and a capacitor body. Applying this capacitor to a chip can increase the density of the active region 05 and the density of polysilicon in the chip, thereby improving chip reliability. Furthermore, filling the space between the capacitor body and the substrate 01 with polysilicon can effectively isolate noise coupling between the capacitor body and the substrate 01.

[0051] In practical applications, the inventors discovered that the chip's performance is not only related to the individual densities of polysilicon and active region 05, but also to the density ratio of polysilicon and active region 05.

[0052] Based on this, refer to Figure 1 Optionally, the area of ​​the active region 05 can occupy 30%-70% of the total area of ​​the layout. For example, the area of ​​the active region 05 can occupy 45% of the total area of ​​the layout. In this way, the ratio of the total polysilicon and the active region 05 located below the capacitor body can be more balanced.

[0053] In one alternative approach, the sum of the areas of the first polysilicon region 03 and the second polysilicon region 04 can be made equal to the area of ​​the active region 05. In this case, the area of ​​the active region 05 occupies 50% of the total area of ​​the layout.

[0054] In this way, the area of ​​the polysilicon located below the capacitor body can be equal to the area of ​​the active region 05. Furthermore, by using this capacitor in a chip, the area of ​​the polysilicon in the region where the capacitor is located in the chip can be equal to the area of ​​the active region 05, so that the ratio of polysilicon to active region 05 in the chip is balanced, thereby improving the performance of the chip.

[0055] In practical applications, shallow trench isolation regions 08 are formed below both the first polycrystalline silicon region 03 and the second polycrystalline silicon region 04.

[0056] In some embodiments, to reduce unnecessary parasitic capacitance between the capacitor's surrounding components and the capacitor body, the capacitor provided in this application may further include an isolation structure. The isolation structure is a hollow structure, and the capacitor body can be housed within the isolation structure.

[0057] In this embodiment, by setting an isolation structure, the etching accuracy of the capacitor can be improved, and unnecessary parasitic capacitance between the surrounding devices and the capacitor body can be reduced.

[0058] In the above embodiments, since the capacitor includes a well region 02, to prevent the well resistance from affecting the performance of the capacitor, the isolation structure provided in this embodiment may include a first metal layer 06. The second polysilicon region 04 is connected to the first metal layer 06 through a first contact hole, and the active region 05 is connected to the first metal layer 06 through a second contact hole 07. There may be multiple first and second contact holes 07.

[0059] It can be seen that by setting the first contact hole and the second contact hole 07, the active region 05 and the polysilicon can be connected together through the first metal layer, which can reduce the trap resistance.

[0060] In one embodiment, considering the potential influence of other devices on the capacitor, the isolation structure may further include a second metal layer 13 to improve the overall noise immunity of the capacitor. The first metal layer 06 in the isolation structure is connected to the second metal layer 13 through first vias 14, and there may be multiple first vias 14. The second metal layer 13 is higher than the first metal layer 06, and the projections of the first metal layer 06 onto the plane of the substrate 01 and the second metal layer 13 onto the plane of the substrate 01 can completely overlap. The first metal layer 06 and the first electrode 09 are formed based on the same mask, and the second metal layer 13 and the top metal layer 10 are formed based on the same mask.

[0061] At this time, the first metal layer 06 and the second metal layer 13 are formed on the side of the capacitor body, which can surround the capacitor body from the side and enhance the overall noise immunity of the capacitor. Moreover, the first metal layer 06 and the first electrode plate 09 are formed based on the same mask, and the second metal layer 13 and the top metal layer 10 are formed based on the same mask, which can improve the etching accuracy of the capacitor and reduce the production cost of the capacitor.

[0062] It is worth noting that the capacitor provided in the above embodiments includes a metal material below the capacitor body, and the first plate 09 of the capacitor also includes a metal material. Thus, parasitic capacitance that can adversely affect the performance of the capacitor can easily be generated between the two.

[0063] Therefore, in one alternative embodiment, the isolation structure may further include a second metal layer 13 and a third metal layer 15. The third metal layer 15 is higher than the second metal layer 13, and the projection of the third metal layer 15 onto the plane of the substrate 01 can completely coincide with the projection of the second metal layer 13 onto the plane of the substrate 01. The first metal layer 06 in the isolation structure is connected to the second metal layer 13 through a first via 14, and the second metal layer 13 is connected to the third metal layer 15 through a second via 16. Both the first via 14 and the second via 16 can be multiple. The second metal layer 13 and the first electrode plate 09 are formed based on the same mask, and the third metal layer 15 and the top metal layer 10 are formed based on the same mask. In this case, the second via 16 and the metal via 12 can be formed together.

[0064] The first metal layer 06, the second metal layer 13, and the third metal layer 15 are all formed on the side of the capacitor body, which can surround the capacitor body from the side and enhance the overall noise immunity of the capacitor. Moreover, the second metal layer 13 and the first electrode 09 are formed on the same mask, and the third metal layer 15 and the top metal layer 10 are formed on the same mask. While improving the etching accuracy of the capacitor, it can also make the first electrode 09 farther away from the substrate 01 below, reducing the parasitic capacitance formed between the first electrode 09 and the substrate 01 below.

[0065] In one alternative approach, refer to Figure 2 The isolation structure may further include a fourth metal layer 17, wherein the fourth metal layer 17 is higher than the third metal layer 15. The third metal layer 15 is connected to the fourth metal layer 17 through a third through-hole 18, and there may be multiple third through-holes 18. The fourth metal layer 17 is higher than the top metal layer 10.

[0066] By making the fourth metal layer 17 higher than the top metal layer 10, the parasitic capacitance between other devices adjacent to the capacitor and the top metal layer 10 can be reduced, as well as the parasitic capacitance between other devices higher than the capacitor body and the top metal layer 10, thereby further enhancing the overall noise immunity of the capacitor.

[0067] In practical applications, to ensure that the fourth metal layer 17 better surrounds the capacitor body, refer to... Figure 2 This allows the projection area of ​​the third metal layer 15 onto the plane of substrate 01 to be located within the projection area of ​​the fourth metal layer 17 onto the plane of substrate 01, and the area of ​​the projection area of ​​the fourth metal layer 17 onto the plane of substrate 01 is larger than the area of ​​the projection area of ​​the third metal layer 15 onto the plane of substrate 01. Therefore, the fourth metal layer 17 can better surround the capacitor body, enhancing the overall noise immunity of the capacitor.

[0068] It should be noted that since both the fourth metal layer 17 and the top metal layer 10 are metallic materials, parasitic capacitance will also be generated between them. Based on this, in this embodiment, the projection of the fourth metal layer 17 onto the plane of the substrate 01 and the projection of the capacitor body onto the plane of the substrate 01 can be made to have no overlapping area. In this way, the fourth metal layer 17 will not be located directly above the capacitor body, which enhances the overall noise immunity of the capacitor and greatly reduces the parasitic capacitance generated between the top metal layer 10 and the fourth metal layer 17.

[0069] It should also be noted that, in practical applications, the isolation structure of the capacitor provided in this embodiment can include more metal layers according to actual needs, and the first electrode plate 09 and the top metal layer 10 can be formed based on the same photomask as the corresponding metal layer, and this embodiment does not impose specific limitations on this.

[0070] For example, the isolation structure of the capacitor may further include a fifth metal layer and a sixth metal layer, with the sixth metal layer higher than the fifth metal layer, and the fifth metal layer higher than the fourth metal layer 17. As another example, the first electrode 09 and the third metal layer 15 may be formed based on the same mask, and the second electrode 10 and the fourth metal layer 17 may be formed based on the same mask. In this case, the sixth metal layer is the highest metal layer. Referring to the description of the foregoing embodiments, the projections of the first metal layer 06, the second metal layer 13, the third metal layer 15, the fourth metal layer 17, and the fifth metal layer onto the plane of the substrate 01 can all completely overlap. The projection area of ​​the sixth metal layer onto the plane of the substrate 01 can be larger than the projection area of ​​the fifth metal layer onto the plane of the substrate 01. The projection of the sixth metal layer onto the plane of the substrate 01 and the projection of the capacitor body onto the plane of the substrate 01 do not overlap.

[0071] In other words, those skilled in the art can take into account factors such as the capacitor's noise immunity, the size of the possible parasitic capacitance, and the manufacturing cost to select the most suitable number of metal layers, as well as which metal layer the first electrode plate 09 and the top metal layer 12 are formed on the same mask. This application does not limit this.

[0072] Another embodiment of this application provides a chip including the capacitor provided in any of the above embodiments. The details described in the above embodiments still apply to this embodiment and will not be repeated here.

[0073] The chip provided in this embodiment increases the density of the active region and the density of polysilicon in the area where the capacitor is located, thereby improving the chip's reliability.

[0074] Those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any of the claimed embodiments can be used in any combination.

[0075] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A capacitor, characterized in that, include: The substrate, the well region, the first polysilicon region, the second polysilicon region, the active region, and the capacitor body, wherein; The substrate is doped with ions of the first type; The well region is formed on the surface of the substrate and extends from the surface of the substrate into the interior of the substrate; the well region is doped with a second type of ions; the first type of ions have opposite polarities to the second type of ions; The first polysilicon region and the second polysilicon region are deposited in a portion of the area above the well region; The active region is injected between two adjacent polysilicon second regions; The capacitor body is disposed above the first region of the polycrystalline silicon.

2. The capacitor according to claim 1, characterized in that, The capacitor body includes: a first electrode plate, a second electrode plate, and a top metal layer; The second electrode plate is disposed between the first electrode plate and the top layer metal, and the top layer metal is electrically connected to the second electrode plate.

3. The capacitor according to claim 2, characterized in that, Also includes: An isolation structure, wherein the isolation structure is a hollow structure, and the capacitor body is housed within the isolation structure.

4. The capacitor according to claim 3, characterized in that, The isolation structure includes a first metal layer, the second polysilicon region is connected to the first metal layer through a first contact hole, and the active region is connected to the first metal layer through a second contact hole.

5. The capacitor according to claim 1, characterized in that, The sum of the areas of the first polycrystalline silicon region and the second polycrystalline silicon region is equal to the area of ​​the active region.

6. The capacitor according to claim 1, characterized in that, Shallow trench isolation areas are formed below both the first polycrystalline silicon region and the second polycrystalline silicon region.

7. The capacitor according to claim 4, characterized in that, The isolation structure further includes a second metal layer, and the first metal layer in the isolation structure is connected to the second metal layer through a first through-hole; The first metal layer and the first electrode plate are formed based on the same photomask; The second metal layer and the top metal layer are formed based on the same photomask.

8. The capacitor according to claim 4, characterized in that, The isolation structure further includes a second metal layer and a third metal layer. The first metal layer in the isolation structure is connected to the second metal layer through a first through hole, and the second metal layer is connected to the third metal layer through a second through hole. The second metal layer and the first electrode plate are formed based on the same photomask; The third metal layer and the top metal layer are formed based on the same photomask.

9. The capacitor according to claim 8, characterized in that, The isolation structure further includes a fourth metal layer, and the third metal layer is connected to the fourth metal layer through a third through-hole; The fourth metal layer is higher than the top metal layer.

10. The capacitor according to claim 9, characterized in that, The projection area of ​​the third metal layer on the plane of the substrate is located within the projection area of ​​the fourth metal layer on the plane of the substrate, and the area of ​​the projection area of ​​the fourth metal layer on the plane of the substrate is greater than the area of ​​the projection area of ​​the third metal layer on the plane of the substrate.

11. The capacitor according to claim 10, characterized in that, The projection of the fourth metal layer onto the plane of the substrate and the projection of the capacitor body onto the plane of the substrate do not overlap.

12. The capacitor according to claim 1, characterized in that, The first type is type P, and the second type is type N.

13. The capacitor according to claim 1, characterized in that, The first type is type N, and the second type is type P.

14. A chip, characterized in that, Including the capacitor as described in any one of claims 1 to 13.

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