A semiconductor device layout structure and a semiconductor device forming method

Abstract

The application relates to the field of semiconductors and discloses a semiconductor device layout structure and a semiconductor device forming method. The semiconductor device layout structure comprises an active region layout layer and a plurality of sub-device layout layers on the active region layout layer, each of the sub-device layout layers comprises a gate pattern region, a source pattern region and a drain pattern region; the gate pattern regions of at least two sub-device layout layers are connected to form a gate connection pattern region, the source pattern regions are connected to form a source connection pattern region, the gate connection pattern region is connected with a gate test terminal, and the source connection pattern region is connected with a source test terminal. The semiconductor device layout structure is suitable for the layout structure design of the same type of device, the design integrates MOS devices of different sizes in one test unit through the mode that at least two devices share the source and the gate, the drain test terminals are separately led out, the occupied space of the test unit can be greatly saved, and meanwhile, the structure can also be used for process structure characterization.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device layout structure and a method for forming a semiconductor device. Background Technology

[0002] With the development of large-scale semiconductor technology, device sizes are becoming smaller and integration levels are becoming higher. To save costs, it is necessary to minimize the area of ​​the dicing channels on a single wafer, thereby increasing the number of chips. However, the needs of process development also require the inclusion of devices of larger sizes, such as... Figure 1 The diagram shows the layout structure of a traditional MOS (Metal Oxide Semiconductor) device. Each device requires four PADs (probe contact test terminals) to be brought out separately (source, drain, gate, and well), which greatly limits the number of devices that can be placed in a fixed cut area. Summary of the Invention

[0003] This invention discloses a semiconductor device layout structure and a semiconductor device formation method, which saves the area occupied by test cells.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] In a first aspect, the present invention provides a semiconductor device layout structure, comprising:

[0006] An active region layout layer and multiple sub-device layout layers located on the active region layout layer, each sub-device layout layer including a gate pattern area, a source pattern area and a drain pattern area; the gate pattern areas of at least two sub-device layout layers are connected to form a gate connection pattern area, and the source pattern areas are connected to form a source connection pattern area, the gate connection pattern area is connected to the gate test terminal, and the source connection pattern area is connected to the source test terminal.

[0007] The above semiconductor device layout structure is applicable to the layout structure design of the same type of device. This design integrates MOS devices of different sizes into one test cell by connecting the gate pattern areas of at least two sub-devices in a shared source and gate configuration. The gate connection pattern area is connected to the gate test terminal through the shared gate pattern area. The source pattern areas are connected to form the source connection pattern area through the shared source connection pattern area, which is connected to the source test terminal. The drain test terminal is brought out separately. Taking the integration of 5 MOS devices as an example, the traditional design requires 20 PADs, while the above layout structure can achieve the requirement of only 8 PADs (including the gate test terminal, source test terminal, drain test terminal, and well test terminal), which can greatly save the space occupied by the test cell. At the same time, this structure can also be used for process structure characterization.

[0008] Optionally, the gate pattern areas of multiple sub-device layout layers are connected together to form a gate connection pattern area, and the source pattern areas are connected together to form a source connection pattern area.

[0009] Optionally, the plurality of gate pattern regions are arranged along a first direction, and the gate connection pattern region extends along the first direction;

[0010] In the same sub-device layout layer, the drain pattern region and the source pattern region are located on both sides of the gate pattern region along the first direction.

[0011] Optionally, a gate auxiliary pattern region is provided between two adjacent gate pattern regions.

[0012] Optionally, in any two adjacent sub-device layout layers, along the first direction, the gate auxiliary pattern area is located between the drain pattern area of ​​the previous sub-device layout layer and the source pattern area of ​​the next sub-device layout layer.

[0013] Optionally, the source connection pattern area extends along the first direction.

[0014] Optionally, the gate connection pattern region and the source connection pattern region are located on both sides of each gate pattern region.

[0015] Optionally, the semiconductor device layout structure further includes a well region layout layer, the active region layout layer is located within the area of ​​the well region layout layer, and a well region connection pattern area is formed on the well region layout layer, the well region connection pattern area being connected to the well region test terminal.

[0016] Optionally, the active area pattern layer includes a first active area pattern area and a plurality of second active area pattern areas, wherein the second active area pattern areas correspond one-to-one with the gate pattern area;

[0017] The well region connecting the pattern area is located within the area of ​​the first active region pattern area.

[0018] Optionally, the first active area graphic region includes a first strip region, a second strip region, and a third strip region connected in sequence, the second strip region extending along the first direction, and the extension directions of the first strip region and the third strip region being perpendicular to the first direction.

[0019] Secondly, the present invention also provides a method for manufacturing a semiconductor device, comprising:

[0020] A well region plate layer is formed on the substrate;

[0021] An active area layer is formed on the well area layer, the active area layer including a first active area graphic area and a plurality of second active area graphic areas;

[0022] A gate pattern region, a source pattern region, and a drain pattern region, each corresponding to one of the second active region pattern regions, are formed on the active region layout layer. The gate pattern region, the source pattern region, and the drain pattern region, which correspond one-to-one with the second active region pattern region, and the active region layout layer together form a sub-device layout layer. The gate pattern regions of at least two sub-device layout layers are connected together to form a gate connection pattern region, and the source pattern regions are connected together to form a source connection pattern region.

[0023] A gate test terminal is formed on the gate connection pattern area, and the gate test terminal is connected to the gate connection pattern area.

[0024] A source test terminal is formed on the source connection pattern area, and the source test terminal is connected to the source connection pattern area.

[0025] Optionally, the gate pattern areas of multiple sub-device layout layers are connected together to form a gate connection pattern area, and the source pattern areas are connected together to form a source connection pattern area.

[0026] Optionally, forming a gate pattern region, a source pattern region, and a drain pattern region on the active region layer that correspond one-to-one with the second active region pattern region includes:

[0027] A gate pattern area and a first sub-gate connection pattern area are formed on the active area plate layer by a patterning process, and at least two of the gate pattern areas are connected to the first sub-gate connection pattern area.

[0028] A first interlayer dielectric layer is formed on the gate pattern region and the first sub-gate connection pattern region;

[0029] A first contact structure is formed in the first interlayer dielectric layer. The first contact structure includes a first contact hole region, a second contact hole region, and a third contact hole region. The first contact hole region corresponds to the first sub-gate connection pattern region. The second contact hole region and the third contact hole region each correspond one-to-one with the second active region pattern region. The second contact hole region and the third contact hole region are located on both sides of the gate pattern region.

[0030] A first conductive layer is formed on the first interlayer dielectric layer and the first contact structure. The first conductive layer includes a second sub-gate connection pattern region, a source connection pattern region, a source pattern region, and a drain conductive layer. The second sub-gate connection pattern region is connected to the first sub-gate connection pattern region through the first contact hole to form the gate connection pattern region. The source pattern region corresponds one-to-one with the second active region pattern region. The source pattern region is connected to the second active region pattern region through the second contact hole region. The drain conductive layer corresponds one-to-one with the second active region pattern region. The drain conductive layer is connected to the second active region pattern region through the third contact hole region.

[0031] A second interlayer dielectric layer is formed on the first conductive layer, and the second interlayer dielectric layer covers the drain conductive layer;

[0032] A second contact structure is formed in the second interlayer dielectric layer;

[0033] A second conductive layer corresponding to each of the plurality of drain conductive layers is formed on the second interlayer dielectric layer and the second contact structure. The second conductive layer includes a drain pattern region and a drain test terminal. The drain pattern region is connected to the drain conductive layer through the second contact structure, and the drain test terminal is connected to the drain pattern region.

[0034] Optionally, a gate auxiliary pattern region is provided between any two adjacent second active region pattern regions.

[0035] Optionally, the first contact structure further includes a fourth contact hole area, which penetrates the first active area pattern area;

[0036] The first conductive layer also includes a well region connection pattern area corresponding to the fourth contact hole region;

[0037] The semiconductor device fabrication method further includes:

[0038] A well area test terminal is formed on the well area connection pattern area, and the well area test terminal is connected to the well area connection pattern area.

[0039] Optionally, the first conductive layer further includes a well region connection pattern area, which is connected to the first active region pattern area through the fourth contact hole area. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the layout structure of a traditional MOS device;

[0041] Figure 2 This is a schematic diagram of a semiconductor device layout structure provided in an embodiment of the present invention;

[0042] Figure 3 for Figure 2 A schematic diagram of the structure of the source area plate layer;

[0043] Figure 4 This is a schematic diagram of another semiconductor device layout structure provided in an embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of a semiconductor device fabrication method provided in an embodiment of the present invention;

[0045] Figures 6a-6f for Figure 4 Schematic diagram of the preparation of the medium structure.

[0046] Icons: 001 - Source; 002 - Drain; 003 - Gate; 004 - Well region; 100 - Active region layout layer; 110 - First active region pattern area; 111 - First stripe region; 112 - Second stripe region; 113 - Third stripe region; 120 - Second active region pattern area; 200 - Sub-device layout layer; 210 - Gate pattern area; 220 - Source pattern area; 221 - Second contact hole region; 230 - Drain pattern area; 231 - Third contact hole region 240 - Gate auxiliary pattern area; 300 - Gate connection pattern area; 310 - Gate test terminal; 320 - First sub-gate connection pattern area; 321 - First contact hole area; 400 - Source connection pattern area; 410 - Source test terminal; 500 - Drain test terminal; 600 - Drain conductive layer; 610 - Second contact structure; 700 - Well area layout layer; 800 - Well area connection pattern area; 810 - Fourth contact hole area; 900 - Well area test terminal. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] Firstly, such as Figures 1 to 4As shown, this embodiment of the invention provides a semiconductor device layout structure, including: an active region layout layer 100 and a plurality of sub-device layout layers 200 located on the active region layout layer 100. Each sub-device layout layer 200 includes a gate pattern region 210, a source pattern region 220 and a drain pattern region 230. The gate pattern regions 210 of at least two sub-device layout layers 200 are connected to form a gate connection pattern region 300, and the source pattern regions 220 are connected to form a source connection pattern region 400. The gate connection pattern region 300 is connected to a gate test terminal 310, and the source connection pattern region 400 is connected to a source test terminal 410.

[0049] The above semiconductor device layout structure is applicable to the layout structure design of the same type of device. This design uses at least two devices to share the source and gate, that is, the gate pattern areas 210 of at least two sub-device layout layers 200 are connected to form a gate connection pattern area 300, and the gate connection pattern area 300 is connected to the gate test terminal 310. The source pattern areas 220 are connected to form a source connection pattern area 400, and the source connection pattern area 400 is connected to the source test terminal 410. Different sizes of MOS devices are integrated into a test unit. The drain test terminal 500 is brought out separately. Taking the integration of 5 MOS devices as an example, the traditional design requires 20 PADs. With the above layout structure, only 8 PADs are needed (including the gate test terminal 310, the source test terminal 410, the drain test terminal 500, and the well test terminal 900), which can greatly save the space occupied by the test unit. At the same time, this structure can also be used for process structure characterization.

[0050] Optionally, the gate pattern areas 210 of multiple sub-device layout layers 200 are connected together to form a gate connection pattern area 300, and the source pattern areas 220 are connected together to form a source connection pattern area 400.

[0051] In one possible implementation, the gate pattern areas 210 of all sub-device layout layers 200 in the semiconductor device layout structure are connected together to form a gate connection pattern area 300, and the source pattern areas 220 are connected together to form a source connection pattern area 400. That is, all sub-device layout layers 200 share the same gate connection pattern area 300 and are connected to the gate connection terminal through this gate connection pattern area 300. All sub-device layout layers 200 share the same source connection pattern area 400 and are connected to the source connection terminal through this source connection pattern area 400. Therefore, the above semiconductor device layout structure only needs to set one gate connection terminal and one source connection terminal, thereby saving the area occupied by the entire test unit due to the reduction in the number of gate connection terminals and source connection terminals.

[0052] Optionally, multiple gate pattern regions 210 are arranged along a first direction, and the gate connection pattern region 300 extends along the first direction; in the same sub-device layout layer 200, the drain pattern region 230 and the source pattern region 220 are located on both sides of the gate pattern region 210 along the first direction.

[0053] In one possible implementation, refer to Figure 2 The semiconductor device layout structure includes five sub-device layout layers 200, such as five MOS devices of different sizes, and the five sub-device layout layers 200 share the same gate connection pattern area 300 and the same source connection pattern area 400. The five gate pattern areas 210 are along a first direction (i.e., Figure 2 The five gate pattern regions 210 are spaced apart along the first direction (A-direction), and the gate connection pattern region 300 shared by the five gate pattern regions 210 extends along the first direction. The drain pattern region 230 and the source pattern region 220 are respectively located on both sides of the gate pattern region 210 along the first direction. Using this structure along the first direction (A-direction), the five gate pattern regions 210 are arranged at intervals, and the gate connection pattern region 300 shared by the five gate pattern regions 210 extends along the first direction. The drain pattern region 230 and the source pattern region 220 are respectively located on both sides of the gate pattern region 210 along the first direction. Figure 2 (The dashed line in the middle) is used for TEM (Transmission Electron Microscope) sectioning. A single section can verify the actual size of five different devices at the same time, which greatly saves sectioning time and cost and effectively improves the development efficiency of the process.

[0054] Optionally, a gate auxiliary pattern region 240 is provided between two adjacent gate pattern regions 210.

[0055] Optionally, in any two adjacent sub-device layout layers 200, along the first direction, the gate auxiliary pattern area 240 is located between the drain pattern area 230 of the previous sub-device layout layer 200 and the source pattern area 220 of the subsequent sub-device layout layer 200.

[0056] It should be noted that a gate auxiliary pattern area 240 is set between two adjacent sub-device layout layers 200. For example, the gate auxiliary pattern area, the source pattern area of ​​one MOS device and the drain pattern area of ​​another MOS device can form an auxiliary MOS device, which is equivalent to a MOS field-effect transistor, thus improving the body effect of the MOS device.

[0057] Optionally, the source-connected graphic area 400 extends along a first direction.

[0058] It is understandable that the source pattern areas 220 of the multiple sub-device layout layers 200 are arranged along the first direction, and the source connection pattern areas 400 extend along the first direction to facilitate wiring between the source connection pattern areas 400 and each source pattern area 220. It is only necessary to extend each source pattern area 220 to connect with the source connection pattern area 400.

[0059] Optionally, the gate connection pattern region 300 and the source connection pattern region 400 are located on both sides of each gate pattern region 210.

[0060] In one possible implementation, refer to Figure 2 The gate connection pattern area 300 and the source connection pattern area 400 shared by multiple sub-devices both extend along the first direction, and the layout layer 200 of each sub-device is located between the gate connection pattern area 300 and the source connection pattern area 400, which avoids interference between the connection between the gate pattern area 210 and the gate connection pattern area 300 and the connection between the source pattern area 220 and the source connection pattern area 400, and further saves the area occupied by the entire semiconductor device layout structure.

[0061] Optionally, the semiconductor device layout structure also includes a well region layout layer 700, an active region layout layer 100 located within the area of ​​the well region layout layer 700, and a well region connection pattern area 800 formed on the well region layout layer 700, which is connected to the well region test terminal 900.

[0062] In one possible implementation, refer to Figure 2 Each sub-device layer 200 shares a gate test terminal 310, a source test terminal 410, and a well test terminal 900. Compared with the traditional layout structure, this saves the number of test terminals and thus saves the area occupied by the test cells.

[0063] Optionally, the active region pattern layer 100 includes a first active region pattern area 110 and a plurality of second active region pattern areas 120, with each second active region pattern area 120 corresponding to a gate pattern area 210; the well region connection pattern area 800 is located within the area of ​​the first active region pattern area 110.

[0064] In one possible implementation, refer to Figure 3 and combined Figure 2 The active area layout layer 100 includes a first active area graphic area 110 and multiple second active area graphic areas 120. The first active area graphic area 110 partially surrounds the multiple second active area graphic areas 120. Each second active area graphic area 120 corresponds to a sub-device layout layer 200. The well area connection graphic area 800 is located within the area of ​​the first active area graphic area 110. The well area connection graphic area 800 is connected to the well area shared by all sub-devices through a contact hole structure.

[0065] Optionally, the first active area graphic area 110 includes a first strip area 111, a second strip area 112 and a third strip area 113 connected in sequence. The second strip area 112 extends along a first direction, and the extension directions of the first strip area 111 and the third strip area 113 are perpendicular to the first direction.

[0066] Reference Figure 3 In the first active region pattern area 110, the first strip area 111 and the third strip area 113 are arranged in parallel and are both parallel to the gate pattern area 210. The second strip area 112 is parallel to the gate connection pattern area 300, which can make full use of the wafer area.

[0067] It should be noted that, for the same type of device, those skilled in the art are more concerned with the performance of the drain of the MOS device. This invention proposes a semiconductor device layout structure by sharing the source test terminal 410, the gate test terminal 310, and the well test terminal 900. (Refer to...) Figure 4 By integrating MOS devices of different sizes into a single test cell, with the drain test terminal 500 brought out separately, the area occupied by the test cell can be greatly reduced. At the same time, this layout structure can also be used for process structure characterization.

[0068] Secondly, refer to Figure 5 Based on the same inventive concept, embodiments of the present invention also provide a method for fabricating a semiconductor device, comprising:

[0069] S501, Form a well region plate layer on the substrate;

[0070] S502. An active area plate layer is formed on the trap area plate layer. The active area plate layer includes a first active area graphic area and multiple second active area graphic areas.

[0071] S503. A gate pattern area, a source pattern area, and a drain pattern area corresponding one-to-one with the second active region pattern area are formed on the active region layout layer. The gate pattern area, source pattern area, and drain pattern area corresponding one-to-one with the second active region pattern area, as well as the active region layout layer, form a sub-device layout layer. The gate pattern areas of at least two sub-device layout layers are connected together to form a gate connection pattern area, and the source pattern areas are connected together to form a source connection pattern area.

[0072] S504. A gate test terminal is formed on the gate connection pattern area, and the gate test terminal is connected to the gate connection pattern area.

[0073] S505. A source test terminal is formed on the source connection pattern area, and the source test terminal is connected to the source connection pattern area.

[0074] In one possible implementation, refer to Figure 6a An active area layer 100 is formed on the trap area layer 700. The active area layer 100 includes a first active area graphic area 110 and multiple second active area graphic areas 120.

[0075] Optionally, the gate pattern areas of multiple sub-device layout layers are connected together to form a gate connection pattern area, and the source pattern areas are connected together to form a source connection pattern area.

[0076] Optionally, a gate pattern region, a source pattern region, and a drain pattern region corresponding one-to-one with the second active region pattern region are formed on the active region layout layer, including:

[0077] A gate pattern area and a first sub-gate connection pattern area are formed on the active area layout layer by a patterning process, and at least two gate pattern areas are connected to the first sub-gate connection pattern area.

[0078] A first interlayer dielectric layer is formed on the gate pattern region and the first sub-gate connection pattern region;

[0079] A first contact structure is formed in the first interlayer dielectric layer. The first contact structure includes a first contact hole region, a second contact hole region, and a third contact hole region. The first contact hole region corresponds to the first sub-gate connection pattern region. The second contact hole region and the third contact hole region each correspond to the second active region pattern region. The second contact hole region and the third contact hole region are located on both sides of the gate pattern region.

[0080] A first conductive layer is formed on the first interlayer dielectric layer and the first contact structure. The first conductive layer includes a second sub-gate connection pattern region, a source connection pattern region, a source pattern region, and a drain conductive layer. The second sub-gate connection pattern region is connected to the first sub-gate connection pattern region through a first contact hole to form a gate connection pattern region. The source pattern region corresponds one-to-one with the second active region pattern region and is connected to the second active region pattern region through a second contact hole region. The drain conductive layer corresponds one-to-one with the second active region pattern region and is connected to the second active region pattern region through a third contact hole region.

[0081] A second interlayer dielectric layer is formed on the first conductive layer, and the second interlayer dielectric layer covers the drain conductive layer.

[0082] A second contact structure is formed in the second interlayer dielectric layer;

[0083] A second conductive layer corresponding to a plurality of drain conductive layers is formed on the second interlayer dielectric layer and the second contact structure. The second conductive layer includes a drain pattern region and a drain test terminal. The drain pattern region is connected to the drain conductive layer through the second contact structure, and the drain test terminal is connected to the drain pattern region.

[0084] Optionally, a gate auxiliary pattern region may be provided between any two adjacent second active region pattern regions.

[0085] In one possible implementation, refer to Figure 6bA gate pattern area 210 and a first sub-gate connection pattern area 320 are formed on the active region pattern layer 100 through a patterning process. The gate pattern area 210 corresponds one-to-one with the second active region pattern area 120. Multiple gate pattern areas 210 are connected to the first sub-gate connection pattern area 320. A gate auxiliary pattern area 240 is provided between any two adjacent second active region pattern areas 120.

[0086] Optionally, the first contact structure further includes a fourth contact hole region, which penetrates the first active area pattern region;

[0087] The first conductive layer also includes a well region connection pattern area corresponding to the fourth contact hole region;

[0088] Semiconductor device fabrication methods also include:

[0089] A well test terminal is formed on the well connection pattern area, and the well test terminal is connected to the well connection pattern area.

[0090] Optionally, the first conductive layer further includes a well region connection pattern area, which is connected to the first active region pattern area through a fourth contact hole area.

[0091] In one possible implementation, refer to Figure 6c A first contact structure is formed on the upper layer of the corresponding areas of the gate pattern region 210 and the first sub-gate connection pattern region 320. The first contact structure includes a first contact hole region 321, a second contact hole region 221, a third contact hole region 231, and a fourth contact hole region 810. Specifically: the area where the first contact hole region 321 is located corresponds to the area where the first sub-gate connection pattern region 320 is located; there are multiple second contact hole regions 221 and third contact hole regions 231, each corresponding one-to-one with the second active region pattern region 120, and in each corresponding group of second active region pattern region 120, second contact hole region 221, and third contact hole region 231, the second contact hole region 221 and third contact hole region 231 are located on both sides of the gate pattern region 210; the area where the fourth contact hole region 810 is located corresponds to the area where the first active region pattern region 110 is located. (Refer to...) Figure 6dThrough a patterning process, a second sub-gate connection pattern region 320 is formed on the first contact hole region 321. The second sub-gate connection pattern region 320 forms a gate connection pattern region 300 through the first contact hole region 321 and the first sub-gate connection pattern region 320. A gate connection terminal is formed on the side of the gate connection pattern region 300 away from the gate pattern region 210. Source pattern regions 220 are formed on all the second contact hole regions 221 respectively. A source connection pattern region 400 is formed on the end of the multiple source pattern regions 220 away from the gate connection pattern region 300. The source connection pattern region 400 is connected to all the source pattern regions 220. A source test terminal 410 is formed on one end of the source connection pattern region 400. Drain conductive layers 600 are formed on all the third contact hole regions 231 respectively. A well region connection pattern region 800 is formed on the fourth contact hole region 810. A well region test terminal 900 extending along the first direction is formed on one end of the well region connection pattern region 800. It should be noted that, along the first direction, in the last sub-device layout layer 200, the drain conductive layer 600 can serve as the drain pattern area 230 in that sub-device layout layer 200, and the drain test terminal 500 of that sub-device layout layer 200 is formed at the end of the drain pattern area 230 away from the gate connection pattern area 300. The method for forming the drain pattern area 230 of the remaining sub-device layout layers 200 is as follows. Figure 6e and Figure 6f , refer to Figure 6e A second contact structure 610 is formed on the drain conductive layer 600 of the remaining sub-device layout layer 200. Multiple second contact structures 610 are formed, and each second contact structure 610 corresponds one-to-one with a drain conductive layer 600. (Refer to...) Figure 6f Through patterning technology, corresponding drain pattern regions 230 are formed on the second contact structure 610. One end of each drain pattern region 230 forms a drain test terminal 500, and the drain test terminals 500 of two adjacent drain pattern regions 230 are located on both sides of the second active region pattern region 120.

[0092] It should be noted that, referring to Figure 6f This invention integrates five sub-devices of the same type but different sizes into a single test unit. The source, gate, and well regions of the five sub-devices share a single pad, while the drain regions are individually led out and connected to separate pads. Traditional designs require twenty pads, but this embodiment only requires eight, significantly saving space in the test unit. However, the number of sub-devices is not limited to five and can be increased or decreased according to actual needs.

[0093] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the invention. Therefore, if these modifications and variations fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A semiconductor device layout structure, characterized in that, include: An active region layout layer and multiple sub-device layout layers located on the active region layout layer, each of the sub-device layout layers including a gate pattern area, a source pattern area and a drain pattern area; The active area pattern layer includes a first active area pattern area and multiple second active area pattern areas, and the second active area pattern areas correspond one-to-one with the gate pattern area. The gate pattern areas of multiple sub-device layout layers are connected to form a gate connection pattern area extending along a first direction, and the source pattern areas are connected to form a source connection pattern area extending along the first direction. The multiple gate pattern areas are arranged along the first direction. In the same sub-device layout layer, the drain pattern area and the source pattern area are located on both sides of the gate pattern area along the first direction. The gate connection pattern area is connected to a gate test terminal, the source connection pattern area is connected to a source test terminal, and the drain pattern area of ​​each sub-device layer is individually connected to an independent drain test terminal. The drain test terminals of two adjacent drain pattern areas are respectively located on both sides of the second active area pattern area. The extension direction of the drain test terminal is parallel to the first direction and perpendicular to the extension direction of the gate test terminal.

2. The semiconductor device layout structure according to claim 1, characterized in that, A gate auxiliary pattern region is provided between two adjacent gate pattern regions.

3. The semiconductor device layout structure according to claim 2, characterized in that, In any two adjacent sub-device layout layers, along the first direction, the gate auxiliary pattern area is located between the drain pattern area of ​​the previous sub-device layout layer and the source pattern area of ​​the next sub-device layout layer.

4. The semiconductor device layout structure according to claim 1, characterized in that, The gate connection pattern region and the source connection pattern region are located on both sides of each gate pattern region.

5. The semiconductor device layout structure according to claim 1, characterized in that, The semiconductor device layout structure also includes a well region layout layer. The active region layout layer is located within the area of ​​the well region layout layer, and a well region connection pattern area is formed on the well region layout layer. The well region connection pattern area is connected to the well region test terminal.

6. The semiconductor device layout structure according to claim 5, characterized in that, The well region connecting the pattern area is located within the area of ​​the first active region pattern area.

7. The semiconductor device layout structure according to claim 6, characterized in that, The first active area graphic region includes a first strip region, a second strip region, and a third strip region connected in sequence. The second strip region extends along the first direction, and the extension directions of the first strip region and the third strip region are perpendicular to the first direction.

8. A method for fabricating a semiconductor device, characterized in that, include: A well region plate layer is formed on the substrate; An active area layer is formed on the well area layer, the active area layer including a first active area graphic area and a plurality of second active area graphic areas; A gate pattern area, a source pattern area, and a drain pattern area, each corresponding to one of the second active region pattern areas, are formed on the active region layout layer. The gate pattern area, the source pattern area, and the drain pattern area, each corresponding to one of the second active region pattern areas, together with the active region layout layer, form a sub-device layout layer. The gate pattern areas of all the sub-device layout layers are connected to form a gate connection pattern area extending along the first direction, and the source pattern areas of all the sub-device layout layers are connected to form a source connection pattern area extending along the first direction. A gate test terminal is formed on the gate connection pattern area, and the gate test terminal is connected to the gate connection pattern area. A source test terminal is formed on the source connection pattern area. The source test terminal is connected to the source connection pattern area. Each drain pattern area of ​​each sub-device layer is individually connected to an independent drain test terminal. The drain test terminals of two adjacent drain pattern areas are located on both sides of the second active area pattern area. The extension direction of the drain test terminal is parallel to the first direction and perpendicular to the extension direction of the gate test terminal.

9. The method according to claim 8, characterized in that, The step of forming a gate pattern region, a source pattern region, and a drain pattern region on the active region layout layer that correspond one-to-one with the second active region pattern region includes: The gate pattern area and the first sub-gate connection pattern area are formed on the active area plate layer by a patterning process, and at least two of the gate pattern areas are connected to the first sub-gate connection pattern area. A first interlayer dielectric layer is formed on the gate pattern region and the first sub-gate connection pattern region; A first contact structure is formed in the first interlayer dielectric layer. The first contact structure includes a first contact hole region, a second contact hole region, and a third contact hole region. The first contact hole region corresponds to the first sub-gate connection pattern region. The second contact hole region and the third contact hole region each correspond one-to-one with the second active region pattern region. The second contact hole region and the third contact hole region are located on both sides of the gate pattern region. A first conductive layer is formed on the first interlayer dielectric layer and the first contact structure. The first conductive layer includes a second sub-gate connection pattern region, a source connection pattern region, a source pattern region, and a drain conductive layer. The second sub-gate connection pattern region is connected to the first sub-gate connection pattern region through the first contact hole to form the gate connection pattern region. The source pattern region corresponds one-to-one with the second active region pattern region. The source pattern region is connected to the second active region pattern region through the second contact hole region. The drain conductive layer corresponds one-to-one with the second active region pattern region. The drain conductive layer is connected to the second active region pattern region through the third contact hole region. A second interlayer dielectric layer is formed on the first conductive layer, and the second interlayer dielectric layer covers the drain conductive layer; A second contact structure is formed in the second interlayer dielectric layer; A second conductive layer corresponding to each of the plurality of drain conductive layers is formed on the second interlayer dielectric layer and the second contact structure. The second conductive layer includes the drain pattern region and the drain test terminal. The drain pattern region is connected to the drain conductive layer through the second contact structure, and the drain test terminal is connected to the drain pattern region.

10. The method according to claim 9, characterized in that, A gate auxiliary pattern area is provided between any two adjacent second active region pattern areas.

11. The method according to claim 9, characterized in that, The first contact structure further includes a fourth contact hole region, which penetrates the first active region pattern region; the first conductive layer further includes a well region connection pattern region corresponding to the fourth contact hole region; The semiconductor device fabrication method further includes: A well area test terminal is formed on the well area connection pattern area, and the well area test terminal is connected to the well area connection pattern area.

Images