High electron mobility transistor

Abstract

A high electron mobility transistor includes a channel layer; a barrier layer on the channel layer and having a band gap greater than a band gap of the channel layer; a gate structure on the barrier layer; a source electrode and a drain electrode spaced apart from each other on the barrier layer with the gate structure therebetween; a field plate electrically connected to the source electrode and extending over the gate structure; and a field dispersion layer in contact with the barrier layer and the drain electrode. The field dispersion layer can extend toward the gate structure.

Description

Technical Field

[0001] This disclosure relates to high electron mobility transistors. Background Technology

[0002] In power conversion systems, the efficiency of power switching devices significantly impacts the overall system efficiency. Silicon-based power metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs) have been primarily used as switching devices, but limitations in their material properties can restrict improvements in efficiency. As an attempt to overcome these material limitations, research into high electron mobility transistors (HEMTs) is actively underway.

[0003] HEMTs can include semiconductor layers with different polarization characteristics. A semiconductor layer with relatively high polarizability in an HEMT can induce a two-dimensional electron gas (2DEG) in another semiconductor layer heterobonded to it. The 2DEG can be used as a channel between the drain and source electrodes, and the current flowing through the channel can be controlled by a bias voltage applied to the gate electrode. Typical HEMT structures, such as HEMTs using heterojunctions with group III nitride semiconductors, can have normally-on characteristics. To achieve normally-off characteristics in an HEMT, a gate semiconductor layer with a depletion region formed in the channel can be employed. Summary of the Invention

[0004] It provides a high electron mobility transistor (HEMT) that distributes the electric field generated between the drain and source electrodes in the normally off state.

[0005] HEMTs that improve current collapse caused by electron traps are provided.

[0006] Other aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing the embodiments proposed in this disclosure.

[0007] According to one embodiment, a high electron mobility transistor may include: a channel layer; a barrier layer on the channel layer having a band gap larger than that of the channel layer; a gate structure on the barrier layer; a source electrode and a drain electrode spaced apart from each other on the barrier layer with the gate structure therebetween; a field plate electrically connected to the source electrode and extending over the gate structure; and a field dispersion layer in contact with the barrier layer and the drain electrode. The field dispersion layer may extend toward the gate structure.

[0008] In some implementations, a portion of the barrier layer may not overlap with the field dispersion layer.

[0009] In some implementations, the portion of the barrier layer may be located between the gate structure and the drain electrode.

[0010] In some implementations, the spacing between the field plate and the field dispersion layer in the width direction of the channel layer can be smaller than the spacing between the gate structure and the drain electrode in the width direction.

[0011] In some implementations, a portion of the field dispersion layer may overlap with the field plate in the thickness direction of the channel layer.

[0012] In some implementations, the bulk material of the field dispersion layer may include the same material as the barrier layer.

[0013] In some implementations, the field dispersion layer may include a p-type doped semiconductor material.

[0014] In some embodiments, the field dispersion layer may include a plurality of first field dispersion layers arranged separately from each other in a direction intersecting the width direction of the channel layer.

[0015] In some embodiments, the plurality of first field dispersion layers may be arranged separately from each other in a direction perpendicular to the width direction of the channel layer.

[0016] In some embodiments, at least one of the plurality of first field dispersion layers may be in contact with the drain electrode.

[0017] In some embodiments, at least one of the plurality of first field dispersion layers may be in contact with the gate structure.

[0018] In some embodiments, the field dispersion layer may further include a second field dispersion layer. One end of the second field dispersion layer may contact the plurality of first field dispersion layers, and the other end of the second field dispersion layer may contact the drain electrode.

[0019] In some implementations, the field dispersion layer may include a mesh structure.

[0020] In some implementations, the thickness of the field dispersion layer can be less than the thickness of the barrier layer.

[0021] In some embodiments, the gate structure may include a gate electrode, a first semiconductor layer, and a second semiconductor layer that may be sequentially arranged on the barrier layer.

[0022] In some embodiments, at least one material in the first semiconductor layer may be different from at least one material in the second semiconductor layer.

[0023] In some implementations, the second semiconductor layer may be doped with the same type of dopant as the first semiconductor layer.

[0024] In some implementations, the host material of the second semiconductor layer may be the same as the host material of the field dispersion layer.

[0025] In some implementations, the doping concentration of the second semiconductor layer may be the same as that of the field dispersion layer.

[0026] In some implementations, the thickness of the second semiconductor layer may be the same as the thickness of the field dispersion layer.

[0027] In some implementations, the second semiconductor layer may be in contact with the source electrode.

[0028] In some implementations, the field plate may include a conductive material.

[0029] In some implementations, a portion of the field plate may overlap with the gate structure in the thickness direction of the channel layer.

[0030] In some implementations, the etch stop layer may be located between the barrier layer and the gate structure. Alternatively, the etch stop layer may be located between the barrier layer and the field dispersion layer.

[0031] According to one embodiment, a high electron mobility transistor may include: a channel layer; a barrier layer on the channel layer and configured to form a two-dimensional electron gas (2DEG) in the channel layer; a source electrode and a drain electrode, spaced apart from each other and respectively connected to a first end and a second end of the barrier layer; a gate structure on a portion of the barrier layer between the first end and the second end of the barrier layer; a field plate electrically connected to the source electrode and extending over the gate structure; and a field dispersion layer on the barrier layer between the gate structure and the drain electrode. The gate structure may be configured to form a depletion region in the 2DEG beneath the gate structure. The field dispersion layer may contact the drain electrode. The field dispersion layer may include a p-type doped semiconductor material.

[0032] In some implementations, the channel layer may include Al x In y Ga 1-x-y N, where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1. The barrier layer may include Al. x In y Ga 1-x-y N, where 0≤x≤1, 0≤y≤1, x+y≤1. The channel layer and the barrier layer can differ from each other in at least one of the following aspects: polarization characteristics, band gap, and lattice constant.

[0033] In some embodiments, the gate structure may include a first semiconductor layer on the barrier layer, a second semiconductor layer on the first semiconductor layer, and a gate electrode on the second semiconductor layer. The first semiconductor layer and the second semiconductor layer may differ in at least one aspect, such as doping concentration and host material.

[0034] In some implementations, the spacing between the field plate and the field dispersion layer in the width direction of the channel layer may be smaller than the spacing between the gate structure and the drain electrode in the width direction, or a portion of the field dispersion layer may overlap with the field plate in the thickness direction of the channel layer.

[0035] In some implementations, the thickness of the field dispersion layer can be less than the thickness of the barrier layer. Attached Figure Description

[0036] The above and other aspects, features and advantages of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0037] Figure 1A This is a cross-sectional view of a high electron mobility transistor (HEMT) according to one embodiment;

[0038] Figure 1B yes Figure 1A A plan view of the HEMT without the field plate;

[0039] Figure 2A This is a graph showing the IV characteristics in HEMT before and after stress;

[0040] Figure 2B This is a graph showing the results of measuring the dynamic on-resistance during HEMT operation;

[0041] Figure 3 This is a view of a field dispersion layer comprising multiple layers according to one embodiment;

[0042] Figure 4 This is a view of a field dispersion layer comprising multiple layers according to another embodiment;

[0043] Figure 5 This is a view of a field dispersion layer comprising multiple layers according to another embodiment;

[0044] Figure 6 This is a view of a field dispersion layer comprising multiple layers according to another embodiment;

[0045] Figure 7 This is a view of a field dispersion layer having a mesh structure according to one embodiment;

[0046] Figure 8 This is a view of a patterned field dispersion layer according to one embodiment;

[0047] Figure 9 This is a cross-sectional view of a HEMT according to one embodiment, wherein the field plate does not overlap with the field dispersion layer.

[0048] Figure 10This is a cross-sectional view of a HEMT including an etch stop layer according to one embodiment;

[0049] Figure 11 This is a cross-sectional view of a HEMT including a second barrier layer according to one embodiment;

[0050] Figure 12 This is a cross-sectional view of a HEMT in one embodiment, wherein the second semiconductor layer is connected to the source electrode;

[0051] Figure 13 This is a cross-sectional view of a HEMT according to one embodiment, wherein the second semiconductor layer has a width different from that of the gate electrode; and

[0052] Figure 14 This is a schematic diagram of an electronic device including a HEMT according to an example embodiment. Detailed Implementation

[0053] The embodiments will now be described in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, embodiments may exist in different forms and should not be construed as limited to the description set forth herein. Therefore, aspects are explained below by describing only embodiments with reference to the accompanying drawings. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire column of elements when following a list of elements, without modifying any individual element within that column.

[0054] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings. In this regard, embodiments may exist in different forms and should not be construed as limited to the description set forth herein. Throughout the drawings, the same reference numerals refer to the same elements. For clarity and ease of explanation, the thickness or dimensions of each layer shown in the drawings may be exaggerated.

[0055] In a layered structure, when a component is positioned "above" or "on" another component, the component may be directly on the other component or be placed on the other component in a non-contact manner.

[0056] Terms such as “first” and “second” are used herein only to describe various constituent elements, but the constituent elements are not limited by these terms. Such terms are used only for the purpose of distinguishing one constituent element from another. These terms do not limit the materials or structures of the constituent elements to be different from each other.

[0057] A statement used in the singular form covers a plural statement unless it has a distinct meaning in the context. It will also be understood that the terms “comprising” and / or “including” as used herein indicate the presence of a stated feature or component, but do not exclude the presence or addition of one or more other features or components.

[0058] The use of the terms “a” and “the”, and similar designations, in the context of describing this disclosure shall be interpreted to cover both singular and plural forms.

[0059] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended to mean that the relevant numerical value includes a tolerance of + / - 10% around the stated value. When a range is specified, the range includes all values ​​within that range, such as increments of 0.1%.

[0060] Figure 1A This is a cross-sectional view of a high electron mobility transistor (HEMT) according to one embodiment. Figure 1B yes Figure 1A A plan view of the HEMT excluding the field plate 60. (See attached image.) Figure 1A and Figure 1B As shown, a HEMT may include: a channel layer 10; a barrier layer 20 disposed on the channel layer 10; and a gate structure 30, a source electrode (S) 40, and a drain electrode (D) 50 spaced apart from each other on the barrier layer 20. Furthermore, the HEMT may also include a field plate 60 electrically connected to the source electrode 40 and extending above the gate structure 30, and a field dispersion layer 70 contacting the barrier layer 20 and the drain electrode 50 and extending toward the gate structure 30.

[0061] The channel layer 10 can form a path for current to flow between the source electrode 40 and the drain electrode 50. The channel layer 10 can have a single-layer or multi-layer structure comprising one or more materials selected from nitrides of at least one group III-V materials (e.g., Al, Ga, or In). The channel layer 10 may include Al. x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1). For example, the channel layer 10 may include at least one of AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, etc. The channel layer 10 may be an undoped layer or a doped layer. The channel layer 10 may have a thickness of several hundred nanometers or less (e.g., 700 nm or less, 500 nm or less, 300 nm or less).

[0062] A barrier layer 20 may be disposed on the channel layer 10. The barrier layer 20 may comprise a material different from the channel layer 10. A two-dimensional electron gas (2DEG) may be formed in the barrier layer 20 within the channel layer 10. For example, the 2DEG may be an additional channel for a semiconductor device. The 2DEG may be formed adjacent to the interface between the channel layer 10 and the barrier layer 20. For example, the 2DEG may extend in a direction parallel to the upper surface of the channel layer 10.

[0063] The barrier layer 20 may differ from the channel layer 10 in at least one aspect of polarization characteristics, band gap, and lattice constant. For example, the barrier layer 20 may have a larger band gap than the channel layer 10. The barrier layer 20 may comprise one or more materials selected from nitrides including at least one of Al, Ga, and In. The barrier layer 20 may comprise Al x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1). For example, the barrier layer 20 may include at least one of AlGaN, AlInN, InGaN, AlN, and AlInGaN. The barrier layer 20 may have a single-layer structure or a multi-layer structure.

[0064] The barrier layer 20 may be doped with dopants diffused from adjacent other layers (e.g., the field dispersion layer 70 and the second semiconductor layer 33 described below).

[0065] When a barrier layer 20 is formed on the channel layer 10, 2DEGs can be induced in the channel layer 10 not only due to spontaneous polarization but also due to piezoelectric polarization caused by the difference in lattice constants between the channel layer 10 and the barrier layer 20. 2DEGs exhibit very high electron mobility.

[0066] The source electrode 40 and the drain electrode 50 can be arranged on the barrier layer 20. The source electrode 40 and the drain electrode 50 can be arranged separately from each other.

[0067] The source electrode 40 and drain electrode 50 can be electrically connected to the 2DEG. For example, the source electrode 40 and drain electrode 50 can extend into the interior of the channel layer 10 to directly contact the 2DEG. The source electrode 40 and drain electrode 50 can be in ohmic contact with the barrier layer 20. The source electrode 40 and drain electrode 50 can be connected to the first and second ends of the barrier layer 20, respectively.

[0068] The source electrode 40 and the drain electrode 50 may have a single-layer structure or a multi-layer structure. The source electrode 40 and the drain electrode 50 may each include a conductive material, such as a metallic material and / or a metallic alloy.

[0069] The gate structure 30 can be disposed on the barrier layer 20 between the source electrode 40 and the drain electrode 50. The gate structure 30 can be disposed closer to the source electrode 40 than to the drain electrode 50. The gate structure 30 may include a gate electrode (G) 31, a first semiconductor layer 32, and a second semiconductor layer 33.

[0070] The gate electrode 31 can control the current flowing between the source electrode 40 and the drain electrode 50. The gate electrode 31 may include a conductive material, such as a metal material and / or a metal alloy.

[0071] The first semiconductor layer 32 may include a p-type semiconductor to form a depletion region 11 in the 2DEG formed in the channel layer 10. Therefore, the 2DEG may not be formed in the region corresponding to the first semiconductor layer 32, or may have different characteristics (electron concentration, etc.) in the region corresponding to the first semiconductor layer 32 than in other regions.

[0072] The first semiconductor layer 32 can realize the normally off characteristic of the HEMT. The normally off characteristic means that when no voltage is applied to the gate electrode 31, that is, under normal conditions, the HEMT enters the off state, and when a voltage is applied to the gate electrode 31, the HEMT enters the on state.

[0073] The first semiconductor layer 32 may include a semiconductor material doped with a p-type dopant. The first semiconductor layer 32 may include one or more materials selected from nitrides of at least one group III-V materials (e.g., Al, Ga, or In). The first semiconductor layer 32 may include Al. x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1). The first semiconductor layer 32 may include at least one of GaN, InN, AlGaN, AlInN, InGaN, AlN, AlInGaN, etc. For example, the first semiconductor layer 32 may include p-type GaN.

[0074] The first semiconductor layer 32 can have a thickness of about 10 nm to about 150 nm. When the thickness of the first semiconductor layer 32 is less than 10 nm, it may not include a sufficient amount of p-type impurities to form a depletion region 11 in the channel layer 10; therefore, a normally conducting characteristic in which current flows in the off state may occur. When the thickness of the first semiconductor layer 32 exceeds 150 nm, the bias voltage applied to the gate electrode 31 may increase excessively because the band level of the barrier layer 20 in the gate region GTA may be too high to set the HEMT to the on state.

[0075] The first semiconductor layer 32 has a shape corresponding to the gate electrode 31. For this purpose, the first semiconductor layer 32 can be patterned in various ways. In one example, an etching process can be used to optionally remove the remaining area of ​​the first semiconductor layer 32, excluding the gate formation region. Dry etching can be used as an example of an etching process, and chlorine (Cl2) gas and / or boron chloride (BCl3) gas can be used as examples of etching gases. Therefore, the first semiconductor layer 32 is formed below the gate electrode 31, and not on the side of the gate electrode 31.

[0076] The second semiconductor layer 33 can be disposed between the barrier layer 20 and the first semiconductor layer 32. The second semiconductor layer 33 can have a different band gap than the first semiconductor layer 32.

[0077] The second semiconductor layer 33 may differ from the first semiconductor layer 32 in at least one aspect of doping concentration and host material. The second semiconductor layer 33 may include a III-V group material, but may differ from the first semiconductor layer 32 in at least one material aspect. At least one material in the first semiconductor layer 32 may differ from at least one material in the second semiconductor layer 33. The second semiconductor layer 33 may include Al. x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1). The second semiconductor layer 33 may include at least one of GaN, InN, AlGaN, AlInN, InGaN, AlN, AlInGaN, etc. For example, when the first semiconductor layer 32 includes GaN material, the second semiconductor layer 33 may include AlGaN material.

[0078] The second semiconductor layer 33 may be doped with a dopant. The dopant may include a p-type dopant that provides holes. For example, the dopant may include magnesium (Mg).

[0079] The second semiconductor layer 33 may have a different doping concentration than the first semiconductor layer 32. For example, the second semiconductor layer 33 may have a lower doping concentration than the first semiconductor layer 32. The doping concentration of the second semiconductor layer 33 may be from 1% to 50% of the doping concentration of the first semiconductor layer 32.

[0080] The second semiconductor layer 33 may have a thickness that does not affect the depletion region 11 formed by the first semiconductor layer 32. The thickness of the second semiconductor layer 33 may be less than the thickness of the barrier layer 20 and the thickness of the first semiconductor layer 32. For example, the second semiconductor layer 33 may have a thickness of about 10 nm or less.

[0081] Because the channel layer 10 and the barrier layer 20 differ from each other in lattice constant, band gap, etc., defects may occur at the interface between the channel layer 10 and the barrier layer 20. As the HEMT is repeatedly operated, stress may be generated due to the aforementioned defects, and this stress may increase the on-resistance of the HEMT.

[0082] Figure 2A This is a graph showing the IV characteristics in HEMT before and after stress. Figure 2B This is a graph showing the results of measuring the dynamic on-resistance during HEMT operation. (See figure.) Figure 2A As shown, when stress is generated at the interface between the channel layer 10 and the barrier layer 20, it can be seen that the current flowing in the drain electrode due to the voltage applied to the drain electrode decreases. This means that the on-resistance increases in the channel layer 10. Figure 2B As shown, the on-resistance gradually increases due to the repeated operation of the HEMT. This is because electron traps increase at the interface between channel layer 10 and barrier layer 20, resulting in current collapse.

[0083] According to one embodiment, the HEMT may further include a field plate 60 and a field dispersion layer 70 to limit and / or prevent an increase in on-resistance.

[0084] A field plate 60 may extend from the source electrode 40 over the gate structure 30. The field plate 60 may be electrically connected to the source electrode 40. For example, the field plate 60 may be in direct contact with the source electrode 40. Therefore, the source electrode 40 and the field plate 60 may have the same potential. Since the field plate 60 extends from the source electrode 40 over the gate structure 30, a portion of the field plate 60 may overlap with the gate structure 30 in the thickness direction d2 of the channel layer 10. In the width direction d1 of the channel layer 10, the spacing between the field plate 60 and the drain electrode 50 may be smaller than the spacing between the gate structure 30 and the drain electrode 50.

[0085] Field plate 60 may include a conductive material. For example, field plate 60 may include a metal or metal alloy and may include the same material as source electrode 40. Field plate 60 and field dispersion layer 70 described below may limit and / or prevent electric field concentration on channel layer 10 due to the voltage difference between source electrode 40 and drain electrode 50.

[0086] The field dispersion layer 70 can be in direct contact with the barrier layer 20 and the drain electrode 50, and can be arranged to face the gate structure 30 from the drain electrode 50. In the width direction d1 of the channel layer 10, the spacing between the field dispersion layer 70 and the field plate 60 can be smaller than the spacing between the field dispersion layer 70 and the gate electrode 31. The field dispersion layer 70 can partially overlap with the field plate 60 in the thickness direction d2 of the channel layer 10. When a portion of the field plate 60 overlaps with a portion of the field dispersion layer 70 in the thickness direction d2 of the channel layer 10, the spacing between the field dispersion layer 70 and the field plate 60 in the width direction d1 of the channel layer 10 can be referred to as 0. However, this disclosure is not limited thereto. In some embodiments, the field dispersion layer 70 may not overlap with the field plate 60 in the thickness direction d2 of the channel layer 10.

[0087] The field dispersion layer 70 may include one or more materials selected from nitrides of at least one group III-V materials (e.g., Al, Ga, or In). The field dispersion layer 70 may include Al. x In y Ga 1-x-y N(0≤x≤1, 0≤y≤1, x+y≤1). The field dispersion layer 70 may include at least one of GaN, InN, AlGaN, AlInN, InGaN, AlN, AlInGaN, etc.

[0088] The field dispersion layer 70 may be doped with dopants to improve electrical properties. For example, the doping concentration of the field dispersion layer 70 may be greater than the doping concentration of the barrier layer 20. The field dispersion layer 70 may be doped with p-type dopants. The field dispersion layer 70 may include p-type doped semiconductor materials.

[0089] When a large amount of dopant is doped in the field dispersion layer 70, similar to the first semiconductor layer 32, the 2DEG will be depleted. Therefore, the field dispersion layer 70 needs to have a thickness and doping concentration that prevents the 2DEG beneath it from being depleted, and the field dispersion layer 70 may include a material with a band gap similar to that of the barrier layer 20, and may be formed to facilitate the formation of 2DEG, just like the barrier layer 20. The bulk material of the field dispersion layer 70 may include the same material as the barrier layer 20.

[0090] In this state, the doping concentration of the field dispersion layer 70 can be at a concentration level of 1% to 50% of the doping concentration of the first semiconductor layer 32, and the thickness of the field dispersion layer 70 can be less than 10 nm.

[0091] When the field dispersion layer 70 is not configured to cover the entire barrier layer 20, the thickness and doping concentration of the field dispersion layer 70 can be further increased. This is because even when the 2DEG below the field dispersion layer 70 is slightly depleted by the field dispersion layer 70, the 2DEG in the region not covered by the field dispersion layer 70 can be used to ensure the on-resistance.

[0092] A portion of the barrier layer 20 may not overlap with the field dispersion layer 70. For example, one end of the field dispersion layer 70 may be in direct contact with the drain electrode 50, while the other end may be separately arranged from the gate structure 30.

[0093] In the off state, the voltage applied to the source electrode 40 can be distributed to the field plate 60, and the voltage applied to the drain electrode 50 can be distributed to the field dispersion layer 70. While an electric field is formed in the channel layer 10 between the source electrode 40 and the drain electrode 50 due to the voltage difference between them, an electric field can also be formed between the field plate 60 and the field dispersion layer 70. Therefore, the concentration of the electric field on the channel layer 10 can be reduced or mitigated.

[0094] Furthermore, since the field dispersion layer 70 is doped with a p-type dopant, the hole injection efficiency of the channel layer 10 and / or the barrier layer 20 can be improved in the on-state. Because of the improved hole injection efficiency, the 2DEG concentration of the channel layer 10 can be increased, thereby reducing the on-resistance of the channel layer 10. This is because electron trapping can be reduced by providing holes to the interface between the barrier layer 20 and the channel layer 10.

[0095] The thickness of the field dispersion layer 70 can be less than the thickness of the drain electrode 50. The thickness of the field dispersion layer 70 can be less than the thickness of the barrier layer 20. For example, the thickness of the field dispersion layer 70 can be half or less of the thickness of the barrier layer 20. The thickness of the field dispersion layer 70 can be about 10 nm or less.

[0096] The thickness of the field dispersion layer 70 can be equal to the thickness of the second semiconductor layer 33. This is because the field dispersion layer 70 and the second semiconductor layer 33 can be epitaxially grown. Furthermore, the host material of the field dispersion layer 70 can be the same as the host material of the second semiconductor layer 33, and the doping concentration of the field dispersion layer 70 can be the same as or different from the doping concentration of the second semiconductor layer 33. The field dispersion layer 70 can disperse the electric field in the off state and can improve the hole injection efficiency in the on state.

[0097] The field dispersion layer 70 is shown as a single layer, but this disclosure is not limited thereto. In some embodiments, the field dispersion layer 70 may include multiple layers.

[0098] Figure 3 This is a view of a field dispersion layer 70a comprising multiple layers according to one embodiment. (See figure) Figure 3As shown, the field dispersion layer 70a may include a plurality of first field dispersion layers 110 spaced apart from each other on the barrier layer 20. The first field dispersion layers 110 may be arranged sequentially in a direction intersecting the width direction d1 of the channel layer 10. For example, the first field dispersion layers 110 may be arranged sequentially in a direction d3 perpendicular to the width direction d1 of the channel layer 10.

[0099] At least one of the plurality of first field dispersion layers 110 may be in contact with the drain electrode 50. For example, one end of each first field dispersion layer 110 may be in contact with the drain electrode 50, while its other end may be disposed separately from the gate structure 30. The first field dispersion layer 110 may be strip-shaped, but this disclosure is not limited thereto. Since the field dispersion layer 70a includes first field dispersion layers 110 arranged spaced apart from each other, the area of ​​overlap between the barrier layer 20 and the field dispersion layer 70a can be reduced. Since the area of ​​overlap between the barrier layer 20 and the field dispersion layer 70a is reduced, the influence of the field dispersion layer 70a on the 2DEG can be reduced.

[0100] Figure 4 This is a view of a field dispersion layer 70b comprising multiple layers according to another embodiment. Figure 4 In, with Figure 3 In contrast, at least one of the plurality of first field dispersion layers 110a may be in contact with the gate structure 30. For example, at least one of the first field dispersion layers 110a may be in contact with the second semiconductor layer 33 of the gate structure 30.

[0101] The field dispersion layer 70b can have the same thickness as the second semiconductor layer 33 and can include the same bulk material as the second semiconductor layer 33. The field dispersion layer 70b can not only distribute the electric field together with the field plate 60, but also improve the hole injection efficiency like the second semiconductor layer 33. Therefore, the increase in on-resistance can be reduced.

[0102] Figure 5 This is a view of a field dispersion layer 70c comprising multiple layers according to another embodiment. (See figure) Figure 5 As shown, the field dispersion layer 70c may include a plurality of first field dispersion layers 110b arranged at intervals on the barrier layer 20, and a second field dispersion layer 120 having one end in contact with the first field dispersion layer 110b and the other end in contact with the drain electrode 50.

[0103] The first field dispersion layer 110b can be arranged sequentially in a direction intersecting the width direction d1 of the channel layer 10. For example, the first field dispersion layer 110b can be arranged sequentially on the barrier layer 20 in a direction d3 perpendicular to the width direction d1 of the channel layer 10. In direction d3, the length of the second field dispersion layer 120 can correspond to the length of the drain electrode 50. The second field dispersion layer 120 can enhance the contact with the drain electrode 50, and the first field dispersion layer 110b can reduce the influence on the 2DEG.

[0104] Figure 6 This is a view of a field dispersion layer 70d comprising multiple layers according to another embodiment. Figure 6 In, with Figure 5 In contrast, at least one of the plurality of first field dispersion layers 110c may be in contact with the gate structure 30. For example, at least one of the first field dispersion layers 110c may be in contact with the second semiconductor layer 33 of the gate structure 30.

[0105] The field dispersion layer 70d can have the same thickness as the second semiconductor layer 33 and include the same bulk material as the second semiconductor layer 33. Like the second semiconductor layer 33, the field dispersion layer 70d can be doped with a p-type dopant, thereby exhibiting a carrier generation effect. Therefore, the increase in on-resistance can be reduced.

[0106] Figure 7 This is a view of a field dispersion layer 70e having a mesh structure according to one embodiment. (See figure) Figure 7 As shown, the field dispersion layer 70e may include a mesh structure having one or more openings for exposing the barrier layer 20. For example, the field dispersion layer 70e may include a plurality of first field dispersion layers 110d arranged spaced apart from the barrier layer 20, a second field dispersion layer 120a having one end in contact with the first field dispersion layer 110d and the other end in contact with the drain electrode 50, and a third field dispersion layer 120b having one end in contact with the first field dispersion layer 110d and the other end spaced apart from the gate structure 30.

[0107] In the direction d3 perpendicular to the width direction d1 of the channel layer 10, the length of the second field dispersion layer 120a can correspond to the length of the drain electrode 50. The contact with the drain electrode 50 can be strengthened by the second field dispersion layer 120a, and the increase in on-resistance can be reduced by the second field dispersion layer 120a.

[0108] In direction d3, the length of the third field dispersion layer 120b can correspond to the length of the field plate 60, and the third field dispersion layer 120b can overlap with the field plate 60 in the thickness direction d2 of the channel layer 10. The third field dispersion layer 120b can completely overlap with the field plate 60 in the thickness direction d2 of the channel layer 10. Therefore, since the third field dispersion layer 120b increases the overlap area between the field dispersion layer 70 and the field plate 60, the concentration of the electric field can be further reduced.

[0109] Figure 8 This is a view of a patterned field dispersion layer according to one embodiment.

[0110] like Figure 8 As shown, the field dispersion layer 70f can be patterned. For example, the field dispersion layer 70f may include a pattern defining a plurality of openings O that extend through the field dispersion layer 70f in the thickness direction. The openings O may expose underlying layers, such as barrier layer 20 or related layers. Figure 10 The etch stop layer 80 is discussed.

[0111] Although Figure 8 The field dispersion layer 70f includes a plurality of rectangular openings O spaced apart from each other in a direction d3 intersecting the width direction d1, but the example embodiment is not limited thereto. The openings O may alternatively have other shapes (e.g., circular) and may alternatively be arranged in an array or other pattern.

[0112] Figure 9 This is a cross-sectional view of a HEMT according to one embodiment, wherein the field plate 60a does not overlap with the field dispersion layer 70. Figure 9 In comparison with Figure 1, Figure 9 The field plate 60a and the field dispersion layer 70 may not overlap each other in the thickness direction d2 of the channel layer 10. Even when the field plate 60a and the field dispersion layer 70 do not overlap each other, the spacing between the field plate 60a and the field dispersion layer 70 in the width direction d1 of the channel layer 10 may be smaller than the spacing between the gate electrode 31 and the field dispersion layer 70. Furthermore, the average distance between the field plate 60a and the field dispersion layer 70 may be smaller than the average distance between the source electrode 40 and the drain electrode 50. Therefore, in the off state, an electric field can be formed not only in the channel layer 10 but also in the field plate 60a and the field dispersion layer 70.

[0113] Second semiconductor layers 33 and 33a (see Figure 12 The field dispersion layers 70, 70a, 70b, 70c, 70d, 70e, and 70f can be formed on the barrier layer 20 by an etching process. According to one embodiment, the HEMT can use an etch stop layer to limit and / or prevent damage to the barrier layer 20 during the etching process. Figure 10This is a cross-sectional view of a HEMT including an etch stop layer 80 according to one embodiment.

[0114] like Figure 10 As shown, an etch stop layer 80 may be disposed on the barrier layer 20, and a second semiconductor layer 33 and a field dispersion layer 70 may be disposed on the etch stop layer 80. This is to limit and / or prevent unnecessary etching of the barrier layer 20 beneath the second semiconductor layer 33 and the field dispersion layer 70 when the second semiconductor layer 33 and the field dispersion layer 70 are formed. In one example, the etch stop layer 80 may include at least one of InGaN, AlGaN, and AlInGaN.

[0115] Excessive dopant infiltration into the channel layer 10 can degrade the characteristics of the 2DEG. As dopant diffuses from the barrier layer 20 towards the channel layer 10, the dopant concentration in the channel layer 10 can increase, potentially degrading the characteristics of the 2DEG. Furthermore, as the dopant concentration in the barrier layer 20 decreases, the desired threshold voltage or on-resistance may not be achieved.

[0116] Figure 11 This is a cross-sectional view of a HEMT including a second barrier layer 90 according to one embodiment. (Refer to...) Figure 11 Another barrier, such as a second barrier layer 90, can be disposed between the channel layer 10 and the barrier layer 20 to enhance polarization. The second barrier layer 90 may comprise one or more materials selected from nitrides of at least one group III-V materials (e.g., Al, Ga, or In). The second barrier layer 90 may be an undoped material layer. The second barrier layer 90 may include undoped Al. x In y Ga 1-x-y N(0≤x≤1, 0≤y≤1, x+y≤1). The second barrier layer 90 may include at least one of GaN, InN, AlGaN, AlInN, InGaN, AlN, AlInGaN, etc.

[0117] The thickness of the second barrier layer 90 can be from about 0.5 nm to about 1.5 nm. Since the second barrier layer 90 increases the polarization phenomenon, the characteristics of the 2DEG can be improved.

[0118] Figure 12 This is a cross-sectional view of a HEMT according to one embodiment, in which the second semiconductor layer 33a is connected to the source electrode. Since the second semiconductor layer 33a is doped with a p-type dopant, holes are supplied to the channel layer 10, thereby reducing electron trapping. To limit and / or prevent excessive hole injection into the channel layer 10, the thickness of the second semiconductor layer 33a can be less than the thickness of the barrier layer 20. For example, the thickness of the second semiconductor layer 33a can be about 10 nm or less.

[0119] To provide holes to a larger area of ​​the channel layer 10, the area of ​​the second semiconductor layer 33a can be larger than the area of ​​the gate electrode 31. The second semiconductor layer 33a can extend from the first semiconductor layer 32 toward at least one of the source electrode 40 and the drain electrode 50. For example, the second semiconductor layer 33a can extend toward the source electrode 40 to contact the source electrode 40, and can be arranged spaced apart from the field dispersion layer 70.

[0120] In the gate structure 30a, the gate electrode 31 may have the same width as the first semiconductor layer 32 in the width direction d1. The sidewalls of the gate electrode 31 and the sidewalls of the first semiconductor layer 32 may be coplanar with each other. However, the example embodiment is not limited to this.

[0121] Figure 13 This is a cross-sectional view of a HEMT according to one embodiment, wherein the second semiconductor layer has a width different from that of the gate electrode.

[0122] like Figure 13 As shown, the second semiconductor layer 33b can extend from a first side of the first semiconductor layer 32 toward the source electrode 40 and from a second side of the first semiconductor layer 32 toward the drain electrode 50. The second semiconductor layer 33b can be spaced apart from the field dispersion layer 70. Although Figure 13 A second semiconductor layer 33b spaced apart from the source electrode 40 is shown, but the example embodiment is not limited thereto. In other embodiments, the second semiconductor layer 33b may contact the source electrode 40.

[0123] The thickness of the second semiconductor layer 33b can be less than the thickness of the barrier layer 20. For example, the thickness of the second semiconductor layer 33b can be about 10 nm or less.

[0124] Figure 14 This is a schematic diagram of an electronic device including a HEMT according to an example embodiment.

[0125] like Figure 14 As shown, electronic device 1400 includes one or more electronic device components, including a processor (e.g., processing circuitry) 1420 and a memory 1430 that are communicatively connected together via a bus 1410.

[0126] Processing circuitry 1420 may include one or more instances of processing circuitry and / or may be implemented by one or more instances of processing circuitry, such as: hardware including logic circuitry; hardware / software combinations, such as a processor running software; or combinations thereof. For example, processing circuitry 1420 may include, but is not limited to, a central processing unit (CPU), application processor (AP), arithmetic logic unit (ALU), graphics processing unit (GPU), digital signal processor, microcomputer, field-programmable gate array (FPGA), system-on-a-chip (SoC), programmable logic unit, microprocessor, or application-specific integrated circuit (ASIC). In some example embodiments, memory 1430 may include a non-transitory computer-readable storage device storing instruction programs, such as a solid-state drive (SSD), and processing circuitry 1420 may be configured to run instruction programs to implement the functions of electronic device 1400.

[0127] In some example embodiments, electronic device 1400 may include one or more additional components 1440 coupled to bus 1410, which may include, for example, a power supply, a light sensor, a light-emitting device, any combination thereof, etc. In some example embodiments, processing circuitry 1420, memory 1430, and one or more additional components 1440 may include power devices, which may include any HEMT (such as...) according to the example embodiments described herein. Figure 1A , Figure 1B and Figures 9 to 13 HEMTs and those HEMT-based Figures 3 to 8 Variations of any of the field dispersion layers 70a to 70f discussed herein. Therefore, the electronic device 1400 can be a power device possessing improved electrical characteristics (e.g., reduced electron trapping, reduced on-resistance) resulting in improved performance and / or reliability.

[0128] The HEMT according to the exemplary embodiments described with reference to the above figures can be used as, for example, a power device. However, the application of the HEMT according to the embodiments of this disclosure is not limited to power devices, and various modifications can be made. In other words, the HEMT according to the exemplary embodiments can be used not only as a power device, but also for other purposes (such as RF switching devices).

[0129] It should be understood that the embodiments described herein are to be considered descriptive only and not for limiting purposes. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

[0130] This application is based on and claims priority to Korean Patent Application No. 10-2021-0091855, filed on July 13, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A high electron mobility transistor, comprising: Channel layer; A barrier layer, on the channel layer, having a band gap larger than that of the channel layer; A gate structure is located on the barrier layer; The source electrode and drain electrode are spaced apart from each other on the barrier layer and the gate structure is therebetween; A field plate, electrically connected to the source electrode and extending over the gate structure; as well as A field dispersion layer is in contact with the barrier layer and the drain electrode, and the field dispersion layer extends toward the gate structure. A portion of the field dispersion layer overlaps with the field plate in the thickness direction of the channel layer, and an electric field is formed between the field plate and the field dispersion layer through the voltage difference between the source electrode and the drain electrode.

2. The high electron mobility transistor according to claim 1, The portion of the barrier layer does not overlap with the field dispersion layer.

3. The high electron mobility transistor according to claim 2, The portion of the barrier layer is located between the gate structure and the drain electrode.

4. The high electron mobility transistor according to claim 1, The spacing between the field plate and the field dispersion layer in the width direction of the channel layer is smaller than the spacing between the gate structure and the drain electrode in the width direction.

5. The high electron mobility transistor according to claim 1, The bulk material of the field dispersion layer is the same as that of the barrier layer.

6. The high electron mobility transistor according to claim 1, The field dispersion layer comprises a p-type doped semiconductor material.

7. The high electron mobility transistor according to claim 1, The field dispersion layer includes a plurality of first field dispersion layers, which are arranged separately from each other in a direction intersecting the width direction of the channel layer.

8. The high electron mobility transistor according to claim 7, The plurality of first field dispersion layers are arranged separately from each other in a direction perpendicular to the width direction of the channel layer.

9. The high electron mobility transistor according to claim 7, At least one of the plurality of first field dispersion layers is in contact with the drain electrode.

10. The high electron mobility transistor according to claim 7, At least one of the plurality of first field dispersion layers is in contact with the gate structure.

11. The high electron mobility transistor according to claim 7, wherein... The field dispersion layer further includes a second field dispersion layer. One end of the second field dispersion layer is in contact with the plurality of first field dispersion layers, and The other end of the second field dispersion layer is in contact with the drain electrode.

12. The high electron mobility transistor according to claim 1, The field dispersion layer comprises a mesh structure.

13. The high electron mobility transistor according to claim 1, The thickness of the field dispersion layer is less than the thickness of the barrier layer.

14. The high electron mobility transistor according to claim 1, The gate structure includes a gate electrode, a first semiconductor layer, and a second semiconductor layer arranged sequentially on the barrier layer.

15. The high electron mobility transistor according to claim 14, The first semiconductor layer contains at least one material that is different from the second semiconductor layer.

16. The high electron mobility transistor according to claim 1, further comprising: An etch stop layer between the barrier layer and the gate structure, wherein The etch stop layer is located between the barrier layer and the field dispersion layer.

17. A high electron mobility transistor, comprising: Channel layer; A barrier layer on the channel layer, the barrier layer being configured to form a two-dimensional electron gas in the channel layer; The source electrode and the drain electrode are spaced apart from each other and are respectively connected to the first end of the barrier layer and the second end of the barrier layer; A gate structure is provided on a portion of the barrier layer between the first end and the second end of the barrier layer, the gate structure being configured to form a depletion region in the two-dimensional electron gas below the gate structure; A field plate, electrically connected to the source electrode and extending over the gate structure; as well as A field dispersion layer is disposed on the barrier layer between the gate structure and the drain electrode, the field dispersion layer contacting the drain electrode, and the field dispersion layer comprising a p-type doped semiconductor material. A portion of the field dispersion layer overlaps with the field plate in the thickness direction of the channel layer, and an electric field is formed between the field plate and the field dispersion layer through the voltage difference between the source electrode and the drain electrode.

18. The high electron mobility transistor of claim 17, wherein... The channel layer includes Al x In y Ga 1-x-y N, where 0≤x≤1, 0≤y≤1, x+y≤1, The barrier layer comprises Al x In y Ga 1-x-y N, where 0≤x≤1, 0≤y≤1, x+y≤1, and The channel layer and the barrier layer differ from each other in at least one of the following aspects: polarization characteristics, band gap, and lattice constant.

19. The high electron mobility transistor according to claim 17, wherein... The gate structure includes a first semiconductor layer on the barrier layer, a second semiconductor layer on the first semiconductor layer, and a gate electrode on the second semiconductor layer. The first semiconductor layer and the second semiconductor layer differ in at least one aspect of doping concentration and host material.

20. The high electron mobility transistor of claim 17, wherein... The spacing between the field plate and the field dispersion layer in the width direction of the channel layer is smaller than the spacing between the gate structure and the drain electrode in the width direction.

21. The high electron mobility transistor of claim 17, wherein... The thickness of the field dispersion layer is less than the thickness of the barrier layer.

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