Method for preparing epitaxial structure, gallium nitride device and device preparation method

Abstract

The application provides a preparation method of an epitaxial structure, a gallium nitride device and a device preparation method. The preparation method of the epitaxial structure comprises the following steps: providing a substrate and cleaning the substrate; placing the cleaned substrate into a reaction cavity of a MOCVD device and inputting H2 and NH3 to perform high-temperature treatment; generating an AlN nucleation layer on the substrate after the high-temperature treatment; sequentially growing a buffer layer and a GaN channel layer on the AlN nucleation layer; epitaxially growing an AlN space insertion layer on the GaN channel layer; epitaxially growing an Al x GaN barrier layer on the AlN space insertion layer; epitaxially growing an AlN passivation layer on the Al x GaN barrier layer; epitaxially growing a SiN passivation layer on the AlN passivation layer; and the SiN / AlN / Al x GaN / AlN / GaN layers are all in-situ performed in the reaction cavity of the MOCVD device. Since the AlN grown by the MOCVD at high temperature is a single crystal, the lattice mismatch with the GaN is small, so that a high-quality interface can be formed, and the dynamic characteristics are greatly improved. The nitride semiconductor device using the epitaxial structure can effectively inhibit the "current collapse" effect of the device, and meanwhile, the voltage resistance performance of the nitride semiconductor device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a method for preparing an epitaxial structure, a gallium nitride device, and a method for preparing the device. Background Technology

[0002] Due to the numerous impurities and defects generated during epitaxial growth, the surface of the barrier layer in nitride semiconductor devices typically contains a large number of trapped states. During device switching, the dynamic charging and discharging process of these traps leads to increased on-resistance and decreased output current, resulting in device performance degradation known as "current collapse." To suppress this negative effect, surface passivation is a widely used technique. A highly effective passivation material is aluminum nitride (AlN). The high-density positive charge generated by polarization in a single-crystal AlN layer can compensate for the deep-level traps on the nitride surface, effectively suppressing current collapse and improving breakdown voltage.

[0003] AlN passivation layers on traditional nitride semiconductor devices are mostly deposited using ALD. The AlN obtained by this method is usually amorphous or polycrystalline. Because its growth temperature is relatively low, it still has certain defects. Summary of the Invention

[0004] This invention provides a method for preparing an epitaxial structure, a gallium nitride device, and a device preparation method, in order to improve the quality of the passivation layer used in nitride semiconductor devices.

[0005] According to a first aspect of the present invention, a method for preparing an epitaxial structure is provided, comprising:

[0006] S1: Provide a substrate and clean the substrate;

[0007] S2: Place the cleaned substrate into the reaction chamber of the metal-organic chemical vapor deposition equipment and introduce H2 and NH3 for high-temperature treatment;

[0008] S3: An AlN nucleation layer is formed on the substrate after high-temperature treatment;

[0009] S4: Grow a buffer layer on the AlN nucleation layer;

[0010] S5: Grow a GaN channel layer on the buffer layer;

[0011] S6: An epitaxial AlN spatial insertion layer on the GaN channel layer;

[0012] S7: Epitaxial Al on the AlN space insertion layer x GaN barrier layer;

[0013] S8: In the Al xAn epitaxial AIN passivation layer is formed on top of a GaN barrier layer;

[0014] S9: An epitaxial SiN passivation layer is formed on the AlN passivation layer;

[0015] In particular, steps S3 to S9 are all performed in situ in the reaction chamber of the metal-organic chemical vapor deposition equipment, and the AlN passivation layer is in a single crystal state.

[0016] Optionally, the preparation process conditions for the AlN spatial insertion layer in step S6 are as follows: AlN is epitaxially grown by introducing TMA and NH3 gas at 1000℃~1200℃.

[0017] Optionally, in step S7, Al x The fabrication process conditions for the GaN barrier layer are as follows: epitaxial growth of Al2O3 under TMG, TMA, and NH3 gases at 1000℃~1200℃. x GaN.

[0018] Optionally, the preparation process conditions for the AlN passivation layer in step S8 are as follows: AlN is epitaxially grown by introducing TMA and NH3 gas at 1000℃~1200℃.

[0019] Optionally, the preparation process conditions for the SiN passivation layer in step S9 are as follows: SiN is epitaxially grown by introducing SiH4 and NH3 gases at 1000℃~1200℃.

[0020] According to a second aspect of the present invention, a device structure for a nitride device is provided, comprising:

[0021] An epitaxial structure obtained using the method for preparing an epitaxial structure according to the first aspect of the present invention;

[0022] The source ohmic contact electrode and the drain ohmic contact electrode penetrate the SiN passivation layer and the AlN passivation layer, respectively, and then connect to the Al... x GaN barrier layer contact;

[0023] Gate structure;

[0024] A passivation isolation layer covers the source ohmic contact electrode, the drain ohmic contact electrode, and the gate structure;

[0025] The metal interconnect layer includes a source metal interconnect layer, a drain metal interconnect layer, and a gate metal interconnect layer. The source metal interconnect layer, drain metal interconnect layer, and gate metal interconnect layer penetrate the passivation isolation layer and are electrically connected to the source ohmic contact electrode, drain ohmic contact electrode, and gate structure, respectively.

[0026] Optionally, the gate structure includes a gate metal layer formed on the SiN passivation layer.

[0027] Optional:

[0028] The gate structure includes a gate metal layer and a gate dielectric layer;

[0029] The epitaxial structure has a gate groove that penetrates the SiN passivation layer, the AlN passivation layer, and the Al... x The GaN barrier layer stops on the AlN space insertion layer; the gate dielectric layer is deposited on the inner wall of the gate groove and covers the SiN passivation layer, the source ohmic contact electrode and the drain ohmic contact electrode.

[0030] The gate metal layer fills the gate recess and is located on the gate dielectric layer;

[0031] The passivation isolation layer is formed on the gate dielectric layer and the gate metal layer;

[0032] The source metal interconnect layer and the drain metal interconnect layer penetrate the passivation isolation layer and the gate dielectric layer, and are electrically connected to the source ohmic contact electrode and the drain ohmic contact electrode, respectively.

[0033] According to a third aspect of the present invention, a method for fabricating a nitride device relating to the second aspect and alternative embodiments of the present invention is provided.

[0034] include:

[0035] Prepare the epitaxial structure described in the first aspect of the present invention;

[0036] A source ohmic contact electrode and a drain ohmic contact electrode are formed. The source ohmic contact electrode and the drain ohmic contact electrode penetrate the SiN passivation layer and the AlN passivation layer, respectively, and then connect with the Al... x GaN barrier layer contact;

[0037] Forming a gate structure;

[0038] A passivation isolation layer is formed, which covers the source ohmic contact electrode, the drain ohmic contact electrode, and the gate structure;

[0039] A metal interconnect layer is formed, comprising a source metal interconnect layer, a drain metal interconnect layer, and a gate metal interconnect layer. The source metal interconnect layer, drain metal interconnect layer, and gate metal interconnect layer penetrate the passivation isolation layer and are electrically connected to the source ohmic contact electrode, the drain ohmic contact electrode, and the gate structure, respectively.

[0040] Optionally, forming the gate structure specifically includes:

[0041] A gate metal layer is formed on the SiN passivation layer.

[0042] Optionally, forming the gate structure specifically includes:

[0043] A gate trench is formed in the epitaxial structure, the gate trench penetrating the SiN passivation layer, the AlN passivation layer, and the Al... x The GaN barrier layer is then stopped on the AlN spatial insertion layer;

[0044] A gate dielectric layer is deposited on the inner wall of the gate recess and covers the SiN passivation layer, the source ohmic contact electrode, and the drain ohmic contact electrode.

[0045] A gate metal layer is deposited, which fills the gate recess and is located on the gate dielectric layer.

[0046] Optionally, the passivation isolation layer is formed on the gate dielectric layer and the gate metal layer; the source metal interconnect layer and the drain metal interconnect layer penetrate the passivation isolation layer and the gate dielectric layer and are electrically connected to the source ohmic contact electrode and the drain ohmic contact electrode, respectively.

[0047] Optionally, the method further includes, after forming the epitaxial structure and before forming the source and drain ohmic contact electrodes:

[0048] Active region isolation is performed on the SiN passivation layer, AlN passivation layer, and Al... x An isolation layer is formed in the GaN barrier layer, the AlN insertion layer, and the GaN layer.

[0049] The method for preparing the epitaxial structure provided by this invention involves in-situ epitaxy of SiN / AlN / Al using a metal-organic chemical vapor deposition (MOCVD) process. x GaN / AlN / GaN layer. Since the AlN grown at high temperatures using MOCVD is a single crystal, the lattice mismatch with GaN is very small, thus forming a high-quality interface. Furthermore, the strong polarization of single-crystal AlN can induce trapped states on the surface of positively fixed-charge-compensated (Al)GaN at the interface, thereby greatly improving its dynamic characteristics. The in-situ SiN dielectric can serve as the top layer of the epitaxial structure to prevent AlN / AlGaN / GaN from being oxidized in air, and also avoids surface damage in subsequent processes.

[0050] Furthermore, using this epitaxial structure can effectively suppress the "current collapse" effect of nitride semiconductor devices, while improving the voltage withstand performance of nitride semiconductor devices. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of a method for preparing an epitaxial structure according to an embodiment of the present invention;

[0053] Figure 2 This is a schematic cross-sectional view of the extensional structure provided in an embodiment of the present invention;

[0054] Figure 3 This is a schematic cross-sectional view of a depletion-type gallium nitride device provided in an embodiment of the present invention;

[0055] Figures 4A-4D This is a schematic cross-sectional view of the device structure at different fabrication stages of a depletion-type gallium nitride device according to an embodiment of the present invention;

[0056] Figure 5 This is a schematic cross-sectional view of the structure of an enhanced gallium nitride device provided in an embodiment of the present invention;

[0057] Figures 6A-6F This is a schematic cross-sectional view of the device structure at different fabrication stages of an enhanced gallium nitride device according to an embodiment of the present invention.

[0058] Explanation of reference numerals in the attached figures:

[0059] 201-substrate layer;

[0060] 202-AlN nucleation layer;

[0061] 203 - Buffer layer;

[0062] 204-GaN channel layer;

[0063] 205-AlN spatial insertion layer;

[0064] 206-Al x GaN barrier layer;

[0065] 207-AlN passivation layer;

[0066] 208-SiN passivation layer;

[0067] 209 - Active area isolation layer;

[0068] 210 - Source Ohmic Contact Electrode;

[0069] 211 - Drain ohmic contact electrode;

[0070] 212 - Gate metal layer;

[0071] 213 - Passivation layer;

[0072] 214-Source metal interconnect layer;

[0073] 215 - Drain metal interconnect layer;

[0074] 216 - Gate metal interconnect layer;

[0075] 217 - Gate dielectric layer. Detailed Implementation

[0076] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0077] In the description of this invention, it should be understood that the terms "upper part", "lower part", "upper end", "lower end", "lower surface", "upper surface", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0078] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0079] In the description of this invention, "a plurality of" means multiple, such as two, three, four, etc., unless otherwise explicitly specified.

[0080] In the description of this invention, unless otherwise explicitly specified and limited, the term "connection" and other such terms should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a mechanical connection, an electrical connection, or a connection that allows communication between the components; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0081] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0082] Gallium nitride high electron mobility transistors (AlGaN / GaN HEMTs) are a new generation of power switching devices, attracting widespread and intense research interest from academia and industry. Due to the numerous advantages of gallium nitride materials, such as wide bandgap, high electron mobility, and high electron saturation velocity, these devices exhibit high breakdown voltage and low power consumption, and are suitable for operation at high frequencies. Strong piezoelectric polarization and spontaneous polarization effects induce a high-concentration, high-electron-mobility two-dimensional electron gas (2DEG) in the AlGaN / GaN heterojunction. However, due to defects generated during heteroepitaxial growth and impurities present in the epitaxial process, a large number of trapped states typically exist on the surface of the AlGaN barrier layer, the AlGaN / GaN interface, and the buffer layer. During device switching, the dynamic charging and discharging process of these traps leads to increased on-resistance and decreased output current, resulting in device performance degradation known as "current collapse." To suppress this negative effect, surface passivation is considered an effective method.

[0083] Oxides grown via atomic layer deposition (ALD), such as Al₂O₃, Hf₂O, or SiO₂, are commonly used passivation methods. However, the presence of the precursor O may induce some deep-level traps. SiN grown by plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) does not have the same density as oxide films grown by ALD and generally requires a field plate to suppress current collapse. Another very effective passivation material is AlN. The high-density positive charge generated by polarization effect in a single-crystal AlN layer can compensate for the slow traps on the (Al)GaN surface. Therefore, AlN can effectively suppress current collapse and improve breakdown voltage without a field plate.

[0084] However, the applicant discovered that existing AlN passivation layers are usually obtained by ALD deposition. Although the AlN film deposited by ALD is relatively dense, the entire ALD process cannot be self-limiting because ALD is designed to suppress the thermal decomposition of the precursor at high temperatures. Therefore, the growth temperature of AlN films deposited by ALD is usually low (usually 200-300℃). The AlN films grown at low temperatures are mostly amorphous, and therefore still have certain defects, which affect the passivation effect when used as a passivation layer.

[0085] High-quality thin films with low defect density are expected to significantly improve the surface properties of AlGaN when used as passivation layers.

[0086] The applicant, through research on the properties of thin films under various conditions, discovered that single-crystal thin films possess the highest quality. Their fabrication generally requires energy to achieve atomic ordering; therefore, high-temperature methods such as MOCVD can be used to prepare high-quality single-crystal thin films. In gallium nitride (GaN) devices, GaN layer epitaxy is typically performed on sapphire, SiC, and Si using metal-organic chemical vapor deposition (MOCVD). This type of MOCVD can usually achieve in-situ epitaxy of GaN, AlN, and Al... x Ga 1-x Nitrides such as N and SiN are used, and the AlN grown at high temperature by MOCVD is a single crystal with a small lattice mismatch with GaN, thus forming a high-quality interface. Furthermore, the strong polarization of single-crystal AlN can induce the generation of positive fixed charge compensation trap states on the surface of (Al)GaN at the interface, thereby greatly improving its dynamic characteristics. The in-situ SiN dielectric can be used as the top layer of the epitaxial structure to prevent AlN / AlGaN / GaN from being oxidized in air, and can also avoid surface damage in subsequent processes.

[0087] Based on this, the present invention provides a method for fabricating an in-situ SiN / AlN / AlGaN / GaN epitaxial structure, and proposes depletion-mode and enhancement-mode gallium nitride device structures and corresponding fabrication processes for this epitaxial structure. This proposed epitaxial structure can significantly improve the surface states of the AlGaN barrier layer, thereby significantly suppressing the "current collapse" phenomenon in gallium nitride devices.

[0088] To facilitate the explanation of the epitaxial structure fabrication method and the gallium nitride device and device fabrication method comprising the epitaxial structure provided in the embodiments of the present invention, the following will be combined with Figures 1 to 6F Describe it.

[0089] Please refer to Figure 1 In this embodiment of the invention, the method for preparing the epitaxial structure includes steps S1-S8, as follows:

[0090] S1: Provide a substrate 201 and clean the substrate.

[0091] In specific examples, the substrate material can be Si, SiC, sapphire, etc., and the cleaning method can be a wet process, using solutions such as acetone, isopropanol, hydrochloric acid, and hydrofluoric acid to perform wet cleaning on the Si, SiC, sapphire, etc.

[0092] S2: Place the cleaned substrate into the reaction chamber of the metal-organic chemical vapor deposition equipment and introduce H2 and NH3 for high-temperature treatment.

[0093] The specific high-temperature treatment method is as follows: the temperature of the reaction chamber is raised to 900℃~1100℃, H2 is introduced into the reaction chamber to clean the substrate surface, and then NH3 is introduced to nitrid the substrate surface.

[0094] S3: An AlN nucleation layer 202 is formed on the substrate after high-temperature treatment.

[0095] Specifically, the AlN nucleation layer is formed by setting the reaction chamber temperature to 500℃~700℃, introducing precursor gases TMA and NH3, and reacting to generate the AlN nucleation layer. However, it should be understood that the present invention is not limited thereto, and other precursor gases are also within the scope of protection of the present invention. The generated AlN nucleation layer has a thickness of 150~250nm.

[0096] S4: Grow a buffer layer 203 on the AlN nucleation layer 202.

[0097] Specifically, the buffer layer is formed by introducing TMG, TMA and NH3 gases at 1000℃~1200℃ to generate a buffer layer with a thickness of 2~5μm.

[0098] S5: Grow a GaN channel layer 204 on the buffer layer 203.

[0099] Specifically, the GaN channel layer is formed by maintaining the temperature at 1000℃~1200℃, introducing TMG and NH3 gas, and epitaxially generating the GaN channel layer, wherein the thickness of the buffer layer is 200~300nm.

[0100] S6: An epitaxial AlN space insertion layer 205 is formed on the GaN channel layer 204.

[0101] S7: Epitaxial Al on the AlN space insertion layer 205 x GaN barrier layer 206;

[0102] S8: In the Al x An epitaxial AlN passivation layer 207 is formed on a GaN barrier layer 206;

[0103] S9: An epitaxial SiN passivation layer 208 is formed on the AlN passivation layer 207;

[0104] In particular, steps S3 to S9 are all performed in situ in the reaction chamber of the metal-organic chemical vapor deposition equipment, and the AlN passivation layer is in a single crystal state.

[0105] In one embodiment, the preparation process conditions for the AlN space-intercalation layer 205 in step S6 are as follows: the AlN space-intercalation layer is formed by setting the reaction chamber temperature at 500℃~700℃, introducing precursor gases TMA and NH3, and reacting to generate the AlN space-intercalation layer. However, it should be understood that the present invention is not limited thereto, and other precursor gases are also within the scope of protection of the present invention. The thickness of the generated AlN space-intercalation layer is 0.8~1.2nm.

[0106] As one implementation method, in step S7, Al x The fabrication process conditions for the GaN barrier layer 206 are as follows: epitaxial growth of Al using TMG, TMA, and NH3 gases. x GaN, where Al x The molecular proportion X of Al in the GaN structure is 0.2 to 0.3.

[0107] In one embodiment, the preparation conditions for the AlN passivation layer 207 in step S8 are as follows: the reaction chamber temperature is set at 500℃~700℃, and precursor gases TMA and NH3 are introduced to react and generate the AlN passivation layer. However, it should be understood that the present invention is not limited thereto, and other precursor gases are also within the scope of protection of the present invention. The thickness of the generated AlN passivation layer is 2~5nm.

[0108] In this embodiment, the AlN grown by high temperature via MOCVD is a single crystal structure with a small lattice mismatch with GaN, thus forming a high-quality interface. Furthermore, the strong polarization of the single crystal AlN can induce the generation of trap states on the surface of the positive fixed charge compensated (Al)GaN at the interface, which can greatly improve the surface states and dynamic characteristics of the AlGaN barrier layer, thereby significantly suppressing the "current collapse" phenomenon in gallium nitride devices.

[0109] In one embodiment, the preparation process conditions of the SiN passivation layer 208 in step S9 are as follows: SiN is epitaxially grown by introducing SiH4 and NH3 gases at 1000℃~1200℃, and the thickness of the generated SiN passivation layer is 10~60nm.

[0110] The in-situ SiN dielectric grown using this method can serve as the top layer of the epitaxial structure to prevent AlN / AlGaN / GaN from being oxidized in air, and can also avoid surface damage in subsequent processes.

[0111] In a second embodiment of the present invention, a device structure for a nitride device is also provided, such as... Figure 3 , Figure 5 As shown, it includes:

[0112] The epitaxial structure obtained by the method for preparing the epitaxial structure according to the first embodiment of the present invention, such as... Figure 2 As shown;

[0113] Source ohmic contact electrode 210 and drain ohmic contact electrode 211, the source ohmic contact electrode and the drain ohmic contact electrode penetrate the SiN passivation layer 208 and the AlN passivation layer 207 and then connect with the Al x GaN barrier layer 206 contact;

[0114] Gate structure;

[0115] A passivation isolation layer covers the source ohmic contact electrode 210, the drain ohmic contact electrode 211, and the gate structure;

[0116] The metal interconnect layer includes a source metal interconnect layer 214, a drain metal interconnect layer 215, and a gate metal interconnect layer 216. The source metal interconnect layer 214, the drain metal interconnect layer 215, and the gate metal interconnect layer 216 penetrate the passivation isolation layer 213 and are electrically connected to the source ohmic contact electrode 210, the drain ohmic contact electrode 211, and the gate structure, respectively.

[0117] As one implementation method, such as Figure 3 As shown, the gate structure includes a gate metal layer 212, which is formed on the SiN passivation layer 208.

[0118] As one implementation method, such as Figure 5 As shown, the gate structure includes a gate metal layer 212 and a gate dielectric layer 217;

[0119] The epitaxial structure has a gate groove that penetrates the SiN passivation layer 208, the AlN passivation layer 207, and the Al... x The GaN barrier layer 206 stops on the AlN space insertion layer 205; the gate dielectric layer 217 is deposited on the inner wall of the gate groove and covers the SiN passivation layer 208, the source ohmic contact electrode 210 and the drain ohmic contact electrode 21.

[0120] The gate metal layer 212 fills the gate recess and is located on the gate dielectric layer 217;

[0121] The passivation isolation layer 213 is formed on the gate dielectric layer 217 and the gate metal layer 212;

[0122] The source metal interconnect layer 214 and the drain metal interconnect layer 215 penetrate the passivation isolation layer 213 and the gate dielectric layer 217 and are electrically connected to the source ohmic contact electrode 210 and the drain ohmic contact electrode 211, respectively.

[0123] In a third embodiment of the present invention, a method for fabricating the nitride device involved in the second embodiment of the present invention is provided, such as... Figures 4A-4D As shown in Figures 6A-6F, the method includes:

[0124] The epitaxial structure is obtained by the method for preparing the epitaxial structure according to the first embodiment of the present invention, such as... Figure 2 As shown;

[0125] A source ohmic contact electrode 210 and a drain ohmic contact electrode 211 are formed. The source ohmic contact electrode 210 and the drain ohmic contact electrode 211 penetrate the SiN passivation layer 208 and the AlN passivation layer 207, respectively, and then connect with the Al... x GaN barrier layer 206 contact;

[0126] Forming a gate structure;

[0127] A passivation isolation layer 213 is formed, which covers the source ohmic contact electrode 210, the drain ohmic contact electrode 211, and the gate structure;

[0128] A metal interconnect layer is formed, the metal interconnect layer including a source metal interconnect layer 214, a drain metal interconnect layer 215 and a gate metal interconnect layer 216. The source metal interconnect layer 214, the drain metal interconnect layer 215 and the gate metal interconnect layer 216 penetrate the passivation isolation layer 213 and are electrically connected to the source ohmic contact electrode 20, the drain ohmic contact electrode 211 and the gate structure, respectively.

[0129] As one implementation, the formation of the gate structure, such as Figures 4A-4D As shown, it specifically includes:

[0130] A gate metal layer 212 is formed on the SiN passivation layer 208.

[0131] As one implementation method, such as Figures 6A-6F As shown, forming the gate structure specifically includes:

[0132] A gate trench is formed in the epitaxial structure, the gate trench penetrating the SiN passivation layer 208, the AlN passivation layer 207, and the Al... x The GaN barrier layer 206 then stops on the AlN spatial insertion layer 205;

[0133] A gate dielectric layer 217 is deposited on the inner wall of the gate recess and covers the SiN passivation layer 208, the source ohmic contact electrode 210 and the drain ohmic contact electrode 21.

[0134] A gate metal layer 212 is deposited, which fills the gate recess and is located on the gate dielectric layer 217.

[0135] In one embodiment, the passivation isolation layer 213 is formed on the gate dielectric layer 217 and the gate metal layer 212; the source metal interconnect layer 214 and the drain metal interconnect layer 215 penetrate the passivation isolation layer 213 and the gate dielectric layer 217 and are electrically connected to the source ohmic contact electrode 210 and the drain ohmic contact electrode 211, respectively.

[0136] In one implementation, the method further includes, after forming the epitaxial structure and before forming the source and drain ohmic contact electrodes:

[0137] Active region isolation is performed in the SiN passivation layer 208, AlN passivation layer 207, and Al... x An isolation layer 209 is formed in the GaN barrier layer 206, the AlN insertion layer 205, and the GaN layer 204.

[0138] The nitride device prepared by this method, due to the use of the epitaxial layer in the first embodiment of the present invention, can effectively suppress the "current collapse" effect of the nitride semiconductor device and improve the voltage withstand performance of the nitride semiconductor device.

[0139] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing an epitaxial structure, characterized in that, include: S1: Provide a substrate and clean the substrate; S2: Place the cleaned substrate into the reaction chamber of the metal-organic chemical vapor deposition equipment and introduce H2 and NH3 for high-temperature treatment; S3: An AlN nucleation layer is formed on the substrate after high-temperature treatment; S4: Grow a buffer layer on the AlN nucleation layer; S5: Grow a GaN channel layer on the buffer layer; S6: An epitaxial AlN spatial insertion layer on the GaN channel layer; S7: Epitaxial Al on the AlN space insertion layer x GaN barrier layer; S8: In the Al x On a GaN barrier layer, TMA and NH3 gas are introduced at 1000℃~1200℃, and an epitaxial AlN passivation layer is formed, wherein the thickness of the AlN passivation layer is 2nm~5nm. S9: On the AlN passivation layer, SiH4 and NH3 gases are introduced at 1000℃~1200℃ to form an epitaxial SiN passivation layer. The thickness of the SiN passivation layer is 10nm~60nm. The AlN passivation layer and the SiN passivation layer together constitute the surface passivation stack of the epitaxial structure. In particular, all of the above steps S3 to S9 are performed in situ in the reaction chamber of the metal-organic chemical vapor deposition equipment, and the AlN passivation layer is in a single crystal state.

2. The method for preparing the epitaxial structure according to claim 1, characterized in that, The preparation process conditions for the AlN spatial insertion layer in step S6 are as follows: AlN is epitaxially grown at 1000℃~1200℃ by introducing TMA and NH3 gas.

3. The method for preparing the epitaxial structure according to claim 1, characterized in that, In step S7, Al x The fabrication process conditions for the GaN barrier layer are as follows: epitaxial growth of Al2O3 under TMG, TMA, and NH3 gases at 1000℃~1200℃. x GaN.

4. A gallium nitride power device, characterized in that, include: The epitaxial structure obtained by the method for preparing the epitaxial structure according to any one of claims 1 to 3; The source ohmic contact electrode and the drain ohmic contact electrode penetrate the SiN passivation layer and the AlN passivation layer, respectively, and then connect to the Al... x GaN barrier layer contact; Gate structure; A passivation isolation layer covers the source ohmic contact electrode, the drain ohmic contact electrode, and the gate structure; The metal interconnect layer includes a source metal interconnect layer, a drain metal interconnect layer, and a gate metal interconnect layer. The source metal interconnect layer, drain metal interconnect layer, and gate metal interconnect layer penetrate the passivation isolation layer and are electrically connected to the source ohmic contact electrode, drain ohmic contact electrode, and gate structure, respectively.

5. The gallium nitride power device as described in claim 4, characterized in that, The gate structure includes a gate metal layer formed on the SiN passivation layer.

6. The gallium nitride power device as described in claim 4, characterized in that, The gate structure includes a gate metal layer and a gate dielectric layer; The epitaxial structure has a gate groove that penetrates the SiN passivation layer, the AlN passivation layer, and the Al... x The GaN barrier layer stops on the AlN space insertion layer; the gate dielectric layer is deposited on the inner wall of the gate groove and covers the SiN passivation layer, the source ohmic contact electrode and the drain ohmic contact electrode. The gate metal layer fills the gate recess and is located on the gate dielectric layer; The passivation isolation layer is formed on the gate dielectric layer and the gate metal layer; The source metal interconnect layer and the drain metal interconnect layer penetrate the passivation isolation layer and the gate dielectric layer, and are electrically connected to the source ohmic contact electrode and the drain ohmic contact electrode, respectively.

7. A method for fabricating a gallium nitride power device, used to fabricate the gallium nitride power device as described in any one of claims 4 to 6, characterized in that, The method includes: Prepare the epitaxial structure; A source ohmic contact electrode and a drain ohmic contact electrode are formed. The source ohmic contact electrode and the drain ohmic contact electrode penetrate the SiN passivation layer and the AlN passivation layer, respectively, and then connect with the Al... x GaN barrier layer contact; Forming a gate structure; A passivation isolation layer is formed, which covers the source ohmic contact electrode, the drain ohmic contact electrode, and the gate structure; A metal interconnect layer is formed, comprising a source metal interconnect layer, a drain metal interconnect layer, and a gate metal interconnect layer. The source metal interconnect layer, drain metal interconnect layer, and gate metal interconnect layer penetrate the passivation isolation layer and are electrically connected to the source ohmic contact electrode, the drain ohmic contact electrode, and the gate structure, respectively.

8. The method for fabricating a gallium nitride power device as described in claim 7, characterized in that, The formation of the gate structure specifically includes: A gate metal layer is formed on the SiN passivation layer.

9. The method for fabricating a gallium nitride power device as described in claim 8, characterized in that, The formation of the gate structure specifically includes: A gate trench is formed in the epitaxial structure, the gate trench penetrating the SiN passivation layer, the AlN passivation layer, and the Al... x The GaN barrier layer is then stopped on the AlN spatial insertion layer; A gate dielectric layer is deposited on the inner wall of the gate recess and covers the SiN passivation layer, the source ohmic contact electrode, and the drain ohmic contact electrode. A gate metal layer is deposited, which fills the gate recess and is located on the gate dielectric layer.

10. The method for fabricating a gallium nitride power device as described in claim 9, characterized in that, The passivation isolation layer is formed on the gate dielectric layer and the gate metal layer; the source metal interconnect layer and the drain metal interconnect layer penetrate the passivation isolation layer and the gate dielectric layer and are electrically connected to the source ohmic contact electrode and the drain ohmic contact electrode, respectively.

11. The method for fabricating a gallium nitride power device according to any one of claims 7 to 10, characterized in that, The method, after forming the epitaxial structure and before forming the source and drain ohmic contact electrodes, also includes: Active region isolation is performed on the SiN passivation layer, AlN passivation layer, and Al... x An isolation layer is formed in the GaN barrier layer, the AlN insertion layer, and the GaN layer.

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