Semiconductor device

Abstract

The present application relates to a semiconductor device. According to one embodiment, the semiconductor device comprises: an insulating substrate; a gate electrode disposed on the insulating substrate; a first insulating layer covering the gate electrode; an oxide semiconductor disposed directly above the gate electrode and on the first insulating layer; a source electrode in contact with the oxide semiconductor; and a drain electrode in contact with the oxide semiconductor, each of the source electrode and the drain electrode comprising: an oxide conductive layer in contact with the oxide semiconductor; a first metal layer stacked on the oxide conductive layer; a second metal layer formed of a different material from the first metal layer and stacked on the first metal layer; and a third metal layer formed of the same material as the first metal layer and stacked on the second metal layer.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority based on Japanese Patent Application No. 2021-115890, filed on July 13, 2021, and incorporates all the contents of that Japanese application. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0004] Regarding liquid crystal display devices, a technique has been proposed in which a transistor with an oxide semiconductor is provided in the pixel circuit of the display area, and a transistor with a silicon semiconductor is provided in the driving circuit of the peripheral area. Summary of the Invention

[0005] The purpose of this implementation is to provide a semiconductor device capable of miniaturizing transistors.

[0006] According to one embodiment, the semiconductor device includes:

[0007] An insulating substrate; a gate electrode disposed on the insulating substrate; a first insulating layer covering the gate electrode; an oxide semiconductor disposed directly above the gate electrode and on the first insulating layer; a source electrode connected to the oxide semiconductor; and a drain electrode connected to the oxide semiconductor.

[0008] Each of the above-mentioned source and drain electrodes comprises: an oxide conductive layer in contact with the oxide semiconductor; a first metal layer stacked on the oxide conductive layer; a second metal layer formed of a material different from the first metal layer and stacked on the first metal layer; and a third metal layer formed of the same material as the first metal layer and stacked on the second metal layer.

[0009] According to one embodiment, the semiconductor device includes:

[0010] An insulating substrate; a gate electrode disposed on the insulating substrate; a first insulating layer covering the gate electrode; an oxide semiconductor disposed directly above the gate electrode and on the first insulating layer; a source electrode connected to the oxide semiconductor; a drain electrode connected to the oxide semiconductor; a passivation film covering the source electrode and the drain electrode; and an upper gate electrode disposed directly above the gate electrode, on the passivation film, and electrically connected to the gate electrode.

[0011] Each of the above-mentioned gate, source, drain and upper gate comprises: a first metal layer containing molybdenum (Mo); a second metal layer containing aluminum (Al) and stacked on the first metal layer; and a third metal layer containing molybdenum (Mo) and stacked on the second metal layer.

[0012] According to the implementation method, a semiconductor device capable of miniaturizing transistors can be provided. Attached Figure Description

[0013] Figure 1 This is a top view showing the configuration of a display device DSP, which is an example of a semiconductor device.

[0014] Figure 2 This is a cross-sectional view showing an example configuration of a semiconductor device 1 equipped with a transistor TR.

[0015] Figure 3 It is Figure 2 The image shows an enlarged cross-sectional view of region A, which includes the drain electrode DE.

[0016] Figure 4 This is a graph showing the relationship between the threshold voltage of transistor TR and the channel length.

[0017] Figure 5 This is a cross-sectional view showing another configuration example of a semiconductor device 1 equipped with a transistor TR.

[0018] Figure 6 This is a cross-sectional view showing another configuration example of a semiconductor device 1 equipped with a transistor TR.

[0019] Figure 7 This is a cross-sectional view showing another configuration example of a semiconductor device 1 equipped with a transistor TR.

[0020] Figure 8 This is a cross-sectional view showing another configuration example of a semiconductor device 1 equipped with a transistor TR. Detailed Implementation

[0021] Hereinafter, this embodiment will be described with reference to the accompanying drawings. Furthermore, the disclosure is merely an example, and appropriate modifications that can be readily conceived by those skilled in the art while maintaining the spirit of the invention are of course included within the scope of this invention. Additionally, in the drawings, to make the description clearer, the width, thickness, shape, etc., of various parts are sometimes schematically shown compared to the actual form; this is merely an example and does not limit the interpretation of the invention. Furthermore, in this specification and the various drawings, constituent elements that perform the same or similar functions as those described with respect to prior art are marked with the same reference numerals, and sometimes repeated detailed descriptions are appropriately omitted.

[0022] Furthermore, in the accompanying drawings, for ease of understanding, the mutually orthogonal X-axis, Y-axis, and Z-axis are shown. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis as the second direction Y, and the direction along the Z-axis as the third direction Z. The surface defined by the X-axis and Y-axis is called the XY plane, and the observation of the XY plane is referred to as the top view.

[0023] The semiconductor device of this embodiment can be applied to various display devices such as liquid crystal display devices, organic electroluminescent display devices, electrophoretic display devices, and LED display devices, as well as various sensors such as electrostatic capacitive sensors and optical sensors, and electronic devices such as lighting devices.

[0024] Figure 1 This is a top view showing the configuration of a display device DSP, which is an example of a semiconductor device.

[0025] The display device DSP has a display area DA for displaying images and a peripheral area (non-display area) SA surrounding the display area DA. Figure 1 In the example shown, the surrounding area SA is formed as a frame that surrounds the display area DA.

[0026] The display device DSP has gate drivers GD1 and GD2 and source driver SD in the peripheral area SA. Gate drivers GD1 and GD2 each have multiple shift registers SR. Shift registers SR have a first transistor TR1. In this way, gate drivers GD1 and GD2 are formed together with the elements of the display area DA on the same substrate.

[0027] The display device DSP includes, in the display area DA, multiple pixels PX, multiple gate lines GL, multiple source lines SL, multiple capacitor lines CW, and a common electrode CE. The multiple pixels PX are arranged in a matrix in the first direction X and the second direction Y.

[0028] Multiple gate lines GL extend along a first direction X and are arranged at intervals along a second direction Y. Gate lines GL are electrically connected to gate drivers GD1 and GD2. For example, the odd-numbered gate line GL is connected to the shift register SR of gate driver GD1, and the even-numbered gate line GL is connected to the shift register SR of gate driver GD2. Each gate line GL is driven by gate drivers GD1 and GD2.

[0029] Multiple source lines SL extend along the second direction Y and are arranged at intervals along the first direction X. In the display area DA, the multiple source lines SL intersect with multiple gate lines GL. The source lines SL are electrically connected to source drivers SD. Each source line SL is driven by a source driver SD.

[0030] Multiple capacitor wires CW extend along a first direction X or a second direction Y. These multiple capacitor wires CW are connected, for example, in the peripheral region SA to a voltage supply unit Vpc that supplies a specified voltage.

[0031] The common electrode CE is distributed across multiple pixel PX areas. The common electrode CE is connected to the voltage supply unit Vcom, which supplies a specified voltage.

[0032] As in Figure 1 As shown in the magnified view, each pixel PX has a second transistor TR2 and a pixel electrode PE. As described later, the first transistor TR1 and the second transistor TR2 are, for example, composed of thin-film transistors (TFTs). The second transistor TR2 is electrically connected to a gate line GL and a source line SL. The gate line GL is electrically connected to the second transistor TR2 of each pixel PX arranged in the first direction X. The source line SL is electrically connected to the second transistor TR2 of each pixel PX arranged in the second direction Y.

[0033] The pixel electrode PE is electrically connected to the second transistor TR2. Each pixel electrode PE is opposite to the common electrode CE. Capacitor C1 is formed between the pixel electrode PE and the capacitor line CW. Capacitor C2 is formed between the common electrode CE and the pixel electrode PE.

[0034] Next, the transistor TR, which can be applied to at least one of the first transistor TR1 and the second transistor TR2, will be described.

[0035] Figure 2 This is a cross-sectional view showing an example configuration of a semiconductor device 1 equipped with a transistor TR.

[0036] The semiconductor device 1 includes: an insulating substrate 10, insulating layers 11 to 14, a transistor TR, and a component electrode 30.

[0037] The transistor TR comprises: an oxide semiconductor SC, a gate (lower gate) GE1, a source SE, a drain DE, and a gate (upper gate) GE2. Gates GE1 and GE2 are electrically connected to each other and are... Figure 1 The gate line GL is electrically connected. However, the gate GE2 can also be omitted. The source SE is electrically connected to the source line SL. The drain DE is separated from the source SE and electrically connected to the connection electrode CN. Element electrode 30 is electrically connected to the connection electrode CN.

[0038] The insulating substrate 10 is formed of insulating materials such as glass and resin film. The gate GE1 is disposed on the insulating substrate 10.

[0039] The insulating layer (first insulating layer) 11 is an inorganic insulating layer disposed on the insulating substrate 10 and covering the gate GE1. The insulating layer 11 is, for example, a stack of a silicon nitride layer 111 and a silicon oxide layer 112. The silicon nitride layer 111 directly covers the insulating substrate 10 and the gate GE1. The silicon oxide layer 112 is directly stacked on top of the silicon nitride layer 111. For example, the silicon oxide layer 112 is thinner than the silicon nitride layer 111. Alternatively, the insulating layer 11 may also be a single layer of silicon oxide.

[0040] The oxide semiconductor SC is located directly above the gate GE1 and is disposed on the insulating layer 11.

[0041] The insulating layer (second insulating layer or etch barrier layer) 12 is an inorganic insulating layer disposed on the insulating layer 11 and covering the oxide semiconductor SC. The insulating layer 12 has through holes CH1 and CH2 extending to the oxide semiconductor SC. The insulating layer 12 is a silicon oxide layer. That is, the oxide semiconductor SC is in contact with the silicon oxide layer 112 of the insulating layer 11 and the insulating layer 12, which is a silicon oxide layer.

[0042] The source electrode SE is disposed on the insulating layer 12 and is connected to the oxide semiconductor SC at the through-hole CH1. The drain electrode DE is disposed on the insulating layer 12 and is connected to the oxide semiconductor SC at the through-hole CH2. The source electrode SE and the drain electrode DE are located in the same layer, which is a conductive layer formed of the same material.

[0043] The insulating layer 13 (passivation film) is an inorganic insulating layer disposed on the insulating layer 12 and covering the source electrode SE and the drain electrode DE. Furthermore, the insulating layer 13 is connected to the insulating layer 12 between the source electrode SE and the drain electrode DE. The insulating layer 13 has a through-hole CH3 extending to the drain electrode DE. The insulating layer 13 is, for example, a laminate of a silicon nitride layer and a silicon oxide layer, but is not limited thereto; it can also be a single layer of silicon nitride.

[0044] Gate GE2 is located directly above gate GE1 and is disposed on insulating layer 13. Connecting electrode CN is disposed on insulating layer 13 and is connected to drain DE at through-hole CH3. Gate GE2 and connecting electrode CN are located in the same layer, which is a conductive layer formed of the same material.

[0045] An insulating layer 14 is disposed on the insulating layer 13 and covers the gate electrode GE2 and the connection electrode CN. The insulating layer 14 has a through-hole CH4 extending to the connection electrode CN. The insulating layer 14 is, for example, a transparent organic insulating layer formed of acrylic acid or polyimide.

[0046] The component electrode 30 is disposed on the insulating layer 14 and is connected to the connecting electrode CN at the through hole CH4. The component electrode 30 constitutes a pixel electrode, lower electrode, anode, or cathode in various electronic devices. The component electrode 30 is, for example, a transparent electrode formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). In addition, the component electrode 30 can also be a metal electrode formed of a metal material such as silver or aluminum. Furthermore, the component electrode 30 can also be a stack of transparent electrodes and metal electrodes. For example, the component electrode 30 can be constructed as a stack of transparent electrodes, metal electrodes, and transparent electrodes stacked sequentially, or it can be constructed as a stack of three or more layers.

[0047] The gate GE1 is a multilayer comprising a first metal layer M11, a second metal layer M12, and a third metal layer M13. The first metal layer M11 is connected to the insulating substrate 10. The second metal layer M12 is stacked on the first metal layer M11. The third metal layer M13 is stacked on the second metal layer M12.

[0048] The first metal layer M11 and the third metal layer M13 are formed from the same material. The second metal layer M12 is formed from a different material than the first metal layer M11. In one example, the first metal layer M11 and the third metal layer M13 are layers containing molybdenum (Mo), and the second metal layer M12 is a layer containing aluminum (Al). In this specification, the molybdenum-containing layer can be a layer formed from elemental molybdenum or a layer formed from a molybdenum alloy. Similarly, the aluminum-containing layer can be a layer formed from elemental aluminum or a layer formed from an aluminum alloy.

[0049] The source (SE) and drain (DE) are each multilayer structures comprising an oxide conductive layer M20, a first metal layer M21, a second metal layer M22, and a third metal layer M23. The oxide conductive layer M20 serves as the substrate layer of the first metal layer M21 and is connected to the insulating layer 12 and the oxide semiconductor SC. The first metal layer M21 is stacked on the oxide conductive layer M20. The second metal layer M22 is stacked on the first metal layer M21. The third metal layer M23 is stacked on the second metal layer M22.

[0050] The first metal layer M21 and the third metal layer M23 are formed from the same material. The second metal layer M22 is formed from a different material than the first metal layer M21. In one example, the oxide conductive layer M20 is formed from indium tin oxide (ITO), but it can also be formed from other transparent conductive materials such as indium zinc oxide (IZO). The first metal layer M21 and the third metal layer M23 are layers containing molybdenum (Mo), and the second metal layer M22 is a layer containing aluminum (Al).

[0051] The gate GE2 and the connecting electrode CN are each a multilayer having a first metal layer M31, a second metal layer M32, and a third metal layer M33. The first metal layer M31 is connected to the insulating layer 13. The second metal layer M32 is stacked on the first metal layer M31. The third metal layer M33 is stacked on the second metal layer M32.

[0052] The first metal layer M31 and the third metal layer M33 are formed of the same material. The second metal layer M32 is formed of a different material than the first metal layer M31. In one example, the first metal layer M31 and the third metal layer M33 are layers containing molybdenum (Mo), and the second metal layer M32 is a layer containing aluminum (Al).

[0053] The first metal layers M11, M21, M31 and the third metal layers M13, M23, M33 mentioned above can also be replaced with layers containing titanium (Ti). In addition, the gate GE2 and the connecting electrode CN can also be layers formed of elemental molybdenum.

[0054] Figure 3 It is Figure 2 The image shows an enlarged cross-sectional view of region A, which includes the drain electrode DE.

[0055] The side surface S22 of the second metal layer M22 is located further outward than the side surface S23 of the third metal layer M23. The side surface S21 of the first metal layer M21 is located further outward than the side surface S22 of the second metal layer M22. The side surface S20 (first side surface) of the oxide conductive layer M20 is located further outward than the side surface S21 (second side surface) of the first metal layer M21.

[0056] In addition, the slope θ20 of side surface S20 relative to the upper surface 12T of insulating layer 12 is less than the slope θ21 of side surface S21 relative to the upper surface 20T of oxide conductive layer M20 (θ20 < θ21).

[0057] This cross-sectional shape is formed not only at the end of the drain electrode DE, but also at the end of the source electrode SE.

[0058] These drains (DE) and sources (SE) are formed, for example, as described below.

[0059] First, an ITO layer, a molybdenum layer, an aluminum layer, and another molybdenum layer are sequentially formed on the insulating layer 12. Then, a photoresist of a predetermined shape is formed on the molybdenum layer. Using this photoresist as a mask, the image is immersed in an etching solution (wet etching). If ITO, molybdenum, and aluminum coexist in the etching solution, the etching of molybdenum and aluminum is accelerated because the immersion potential of ITO is higher than that of molybdenum or aluminum, while the etching of ITO is suppressed. Due to this electrochemical mechanism, a layer with good reproducibility can be formed. Figure 3 The electrode has a well-defined tapered shape.

[0060] Then, an insulating layer 13 is formed by vapor deposition. The insulating layer 13 is uniformly deposited on each side of the drain DE. Therefore, no cracks or pores are formed in the insulating layer 13, and the drain DE can be reliably covered by the insulating layer 13. For the same reason, the source SE can also be reliably covered by the insulating layer 13. Therefore, the infiltration of moisture through the insulating layer 13 is suppressed, the performance degradation of the transistor TR is suppressed, and the reliability is improved.

[0061] In the semiconductor device 1 described above, the other electrodes constituting the transistor TR, namely the gates GE1 and GE2, and the connecting electrode CN, are, as described above, a molybdenum / aluminum / molybdenum stack, which can be patterned by the same wet etching process as the drain DE.

[0062] Therefore, manufacturing costs can be reduced compared to the case where various electrodes are formed from materials that require dry etching.

[0063] An insulating layer 12, serving as an etch barrier layer, is sandwiched between the oxide semiconductor SC and the source SE, and between the oxide semiconductor SC and the drain DE. Therefore, during wet etching to form the source SE and drain DE, the oxide semiconductor SC is almost never exposed to the etchant, thus suppressing damage to the oxide semiconductor SC. Furthermore, this expands the options for materials used to form the oxide semiconductor SC.

[0064] The source (SE) and drain (DE) have an oxide conductive layer (M20) that is in contact with the oxide semiconductor (SC). Therefore, compared with the case where the metal layer is in direct contact with the oxide semiconductor (SC), the excessive removal (metallization) of oxygen from the oxide semiconductor (SC) to the source (SE) or drain (DE) is suppressed.

[0065] Therefore, the source region in contact with the source SE and the drain region in contact with the drain DE in the oxide semiconductor SC are reduced in resistance, and the expansion of the reduced-resistance region is suppressed. Thus, it is possible to achieve a smaller size with the same channel length as that of a top-gate transistor in the bottom-gate transistor TR as described above.

[0066] Furthermore, in oxide semiconductor (SC), a low-resistance region is formed around the source region, where the resistivity is higher than that of the source region and lower than that of the channel region. Similarly, a low-resistance region is formed around the drain region, where the resistivity is higher than that of the drain region and lower than that of the channel region. These low-resistance regions mitigate electric field concentration and suppress the generation of hot carriers. Therefore, the change in the threshold voltage during the transistor's transition from the non-conducting state to the conducting state is suppressed, improving reliability.

[0067] According to the inventors' research, from the viewpoint of forming an oxide conductive layer M20 with a uniform film thickness, the film thickness of the oxide conductive layer M20 is preferably 10 nm or more. Furthermore, from the viewpoint of suppressing the contact resistance between the oxide conductive layer M20 and the oxide semiconductor SC to an acceptable range, the film thickness of the oxide conductive layer M20 is preferably 50 nm or less.

[0068] Next, the inventors studied the relationship between the channel length (L_length) and threshold voltage (V_th) of the transistor TR.

[0069] Figure 4This is a graph showing the relationship between the threshold voltage of transistor TR and the channel length.

[0070] The horizontal axis of the graph represents the channel length (μm), and the vertical axis represents the threshold voltage (V). The inventors conducted experiments to measure the threshold voltage of multiple transistors (TR) with different channel lengths. A in the graph represents a reference. Figure 2 The experimental results for the transistor TR are illustrated. B in the figure represents the reference. Figure 2 Experimental results for transistors with oxide conductive layer M20 are omitted from the transistor TR description.

[0071] Without the oxide conductive layer M20, it was confirmed that off-state leakage current occurs when the channel length is less than 3.5 μm, resulting in insufficient transistor performance. In other words, without the oxide conductive layer M20, a channel length of more than 3.5 μm is required to achieve transistor performance.

[0072] It was confirmed that with the presence of the oxide conductive layer M20, sufficient transistor performance can be achieved if the channel length is 1.5 μm or more. This allows for transistor miniaturization by shortening the channel length and enables higher on-state current.

[0073] Next, other configuration examples of transistor TR will be described.

[0074] Figure 5 This is a cross-sectional view showing another configuration example of a semiconductor device 1 equipped with a transistor TR.

[0075] Figure 5 The example shown is similar to Figure 2 The configuration shown differs from the example shown in that the insulating layer 12 is omitted. For other configurations of the semiconductor device 1, please refer to... Figure 2 As explained, the same reference symbol is used and detailed explanations are omitted.

[0076] Gate GE1 is disposed on insulating substrate 10. Gate GE1 is a multilayer having a first metal layer M11, a second metal layer M12, and a third metal layer M13. In one example, the first metal layer M11 and the third metal layer M13 are layers containing molybdenum (Mo), and the second metal layer M12 is a layer containing aluminum (Al).

[0077] The oxide semiconductor SC is located directly above the gate GE1 and is disposed on the insulating layer 11.

[0078] The source electrode SE is disposed on the insulating layer 11 and is connected to the oxide semiconductor SC. The drain electrode DE is disposed on the insulating layer 11 and is connected to the oxide semiconductor SC. The source electrode SE and the drain electrode DE are located in the same layer, which is a conductive layer formed by the same material.

[0079] The source (SE) and drain (DE) are each multilayer structures comprising an oxide conductive layer M20, a first metal layer M21, a second metal layer M22, and a third metal layer M23. The oxide conductive layer M20 is connected to the insulating layer 11 and the oxide semiconductor SC. In one example, the oxide conductive layer M20 is formed of indium tin oxide (ITO). The first metal layer M21 and the third metal layer M23 are layers containing molybdenum (Mo), and the second metal layer M22 is a layer containing aluminum (Al).

[0080] The insulating layer 13 (passivation film) is an inorganic insulating layer disposed on the insulating layer 11 and covers the source SE and drain DE. In addition, the insulating layer 13 is connected to the oxide semiconductor SC between the source SE and the drain DE.

[0081] The gate GE2 and the connection electrode CN are each a multilayer having a first metal layer M31, a second metal layer M32, and a third metal layer M33. In one example, the first metal layer M31 and the third metal layer M33 are layers containing molybdenum (Mo), and the second metal layer M32 is a layer containing aluminum (Al).

[0082] The first metal layers M11, M21, M31 and the third metal layers M13, M23, M33 mentioned above can be replaced with layers containing titanium (Ti). Additionally, the gate GE2 and the connecting electrode CN can also be layers formed of elemental molybdenum. The gate GE2 can also be omitted.

[0083] Similarly, in this configuration example, since the insulating layer 13 is uniformly deposited on each side of the source electrode SE and the drain electrode DE, the infiltration of moisture through the insulating layer 13 is suppressed.

[0084] Since the source (SE) and drain (DE) have an oxide conductive layer (M20) connected to the oxide semiconductor (SC), excessive oxygen extraction (metallization) from the oxide semiconductor (SC) to the source (SE) or drain (DE) is suppressed. Therefore, in the bottom-gate transistor TR described above, it is possible to achieve a smaller size with the same channel length as the top-gate transistor.

[0085] Furthermore, in the configuration example described here, the etch barrier layer is omitted. Therefore, the oxide semiconductor layer SC is formed of a material that has high resistance to the etchant used to etch the source SE and drain DE. Therefore, the gates GE1 and GE2, the source SE, the drain DE, and the connection electrode CN can all be patterned by wet etching. As a result, manufacturing costs can be reduced compared to the case where various electrodes are formed from materials that require dry etching.

[0086] Figure 6This is a cross-sectional view showing another configuration example of a semiconductor device 1 equipped with a transistor TR.

[0087] Figure 6 The example shown is similar to Figure 2 Compared to the configuration shown, the difference lies in the omission of the oxide conductive layers in the source (SE) and drain (DE). For other configurations of semiconductor device 1, please refer to... Figure 2 As explained, the same reference symbol is used and detailed explanations are omitted.

[0088] The source (SE) and drain (DE) are each multilayer structures comprising a first metal layer M21, a second metal layer M22, and a third metal layer M23. The first metal layer M21 is connected to the insulating layer 12 and the oxide semiconductor SC. In one example, the first metal layer M21 and the third metal layer M23 are layers containing molybdenum (Mo), and the second metal layer M22 is a layer containing aluminum (Al).

[0089] Gate GE1 is a multilayer comprising a first metal layer M11, a second metal layer M12, and a third metal layer M13. In one example, the first metal layer M11 and the third metal layer M13 are layers containing molybdenum (Mo), and the second metal layer M12 is a layer containing aluminum (Al).

[0090] The gate GE2 and the connection electrode CN are each a multilayer having a first metal layer M31, a second metal layer M32, and a third metal layer M33. In one example, the first metal layer M31 and the third metal layer M33 are layers containing molybdenum (Mo), and the second metal layer M32 is a layer containing aluminum (Al).

[0091] The first metal layers M11, M21, M31 and the third metal layers M13, M23, M33 mentioned above can be replaced with layers containing titanium (Ti). Additionally, the gate GE2 and the connecting electrode CN can also be layers formed of elemental molybdenum. The gate GE2 can also be omitted.

[0092] Similarly, in this configuration example, the gates GE1 and GE2, the source SE, the drain DE, and the connection electrode CN can all be patterned using wet etching. This reduces manufacturing costs compared to forming various electrodes from materials that require dry etching.

[0093] An insulating layer 12, serving as an etch barrier layer, is sandwiched between the oxide semiconductor SC and the source SE, and between the oxide semiconductor SC and the drain DE. Therefore, during wet etching to form the source SE and drain DE, the oxide semiconductor SC is almost never exposed to the etchant, thus suppressing damage to the oxide semiconductor SC. Furthermore, this expands the options for materials used to form the oxide semiconductor SC.

[0094] Furthermore, in oxide semiconductors (SCs), low-resistance regions with lower resistance than the channel region are formed around the source and drain regions. In such low-resistance regions, even when a high voltage is applied between the source and drain, the generation of hot carriers is suppressed, thus suppressing changes in the threshold voltage and improving reliability.

[0095] Figure 7 This is a cross-sectional view showing another configuration example of a semiconductor device 1 equipped with a transistor TR.

[0096] Figure 7 The example shown is similar to Figure 5 Compared to the configuration shown, the difference lies in the omission of the oxide conductive layers in the source (SE) and drain (DE). For other configurations of semiconductor device 1, please refer to... Figure 2 As explained, the same reference symbol is used and detailed explanations are omitted.

[0097] The source (SE) and drain (DE) are each multilayer structures comprising a first metal layer M21, a second metal layer M22, and a third metal layer M23. The first metal layer M21 is connected to the insulating layer 11 and the oxide semiconductor SC. In one example, the first metal layer M21 and the third metal layer M23 are layers containing molybdenum (Mo), and the second metal layer M22 is a layer containing aluminum (Al).

[0098] Gate GE1 is a multilayer comprising a first metal layer M11, a second metal layer M12, and a third metal layer M13. In one example, the first metal layer M11 and the third metal layer M13 are layers containing molybdenum (Mo), and the second metal layer M12 is a layer containing aluminum (Al).

[0099] The gate GE2 and the connection electrode CN are each a multilayer having a first metal layer M31, a second metal layer M32, and a third metal layer M33. In one example, the first metal layer M31 and the third metal layer M33 are layers containing molybdenum (Mo), and the second metal layer M32 is a layer containing aluminum (Al).

[0100] The first metal layers M11, M21, M31 and the third metal layers M13, M23, M33 mentioned above can be replaced with layers containing titanium (Ti). Additionally, the gate GE2 and the connecting electrode CN can also be layers formed of elemental molybdenum. The gate GE2 can also be omitted.

[0101] In the configuration example described here, the etch barrier layer is omitted. Therefore, the oxide semiconductor layer SC is formed of a material that is highly resistant to the etchant used to etch the source SE and drain DE. Thus, the gates GE1 and GE2, the source SE, the drain DE, and the connection electrode CN can all be patterned using wet etching. This reduces manufacturing costs compared to forming various electrodes from materials that require dry etching.

[0102] for Figure 2 and Figure 6 The transistors TR in the illustrated configurations exhibit high withstand voltage characteristics, allowing for the application of high voltages between the source and drain. As an example, a stress test was conducted at 60°C with the applied voltage to the gate GE1 set to 40V and the applied voltage between the source SE and drain DE set to ±30V, followed by continuous voltage application for 1000 seconds. The results of this stress test confirmed that the threshold voltage remained almost unchanged. Therefore, Figure 2 and Figure 6 The transistors TR in the various configuration examples shown can be applied to semiconductor devices where high voltages can be applied.

[0103] Figure 5 and Figure 7 The transistor TR in each of the configuration examples shown Figure 2 and Figure 6 Compared to the transistor TR shown, it has lower voltage withstand characteristics, but it can be used in semiconductor devices driven by relatively low voltages, such as liquid crystal display devices.

[0104] Figure 8 This is a cross-sectional view showing another configuration example of a semiconductor device 1 equipped with a transistor TR.

[0105] Figure 8 The example shown is similar to Figure 2 Compared to the configuration example shown, the semiconductor device 1 differs in that it further includes a common electrode 31 and an insulating layer 15.

[0106] A common electrode 31 is disposed on the insulating layer 14. The common electrode 31, for example, also serves as... Figure 1 The capacitor wiring CW and the common electrode CE shown are configured across multiple pixels PX in the display area DA. In each pixel PX, the common electrode 31 overlaps with the transistor TR. Furthermore, the common electrode 31 has an opening OP. The opening OP is formed in a manner that overlaps with the through-hole CH4. Such a common electrode 31 is, for example, a transparent electrode formed from a transparent conductive material such as ITO or IZO.

[0107] Insulating layer 15 is an inorganic insulating layer disposed on insulating layer 14 and covering common electrode 31. Insulating layer 15 has a through hole CH5 extending through the opening OP to the connecting electrode CN. Insulating layer 15 is, for example, a silicon nitride layer.

[0108] Component electrode 30 is disposed on insulating layer 15 and is connected to connecting electrode CN at through holes CH4 and CH5. Additionally, component electrode 30 is positioned opposite common electrode 31 across insulating layer 15. Component electrode 30 is, for example, a pixel electrode disposed in each pixel PX.

[0109] For other configurations of semiconductor device 1, see reference 1. Figure 2 As explained, the same reference symbol is used and detailed explanations are omitted.

[0110] In such a configuration example, one can also obtain the same as... Figure 2 The example shown has the same effect.

[0111] Here, as Figure 2 The variation shown illustrates a configuration example with the addition of a common electrode 31 and an insulating layer 15. Figures 5-7 In each of the illustrated configuration examples, additional components may also be added. Figure 8 The common electrode 31 and insulating layer 15 are shown.

[0112] As explained above, according to this embodiment, a semiconductor device capable of miniaturizing transistors can be provided.

[0113] Furthermore, the present invention is not limited to the embodiments described above. During its implementation, the constituent elements can be modified and embodied by variations without departing from its spirit. Additionally, various inventions can be formed by appropriately combining the multiple constituent elements disclosed in the above embodiments. For example, some constituent elements can be deleted from all the constituent elements shown in the embodiments. Furthermore, constituent elements from different embodiments can be appropriately combined.

Claims

1. A semiconductor device comprising: Insulating substrate; A gate disposed on the insulating substrate; A first insulating layer covering the gate; An oxide semiconductor disposed directly above the gate and on the first insulating layer; The source electrode connected to the oxide semiconductor; as well as The drain electrode connected to the oxide semiconductor. Each of the source and the drain has: An oxide conductive layer in contact with the oxide semiconductor; A first metal layer stacked on the oxide conductive layer; A second metal layer formed of a material different from the first metal layer and stacked on top of the first metal layer; as well as A third metal layer formed of the same material as the first metal layer and stacked on top of the second metal layer. The first side of the oxide conductive layer is located further outward than the second side of the first metal layer. The slope of the first side is less than the slope of the second side.

2. The semiconductor device according to claim 1, wherein, The oxide conductive layer is formed of indium tin oxide or indium zinc oxide.

3. The semiconductor device according to claim 1, wherein, The first metal layer and the third metal layer are formed of a material containing molybdenum (Mo). The second metal layer is formed of a material containing aluminum (Al).

4. The semiconductor device according to claim 1, further comprising: A second insulating layer covering the oxide semiconductor; and A passivation film covering the source and the drain. The oxide conductive layer is connected to the second insulating layer, and is connected to the oxide semiconductor at the through-hole of the second insulating layer. The passivation film is in contact with the second insulating layer between the source and the drain.

5. The semiconductor device according to claim 1, It further comprises a passivation film covering the source and the drain. The oxide conductive layer is connected to the first insulating layer and the oxide semiconductor. The passivation film is connected to the oxide semiconductor between the source and the drain.

6. A semiconductor device comprising: Insulating substrate; A gate disposed on the insulating substrate; A first insulating layer covering the gate; An oxide semiconductor disposed directly above the gate and on the first insulating layer; The source electrode connected to the oxide semiconductor; The drain electrode connected to the oxide semiconductor; A passivation film covering the source and the drain; as well as The upper gate, located directly above the gate, disposed on the passivation film, and electrically connected to the gate, The gate, the source, the drain, and the upper gate each have: A first metal layer containing molybdenum (Mo); A second metal layer comprising aluminum (Al) and stacked on the first metal layer; and A third metal layer comprising molybdenum (Mo) and stacked on top of the second metal layer. The source and the drain each have an oxide conductive layer connected to the oxide semiconductor as the substrate of the first metal layer. The first side of the oxide conductive layer is located further outward than the second side of the first metal layer. The slope of the first side is less than the slope of the second side.

7. The semiconductor device according to claim 6, It further comprises a second insulating layer covering the oxide semiconductor. The passivation film is in contact with the second insulating layer between the source and the drain.

8. The semiconductor device according to claim 6, wherein, The passivation film is connected to the oxide semiconductor between the source and the drain.

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