Amplifier for radio frequency receivers

Abstract

Embodiments of the present disclosure relate to an amplifier for a radio frequency receiver. In one embodiment, the amplifier comprises a first MOS transistor having a drain connected to an output of the amplifier, a source coupled to a first node configured to receive a first supply potential, a first capacitive element connected between an input of the amplifier and a gate of the first MOS transistor, a first current source connecting the drain of the first MOS transistor to a second node configured to receive a second supply potential, and a resistive element and a second capacitive element connected in parallel between the gate and the drain of the first MOS transistor, the resistive element comprising a switched capacitor.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to French patent application No. 2107598, filed on July 13, 2021, which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to electronic circuits, and more specifically to amplifier circuits, and is even more simply referred to as amplifiers, such as amplifiers used in radio frequency receiver chains. Background Technology

[0004] Amplifiers are implemented in many more complex systems or circuits, for example, in the radio frequency receiving chain of a radio frequency receiver or radio frequency receiver.

[0005] Known radio frequency (RF) receivers are configured to receive amplitude-modulated (AM) RF signals, for example, to receive AM RF signals completely or not at all (OOK – “on-off keying”). To obtain data transmitted via amplitude modulation of the RF signal, these known receivers include known receiver chains that implement multiple functions, particularly amplification and low-pass filtering of the envelope signal of the received RF signal.

[0006] Known amplifiers, for example when used in a receiver chain to amplify the envelope signal, have various drawbacks. Summary of the Invention

[0007] One embodiment overcomes all or part of the disadvantages of known amplifiers, such as those implemented in a radio frequency receiver chain to amplify the envelope signal, for example, in a wake-up radio (WUR) receiver or an activation radio frequency receiver.

[0008] For example, the embodiments provide a bandpass amplifier, that is, an amplifier that further implements bandpass filtering function.

[0009] For example, one embodiment provides a bandpass amplifier with a low cutoff frequency, i.e., the amplifier below the cutoff frequency blocks low frequencies less than 500 Hz, preferably less than or equal to 100 Hz.

[0010] For example, one embodiment provides a bandpass amplifier with a low controllable cutoff frequency.

[0011] For example, one embodiment provides a bandpass amplifier for setting the common-mode output voltage of the amplifier.

[0012] For example, an embodiment provides a bandpass amplifier that has reduced power consumption compared to the association of known amplifiers and known bandpass filters.

[0013] For example, one embodiment provides a bandpass amplifier that is smaller in size compared to known amplifiers and known bandpass filters.

[0014] For example, one embodiment provides a bandpass amplifier with low noise compared to a combination of a known amplifier and a known bandpass filter.

[0015] One embodiment provides an amplifier including: a first MOS transistor having its drain connected to the output of the amplifier and its source coupled to a first node, the first node being configured to receive a first power supply potential; a first capacitor element connected between the input of the amplifier and the gate of the first MOS transistor; a first current source coupling the drain of the first MOS transistor to a second node, the second node being configured to receive a second power supply potential; and a resistor element and a second capacitor element connected in parallel between the gate and drain of the first MOS transistor, the resistor element being implemented by a switched capacitor.

[0016] According to one embodiment, the resistive element includes: a first switch connected between the gate of the first MOS transistor and a first electrode of the third capacitor element; and a second switch connected between a second electrode of the third capacitor element and the drain of the first MOS transistor.

[0017] According to one embodiment, the first and second switches are configured to control each other in phase, and the switching frequencies of the first and second switches determine the low cutoff frequency of the amplifier.

[0018] According to one embodiment, the resistive element further includes: a third switch connected between the first electrode of the third capacitor element and a third node configured to receive a first bias potential; and a fourth switch connected between the second electrode of the third capacitor element and a fourth node configured to receive a second bias potential.

[0019] According to one embodiment, the third node is the gate of a second MOS transistor, the second MOS transistor having a source configured to receive the first power supply potential, and the drain of the second MOS transistor being connected to the third node and coupled to the second node through a second current source.

[0020] According to one embodiment, the first and second MOS transistors and the first and second current sources are configured such that a first bias potential applies a DC potential to the gate of the first transistor.

[0021] According to an embodiment, the first current source includes a third MOS transistor assembled in mirror image with the fourth MOS transistor, and the second current source includes a fifth MOS transistor assembled in mirror image with the fourth MOS transistor.

[0022] According to one embodiment, the amplifier includes circuitry configured to control the first and second switches in phase opposite to that of the third and fourth switches.

[0023] According to an embodiment, the second bias potential determines the common-mode output voltage of the amplifier.

[0024] According to one embodiment, the second bias potential is equal to half the difference between the first and second power supply potentials.

[0025] According to an embodiment, the fourth node is an intermediate node of the voltage divider bridge connecting the first and second nodes.

[0026] One embodiment provides an amplifier comprising:

[0027] The first amplifier as described above;

[0028] Input, connected to the input of the first amplifier;

[0029] The second amplifier has an input connected to the output of the first amplifier;

[0030] The output is coupled (e.g., connected) to the output of the second amplifier.

[0031] The second amplifier includes:

[0032] First capacitor element;

[0033] The first MOS transistor has a gate coupled to the input of the second amplifier via the first capacitor element, a source coupled (e.g., connected) to one of the first node and the second node of the first amplifier, and a drain coupled to the other of the first and second nodes.

[0034] A first resistive element and a second capacitive element are connected in parallel between the drain and gate of the first transistor. The first resistive element is implemented by a first switched capacitor.

[0035] The second MOS transistor has its source coupled (e.g., connected) to the other node of the first and second nodes, and its drain connected to the drain of the first MOS transistor;

[0036] A second resistive element and a second capacitive element are connected in parallel between the drain and gate of the second transistor, and the second resistive element is implemented by a second switched capacitor; and

[0037] A switch and a third capacitor element, the third capacitor element coupling the gate of the second transistor to the switch, and the switch being configured to selectively couple the third capacitor element to the other of the first and second nodes or to the input of the second amplifier.

[0038] According to one embodiment, the first switched capacitor includes:

[0039] The first switch is connected between the gate of the first MOS transistor of the second amplifier and the first electrode of the fourth capacitor element of the second amplifier.

[0040] The second switch is connected between the second electrode of the third capacitor element of the second amplifier and the drain of the first MOS transistor of the second amplifier.

[0041] A third switch is connected between the first electrode of the third capacitor element of the second amplifier and the third node of the second amplifier, the third node of the second amplifier being configured to receive a first bias potential of the second amplifier; and

[0042] A fourth switch is connected between the second electrode of the third capacitor element of the second amplifier and the fourth node of the second amplifier, the fourth node of the second amplifier being configured to receive the second bias potential of the second amplifier, and

[0043] The second switched capacitor includes:

[0044] The first switch is connected between the gate of the second MOS transistor of the second amplifier and the first electrode of the sixth capacitor element of the second amplifier.

[0045] The second switch is connected between the second electrode of the sixth capacitor element of the second amplifier and the drain of the second MOS transistor of the second amplifier.

[0046] A third switch, connected between the first electrode of the sixth capacitor element of the second amplifier and the fifth node of the second amplifier, is configured to receive this bias potential of the second amplifier; and

[0047] The fourth switch is connected between the second electrode of the third capacitor element of the second amplifier and the fourth node of the second amplifier.

[0048] According to an embodiment, the control frequency of the switching of the switching capacitor of the first amplifier is different from the control frequency of the switching of the first and second switching capacitors of the second amplifier.

[0049] One embodiment provides a radio frequency receiver including an envelope detection circuit having an input coupled to an antenna of the receiver and an output coupled to an input such as the amplifier described above.

[0050] According to an embodiment, the radio frequency receiver forms a wake-up radio frequency receiver or an activation radio frequency receiver.

[0051] According to one embodiment, the radio frequency receiver is configured to receive amplitude-modulated radio frequency signals, for example, according to Manchester encoding, preferably in an all-or-nothing configuration. Attached Figure Description

[0052] The foregoing features and advantages, as well as other features and advantages, will be set forth in the following detailed description of embodiments by way of illustration rather than limitation, with reference to the accompanying drawings, in which:

[0053] Figure 1 Examples of radio frequency transmission systems of the type to which the described embodiments are applicable are schematically shown in the form of boxes;

[0054] Figure 2 An embodiment of a bandpass amplifier is shown; and

[0055] Figure 3 An amplifier according to an embodiment is shown. Detailed Implementation

[0056] In the various figures, the same features are indicated by the same reference numerals. In particular, common structural and / or functional features in the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0057] For clarity, only steps and elements useful for understanding the embodiments described herein are shown and described in detail. In particular, conventional RF receivers that can implement envelope signal amplifiers, such as wake-up or activation RF receivers, are not described in detail; the described embodiments are compatible with these conventional RF receivers.

[0058] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled through one or more other elements.

[0059] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc., or when referring to relative position qualifiers, such as the terms “up,” “down,” “above,” “below,” etc., or when referring to orientation qualifiers, such as “horizontal,” “vertical,” etc., the orientation shown in the figure is used.

[0060] Unless otherwise stated, the expressions “about,” “approximately,” “basically,” and “in the order of” indicate within 10%, preferably within 5%.

[0061] Figure 1An example of a wireless radio frequency transmission system 1 of the type to which the embodiments are applicable is schematically shown in the form of a box.

[0062] System 1 includes a transmitter Tx for radio frequency signal 2 and a receiver Rx for signal 2. Radio frequency signal 2 is a wireless signal. Signal 2 has a frequency in the range of 100 kHz to 10 GHz, for example. Signal 2 is amplitude modulated, for example, all-or-none.

[0063] Transmitter Tx transmits data by amplitude modulation of signal 2, for example, by modulating the amplitude of signal 2 according to Manchester encoding based on the data bits to be transmitted. Signal 2 is transmitted by antenna 3 connected to transmitter Tx.

[0064] Receiver Rx is connected to antenna 4, which is configured to receive signal 2. For example, antenna 4 forms part of receiver Rx.

[0065] The receiver Rx includes a circuit DET configured to receive an amplitude-modulated radio frequency (RF) signal and transmit the envelope signal of the received RF signal, i.e., a voltage signal whose amplitude varies with the envelope amplitude of the RF signal received by the circuit DET. In other words, the circuit DET is an envelope detection circuit. The circuit DET, for example, uses a method such as... Figure 1 The impedance matching network IMP shown receives the radio frequency signal at input 100, which is coupled to antenna 4. Circuit DET transmits the envelope signal at output 102 of circuit DET.

[0066] Impedance matching network IMP couples antenna 4 to input 100 of circuit DET. As an example, the matching network IMP is arranged outside the integrated circuit chip including circuit DET. Furthermore, although in Figure 1 In the example, only the circuit IMP is arranged between antenna 4 and circuit DET, but in other examples, other circuits may be connected between antenna 4 and circuit DET, such as amplifier circuits and / or bandpass filter circuits.

[0067] The output 102 of circuit DET is coupled to the associated components of two successively connected circuits BPF and BBA. Figure 1 In the example, circuit BBA is connected after circuit BPF.

[0068] A circuit BPF, referred to as a baseband filter, is configured to perform bandpass filtering. For example, the filter BPF is configured to retain only the frequency of the envelope signal corresponding to the amplitude modulation frequency of signal 2.

[0069] The circuit BBA, for example, known as a baseband amplifier, is configured to amplify the signal it receives and transmit the amplified signal corresponding to the circuit Q.

[0070] Circuit Q performs quantization on one bit of the signal it receives, and thus transmits a binary signal. This binary signal, for example, corresponds to the Manchester code of the data transmitted via signal 2.

[0071] exist Figure 1 The digital processing circuit (not shown) receives the binary output signal of the receiving circuit Q and is configured to decode the signal to recover the data transmitted from the transmitter Tx to the receiver Rx.

[0072] exist Figure 1 In the example, circuits IMP, DET, BPF, BBA, and Q form the radio frequency receiving chain 104 of receiver Rx, that is, a circuit chain configured, for example, to receive radio frequency signals from antenna 4 and transmit digital signals corresponding to the digital processing circuitry of receiver Rx, such that the processing circuitry is able to decode the digital signals to recover the transmitted data.

[0073] There are many other examples of RF receiver chains, including envelope detection circuits of the DET type, bandpass filters of the BPF type, and amplifier circuits of the BBA type.

[0074] This document provides an embodiment of an amplifier that not only performs the amplification function of the BAA circuit but also the bandpass filtering function of the BPF circuit. In other words, a bandpass amplifier circuit is provided, or more simply, a bandpass amplifier is provided.

[0075] Therefore, the provided amplifier can replace two consecutive stages that implement bandpass filtering and envelope signal amplification with a single stage that simultaneously implements RF signal filtering and envelope signal amplification. For example, according to one embodiment, the amplifier provided herein replaces... Figure 1 The receiver Rx has two-stage OR circuits BBA and BPF.

[0076] This reduction in the number of stages in the RF receiver chain leads to a decrease in power consumption. This reduction in power consumption is particularly advantageous, for example, for wake-up RF receivers. In practice, a wake-up radio receiver is configured to detect whether a wake-up signal is being transmitted on the RF band of interest, and for this purpose, to continuously listen to or observe the band of interest.

[0077] Figure 2 An embodiment of the bandpass amplifier circuit 200 is shown.

[0078] Amplifier 200 includes a MOS ("metal-oxide-semiconductor") transistor 201. Figure 2 In the example, transistor 201 is a PMOS transistor, i.e., a P-channel MOS transistor.

[0079] The source of transistor 201 is configured to receive a power supply potential VDD. For example, the source of transistor 201 is coupled to (preferably connected to) a node 202 configured to receive a potential VDD. The potential VDD is, for example, a reference potential, such as ground GND. For example, the potential VDD is positive. Potentials VDD and GND correspond to the first and second power supply potentials, respectively.

[0080] The drain of transistor 201 is connected to the output OUT of circuit 200. For example, output OUT is coupled to (e.g., connected to) a quantization circuit over one bit. For example, when implementing amplifier 200 instead of... Figure 1 When circuits BBA and BPF are connected, the output OUT of amplifier 200 is connected, for example, to the input of circuit Q of receiver Rx.

[0081] Amplifier 200 includes a capacitor C1 connected between its input IN and node 204. Node 204 is connected to the gate of transistor 201. In other words, capacitor C1 is connected between the input IN and the gate of transistor 201.

[0082] As an example, capacitor element C1 has a first electrode or terminal coupled (preferably connected) to input IN, and a second electrode or terminal coupled (preferably connected) to node 204. For example, input IN is configured to receive the envelope signal of an amplitude-modulated radio frequency signal. For example, input IN is coupled to the antenna of the radio frequency receiver, for example, coupled to the output of an envelope detection circuit having an input coupled to that antenna. For example, when implementing amplifier 200 instead of... Figure 1 When the circuits BBA and BPF are connected, the input IN of amplifier 200 is coupled to (e.g., connected to) the output 102 of detector DET of receiver Rx.

[0083] Amplifier 200 includes a current source 206. Current source 206 is configured to provide a constant current, the value of which is, for example, controllable. Current source 206 couples the drain of transistor 201 (i.e., output OUT) to node 208, which is configured to receive a reference potential (GND in this example). For example, current source 206 has a first terminal coupled (preferably connected) to the drain of transistor 201 and a second terminal coupled (preferably connected) to node 208.

[0084] Amplifier 200 also includes a resistive element R and a capacitive element C2. Elements R and C2 are connected in parallel between each other between node 204 (the gate of transistor 201) and output OUT (the drain of transistor 201). The resistive element R is implemented by a switched capacitor. In other words, the resistive element R includes a switched capacitor, for example, formed by a switched capacitor.

[0085] Using switched capacitors to implement resistive elements R can achieve high resistance values, such as greater than 1 Gohm, on the order of 10 Gohm, while maintaining a reduced size.

[0086] Using a switched capacitor to implement the resistor element R also allows control over the resistance value of the resistor element R, which in turn allows control over the low cutoff frequency of the bandpass filter function of amplifier 200. As a result, the DC component at the input IN is filtered by amplifier 200 and cannot be found at its output OUT.

[0087] Furthermore, using a switched capacitor to implement the resistive element R allows the common-mode voltage at the output OUT of amplifier 200 to be set to a target value. Preferably, the output common-mode voltage, i.e., the common-mode voltage at output OUT, is set to half the value of the power supply potential VDD, which allows the use of the entire dynamic range available for the output signal of amplifier 200.

[0088] According to one embodiment, the resistive element R includes a switch 210, a capacitor element C3, and a switch 212. Switch 210, capacitor C3, and switch 212 are connected in series between the gate 204 and the drain OUT of transistor 201. For example, switch 210 is connected between node 204 and a first electrode or terminal of capacitor C3, while switch 212 is connected between node OUT and a second electrode or terminal of capacitor C3. For example, switch 210 has a conductive terminal connected to node 204 and another conductive terminal connected to capacitor C3, and switch 212 has a conductive terminal connected to element C3 and another conductive terminal connected to node OUT.

[0089] The two switches 210 and 212 are controlled in phase. In other words, when switch 210 is on and off respectively, switch 212 is on and off respectively. Switches 210 and 212 are controlled by a control signal clk provided by, for example, a control circuit ctrl.

[0090] The signal clk is a periodic signal, and its frequency determines the resistance value Rval of the resistive element. In fact, the resistance value Rval of the resistive element R between node 204 and OUT is equal to 1 / (Fclk*C3val), where Fclk is the frequency of the signal clk, and C3val is the capacitance value of the capacitor element C3. For example, capacitor element C3 is implemented using a metal-oxide-metal (MOM) capacitor element. In fact, MOM capacitor elements have a specific capacitance value, which enables them to achieve a specific resistance value Rval.

[0091] Because of the fact that the frequency Fclk determines the value Rval, the frequency Fclk also determines the low cutoff frequency Flow of amplifier 200. In fact, the frequency Flow is equal to 1 / (2*Π*C2val*Rval), and therefore equal to (Fclk*C3val) / (2*Π*C2val), where C2val is the capacitance value of capacitor element C2, and the ratio of value C3val / C2val is well controlled, for example, by implementing each of elements C2 and C3 with metal-oxide-semiconductor capacitors.

[0092] Therefore, the frequency Flow can be controlled by the frequency Fclk, and changes in the frequency Fclk will cause corresponding changes in the frequency Flow.

[0093] Furthermore, the gain G of amplifier 200 is equal to C1val / C2val, where C1val is the capacitance value of capacitor element C1. Therefore, the gain G can be relatively high, for example, on the order of 30dB. Preferably, capacitor elements C1 and C2 are each implemented as metal-oxide-semiconductor capacitors, which are capable of achieving a specific gain value G.

[0094] According to one embodiment, the resistive element R further includes switches 214 and 216. Switch 214 is connected between node 218 and the first electrode or terminal of the capacitive element C3. In other words, switch 214 is connected between node 218 and the connection node from switch 210 to the capacitive element C3. Switch 216 is connected between node 220 and the second electrode or terminal of the capacitive element C3. In other words, switch 216 is connected between node 220 and the connection node from switch 212 to the capacitive element C3. For example, switch 214 has a conductive terminal connected to the first terminal of the capacitive element C3 and another conductive terminal connected to node 218, and switch 216 has a conductive terminal connected to the second terminal of the element C3 and another conductive terminal connected to node 220.

[0095] Two switches, 214 and 216, are controlled in phase with respect to each other and out of phase with respect to switches 210 and 212. In other words, when switches 210 and 212 are on and off respectively, switches 214 and 216 are off and on respectively. Switches 214 and 216 are controlled by a control signal nclk, for example, transmitted by the circuit ctrl. As an example, the signal nclk is the complement of the signal clk, that is, when signal clk is low and high, binary states respectively, signal nclk is high and low, binary states respectively. As an alternative example, the signal nclk may be different from the complementary signal clk to determine that switches 214 and 216, as well as switches 210 and 212, are not simultaneously on.

[0096] Node 218 is configured to receive a bias potential Vpol. The potential Vpol applies a bias potential, i.e., a DC potential, to node 204, thereby applying a bias potential to the gate of transistor 201.

[0097] According to one embodiment, node 218 forms part of circuit 221, which is configured to pass a potential Vpol to node 218 to apply a DC potential to the gate 204 of transistor 201.

[0098] According to an embodiment, circuit 221 includes a MOS transistor 220, which in this example has a P-channel, and node 218 corresponds to the gate of MOS transistor 222, or in other words, node 218 is connected to the gate of transistor 222. The source of transistor 222 is configured to receive a potential VDD. The source of transistor 222 is thus coupled to, preferably connected to, node 202. The drain of transistor 222 is connected to node 218, i.e., connected to the gate 218 of transistor 222. The drain of transistor 222 is further coupled to node 208 via a current source 224. For example, one terminal of current source 224 is coupled (preferably connected) to node 208, and the other terminal is coupled (preferably connected) to the drain of transistor 222 (node ​​218). Those skilled in the art can determine the size of current source 224 and transistor 222 to determine the value of potential Vpol, thereby determining the value of the DC potential of node 204. For example, current source 224 is configured to provide the same current value as current source 206, and transistors 222 and 201 have the same dimensions.

[0099] As an example, current source 224 is implemented by a MOS transistor, while current source 206 is implemented by another MOS transistor, and these two MOS transistors are assembled as mirror images of the same other MOS transistor. For example, these MOS transistors are N-channel MOS or NMOS transistors.

[0100] Node 220 is configured to receive a bias potential Vcm. The output common-mode value of amplifier 200 is determined by the value of potential Vcm, for example, it is equivalent to the value of potential Vcm.

[0101] According to an embodiment, node 220 forms part of circuit 226, which is configured such that the potential Vcm of node 220 is equal to the target common-mode output value of amplifier 200.

[0102] According to one embodiment, circuit 226 is a voltage divider bridge connected between nodes 202 and 208, and node 220 is the intermediate node of voltage divider bridge 226. For example, voltage divider bridge 226 includes two resistive elements R1 and R2, which are connected in series between nodes 202 and 208 and connected to each other at the same level as node 220. Elements R1 and R2 have the same resistance value.

[0103] When switches 214 and 216 are closed (switches 210 and 212 are open), the potential difference across capacitor C3 is equal to the difference between potentials Vpol and Vcm. When switches 214 and 216 are switched off, switches 210 and 212 are switched on, thus the potential difference across capacitor C3 lies between nodes 204 and OUT. Since potential Vpol is equal to the DC potential at node 204, the DC potential at node OUT is equal to potential Vcm. Therefore, Figure 2 The amplifier 200 can control the output common-mode voltage OUT of the amplifier 200 without using a complex and bulky feedback loop.

[0104] Amplifier 200 also includes, for example, a capacitor element C4, referred to as output capacitor C4. Capacitor C4 is connected between the output OUT (the drain of transistor 201) and node 208 at ground potential GND. Capacitor C4 helps filter high frequencies on the output OUT, i.e., frequencies higher than the high cutoff frequency of amplifier 200. In fact, the high cutoff frequency Fhigh of bandpass amplifier 200 is equal to:

[0105] (gm*(C2val / C1val)) / (2*Π*(C2val+C4val+(C2val*C4val) / C1val)), where C4val is the capacitance of capacitor C4, and gm is the transconductance of transistor 201. In other words, the frequency Fhight equals:

[0106] gm / (2*Π*G*(C2val+C4val+C4val / G)).

[0107] For example, capacitor element C4 is implemented by capacitor element MOM.

[0108] Amplifier 200 is able to amplify the envelope signal received at input IN, while suppressing the DC component of the envelope signal provided to input IN and suppressing interference present in envelope signals with frequencies greater than Fhight by setting the common-mode voltage at output OUT.

[0109] As an example of application, with capacitance C1val equal to 8pF, capacitance C2val equal to 240fF plus 25-fF stray capacitance, capacitance C4val equal to 1pF, resistance Rval equal to 10 Gohms, transconductance of transistor 201 equal to 5.3μS, gain G has a theoretical value of 29.6 dB, frequency Flow has a theoretical value of 60 Hz, and frequency Fhigh has a theoretical value of 3 kHz. Simulations have been performed using the simulation tool specified by the trade name Cadence, with the same values ​​of C1val, C2val, C4val, and Rval as described above. Thus, the simulated values ​​of gain G, frequency Flow, and frequency Fhigh are 29.5 dB, 60 Hz, and 2.8 kHz, respectively, consistent with the theoretical values ​​mentioned above. Furthermore, for the aforementioned values ​​C1val, C2val, C4val, and Rval, simulations have shown that the power consumption of amplifier 200 is equal to 200 nA, and the surface area occupied by amplifier 200 is on the order of 100 μm * 100 μm.

[0110] According to an embodiment, amplifier 200 is implemented in a radio frequency (RF) receiver, preferably in a wake-up radio receiver including an envelope detection circuit having an input coupled to the antenna of the RF receiver and an output coupled to, for example, an input IN connected to amplifier 200. The output OUT of amplifier 200 is coupled to, for example, a quantization circuit connected to one bit. Preferably, the RF receiver is configured to receive an amplitude-modulated RF signal, preferably all-or-no-amplification, for example according to Manchester encoding. For example, amplifier 200 replaces... Figure 1 The receiver Rx contains two circuits or stages, BBA and BPF.

[0111] However, those skilled in the art can achieve different combinations Figure 1 Amplifier 200 is implemented in the described radio frequency receiver.

[0112] For example, an amplifier 200 may be provided in the RF receiver to amplify the envelope signal of the RF signal amplitude modulation, instead of using Manchester encoding, or even not using it at all, and at the same time implement bandpass filtering, for example, using high and low cutoff frequencies lower than those of known bandpass amplifiers.

[0113] More generally, amplifier 200 can be provided in all applications or in all systems where it is desirable to simultaneously achieve signal amplification and bandpass filtering, for example, having a low cutoff frequency below 500 Hz, preferably less than or equal to 100 Hz, and / or having reduced power consumption, for example, relative to known circuits capable of achieving these amplification and low-pass filtering functions.

[0114] Furthermore, those skilled in the art can apply the above description of amplifier 200 to the case where the potential VDD is negative relative to the potential GND, for example, by replacing the P-channel and N-channel MOS transistors with N-channel and P-channel MOS transistors respectively. Those skilled in the art can also reverse the positions of current source 206 and transistor 201 by replacing the P-channel transistor 201 with an N-channel transistor, and by replacing the P-channel transistor 222 with an N-channel transistor 222 when the potential Vpol is provided by transistor 222 and current source 224, and by reversing the positions of current source 224 and transistor 222.

[0115] The case where the drain of transistor 201 corresponds to the output OUT of amplifier 200 has been described above. In other embodiments, the drain of transistor 201 corresponds to the output of the first stage of amplifier 300 and is coupled to the input of the second stage of amplifier 300.

[0116] Figure 3 An example of an embodiment of such amplifier 300 is shown.

[0117] Amplifier 300 includes a first stage implemented by the aforementioned amplifier 200, the first stage 200 in Figure 3 It is shown in the form of a box.

[0118] Amplifier 300 includes an input corresponding to the input IN of stage 200, or in other words, the input of amplifier 300 is coupled to, for example, the input IN connected to stage 200.

[0119] Amplifier 300 also includes a second stage or second amplifier 302, which is composed of Figure 3 The dashed line in the middle defines the boundary.

[0120] Stage 302 includes input IN1. Input IN1 is coupled to, for example, output OUT connected to stage 200.

[0121] Stage 302 includes an output OUT1. Output OUT1 is coupled to, for example, the output of amplifier 300. In this example, the output OUT1 of stage 302 corresponds to the output OUT1 of amplifier 300.

[0122] Although this is in Figure 3 Not shown, but a capacitor element can be connected between the output OUT of stage 302 and node 208. This capacitor element is, for example, combined with... Figure 2 The capacitor element C4 is described. This capacitor element is capable of, for example, at least partially determining the cutoff frequency of the low-pass filter function implemented between the input IN and output OUT1 of amplifier 300.

[0123] Amplifier 302 includes MOS transistor 304 and MOS transistor 306. Transistors 304 and 306 are connected in series between nodes 202 and 208. Figure 3 In the example, transistor 304 is a PMOS transistor, and transistor 306 is an NMOS transistor.

[0124] The source of transistor 304 is configured to receive a power supply potential VDD. For example, the source of transistor 304 is coupled to, preferably connected to, node 202.

[0125] The drain of transistor 304 is connected, for example, to the output OUT1 of circuit 302. For example, output OUT1 is coupled to (e.g., connected to) a quantization circuit on one bit. For example, when implementing amplifier 300 instead of... Figure 1 When circuits BBA and BPF are connected, the output of amplifier 300 is coupled to the input of circuit Q, for example, connected to receiver Rx.

[0126] The drain of transistor 304 is further coupled to node 208. More specifically, the drain of transistor 304 is coupled to node 208 via transistor 306.

[0127] Amplifier 302 includes a capacitor C5 that couples the input IN1 of amplifier 302 to node 308 of stage 302. Node 308 is connected to the gate of transistor 304. In other words, the gate 308 of transistor 304 is coupled to input IN1 through capacitor C5.

[0128] As an example, capacitor element C5 has a first electrode or terminal coupled (preferably connected) to input IN1, and a second electrode or terminal coupled (e.g. connected) to node 308.

[0129] Amplifier 302 also includes a resistor R3 and a capacitor C6. R3 and C6 are connected in parallel between each other between node 308 (the gate of transistor 304) and the drain of transistor 304 (output OUT1). This is similar to the element R in stage 200. Figure 2 The resistive element R3 is implemented using a switched capacitor. In other words, the resistive element R3 includes or is formed from a switched capacitor. Element R3 in Figure 3 The middle section is defined by a dashed line.

[0130] Using a switched capacitor to implement the resistive element R3 can achieve a high resistance value, for example, greater than 1 Gohm, on the order of 10 Gohm, while maintaining a reduced size.

[0131] Using a switched capacitor to implement resistor R3 also makes it possible to control the resistance value of resistor R3, which in turn allows control of the low cutoff frequency of the bandpass filter function of amplifier 302, thereby controlling the low cutoff frequency of amplifier 300.

[0132] Furthermore, the use of a switched capacitor to implement the resistor element R3 enables the common-mode voltage on the output OUT1 of stage 302 to be set to a target value, thereby setting the common-mode voltage on the output OUT1 of amplifier 300 to, for example, a value equal to half the voltage between nodes 202 and 208.

[0133] According to one embodiment, the resistive element R3 includes a switch 310, a capacitor element C7, and a switch 312. Switch 310, capacitor C7, and switch 312 are connected in series between the gate 308 and the drain OUT1 of transistor 304. For example, switch 310 is connected between node 308 and a first electrode or terminal of capacitor C7, and switch 312 is connected between the drain of transistor 304 and a second electrode or terminal of capacitor C7. For example, switch 310 has a conductive terminal connected to node 308 and another conductive terminal connected to capacitor C7, and switch 312 has a conductive terminal connected to element C7 and another conductive terminal connected to the drain of transistor 304.

[0134] Two switches, 310 and 312, are controlled in phase. In other words, when switch 310 is turned on and off, switch 312 is turned on and off. Switches 310 and 312 are controlled by, for example, a control signal clk1 provided by a control circuit ctrl.

[0135] Signal clk1 is a periodic signal, and its frequency determines the resistance value Rval3 of resistor R3, which is equal to 1 / (Fclk1*C7val), where Fclk1 is the frequency of signal clk1 and C7val is the capacitance value of capacitor C7. For example, capacitor C7 is implemented using a metal-oxide-metal (MOM) capacitor. In practice, MOM capacitors have precise capacitance values, which makes it possible to obtain a precise resistance value Rval3.

[0136] Because of the fact that frequency Fclk1 determines value Rval3, frequency Fclk1 also at least partially determines the low cutoff frequency of amplifier 300.

[0137] Therefore, the low cutoff frequency of amplifier 300 can be controlled by frequencies Fclk and Fclk1, and a change in one and / or the other of these frequencies causes a corresponding change in the cutoff frequency.

[0138] The resistive element R3 also includes switches 314 and 316. Switch 314 is connected between node 318 and the first electrode or terminal of the capacitive element C7. In other words, switch 314 is connected to the capacitive element C7 between node 318 and the connection node of switch 310. Switch 316 is connected between node 320 and the second electrode or terminal of the capacitive element C7. In other words, switch 316 is connected between node 320 and the connection node from switch 312 to the capacitive element C7. For example, switch 314 has a conductive terminal connected to the first terminal of the capacitive element C7 and another conductive terminal connected to node 318, and switch 316 has a conductive terminal connected to the second terminal of the element C7 and another conductive terminal connected to node 320.

[0139] Two switches, 314 and 316, are controlled in phase with respect to each other and out of phase with respect to switches 310 and 312. In other words, when switches 310 and 312 are on and off respectively, switches 314 and 316 are off and on respectively. Switches 314 and 316 are controlled by a control signal nclk1, for example, provided by the circuit ctrl. As an example, signal nclk1 is the complement of signal clk1, that is, when signal clk1 is in a low / high, binary state, signal nclk1 is in a high / low, binary state. As another example, signal nclk1 may be different from the complement of signal clk1 to ensure that switches 314 and 316 are never simultaneously turned on with switches 310 and 312.

[0140] Node 318 is configured to receive a bias potential Vpoll. The potential Vpoll applies a bias potential, i.e., a DC potential, to node 308, thereby applying a bias potential to the gate of transistor 304.

[0141] According to the embodiment, node 318 is formed. Figure 3 A portion of circuit 321 is defined by a dashed line. Circuit 321 is configured to pass potential Vpol1 to node 318 to apply a DC potential to the gate 308 of transistor 304.

[0142] According to an embodiment, circuit 321 includes a MOS transistor 322, for example having a channel of the same type as transistor 304, and node 318 corresponds to the gate of MOS transistor 322, or in other words, node 318 is connected to the gate of transistor 322. Similar to the source of transistor 304, the source of transistor 322 is configured to receive potential VDD. The source of transistor 322 is thus coupled to, and preferably connected to, node 202. The drain of transistor 322 is connected to node 318. The drain of transistor 322 is also coupled to node 208 via a current source 324. For example, one terminal of current source 324 is coupled (preferably connected) to node 208, and the other terminal is coupled (preferably connected) to the drain of transistor 322 (node ​​318). Those skilled in the art can adjust the size of current source 324 and transistor 322 to determine the value of potential Vpol1. For example, current source 324 is implemented by a MOS transistor of a current mirror.

[0143] Node 320 is configured to receive a bias potential Vcmo. The common-mode output value of stage 302 and amplifier 300 is determined by the value of potential Vcmo, and is, for example, equal to the value of potential Vcmo. As an example, the value of potential Vcmo is equal to the value of potential Vcm ( Figure 2 However, in other examples, these values ​​can be different.

[0144] According to one embodiment, node 320 forms part of circuit 326 configured to deliver a potential Vcm0 at node 320. For example, when potentials Vcm and Vcm0 are equal, circuits 320 and 226 can be implemented by the same circuit, and circuits 320 and 226 are referred to as the same.

[0145] According to one embodiment, circuit 326 is a voltage divider bridge connected between nodes 202 and 208, and node 320 is the intermediate node of voltage divider bridge 326. For example, voltage divider bridge 326 includes two resistive elements R4 and R5, which are connected in series between nodes 202 and 208 and connected to each other at the level of node 320. Elements R4 and R5, for example, have the same resistance value.

[0146] The source of transistor 306 is configured to receive a potential GND. For example, the source of transistor 306 is coupled to, preferably connected to, node 208.

[0147] The drain of transistor 306 is connected to the drain of transistor 304. The drain of transistor 306 is connected, for example, to the output OUT1 of circuit 302. The drain of transistor 306 is further coupled to node 202. More specifically, the drain of transistor 306 is coupled to node 202 via transistor 304.

[0148] Amplifier 302 includes a capacitor element C8 and a switch SW that couples the input IN1 of amplifier 302 to node 328 of stage 302. Node 328 is connected to the gate of transistor 306. In other words, the gate of transistor 306 is coupled to switch SW via capacitor element C8.

[0149] As an example, the capacitor element C8 has a first electrode or terminal coupled (preferably connected) to the switch SW, and a second electrode or terminal coupled (e.g., connected) to the node 328.

[0150] Amplifier 302 also includes a resistor R6 and a capacitor C9. R6 and C9 are connected in parallel between each other between node 328 (the gate of transistor 306) and the drain of transistor 306 (output OUT1). Similar to the element R in stage 200... Figure 2 The resistive element R6 is implemented using a switched capacitor. In other words, the resistive element R6 includes or is formed from a switched capacitor. Element R6 in Figure 3 The middle section is defined by a dashed line.

[0151] Using a switched capacitor to implement the resistive element R6 can achieve a high resistance value, for example, greater than 1 Gohm, on the order of 10 Gohm, while maintaining a reduced size.

[0152] Using a switched capacitor to implement resistor R6 also makes it possible to control the resistance value of resistor R6, which in turn allows control of the low cutoff frequency of the bandpass filter function of amplifier 302, thereby controlling the low cutoff frequency of amplifier 300.

[0153] Furthermore, using a switched capacitor to implement the resistor element R6 enables the common-mode voltage on the output OUT1 of stage 302 and the output OUT1 of amplifier 300 to be set to the target value.

[0154] According to one embodiment, the resistive element R6 includes a switch 330, a capacitor element C10, and a switch 332. Switch 330, capacitor C10, and switch 332 are connected in series between the gate 328 and the drain OUT1 of transistor 306. For example, switch 330 is connected between node 328 and a first electrode or terminal of capacitor C10, and switch 332 is connected between the drain of transistor 306 and a second electrode or terminal of capacitor C10. For example, switch 330 has a conductive terminal connected to node 328 and another conductive terminal connected to capacitor C10, and switch 332 has a conductive terminal connected to element C10 and another conductive terminal connected to the drain of transistor 306.

[0155] Two switches, 330 and 332, are controlled in phase. In other words, when switch 330 is turned on and off, switch 332 is turned on and off, respectively. Switches 330 and 332 are controlled by signal clk1.

[0156] Signal CLK1 determines the resistance value Rval6 of resistor R6, which is equal to 1 / (Fclk1*C10val), where Fclk1 is the frequency of signal clk1 and C10val is the capacitance value of capacitor C10. For example, capacitor C10 is implemented using a metal-oxide-metal (MOM) capacitor. In practice, MOM capacitors have precise capacitance values, which makes it possible to obtain a precise resistance value Rval6.

[0157] Because of the fact that the frequency Fclk1 determines the value Rval6, the frequency Fclk1 also at least partially determines the low cutoff frequency of amplifier 300.

[0158] Therefore, the cutoff frequency of amplifier 300 can be controlled by frequencies Fclk and Fclk1, and a change in one and / or the other of these frequencies causes a corresponding change in the cutoff frequency.

[0159] The resistive element R6 also includes switches 334 and 336. Switch 334 is connected between node 338 and the first electrode or terminal of the capacitive element C10. In other words, switch 334 is connected between node 338 and the connection node from switch 330 to the capacitive element C10. Switch 336 is connected between node 320 and the second electrode or terminal of the capacitive element C10. In other words, switch 336 is connected between node 320 and the connection node from switch 332 to the capacitive element C10. For example, switch 334 has a conductive terminal connected to the first terminal of the capacitive element C10 and another conductive terminal connected to node 338, and switch 336 has a conductive terminal connected to the second terminal of the element C10 and another conductive terminal connected to node 320.

[0160] Two switches, 334 and 336, are controlled in phase with respect to each other and out of phase with respect to switches 330 and 332. In other words, when switches 330 and 332 are turned on and off respectively, switches 334 and 336 are turned off and on respectively. Switches 334 and 336 are controlled by signal nclk1. For example, signal nclk1 is the complementary signal of signal clk1, although signal nclk1 may be different from the complementary signal of signal clk1 to determine that switches 334 and 336, as well as switches 330 and 332, are not turned on simultaneously.

[0161] Node 338 is configured to receive bias potential Vpol2. Potential Vpol2 applies a bias potential, i.e., a DC potential, to node 328 and thus to the gate of transistor 306.

[0162] According to an embodiment, node 338 forms part of circuit 340, in Figure 3 The circuit 340 is configured to pass potential Vpol2 to node 338 to apply a DC potential to the gate 328 of transistor 306.

[0163] According to an embodiment, circuit 340 includes a MOS transistor 342, for example having a channel of the same type as transistor 306, and node 338 corresponds to the gate of MOS transistor 342, or in other words, node 338 is connected to the gate of transistor 342. Similar to the source of transistor 306, the source of transistor 342 is configured to receive potential GND. The source of transistor 342 is thus coupled to, and preferably connected to, node 208. The drain of transistor 342 is connected to node 338, i.e., connected to the gate of transistor 342. The drain of transistor 342 is further coupled to node 202 via a current source 344. For example, one terminal of current source 344 is coupled (preferably connected) to node 202, and the other terminal is coupled (preferably connected) to the drain of transistor 342 (node ​​338). Those skilled in the art can adjust the size of current source 344 and transistor 342 to determine the value of potential Vpol2. For example, current source 344 is implemented by a MOS transistor of a current mirror.

[0164] The switch SW is configured to selectively couple the gate 328 of transistor 306, more specifically, the capacitor element C8, to either input IN1 or node 208. The switch SW is controlled by a control signal A / AB. As an example, signal A / AB is a binary signal having a first binary state controlling the coupling of the gate 328 of transistor 306 to input IN1, and a second binary state controlling the coupling of the gate 328 of transistor 306 to node 208. As an example, the switch SW has an input coupled to node 328, a first output coupled to (preferably connected to) node 208, a second output coupled to (preferably connected to) input IN1, and a control input configured to receive signal A / AB. For example, signal A / AB is provided by circuit ctrl.

[0165] When switch SW couples the gate 328 of transistor 306 to node 208, stage 302 is a Class A amplifier; when switch SW couples the gate 328 of transistor 306 to input IN1, stage 302 is a Class AB amplifier. When stage 302 is controlled in Class A and Class AB respectively, amplifier 300 is a Class A and Class AB amplifier respectively.

[0166] As an example, stage 302 is controlled in class A for the application of a privileged cutoff frequency of the low-pass function between input IN and output OUT1, which is as low as possible relative to the maximum slope (“slew rate”) of the signal available on output OUT1. Conversely, stage 302 is controlled in class AB for the application of a privileged cutoff frequency of the maximum slope of the signal on output OUT1 relative to achieving the lowest possible low-pass cutoff frequency.

[0167] exist Figure 3 In one example, switch SW is coupled to the gate 328 of transistor 306, the source of transistor 306 is configured to receive potential GND, and switch SW is configured to selectively couple gate 328, and more specifically, capacitor element C8, to node 208 or input IN1. In another example not shown, switch SW is coupled to the gate 308 of transistor 304, the source of transistor 304 is configured to receive potential VDD, and switch SW is then configured to couple gate 308 (more specifically, capacitor element C5) to node 202 or input IN1. In this case, switch SW has, for example, an input coupled to node 308, a first output coupled to (preferably connected to) node 202, a second output coupled to (preferably connected to) input IN1, and a control input configured to receive signal A / AB.

[0168] exist Figure 3 In one example, switch SW is configured to selectively couple gate 328 to node 208 or input IN1, and capacitor element C5 is connected to input IN1. In another example, where switch SW is also configured to selectively couple gate 328 to node 208 or input IN1, the same switch as switch SW can be provided between capacitor element C5 and input IN1 and controlled to maintain gate 308, more specifically, to maintain capacitor element C5 coupled to input IN1. This additional switch, the same as switch SW, is currently referred to as a dummy switch and, for example, enables the balancing of the conductive path between input IN1 and node 308 with the conductive path between input IN1 and node 328. Those skilled in the art will be able to adapt such an example to a case where switch SW is configured to selectively couple node 308 to input IN1 or to node 202, and the dummy switch subsequently couples node 328 to input IN1.

[0169] According to another embodiment not shown, the second stage 302 is replaced by the second stage 200. In this case, the second stage 200 is a Class A amplifier, and thus the amplifier 300 is a Class A amplifier.

[0170] According to another embodiment, the second stage 302 does not include a switch SW, and component C8 is connected to input IN1. In this case, stage 302 and amplifier 300 are fixed in class AB.

[0171] Although stage 302 has been disclosed and described as being connected to the rest of stage 200, it can be omitted by directly connecting the input IN1 of stage 302 to the input IN of the amplifier. In other words, stage 302 is an amplifier that can be used in a fixed Class AB configuration when switch SW is omitted, or in a Class A or Class AB configuration selectable by signal A / AB.

[0172] To combine Figure 2 In the same manner as described for capacitor element C3, each of capacitor elements C7 and C10 can be implemented using capacitor elements with controllable capacitance values ​​to control the cutoff frequency of the low-pass filtering function between input IN1 and output OUT1, or more generally, between input IN and output OUT1.

[0173] Preferably, transistors 304 and 306 have similar or identical dimensions, such that the slope of the signal transitioning from a high state to a low state on output OUT1 is similar to or the same as the slope during the transition from a low state to a high state. However, one of transistors 304 and 306 may be selected to be larger than the other to support the rise time or fall time of the signal on output OUT1.

[0174] Combined on the above Figure 3 In the described example, the frequencies of signals clk and nclk are different from the frequencies of signals clk1 and nclk1. In another example, the frequencies of signals clk and nclk are the same as the frequencies of signals clk1 and nclk1, for example, when signals clk and clk1 correspond to the same signal and signals nclk and nclk1 correspond to the same other signal.

[0175] According to an embodiment, amplifier 300 is implemented in a radio frequency (RF) receiver, preferably in a wake-up RF receiver including an envelope detection circuit having an input coupled to an antenna of the RF receiver and an output coupled to, for example, an input IN connected to amplifier 300. The output OUT1 of amplifier 300 is coupled to, for example, a quantization circuit connected to one bit. Preferably, the RF receiver is configured to receive an amplitude-modulated RF signal, preferably all-or-no-amplification, for example according to Manchester encoding. For example, amplifier 300 replaces... Figure 1 The receiver Rx contains two circuits or stages, BBA and BPF.

[0176] However, those skilled in the art can achieve different combinations Figure 1Amplifier 300 is implemented in the described radio frequency receiver.

[0177] For example, an amplifier 302 can be provided in the RF receiver to amplify the amplitude-modulated envelope signal of the RF signal instead of using Manchester encoding, or even without amplitude modulation at all, while simultaneously implementing bandpass filtering, for example, using high and low cutoff frequencies lower than those of known bandpass amplifiers.

[0178] More generally, amplifier 300 can be provided in all applications or in all systems where it is desirable to simultaneously achieve signal amplification and bandpass filtering, for example, having a low cutoff frequency below 500 Hz, preferably less than or equal to 100 Hz, and / or having reduced power consumption, for example, compared to known circuits capable of achieving these amplification and low-pass filtering functions.

[0179] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to them. In particular, those skilled in the art can adapt the above description of amplifier 302 to cases where the potential VDD is negative relative to the potential GND, for example, by replacing the P-channel, N-channel, and MOS transistors with N-channel, P-channel, and MOS transistors respectively.

[0180] Furthermore, the embodiments are not limited to the examples of circuits 221, 226, 326, 321 and 340, and those skilled in the art will be able to provide other implementations for these circuits, for example by replacing at least one of these circuits with a constant voltage source that delivers the same constant potential as the circuit it replaces.

[0181] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art. In particular, the implementation of the switching of the switched capacitor is within the capabilities of those skilled in the art, for example, by implementing each of these switches using MOS transistors.

[0182] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art based on the description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. An amplifier, comprising: A first MOS transistor has a drain connected to the output of the amplifier and a source coupled to a first node, the first node being configured to receive a first power supply potential. A first capacitor element is connected between the input of the amplifier and the gate of the first MOS transistor; A first current source connects the drain of the first MOS transistor to a second node, the second node being configured to receive a second power supply potential; as well as A resistive element and a second capacitive element are connected in parallel between the gate and drain of the first MOS transistor, respectively. The resistive element includes: A first switch is connected between the gate of the first MOS transistor and the first electrode of the third capacitor element. The second switch is connected between the second electrode of the third capacitor element and the drain of the first MOS transistor. A third switch is connected between the first electrode of the third capacitor element and a third node configured to receive a first bias potential. as well as A fourth switch is connected between the second electrode of the third capacitor element and a fourth node configured to receive a second bias potential. The third node is a second MOS transistor having a gate configured to receive the source of the first power supply potential, and the drain of the second MOS transistor is connected to the third node and coupled to the second node via a second current source.

2. The amplifier of claim 1, wherein the first switch and the second switch are controllable in phase with respect to each other, and wherein the switching frequencies of the first switch and the second switch determine the low cutoff frequency of the amplifier.

3. The amplifier of claim 1, wherein the first MOS transistor and the second MOS transistor, as well as the first current source and the second current source, are configured such that the first bias potential applies a DC potential to the gate of the first MOS transistor.

4. The amplifier according to claim 3, The first current source includes a third MOS transistor assembled mirror-image with the fourth MOS transistor, and The second current source includes a fifth MOS transistor assembled in mirror image with the fourth MOS transistor.

5. The amplifier according to claim 1, wherein the first MOS transistor and the second MOS transistor are NMOS transistors.

6. The amplifier of claim 1, further comprising circuitry configured to control the first switch and the second switch in opposite phase relative to the third switch and the fourth switch.

7. The amplifier of claim 6, wherein the circuitry is configured to provide a frequency for determining the resistance value of the resistive element.

8. The amplifier of claim 6, wherein the circuitry is configured to provide a frequency that determines the low cutoff frequency of the amplifier.

9. The amplifier of claim 1, wherein the second bias potential determines the common-mode output voltage of the amplifier.

10. The amplifier of claim 1, wherein the second bias potential is equal to half the difference between the first power supply potential and the second power supply potential.

11. The amplifier of claim 1, wherein the fourth node is an intermediate node of a voltage divider bridge connected between the first node and the second node.

12. The amplifier of claim 1, further comprising a capacitor output element connected between the output of the amplifier and the first node.

13. The amplifier of claim 1, wherein the amplifier is a bandpass amplifier.

14. The amplifier of claim 1, wherein the gain of the amplifier is equal to the ratio of the capacitance of the first capacitor element to the capacitance of the second capacitor element.

15. A radio frequency receiver, comprising: An envelope detection circuit having an input coupled to an antenna coupled to a receiver and an output coupled to an input coupled to an amplifier according to claim 1.

16. The radio frequency receiver of claim 15, wherein the receiver is a wake-up radio frequency receiver.

17. The radio frequency receiver of claim 15, wherein the receiver is configured to receive an amplitude-modulated radio frequency signal.

18. The amplifier of claim 1, further comprising a capacitor output element connected between the output of the amplifier and the first node, the capacitor output element comprising: The first amplifier includes: A first MOS transistor has a drain connected to the output of the first amplifier and a source coupled to a first node, the first node being configured to receive a first power supply potential. A first capacitor element is connected between the input of the first amplifier and the gate of the first MOS transistor of the first amplifier. A first current source connects the drain of the first MOS transistor of the first amplifier to a second node, the second node being configured to receive a second power supply potential; and A resistive element and a second capacitive element are connected in parallel between the gate and drain of the first MOS transistor in the first amplifier, respectively. The resistive element includes a switched capacitor. Input, connected to the input of the first amplifier; A second amplifier has an input connected to the output of the first amplifier, the second amplifier comprising: Fourth capacitor element; The third MOS transistor has a gate coupled to the input of the second amplifier via the fourth capacitor element of the second amplifier, a source coupled to one of the first and second nodes of the first amplifier, and a drain coupled to the other of the first and second nodes of the first amplifier. The first resistive element and the fifth capacitive element are connected in parallel between the drain and the gate of the third MOS transistor, respectively. The first resistive element is the first switched capacitor. The fourth MOS transistor has a source coupled to another node in the first node and the second node of the first amplifier and a drain connected to the drain of the third MOS transistor. A second resistive element and a fifth capacitive element are connected in parallel between the drain and gate of the fourth MOS transistor, respectively. The second resistive element is a second switched capacitor. A switch and a sixth capacitor element, the sixth capacitor element coupling the gate of the fourth MOS transistor to the switch, and the switch being configured to selectively couple the sixth capacitor element to another node of the first node and the second node or to the input of the second amplifier; and The output is connected to the output of the second amplifier.

19. The amplifier according to claim 18, The first switched capacitor includes: The first switch is connected between the gate of the third MOS transistor of the second amplifier and the first electrode of the sixth capacitor element of the second amplifier. The second switch is connected between the second electrode of the sixth capacitor element of the second amplifier and the drain of the third MOS transistor of the second amplifier. A third switch is connected between the first electrode of the sixth capacitor element of the second amplifier and the third node of the second amplifier, the third node of the second amplifier being configured to receive a first bias potential of the second amplifier. A fourth switch is connected between the second electrode of the sixth capacitor element of the second amplifier and the fourth node of the second amplifier, the fourth node of the second amplifier being configured to receive the second bias potential of the second amplifier, and The second switched capacitor includes: The fifth switch is connected between the gate of the fourth MOS transistor of the second amplifier and the first electrode of the seventh capacitor element of the second amplifier. The sixth switch is connected between the second electrode of the seventh capacitor element of the second amplifier and the drain of the fourth MOS transistor of the second amplifier. A seventh switch is connected between the first electrode of the seventh capacitor element of the second amplifier and the fifth node of the second amplifier, the fifth node of the second amplifier being configured to receive the third bias potential of the second amplifier; and The eighth switch is connected between the second electrode of the seventh capacitor element of the second amplifier and the fourth node of the second amplifier.

20. The amplifier of claim 18, wherein the frequency of switching of the switched capacitor for controlling the first amplifier is different from the frequency of switching of the first switched capacitor and the second switched capacitor for controlling the second amplifier.

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