A load switch circuit and chip

Abstract

The application provides a load switch circuit and a chip, which are used for providing overload protection for a load switch, and the load switch circuit at least comprises a protection module, an adjusting module and the load switch, the load switch is used for transmitting electric energy from a power supply to a load; the protection module monitors the electric energy received by the load, and limits the overload electric energy flowing through the load switch in the first time; the adjusting module adjusts the electric energy transmitted by the load switch by collecting the electric energy output by the power supply. The first triode and the second triode in the protection module form a Darlington structure, the electric energy received by the load is monitored, and the overload electric energy flowing through the load switch is limited in the first time, so that the heat breakdown and the latch effect of the load switch caused by the delay of the electric energy flowing through the load switch due to the drop of the electric energy when the load is overloaded at the moment are fundamentally solved, and irreversible damage of the load switch is caused. The structure is simple, the cost is low, the system static power consumption is not increased, and the application scenarios are wide.

Description

Technical Field

[0001] This invention relates to the field of power supply design and application technology, and in particular to a load switching circuit and chip. Background Technology

[0002] In power supply circuits, load switches are typically used as the medium connecting the power supply and the load. They are integrated electronic devices used to turn the power rail on and off. When the load switch is on, it allows electrical energy to flow from the input pin to the output pin and to downstream circuits, such as the load. Currently, the most widely used load switches are N-channel enhancement-mode metal-oxide-semiconductor field-effect transistors, or N-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). This is because N-channel MOSFETs have low on-resistance and are relatively compact. To maintain a low on-resistance when an N-channel MOSFET is turned on, the gate voltage must be sufficiently high so that the voltage difference Vgs from the gate to the source is greater than the threshold voltage Vt of the N-channel MOSFET (typically around 0.7V), and the N-channel MOSFET operates in the linear region.

[0003] However, in practical applications, N-channel MOSFETs often encounter situations where the load is momentarily overloaded, such as a sudden short circuit at the output terminal. In this case, the voltage difference Vgs cannot be reduced in time, causing the N-channel MOSFET to carry an extremely high current for a long period of time, which leads to the entire circuit burning out due to thermal breakdown.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a load switch circuit and chip to solve the problem that the overload current passing through the load switch cannot be reduced in time when the load switch circuit is momentarily overloaded, thus causing damage to the load switch.

[0006] To achieve the above and other related objectives, the present invention provides a load switch circuit for providing overload protection for a load switch. The load switch circuit includes at least: a protection module, a regulating module, and a load switch, wherein:

[0007] The load switch is connected between the power source and the load to transfer electrical energy from the power source to the load;

[0008] The first end of the protection module is connected to the power supply, the second end is connected to the load switch, and the third end is connected to the connection point between the load and the load switch. It monitors the electrical energy received by the load and limits the overload electrical energy flowing through the load switch in the first instance.

[0009] The first end of the adjustment module is connected to the power supply, and the second end is connected to the load switch and the protection module. By collecting the electrical energy output by the power supply, the module adjusts the electrical energy transmitted by the load switch.

[0010] Optionally, the protection module includes: a first capacitor, a first resistor, a second resistor, a first transistor, and a second transistor, wherein: the upper plate of the first capacitor is connected to the power supply; the first end of the first resistor is connected to the lower plate of the first capacitor, and the second end is connected to the connection point between the load and the load switch; the first terminal of the first transistor is connected to the load switch, and the third terminal is connected to the connection point between the load and the load switch; the first terminal of the second transistor is connected to the first terminal of the first transistor, the second terminal is connected to the lower plate of the first capacitor via the second resistor, and the third terminal is connected to the second terminal of the first transistor.

[0011] Optionally, both the first transistor and the second transistor are NPN transistors, wherein the first electrode of the first transistor and the second transistor is the collector, the second electrode is the base, and the third electrode is the emitter.

[0012] Optionally, the ratio of the resistance of the first resistor to the resistance of the second resistor is between 10 and 100.

[0013] Optionally, the load switch includes a first NMOS transistor, wherein the drain of the first NMOS transistor is connected to the power supply, the gate is connected to the regulation module, and the source is connected to the load.

[0014] Optionally, the adjustment module includes: a charge pump, an amplifier, a sampling unit, and a discharge unit, wherein the charge pump is connected to the load switch; the sampling unit is connected to the power supply; the non-inverting input of the amplifier is connected to the sampling unit, and the inverting input is connected to a reference signal; the discharge unit is connected between the output of the amplifier and the output of the charge pump.

[0015] Optionally, the sampling unit is a current sensing resistor, a Hall sensor, or a current transformer.

[0016] Optionally, the discharge unit includes a second NMOS transistor, wherein the drain of the second NMOS transistor is connected to the output terminal of the charge pump, the gate is connected to the output terminal of the amplifier, and the source is connected to reference ground.

[0017] To achieve the above and other related objectives, the present invention provides a chip based on the load switching circuit of the present invention. The chip is connected between the power supply and the load and is used to provide overload protection for the load.

[0018] As described above, the load switching circuit and chip of the present invention have the following beneficial effects:

[0019] 1) The load switch circuit and chip of the present invention are composed of a Darlington structure formed by the first transistor and the second transistor in the protection module. The power received by the load is monitored and the overload power flowing through the load switch is limited in the first time. This fundamentally solves the problem that when the load switch is momentarily overloaded, the power flowing through the load switch decreases due to the time delay, which causes the load switch to thermal breakdown and latch-up, resulting in irreversible damage to the load switch.

[0020] 2) The load switching circuit and chip of the present invention have a simple structure, low cost, and do not cause an increase in the static power consumption of the system, and have a wide range of application scenarios. Attached Figure Description

[0021] Figure 1 The diagram shown is a schematic of an exemplary load switching circuit of the present invention.

[0022] Figure 2 The diagram shown illustrates the relationship between load switch current and voltage in an exemplary load switch circuit of the present invention.

[0023] Figure 3 The diagram shows the working state of an exemplary load switch circuit according to the present invention.

[0024] Figure 4 The diagram shown is a schematic of the load switching circuit of the present invention.

[0025] Figure 5 The diagram shows the working state of the load switch circuit of the present invention.

[0026] Explanation of reference numerals in the attached figures

[0027] 1. Load switching circuit

[0028] 11 Protection Module

[0029] 12 Load switches

[0030] 13 Adjustment Module

[0031] 131 Charge Pump

[0032] 132 Amplifier

[0033] 133 sampling units

[0034] 134 discharge units Detailed Implementation

[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] Please see Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. The illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0037] Figure 1 A load switch circuit is shown, wherein the load switch is Nq1, which is an N-channel enhancement-mode metal-oxide-semiconductor field-effect transistor with its drain connected to the power supply IN1 and its source connected to the OUT1 terminal; CL1 is the load capacitor and RL1 is the load resistor. Both CL1 and RL1 are connected to the OUT1 terminal, and CL1 and RL1 are connected in parallel.

[0038] like Figure 1 As shown, the charge pump provides charge to the gate of Nq1, causing the gate voltage Vg1 of Nq1 to rise. When the voltage difference Vgs1 between the gate and source of Nq1 is greater than the threshold voltage Vt1 of Nq1, Nq1 turns on. The higher the value of Vgs1, the lower the on-resistance of Nq1, the lower the conduction loss, and the higher the efficiency of the load switch circuit. Therefore, designers usually maintain the voltage difference Vgs1 between the gate and source of the load switch Nq1 at a relatively high value, assuming a high voltage value of Vgs1_high, so that the load switch Nq1 operates in the linear region when turned on, at which time the voltage at the OUT1 terminal is approximately equal to the voltage of the power supply IN1.

[0039] However, in actual use, the load connected to the OUT1 terminal (including the load capacitor CL1 and the load resistor RL1) may pose a safety hazard when the load switch Nq1 changes from a light load state to an overload state. That is, the current through the load changes from a small current state to a large current state, which may lead to the damage of the load switch Nq1. This includes: a sudden and significant increase in the load current, and the OUT1 terminal being momentarily disconnected from the reference ground.

[0040] Specifically, as an example, such as Figure 1 As shown, when the load resistor RL1 changes from a light load to an overload instantaneously, the voltage at the OUT1 terminal (the source of the load switch Nq1) is momentarily pulled low, but the drain voltage of the load switch Nq1 (connected to the power supply IN1) does not change. Therefore, the voltage difference Vds1 between the drain and source of the load switch Nq1 increases instantaneously. However, the charge on the parasitic capacitance Cgs1 between the gate and source of the load switch Nq1 does not change abruptly. Therefore, when the state of the load resistor RL1 instantaneously changes from the linear region to the saturation region, the current IL1 through the load switch Nq1 increases instantaneously. More specifically, as... Figure 2 As shown, when the load resistor RL1 becomes overloaded, the current through the load switch Nq1 increases to IL1_max, resulting in the following calculation formula:

[0041] IL1_max=k×(Vgs1_high-Vthn1) 2 ;

[0042] Where k is a relevant constant of load switch Nq1, and Vthn1 is the turn-on voltage of load switch Nq1. Figure 2 The dashed line in the diagram represents the boundary between the linear region and the saturation region.

[0043] like Figure 1 As shown, the sampling module detects the current IL1 passing through the load switch Nq1 and converts it into a corresponding voltage value Vs1. Vs1 is proportional to IL1, Vs1 = IL1 × Rs, where Rs is the current sampling gain of the sampling module. Further, Vs1 serves as the input signal to the non-inverting input of the amplifier, and is compared and amplified with the reference signal Vr1. When Vs1 is greater than the voltage value of the reference signal Vr1, the amplifier's output voltage Vpd1 increases; when Vs1 is less than the voltage value of the reference signal Vr1, the amplifier's output voltage Vpd1 decreases. When Vpd1 is greater than the threshold voltage of the NMOS transistor Npd1, Npd1 is turned on, and Npd1 discharges through the gate of the load switch Nq1, causing the voltage difference Vgs1 between the gate and source of the load switch Nq1 to decrease, thereby reducing the current IL1 passing through the load switch Nq1. When Vpd1 is less than the threshold voltage of the NMOS transistor Npd1, Npd1 is turned off, and Npd1 does not discharge through the gate of the load switch Nq1.

[0044] like Figure 1 As shown, when the load resistor RL1 changes from a light load state to an overload state, the current IL1 through the load switch Nq1 is controlled by a feedback loop consisting of the sampling module, amplifier, and NMOS transistor Npd1. When the feedback loop is stable, the current through the load switch Nq1 is limited. The current limit value of the load switch Nq1 is set to IL1_limit. At this time, the voltages at the non-inverting and inverting inputs of the amplifier are equal, resulting in the following calculation formula:

[0045] IL1_limit=Vr1 / Rs=k×(Vgs1_limit-Vthn1) 2 ;

[0046] Where Vgs1_limit is the gate-source voltage value when the load switch Nq1 is current-limited, Rs is the current sampling gain of the sampling module, and the voltage value of the reference signal Vr1 is represented as Vr1. The relationship between Vgs1_limit and IL1_limit is as follows: Figure 2 As shown.

[0047] like Figure 1 As shown, when the load resistor RL1 changes from a light load state to an overload state, the current through the load switch Nq1 changes from being greater than IL1_limit until the feedback loop adjusts the current of the load switch Nq1 to IL1_limit. This requires a certain delay time Td1, where Td1 includes the response delay of the sampling module and amplifier, and the rise delay of the gate voltage of the NMOS transistor Npd1. If the load switch circuit is used in a control circuit for a low-power scenario, low-power scenarios typically employ a low quiescent current design, which determines that the response delay time of the sampling module and amplifier will be large. The rise process of the gate voltage of the NMOS transistor Npd1 is the process of the amplifier's output current charging the gate voltage of Npd1. In a low quiescent current environment, the rise delay time of the gate voltage of Npd1 is also large. Specifically, Figure 3 The timing relationships of the voltage at OUT1, the gate-source voltage difference Vgs1 of the load switch Nq1, the gate voltage Vpd1 of the NMOS transistor Npd1, and the current IL1 flowing through the load switch Nq1 are shown. IN1 This is the voltage of power supply IN1.

[0048] Specifically, during the delay time Td1, if the current through the load switch Nq1 remains at a large current IL1_max, it typically causes the load switch Nq1 to overheat instantaneously, posing a risk of thermal breakdown. Furthermore, a sustained large current IL1_max may trigger a latch-up problem common in integrated circuits, leading to damage to the load switch circuit. It should be noted that latch-up is a low-impedance path in metal-oxide-semiconductor devices, resulting from the interaction between parasitic PNP and NPN bipolar junction transistors between the power supply and reference ground. This low-impedance path leads to a large current between the power supply and reference ground, potentially causing permanent damage to the device.

[0049] like Figure 1 As shown, to mitigate the high current problem caused by the instantaneous overload of the load switch Nq1, the load capacitor CL1 is usually designed as a large capacitor to reduce the voltage drop at the OUT1 terminal. On the one hand, this makes it difficult to fundamentally solve the problem of untimely protection of the load switch Nq1 due to the existence of the delay time Td1; on the other hand, it also increases the cost of the circuit.

[0050] Therefore, the present invention provides a load switch protection circuit and chip, as detailed below:

[0051] like Figure 4 As shown, this embodiment provides a load switch circuit 1 for providing overload protection for the load switch. The load switch circuit 1 includes: a protection module 11, a regulating module 13, and a load switch 12, wherein:

[0052] like Figure 4 As shown, load switch 12 is connected between power supply IN2 and load to transfer electrical energy from power supply IN2 to load. The load includes load resistor RL2 and load capacitor CL2. Load resistor RL2 and load capacitor CL2 are connected in parallel and are connected between OUT2 terminal and reference ground.

[0053] Specifically, as an example, such as Figure 4As shown, the load switch 12 includes a first NMOS transistor Nq2. The drain of the first NMOS transistor Nq2 is connected to the power supply IN2, the gate is connected to the regulation module 13, and the source is connected to the load. When the load instantly changes from light load to overload, the voltage at the OUT2 terminal (i.e., the source voltage of the first NMOS transistor Nq2) is instantly pulled down. However, the drain of the first NMOS transistor Nq2 remains unchanged because it is connected to the power supply IN2. Therefore, the voltage difference Vds2 between the drain and source of the first NMOS transistor Nq2 increases instantaneously. The charge on the parasitic capacitance Cgs2 between the gate and source of the first NMOS transistor Nq2 does not change abruptly. Therefore, when the load resistor RL2 instantly changes from light load to overload, the voltage difference Vgs2 between the gate and source of the first NMOS transistor Nq2 does not change abruptly. The state of Nq2 instantly changes from the linear region to the saturation region, and the current IL2 passing through Nq2 increases instantaneously. It should be noted that the first NMOS transistor Nq2 has a low on-resistance and a compact size, which meets the requirements of the load switch 12. It should be further noted that the load switch 12 includes, but is not limited to, the first NMOS transistor Nq2. Any device that can be used as the load switch 12 is applicable as long as it can meet the requirements of low on-resistance and compact size, and is not limited to this embodiment.

[0054] like Figure 4 As shown, the first end of the protection module 11 is connected to the power supply IN2, the second end is connected to the load switch 12, and the third end is connected to the connection point between the load and the load switch 12, i.e., the OUT2 end. It monitors the electrical energy received by the load and limits the overload electrical energy flowing through the load switch 12 in the first instance.

[0055] Specifically, as an example, such as Figure 4 As shown, the protection module 11 includes: a first capacitor C1, a first resistor R1, a second resistor R2, a first transistor Q1, and a second transistor Q2. The upper plate of the first capacitor C1 is connected to the power supply IN2. The first end of the first resistor R1 is connected to the lower plate of the first capacitor C1, and the second end is connected to the connection point between the load and the load switch 12, i.e., the OUT2 terminal. The voltage across the lower plate of the first capacitor C1 is denoted as Vc. The first terminal of the first transistor Q1 is connected to the load switch 12, and the third terminal is connected to the connection point between the load and the load switch 12, i.e., the OUT2 terminal. The first terminal of the second transistor Q2 is connected to the first terminal of the first transistor Q1, the second terminal is connected to the lower plate of the first capacitor C1 via the second resistor R2, and the third terminal is connected to the second terminal of the first transistor Q1.

[0056] More specifically, both the first transistor Q1 and the second transistor Q2 are NPN transistors. The first terminal of both transistors Q1 and Q2 is the collector, the second terminal is the base, and the third terminal is the emitter. It should be noted that transistors Q1 and Q2 form a Darlington structure, used to discharge the gate of the first NMOS transistor Nq2 in the load switch 12. The Darlington structure is a composite structure composed of two or more bipolar transistors (or other similar integrated circuits or discrete components). Through the Darlington structure, the current passing through a single bipolar transistor can be further amplified, providing a much higher current gain than any single bipolar transistor, accelerating the flow of electrical energy and speeding up the discharge process of the gate of the first NMOS transistor Nq2, avoiding delays. When the Darlington structure consists of two bipolar transistors, there are four possible configurations: NPN+NPN, PNP+PNP, NPN+PNP, and PNP+NPN. The first two are same-polarity connection methods, and the latter two are opposite-polarity connection methods. In this embodiment, the Darlington structure used is NPN+NPN.

[0057] More specifically, the ratio of the resistance values ​​of the first resistor R1 to the second resistor R2 is between 10 and 100. It should be noted that the upper plate of the first capacitor C1 is connected to the power supply IN2, V. IN2 Given the voltage at power supply IN2, before the load resistor RL2 changes from light load to overload, the voltage at terminal OUT2 can be approximated as the voltage V at power supply IN2. IN2 Equal; the first capacitor C1 discharges through the first resistor R1, and the voltage Vc of the lower plate of the first capacitor C1 can also be approximated as the voltage V of the power supply IN2. IN2 Since they are equal, the amount of charge stored in the first capacitor C1 will not change abruptly. Therefore, in the initial stage of the rapid voltage drop at the OUT2 terminal, Vc equals V. IN2 When the load resistor RL2 changes from light load to overload instantaneously, and the voltage at the OUT2 terminal drops rapidly, the first capacitor C1 charges through the first resistor R1 and the second resistor R2. As the first capacitor C1 charges, the voltage Vc of the lower plate of the first capacitor C1 decreases from V... IN2 As the current begins to decrease, the first resistor R1 is typically chosen to have a relatively large resistance, usually several hundred kilohms or even megahms. The second resistor R2, on the other hand, is usually less than 10 kilohms and is used to adjust the current of the second transistor Q2, thereby adjusting the current through the entire Darlington structure. Since the current through the first resistor R1 is negligible compared to the current through the second resistor R2, the current through the second resistor R2 can be calculated as follows:

[0058] I R2 =(Vc-2×V) BE -V OUT2 ) / R2;

[0059] Among them, V BE V is the voltage difference between the base and emitter of transistors Q1 and Q2 when they are turned on. OUT2 This is the voltage at terminal OUT2. The discharge current of the Darlington structure formed by the first transistor Q1 and the second transistor Q2 to the gate of the first NMOS transistor Nq2 is:

[0060] I discharge =I R2 ×β2+I R2 ×(1+β2)×β1=I R2 ×(β1+β2+β1×β2);

[0061] Where β1 is the amplification factor of the first transistor Q1 and β2 is the amplification factor of the second transistor Q2. It can be seen that by adopting the Darlington structure, the gate discharge current of the first NMOS transistor Nq2 can be increased.

[0062] When the voltage Vc of the lower plate of the first capacitor C1 is greater than the voltage V at the OUT2 terminal... OUT2 Height 2×V BE At this time, the Darlington structure begins to discharge the gate of the first NMOS transistor Nq2; when the voltage Vc of the lower plate of the first capacitor C1 is greater than the voltage V at the OUT2 terminal... OUT2 Low 2×V BE At this point, the Darlington structure stops discharging the gate of the first NMOS transistor Nq2. The discharge current of the gate of the first NMOS transistor Nq2 is adjusted by changing the resistance of resistor R2, and the rate of decrease of the voltage Vc at the lower plate of capacitor C1 is adjusted by changing the capacitance of capacitor C1. When the first NMOS transistor Nq2 is operating stably, no current flows through resistor R1, and Vc equals the voltage V at terminal OUT2. OUT2 .

[0063] It should be further explained that the protection module 11 includes, but is not limited to, the first capacitor C1, the first resistor R1, the second resistor R2, the first transistor Q1, and the second transistor Q2. As long as it can accelerate the flow of electrical energy and accelerate the discharge process of the gate of the first NMOS transistor Nq2 in the first time, thereby avoiding delay, any setting of the protection module 11 is applicable and is not limited to this embodiment.

[0064] like Figure 4 As shown, the first end of the adjustment module 13 is connected to the power supply IN2, and the second end is connected to the load switch 12 and the protection module 11. By collecting the electrical energy output by the power supply IN2, the module adjusts the electrical energy transmitted by the load switch 12.

[0065] Specifically, as an example, such as Figure 4As shown, the adjustment module 13 includes a charge pump 131, an amplifier 132, a sampling unit 133, and a discharge unit 134. The charge pump 131 is connected to the load switch 12; the sampling unit 133 is connected to the power supply IN2; the non-inverting input of the amplifier 132 is connected to the sampling unit 133, and the inverting input is connected to the reference signal Vr2; the discharge unit 134 is connected between the output of the amplifier 132 and the output of the charge pump 131. It should be noted that the charge pump 131 provides charge to the gate of the first NMOS transistor Nq2, causing the gate voltage Vg2 of Nq2 to rise. When the voltage difference Vgs2 between the gate and source of Nq2 is greater than the threshold voltage Vt2 of Nq2, Nq2 is turned on. The higher the value of Vgs2, the smaller the on-resistance of Nq2, the smaller the conduction loss, and the higher the efficiency of the load switch circuit.

[0066] More specifically, such as Figure 4 As shown, the sampling unit 133 is a current sensing resistor, a Hall sensor, or a current transformer. The sampling unit 133 is used to sample the current IL2 passing through the load switch 12 and convert the current IL2 into the corresponding voltage value Vs2. The relationship between Vs2 and the current IL2 will not be elaborated here.

[0067] More specifically, the discharge unit 134 includes a second NMOS transistor Npd2, wherein the drain of the second NMOS transistor Npd2 is connected to the output terminal of the charge pump 131, the gate is connected to the output terminal of the amplifier 132, and the source is connected to the reference ground. Further, when Vs2 is greater than the voltage value of the reference signal Vr2, the output voltage Vpd2 of the amplifier 132 increases; when Vs2 is less than the voltage value of the reference signal Vr2, the output voltage Vpd2 of the amplifier 132 decreases. When Vpd2 is greater than the threshold voltage of the second NMOS transistor Npd2, Npd2 is turned on, and Npd2 discharges to the load switch 12, causing the voltage difference Vgs2 between the gate and source of the first NMOS transistor Nq2 in the load switch 12 to decrease, thereby reducing the current IL2 passing through the load switch 12; when Vpd2 is less than the threshold voltage of the second NMOS transistor Npd2, Npd2 is turned off, and Npd2 does not discharge to the gate of the first NMOS transistor Nq2 in the load switch 12.

[0068] like Figure 4 As shown, when the load resistor RL2 changes from a light load state to an overload state, the current IL2 passing through the first NMOS transistor Nq2 in the load switch 12 is controlled by a feedback loop consisting of the sampling unit 133, amplifier 132, and second NMOS transistor Npd2 in the adjustment module 13. When the feedback loop is stable, the current passing through the load switch 12 is limited, and the current limit value of the load switch 12 is set to IL2_limit.

[0069] When the load resistor RL2 changes from a light load state to an overload state, the current value through the load switch 12, starting from exceeding IL2_limit, requires a certain delay time Td2 for the feedback loop to adjust the current value of the load switch 12 to IL2_limit before the gate voltage of the first NMOS transistor Nq2 in the load switch 12 can be adjusted. Once the output voltage of the amplifier 132 stabilizes, the current through the load switch 12 remains at IL2_limit.

[0070] IL2_limit=Vr2 / Rs=k×(Vgs2_limit-Vthn2) 2 ;

[0071] Vgs2_limit is the gate and source voltage value when Nq2 is current-limited, Rs is the current sampling gain of sampling unit 133, the voltage value of reference signal Vr2 is represented as Vr2, and Vthn2 is the turn-on voltage of the first NMOS transistor Nq2. Td2 includes: the response delay of sampling unit 133 and amplifier 132, and the rise delay of the gate voltage of the second NMOS transistor Npd2.

[0072] However, the Darlington structure in protection module 11 can immediately limit the overload energy flowing through load switch 12, and the voltage V at OUT2 terminal... OUT2 The gate of the first NMOS transistor Nq2 in the load switch 12 is discharged at the instant of rapid drop, reducing the voltage difference Vgs2 between the gate and source of the first NMOS transistor Nq2 immediately. According to the formula IL2=k×(Vgs2-Vthn2), 2 The decrease in Vgs2 can reduce the current flowing through load switch 12, where k is a constant related to the first NMOS transistor Nq2, and Vthn2 is the turn-on voltage of the first NMOS transistor Nq2. The voltage at OUT2 terminal V... OUT2 The greater the drop, the more the gate discharge current of Nq2 is regulated by the second resistor R2 and the first capacitor C1. Since the resistance of the first resistor R1 is greater than that of the second resistor R2, the first resistor R1 can slowly charge and discharge the first capacitor C1, so that the voltage Vc of the lower plate of the first capacitor C1 slowly follows the voltage V of the OUT2 terminal. OUT2 This causes the Darlington structure in the protection module 11 to turn off during normal operation of the load switch 12 and stop discharging the gate of the first NMOS transistor Nq2, reducing the current of the load switch 12 without any delay, avoiding the thermal breakdown and latch-up effect of the load switch 12, fundamentally solving the problem of untimely protection of the load switch 12 due to the existence of the delay time Td2, and at the same time, there is no need to change the capacitance value of the load capacitor CL2.

[0073] Furthermore, when the load switch 12 is operating normally, the voltage Vc of the lower plate of the first capacitor C1 is equal to the voltage V at the OUT2 terminal. OUT2 When the Darlington structure is in the off state, no current flows through the protection module 11, which will not cause an increase in the system's static power consumption.

[0074] Specifically, Figure 5 The timing relationship of the voltage at OUT2 terminal, the voltage difference Vgs2 between the gate and source of the first NMOS transistor Nq2 in load switch 12, the gate voltage Vpd2 of the second NMOS transistor Npd2 in discharge unit 134, and the current IL2 passing through the first NMOS transistor Nq2 is shown. IN2 This is the voltage of power supply IN2.

[0075] This embodiment also provides a chip, which is based on the load switching circuit 1 provided in this embodiment. The chip is connected between the power supply and the load and is used to provide overload protection for the load.

[0076] In summary, the present invention provides a load switch circuit and chip for providing overload protection for a load switch. The load switch circuit includes at least a protection module, a regulating module, and a load switch. The load switch is connected between a power source and a load to transfer electrical energy from the power source to the load. The protection module has a first terminal connected to the power source, a second terminal connected to the load switch, and a third terminal connected to the connection point between the load and the load switch. It monitors the electrical energy received by the load and immediately limits the overload electrical energy flowing through the load switch. The regulating module has a first terminal connected to the power source, a second terminal connected to the load switch and the protection module, and regulates the electrical energy transferred by the load switch by collecting the electrical energy output from the power source. The load switch circuit and chip of this invention, composed of a first transistor and a second transistor forming a Darlington structure in the protection module, monitors the electrical energy received by the load and immediately limits the overload energy flowing through the load switch. This fundamentally solves the problem of thermal breakdown and latch-up effects that can occur when the load switch is momentarily overloaded, due to the delayed decrease in electrical energy flowing through it, leading to irreversible damage. The load switch circuit and chip of this invention are simple in structure, low in cost, and do not increase the system's static power consumption, making them suitable for a wide range of applications. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A load switch circuit for providing overload protection for a load switch, characterized in that, The load switch circuit includes at least: a protection module, a regulation module, and a load switch, wherein: The load switch is connected between the power source and the load to transfer electrical energy from the power source to the load; The first end of the protection module is connected to the power supply, the second end is connected to the load switch, and the third end is connected to the connection point between the load and the load switch. It monitors the electrical energy received by the load and limits the overload electrical energy flowing through the load switch in the first instance. The first end of the adjustment module is connected to the power supply, and the second end is connected to the load switch and the protection module. By collecting the electrical energy output by the power supply, the module adjusts the electrical energy transmitted by the load switch. The protection module includes: a first capacitor, a first resistor, a second resistor, a first transistor, and a second transistor, wherein: the upper plate of the first capacitor is connected to the power supply; the first end of the first resistor is connected to the lower plate of the first capacitor, and the second end is connected to the connection point between the load and the load switch; the first terminal of the first transistor is connected to the load switch, and the third terminal is connected to the connection point between the load and the load switch; the first terminal of the second transistor is connected to the first terminal of the first transistor, the second terminal is connected to the lower plate of the first capacitor via the second resistor, and the third terminal is connected to the second terminal of the first transistor.

2. The load switching circuit according to claim 1, characterized in that: Both the first transistor and the second transistor are NPN transistors, wherein the first electrode of the first transistor and the second transistor is the collector, the second electrode is the base, and the third electrode is the emitter.

3. The load switching circuit according to claim 1, characterized in that: The ratio of the resistance of the first resistor to the resistance of the second resistor is between 10 and 100.

4. The load switching circuit according to claim 1, characterized in that: The load switch includes a first NMOS transistor, wherein the drain of the first NMOS transistor is connected to the power supply, the gate is connected to the regulation module, and the source is connected to the load.

5. The load switching circuit according to claim 1, characterized in that: The adjustment module includes a charge pump, an amplifier, a sampling unit, and a discharge unit. The charge pump is connected to the load switch; the sampling unit is connected to the power supply; the non-inverting input of the amplifier is connected to the sampling unit, and the inverting input is connected to a reference signal; the discharge unit is connected between the output of the amplifier and the output of the charge pump.

6. The load switching circuit according to claim 5, characterized in that: The sampling unit is a current sensing resistor, a Hall sensor, or a current transformer.

7. The load switching circuit according to claim 5, characterized in that: The discharge unit includes a second NMOS transistor, wherein the drain of the second NMOS transistor is connected to the output terminal of the charge pump, the gate is connected to the output terminal of the amplifier, and the source is connected to reference ground.

8. A chip, characterized in that: The chip is implemented based on the load switching circuit as described in any one of claims 1-7. The chip is connected between the power supply and the load to provide overload protection for the load.

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