A video resolution frame rate output method, device, equipment and storage medium

Abstract

The application discloses a video resolution frame rate output method, device, equipment and storage medium. The application constructs a system architecture, the system architecture comprises a main control module, a signal conversion module and a display interface module; after the system is powered on, the main control module is controlled to initialize the signal conversion module through the I2C or SPI protocol interface; the internal drive program of the signal conversion module is controlled to drive the signal conversion module to work, so that the signal conversion module is in a preparation state; an access signal of a display device is acquired, the EDID content of the display device is read through the DDC channel to acquire display parameters; the main control module is controlled to select the maximum video resolution / frame rate according to the EDID content of the display device to realize configuration of DSI parameters; and signal output control of the display device is realized according to the configuration of the DSI parameters. The application can realize adaptive output of video resolution and frame rate, and improve user experience.

Description

Technical Field

[0001] This invention relates to the field of display control technology, and in particular to a video resolution frame rate output method, apparatus, device, and storage medium. Background Technology

[0002] The DDC channel, or Display Data Channel, is a data channel used by the lower-level machine to access the display's memory to obtain EDID format data from the display's EEPROM, thus determining the display's attributes (such as resolution and aspect ratio). A PC graphics card with a DDC channel is required to output DVI format signals.

[0003] The DDC channel is an information channel established between the lower-level machine and the monitor, allowing the monitor's physical data to be directly transmitted to the lower-level machine. However, in existing technology, some MIPI-DSI to HDMI chips lack DDC functionality in their internal HDMI interfaces. Products using these chips cannot output the optimal video resolution / frame rate based on the monitor's supported video resolution / frame rate via their HDMI TX port. Therefore, reliably and efficiently solving the problem of adaptive video resolution and frame rate output has become a pressing issue for engineers in this field. Summary of the Invention

[0004] To address the above-mentioned deficiencies, this invention provides a video resolution frame rate output method, apparatus, device, and storage medium to solve the problems existing in the prior art.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a video resolution frame rate output method, the method comprising:

[0006] A system architecture is constructed, comprising a main control module, a signal conversion module, and a display interface module. The main control module and the signal conversion module are electrically connected via a DSI protocol interface, an I2S protocol interface, an I2C or SPI protocol interface, and a DDC channel and HPD pin, respectively. The signal transmission pins of the signal conversion module are electrically connected to the display interface module.

[0007] After the system is powered on, the main control module initializes the signal conversion module through the I2C or SPI protocol interface;

[0008] The internal driver program of the signal conversion module controls the signal conversion module to work, so that the signal conversion module is in a ready state;

[0009] Obtain the access signal of the display device, and read the EDID content of the display device through the DDC channel to obtain display parameters;

[0010] The main control module selects the maximum video resolution / frame rate based on the EDID content of the display device to configure the DSI parameters;

[0011] The signal output control of the display device is achieved based on the configuration of the DSI parameters.

[0012] Preferably, the step of controlling the signal output of the display device based on the configuration of the DSI parameters includes:

[0013] Enable DSI output and decode PCM data through the Alsa sound card in the 12S protocol interface;

[0014] The signal conversion module is controlled to convert the MIPI signal and the PCM output into a TMDS signal output.

[0015] Preferably, obtaining the access signal of the display device and reading the EDID content of the display device through the DDC channel to obtain display parameters includes:

[0016] When the display device is inserted, the main control module detects that the HPD signal on the HDP pin changes from low to high, and considers that the display device has been connected.

[0017] Preferably, the method further includes setting the chip model of the main control module to LT8912B.

[0018] Preferably, the method further includes initializing the configuration file of the main control module through the Device Tree System (DTS) after the system is powered on.

[0019] Preferably, the method further includes: detecting the level change state of the HDP pin using the HPD detection function lt8912_connector_detect.

[0020] Preferably, the method for obtaining the access signal of the display device and reading the EDID content of the display device through the DDC channel to obtain display parameters includes:

[0021] The EDID content of the display device is read using the edid function lt8912_connector_get_modes.

[0022] To address the aforementioned technical problems, embodiments of the present invention provide a video resolution frame rate output device, the device comprising:

[0023] A construction module is used to build the system architecture. The system structure includes a main control module, a signal conversion module, and a display interface module. The main control module and the signal conversion module are electrically connected via a DSI protocol interface, an I2S protocol interface, an I2C or SPI protocol interface, and a DDC channel and HPD pin, respectively. The signal transmission pins of the signal conversion module are electrically connected to the display interface module.

[0024] An initialization module is used to control the main control module to initialize the signal conversion module through the I2C or SPI protocol interface after the system is powered on.

[0025] A driver module is used to control the internal driver program of the signal conversion module to drive the signal conversion module to work, so that the signal conversion module is in a ready state.

[0026] The read control module is used to acquire the access signal of the display device and read the EDID content of the display device through the DDC channel to obtain display parameters;

[0027] The selection module is used to control the main control module to select the maximum video resolution / frame rate based on the EDID content of the display device in order to configure the DSI parameters;

[0028] The display control module is used to control the signal output of the display device according to the configuration of the DSI parameters.

[0029] To address the aforementioned technical problems, this invention provides a video resolution frame rate output device, comprising: at least one processor, at least one memory, and computer program instructions stored in the memory, which, when executed by the processor, implement the method of the first aspect described above.

[0030] To address the aforementioned technical problems, embodiments of the present invention provide a storage medium storing computer program instructions, which, when executed by a processor, implement the method of the first aspect described above.

[0031] In summary, this invention provides a video resolution and frame rate output method, apparatus, device, and storage medium. The invention constructs a system architecture including a main control module, a signal conversion module, and a display interface module. After power-on, the main control module initializes the signal conversion module via the I2C or SPI protocol interface; the internal driver of the signal conversion module drives the module to operate, putting it in a ready state; the access signal of the display device is acquired, and the EDID content of the display device is read through the DDC channel to obtain display parameters; the main control module selects the maximum video resolution / frame rate based on the EDID content of the display device to configure the DSI parameters; and the signal output control of the display device is implemented based on the configured DSI parameters. Therefore, this invention can achieve adaptive output of video resolution and frame rate, improving the user experience. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a flowchart of a video resolution frame rate output method according to an embodiment of the present invention.

[0034] Figure 2 This is a system architecture diagram of a video resolution frame rate output method according to an embodiment of the present invention.

[0035] Figure 3 This is a pin diagram showing the connection between the main control module and the signal conversion module of a video resolution frame rate output method according to an embodiment of the present invention.

[0036] Figure 4 This is a pin diagram showing the connection between the main control module and the display interface module of a video resolution frame rate output method according to an embodiment of the present invention.

[0037] Figure 5 This is a pin diagram of the main control module of a video resolution frame rate output method according to an embodiment of the present invention.

[0038] Figure 6 This is a schematic diagram of the video resolution and frame rate output device according to an embodiment of the present invention.

[0039] Figure 7 This is a schematic diagram of the structure of a video resolution and frame rate output device according to an embodiment of the present invention. Detailed Implementation

[0040] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present invention and are not configured to limit the present invention. For those skilled in the art, the present invention can be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the invention.

[0041] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0042] Please see Figure 1 , Figure 1 A flowchart illustrating a video resolution and frame rate output method provided in this application.

[0043] Please see Figure 2 , Figure 2 This application provides a system architecture diagram for a video resolution and frame rate output method.

[0044] This application provides a video resolution and frame rate output method, which includes the following steps:

[0045] S1. Construct a system architecture, the system structure including a main control module, a signal conversion module, and a display interface module; the main control module and the signal conversion module are electrically connected via a DSI protocol interface, the main control module and the signal conversion module are electrically connected via an I2S protocol interface, the main control module and the signal conversion module are electrically connected via an I2C or SPI protocol interface, the main control module and the display interface module are electrically connected via a DDC channel and HPD pins, and the signal transmission pins of the signal conversion module are electrically connected to the display interface module;

[0046] S2. After the system is powered on, the main control module initializes the signal conversion module through the I2C or SPI protocol interface;

[0047] S3. Control the internal driver program of the signal conversion module to drive the signal conversion module to work, so that the signal conversion module is in a ready state;

[0048] S4. Obtain the access signal of the display device, and read the EDID content of the display device through the DDC channel to obtain display parameters;

[0049] S5. Control the main control module to select the maximum video resolution / frame rate based on the EDID content of the display device to configure the DSI parameters;

[0050] S6. Control the signal output of the display device according to the configuration of the DSI parameters.

[0051] In summary, this application provides a video resolution and frame rate output method. This method involves constructing a system architecture including a main control module, a signal conversion module, and a display interface module. After the system powers on, the main control module initializes the signal conversion module via the I2C or SPI protocol interface. The internal driver program of the signal conversion module drives the module to operate, putting it in a ready state. The system acquires the access signal from the display device and reads the EDID content of the display device through the DDC channel to obtain display parameters. The main control module selects the maximum video resolution / frame rate based on the EDID content of the display device to configure the DSI parameters. The system then controls the signal output of the display device based on the configured DSI parameters. Therefore, this invention enables adaptive output of video resolution and frame rate, improving the user experience.

[0052] Based on the above embodiments:

[0053] Please refer to Figure 3 , Figure 3 The pin diagram shows the connection between the main control module and the signal conversion module for a video resolution frame rate output method provided in this application.

[0054] Please refer to Figure 4 , Figure 4 The pin diagram shows the connection between the main control module and the display interface module for a video resolution and frame rate output method provided in this application.

[0055] Please refer to Figure 5 , Figure 5 The pin diagram of the main control module for a video resolution frame rate output method provided in this application.

[0056] As a preferred embodiment, the step of controlling the signal output of the display device based on the configuration of the DSI parameters includes:

[0057] Enable DSI output and decode PCM data through the Alsa sound card in the 12S protocol interface;

[0058] The signal conversion module is controlled to convert the MIPI signal and the PCM output into a TMDS signal output.

[0059] As a preferred embodiment, obtaining the access signal of the display device and reading the EDID content of the display device through the DDC channel to obtain display parameters includes:

[0060] When the display device is inserted, the main control module detects that the HPD signal on the HDP pin changes from low to high, and considers that the display device has been connected.

[0061] In a preferred embodiment, the method further includes setting the chip model of the main control module to LT8912B.

[0062] In a preferred embodiment, the method further includes initializing the configuration file of the main control module through the Device Tree System (DTS) after the system is powered on.

[0063] In a preferred embodiment, the method further includes: detecting the level change state of the HDP pin using the HPD detection function lt8912_connector_detect.

[0064] As a preferred embodiment, the method for obtaining the access signal of the display device and reading the EDID content of the display device through the DDC channel to obtain display parameters includes:

[0065] The EDID content of the display device is read using the edid function lt8912_connector_get_modes.

[0066] Specifically, in this embodiment, lt8912_connector_get_modes obtains EDID data by calling drm_get_edid, and updates the display parameters of DSI by reading the basic timing (resolution and frame rate) of the EDID data, thereby achieving the purpose of adaptive resolution and frame rate output in this application.

[0067] Please see Figure 6 This invention provides a video resolution frame rate output device, the device comprising:

[0068] Module 1 is used to construct the system architecture. The system architecture includes a main control module, a signal conversion module, and a display interface module. The main control module and the signal conversion module are electrically connected via a DSI protocol interface, an I2S protocol interface, an I2C or SPI protocol interface, and a DDC channel and HPD pin, respectively. The signal transmission pins of the signal conversion module are electrically connected to the display interface module.

[0069] Initialization module 2 is used to control the main control module to initialize the signal conversion module through the I2C or SPI protocol interface after the system is powered on;

[0070] Driver module 3 is used to control the internal driver program of the signal conversion module to drive the signal conversion module to work, so that the signal conversion module is in a ready state;

[0071] The read control module 4 is used to acquire the access signal of the display device and read the EDID content of the display device through the DDC channel to obtain display parameters.

[0072] Selection module 5 is used to control the main control module to select the maximum video resolution / frame rate based on the EDID content of the display device in order to configure the DSI parameters;

[0073] Display control module 6 is used to control the signal output of the display device according to the configuration of the DSI parameters.

[0074] In addition, combined Figure 1 The video resolution frame rate output method described in this embodiment of the invention can be implemented by a video resolution frame rate output device. Figure 7 A schematic diagram of the hardware structure of the video resolution frame rate output device provided in an embodiment of the present invention is shown.

[0075] The video resolution frame rate output device may include a processor 401 and a memory 402 storing computer program instructions.

[0076] Specifically, the processor 401 may include a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of the present invention.

[0077] Memory 402 may include mass storage for data or instructions. For example, and not limitingly, memory 402 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 402 may include removable or non-removable (or fixed) media. Where appropriate, memory 402 may be internal or external to a data processing device. In a particular embodiment, memory 402 is a non-volatile solid-state memory. In a particular embodiment, memory 402 includes read-only memory (ROM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically rewritable ROM (EAROM), or flash memory, or a combination of two or more of these.

[0078] The processor 401 reads and executes computer program instructions stored in the memory 402 to implement any of the video resolution frame rate output methods in the above embodiments.

[0079] In one example, the video resolution frame rate output device may also include a communication interface 403 and a bus 410. For example, Figure 7 As shown, the processor 401, memory 402, and communication interface 403 are connected through bus 410 and complete communication with each other.

[0080] The communication interface 403 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of the present invention.

[0081] Bus 410 includes hardware, software, or both, that couples components of a video resolution frame rate output device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 410 may include one or more buses. While specific buses are described and illustrated in embodiments of the invention, the invention contemplates any suitable bus or interconnect.

[0082] Furthermore, in conjunction with the video resolution frame rate output method in the above embodiments, this invention can be implemented using a computer-readable storage medium. This computer-readable storage medium stores computer program instructions; when executed by a processor, these computer program instructions implement any of the video resolution frame rate output methods in the above embodiments.

[0083] It should also be noted that the exemplary embodiments mentioned in this invention describe methods or systems based on a series of steps or apparatus. However, this invention is not limited to the order of the steps described above; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0084] The above description is merely a specific embodiment of the present invention. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the protection scope of the present invention.

Claims

1. A method of video resolution frame rate output, characterized by, The method includes: A system architecture is constructed, comprising a main control module, a signal conversion module, and a display interface module. The main control module and the signal conversion module are electrically connected via a DSI protocol interface, an I2S protocol interface, an I2C or SPI protocol interface, and a DDC channel and HPD pin, respectively. The signal transmission pins of the signal conversion module are electrically connected to the display interface module. The chip model of the signal conversion module is set to LT8912B. After the system is powered on, the main control module initializes the signal conversion module through the I2C or SPI protocol interface; The internal driver program of the signal conversion module controls the signal conversion module to work, so that the signal conversion module is in a ready state; Acquire the access signal of the display device, and read the EDID content of the display device through the DDC channel to obtain display parameters; The main control module selects the maximum video resolution / frame rate based on the EDID content of the display device to configure the DSI parameters; The signal output control of the display device is achieved based on the configuration of the DSI parameters; The step of obtaining the access signal of the display device and reading the EDID content of the display device through the DDC channel to obtain display parameters includes: when the display device is inserted, the main control module detects that the HPD signal of the HPD pin changes from low to high, considers that the display device has been connected, and reads the EDID content of the display device through the edid function lt8912_connector_get_modes to obtain display parameters.

2. The video resolution frame rate output method according to claim 1, characterized in that, The process of controlling the signal output of the display device based on the configuration of the DSI parameters includes: Enable DSI output and decode PCM data through the Alsa sound card in the 12S protocol interface; The signal conversion module is controlled to convert the MIPI signal and the PCM output into a TMDS signal output.

3. The video resolution frame rate output method according to claim 1, characterized in that, The method also includes initializing the configuration file of the main control module through the Device Tree System (DTS) after the system is powered on.

4. The video resolution frame rate output method according to claim 1, characterized in that, The method further includes: detecting the level change state of the HPD pin using the HPD detection function lt8912_connector_detect.

5. A video resolution frame rate output device, used to implement the method as described in any one of claims 1-4, characterized in that, The device includes: A construction module is used to build the system architecture, which includes a main control module, a signal conversion module, and a display interface module. The main control module and the signal conversion module are electrically connected via a DSI protocol interface, an I2S protocol interface, an I2C or SPI protocol interface, and a DDC channel and HPD pin, respectively. The signal transmission pins of the signal conversion module are electrically connected to the display interface module. The chip model of the signal conversion module is set to LT8912B. An initialization module is used to control the main control module to initialize the signal conversion module through the I2C or SPI protocol interface after the system is powered on. The driver module is used to control the internal driver program of the signal conversion module to drive the signal conversion module to work, so that the signal conversion module is in a ready state. The read control module is used to acquire the access signal of the display device and read the EDID content of the display device through the DDC channel to obtain display parameters; The selection module is used to control the main control module to select the maximum video resolution / frame rate based on the EDID content of the display device in order to configure the DSI parameters; The display control module is used to control the signal output of the display device according to the configuration of the DSI parameters; The step of obtaining the access signal of the display device and reading the EDID content of the display device through the DDC channel to obtain display parameters includes: when the display device is inserted, the main control module detects that the HPD signal of the HPD pin changes from low to high, considers that the display device has been connected, and reads the EDID content of the display device through the edid function lt8912_connector_get_modes to obtain display parameters.

6. A video resolution frame rate output device, characterized in that, include: At least one processor, at least one memory, and computer program instructions stored in the memory, which, when executed by the processor, implement the method as described in any one of claims 1-4.

7. A storage medium storing computer program instructions thereon, characterized in that, The method as described in any one of claims 1-4 is implemented when the computer program instructions are executed by the processor.

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