A manufacturing process and its applications

Abstract

The present disclosure relates to a mask manufacturing process and its application. The mask manufacturing process includes providing a carrier, forming a plating electrode layer on the carrier, which can be used as a plating electrode in a plating process; forming a composite plating mask layer on the plating electrode layer, which is composed of at least a first material layer and a second material layer; wherein the first material layer has a first etching part, which has a first critical dimension; the second material layer covers at least the sidewall of the first etching part, so as to shape the first etching part into a second etching part with a second critical dimension; wherein the minimum line width that can be distinguished by the first material layer is greater than the minimum line width that can be distinguished by the second material layer.

Description

Technical Field

[0001] This disclosure relates to a manufacturing process, and more specifically, to a mask manufacturing process. Background Technology

[0002] A common technique in chip packaging is flip-chip technology. Flip-chip technology involves using solder bumps to interconnect the active side of the chip, which has bonding pads, with a printed circuit board (PCB) or other substrate.

[0003] Taking resonator chips as an example, Figures 1-4 The existing flip-chip process flow for resonator chips is illustrated. For example... Figure 1 As shown, the resonator chip has a device substrate 10 and a cover substrate 20. A resonator element 11 is formed on the device substrate 10, and the device substrate 10 and the cover substrate 20 are packaged using wafer-level packaging technology. The cover substrate 20 may have multiple through-holes 21, and electrical connection components such as pads, bumps, or redistribution lines can be formed at both ends of the through-holes 21. Pads 12 are formed on the device substrate 10 at positions corresponding to the electrical connection components, and the pads 12 are connected to the electrical connection components for electrical connection with signal lines or ground lines. A polyimide, or PI adhesive layer 24, is formed on the surface of the cover substrate. The PI adhesive layer 24 exposes a portion of the upper surface of the electrical connection components. An under-bump metallization (UBM) layer is formed on the upper surface of the PI adhesive layer 24 and on the electrical connection components. Figure 2 As shown, a patterned photoresist layer 26 is formed on the metal layer 25 under the bump, exposing the area to be electroplated. Copper (Cu) 27, nickel (Ni) 28, and tin (Sn) 29 are sequentially electroplated in the area to be electroplated. After removing the photoresist, wet etching is performed to remove the metal layer outside the electroplated area, and then copper pillars and solder bumps 30 are formed by reflow.

[0004] In the packaging and manufacturing process of the aforementioned resonator chip, the total thickness of each electroplated metal layer is relatively thick, generally requiring more than 70 micrometers. Consequently, the photoresist layer 26 also needs to be relatively thick to better control the dimensions of each metal layer during electroplating and to facilitate the formation of a shape that meets design requirements after reflow. If the thickness of the photoresist layer 26 is too thin, the dimensions of the upper electroplated metal layer will be larger in the horizontal direction compared to the upper metal layer with a thicker photoresist layer 26. During reflow, these liquid Sn particles are prone to collapse or overflow outside the copper pillars.

[0005] Only a very small number of companies in the industry produce photoresists that meet the requirements for chip-level packaging in terms of thickness and exposure size accuracy, and they are very expensive. This results in high chip production costs and makes the company vulnerable to external suppliers in terms of material supply chain. Summary of the Invention

[0006] This disclosure addresses the aforementioned technical problems by designing an electroplating mask manufacturing process through careful improvement of the process flow. This process replaces the exposure method, achieving the same dimensional accuracy as chip-level photoresist masks while providing sufficient thickness for a thicker mask. This disclosure significantly reduces chip production costs while meeting the high-precision requirements of chip manufacturing, and avoids the limitation of relying on photoresist produced by only a very few companies.

[0007] A brief overview of this disclosure is provided below to offer a basic understanding of certain aspects of it. It should be understood that this overview is not an exhaustive summary of the disclosure. It is not intended to identify key or essential parts of the disclosure, nor is it intended to limit its scope. Its purpose is merely to present certain concepts in a simplified form as a prelude to the more detailed description that follows.

[0008] According to one aspect of this disclosure, a mask manufacturing process is provided, the mask manufacturing process comprising: providing a carrier, forming an electroplating electrode layer on the carrier for use in an electroplating process; forming a composite electroplating mask layer on the electroplating electrode layer, comprising at least a first material layer and a second material layer; wherein the first material layer has a first etched portion having a first critical dimension; the second material layer at least covers the sidewall of the first etched portion to shape the first etched portion into a second etched portion having a second critical dimension; wherein the minimum line width that the first material layer can resolve is greater than the minimum line width that the second material layer can resolve.

[0009] Furthermore, the electroplated electrode layer is a bump under-metal layer.

[0010] Furthermore, the first material layer is a dense material to withstand corrosion from the plating solution during the electroplating process.

[0011] Furthermore, the first material layer is a dry film or a silicon oxide layer.

[0012] Furthermore, the second material layer is formed by coating and curing a photoresist that meets chip-level precision requirements.

[0013] Furthermore, one or more coatings with the same or similar solvent components as those in the photoresist are formed between the first material layer and the photoresist to further adjust the viscosity of the photoresist.

[0014] Furthermore, a non-metallic protective layer is formed on the inner sidewall of the second etched portion.

[0015] Furthermore, the surface of the electroplated electrode layer is roughened.

[0016] According to another aspect of this disclosure, a packaging process is provided, which includes employing the aforementioned mask manufacturing process.

[0017] Furthermore, a metal layer is electroplated within the second etched portion, the metal layer comprising a first metal layer, a second metal layer, and a third metal layer.

[0018] Furthermore, the first material layer and the second material layer are removed.

[0019] Furthermore, when the second material layer is a silicon oxide layer, a protective layer is formed on the metal layer before the first material layer is removed.

[0020] Furthermore, the material of the protective layer is the same as the material of the second material layer.

[0021] According to another aspect of this disclosure, a packaging device is provided, which is manufactured using the packaging process of any one of claims 9-13.

[0022] According to another aspect of this disclosure, an electronic device is provided, said electronic device being manufactured using any one of the manufacturing processes of claims 1-8.

[0023] The solution disclosed herein can help achieve at least one of the following effects: reduce chip production costs while meeting the high precision requirements in chip manufacturing, and maintain autonomous production. Attached Figure Description

[0024] The specific details of this disclosure are described below with reference to the accompanying drawings, which will facilitate a more readily understanding of the above and other objects, features, and advantages of this disclosure. The drawings are merely for illustrating the principles of this disclosure. The dimensions and relative positions of the elements are not necessarily drawn to scale in the drawings, and the same reference numerals denote the same parts.

[0025] Figures 1-4 The process flow for flip-chip resonators is shown.

[0026] Figures 5-12 A schematic diagram of the process flow of this disclosure is shown. Detailed Implementation

[0027] Exemplary aspects of this disclosure will be described below with reference to the accompanying drawings. For clarity and brevity, not all features implementing this disclosure are described in the specification. However, it should be understood that many disclosure-specific decisions can be made in developing any such implementation of this disclosure to achieve the developer's specific goals, and these decisions may vary depending on the specific implementation of this disclosure.

[0028] It should also be noted that, in order to avoid obscuring the contents of this disclosure with unnecessary details, only the device structure closely related to the solution according to this disclosure is shown in the accompanying drawings, while other details that are not closely related to this disclosure are omitted.

[0029] It should be understood that this disclosure is not limited to the described embodiments by virtue of the following description with reference to the accompanying drawings. Throughout this document, features may be substituted or borrowed between different embodiments where feasible, and one or more features may be omitted in one embodiment. It should be understood that the manufacturing steps of this disclosure are exemplary in the embodiments, and the order of the steps may be adjusted.

[0030] First Implementation Plan

[0031] See Figures 5-12 Specific embodiments of the manufacturing process of this disclosure are shown, wherein the same reference numerals denote the same parts.

[0032] This embodiment describes the packaging process, especially the fabrication process of the composite electroplated mask layer. Although this embodiment uses a resonator chip as an example, those skilled in the art will understand that the solution disclosed herein is not limited to resonator chips, and is applicable to various devices involving the fabrication of composite electroplated mask layers.

[0033] like Figure 5 As shown, a first substrate 100 and a second substrate 200 are provided.

[0034] The first substrate 100 can be a semiconductor-compatible material such as silicon (Si), gallium arsenide (GaAs), indium phosphide (InP), glass, sapphire, alumina, or silicon carbide (SiC). Those skilled in the art will understand that the first substrate 100 can also be a composite substrate, comprising a substrate and a dielectric layer disposed on the substrate; the substrate material can be silicon, gallium arsenide, indium phosphide, glass, sapphire, alumina, or silicon carbide, etc.; the dielectric layer can be a single layer or multiple layers, and the dielectric layer material can, for example, be silicon dioxide (SiO2), silicon nitride (Si3N4), silicon dioxide / silicon nitride / silicon dioxide (ONO), or alumina (Al2O3), etc.

[0035] Furthermore, a component 110 is formed on the first substrate 100. The component 110 can be a semiconductor component (e.g., a resonator component), a microelectromechanical system (MEMS) component, or a sensor, or other component requiring sealing. In this embodiment, a resonator component is used as an example. After forming the resonator component, bonding pads 102 and contact pads 101 are formed on the first substrate 100 by photolithography and etching. The bonding pads 102 and contact pads 101 can be made of gold, for example. The bonding pads 102 and contact pads 101 can, exemplarily, be arranged in a dotted array, with the bonding pads 102 disposed around the contact pads 101. It is understood that other metal materials and distribution patterns are also applicable, and this disclosure does not specifically limit them. The component 110 can be connected to the contact pads 101 via metal interconnects or leads, etc., the connection method not shown in the figure.

[0036] The second substrate 200 is made of materials such as silicon, high-resistivity silicon (HRS), glass, ceramic, or polymer. The second substrate 200 may simply be a cover substrate, or it may be a functional substrate integrating a cover and other functional modules. Exemplary functional modules may include power amplifiers, low-noise amplifiers, switches, and other circuit functional modules. For example, when the second substrate 200 is a silicon substrate, through-holes 201 are further formed in the second substrate 200 using a deep silicon etching method or a wet etching method using potassium hydroxide (KOH) and tetramethylammonium hydroxide (TMAH). Bumps 202 and / or redistribution lines 203, and other electrical connection structures, are formed on the upper and lower surfaces of the second substrate 200 to cover the through-holes 201. These electrical connection structures are used for electrical connection with signal lines or power lines (not shown in the figure).

[0037] Furthermore, other structures such as contact pads 101, bonding pads 102, and sealing rings (not shown in the figure) can also be formed on the lower surface of the second substrate 200. The contact pads 101, bonding pads 102, and sealing rings can also be made of gold. The bonding pads 102 and contact pads 101 can be exemplary in a dot matrix distribution, but it is understood that other distribution forms are also applicable, and this disclosure does not specifically limit them.

[0038] Furthermore, the materials of the contact pad 101, bonding pad 102 and sealing ring can be other conductive materials, and the materials among them can be the same or different. For example, the materials of the bonding pad 102 and sealing ring can be gold or tin.

[0039] A passivation layer 204 is formed on the upper surface of the second substrate 200, covering the upper surface of the second substrate 200 and potentially covering the outer edge of the electrical connection structure. The passivation layer 204 can be, for example, polyimide or a PI adhesive layer, which simultaneously serves as an antistatic and heat dissipation layer. A bump under-metal layer 205 is formed on the upper surface of the passivation layer 204 and on the electrical connection structure. The bump under-metal layer 205 can be, for example, any metal convenient for use as an electroplating electrode in the electroplating process, such as tin (Sn), indium (In), titanium (Ti), chromium (Cr), gold, nickel, aluminum (Al), or titanium-tungsten alloy (TiW). Preferably, the bump under-metal layer 205 can be made of titanium-tungsten alloy, which has high ductility and strong adhesion, and good transition buffering performance. The bump under-metal layer 205 can be formed by plasma sputtering.

[0040] The first substrate 100 and the second substrate 200 are packaged and bonded together to form a package. It is understood that the order of the above-described package formation process steps is not specifically limited in this disclosure. For example, after forming contact pads 101, bonding pads 102, and a sealing ring on the lower surface of the second substrate 200, the first substrate 100 and the second substrate 200 are first bonded together, and then through-holes 201 are fabricated on the second substrate 200, and redistribution lines 203 and a bump under-metal layer 205 are formed on the upper surface of the second substrate 200, etc. This disclosure does not specifically limit this.

[0041] In this disclosure, after the package is formed, a highly corrosion-resistant and dense composite electroplating mask layer is constructed on the under-bump metal layer of the package. This composite electroplating mask layer replaces the photoresist in the prior art, which is capable of meeting the requirements of chip-level packaging in terms of thickness and exposure dimensional accuracy, to withstand the metal electroplating bath. It is understood that in application, this composite electroplating mask layer is not limited to being formed on the under-bump metal layer; as long as a conductive layer that can be used as an electroplating electrode is formed on a carrier, the composite electroplating mask layer can be formed on it.

[0042] like Figure 6-8 As shown, the composite electroplating mask layer in this disclosure is a combination of a patterned dry film layer 300 and a patterned photoresist layer 400. Dry film is a photosensitive polymer material and can have a relatively thick thickness. When used as a photosensitive material layer, dry film can also, to some extent, block electroplating and etching. However, according to the technical requirements of ordinary dry films, the primary indicator for the minimum resolvable average line width is ≤100μm, and the secondary indicator is ≤150μm. It is evident that dry films are mainly used in scenarios with low dimensional accuracy requirements and cannot meet the dimensional accuracy requirements in chip-level packaging.

[0043] This disclosure successfully proposes a novel process flow for composite electroplating mask layers. By synergistically using dry film and photoresist, the advantages of dry film in forming thick films are utilized, overcoming the shortcomings of low line resolution. Since the cost of photoresist for chip-level packaging is approximately twice that of dry film, it can meet the requirements for thickness and exposure dimensional accuracy. This allows the successful application of dry film, typically used in PCB boards, to chip packaging, reducing chip production costs while meeting the high precision requirements of chip-level packaging and improving the autonomy of production.

[0044] Specifically, such as Figure 6 As shown, a dry film layer 300 is first formed on the under-bump metal layer 205. The thickness of the dry film layer 300 is approximately equal to the desired thickness of the metal plating layer, for example, it can be 0.5-10 mils thick. Then, the dry film layer 300 is selectively subjected to photochemical radiation and development through a mask with a set pattern, thereby removing part of the dry film layer 300 to form the first etched portion 301. The first etched portion 301 exposes the electrical connection structure. The critical dimension of the first etched portion 301 is set based on the line resolution index of the selected dry film material properties. Therefore, the critical dimension of the first etched portion 301 does not meet the chip-level precision requirements.

[0045] Then as Figure 7 As shown, a liquid photoresist is coated onto the patterned dry film layer 300. The liquid photoresist can be, for example, a photosensitive polymer material based on epoxy acrylate, and the material's line resolution must meet chip packaging precision. After coating, the liquid photoresist is allowed to stand and vibrate, allowing it to flow into and fill the first etched portion 301. A suitable temperature is selected based on the material characteristics of the liquid photoresist for low-temperature baking to evaporate its organic solvents, thereby solidifying the liquid photoresist to obtain the photoresist layer 400. It is understood that the patterning of the dry film layer 300 can be directly formed by photolithography of the dry film layer 300 or by forming a photoresist layer on the dry film layer 300 followed by photolithography.

[0046] Then as Figure 8 As shown, a portion of the photoresist layer 400 in the first etched portion 301 is removed using photolithography, leaving only the photoresist layer 400 on the sidewalls of the first etched portion 301. This allows the first etched portion 301 to be shaped, resulting in a second etched portion 401 that meets the critical dimensions of the subsequently formed conductive pillars. In other words, the critical dimensions of the second etched portion 401 satisfy the chip-level precision requirements. After forming the second etched portion 401, as... Figure 9 As shown, the package is placed in an electroplating tank, and the required first metal layer 501, second metal layer 502 and third metal layer 503 are electroplated sequentially in the second etching section 401.

[0047] Furthermore, the first metal layer 501, the second metal layer 502, and the third metal layer 503 can be prepared, for example, by electroless plating to provide a more uniform coverage. Those skilled in the art will understand that the first metal layer 501, the second metal layer 502, and the third metal layer 503 can also be prepared using other plating methods, which are not specifically limited herein. The first metal layer 501 is preferably a metal with excellent electrical conductivity, such as copper, to form conductive pillars for better electrical signal transmission. The second metal layer 502 is selected from metals that can act as a spacer between the first metal layer 501 and the third metal layer 503, such as nickel. The third metal layer 503 can be a metal material with a low melting point, such as tin, lead (Pb), or aluminum, for subsequent fabrication of solder bumps.

[0048] After electroplating is completed, such as Figure 10 As shown, a 3%-5% NaOH solution can be used at 50-60℃ to mechanically spray or immerse the dry film layer 300, thereby removing the photoresist layer 400 on the surface of the dry film layer 300.

[0049] Then as Figure 11 As shown, the photoresist layer 400 on the sidewall of the electroplated metal structure is removed using a wet process, for example, by immersion in a polar aprotic solvent such as an n-methylpyrrolidone (NMP) solution or an edge-removing agent (EBR) for photoresist. Those skilled in the art will understand that a dry process combined with a wet process can also be used to remove the photoresist on the sidewall of the electroplated metal structure. For example, a dry ashing process (asher) at 80-300 degrees Celsius using a plasma gas containing oxygen or oxygen ions, combined with immersion in a polar aprotic solvent such as an n-methylpyrrolidone solution or an edge-removing agent for photoresist, can be used to remove the photoresist layer 400 on the sidewall of the electroplated metal structure.

[0050] Then as Figure 12 As shown, the encapsulated component after de-adhesive removal undergoes a reflow process, which forms conductive pillars and solder bumps 504.

[0051] Those skilled in the art will further understand that plasma bombardment of the surface of the under-bump metal layer 205 can be used before forming a composite electroplating mask layer. While removing the natural oxide layer on the metal surface, the surface of the under-bump metal layer 205 can be roughened, thereby increasing the adhesion between the composite electroplating mask layer and the under-bump metal layer 205.

[0052] Those skilled in the art will further understand that after patterning the dry film layer 300 to form the first etched portion 301, one or more other coatings can be added before applying the liquid photoresist. The material of these other coatings is preferably a diluent with the same or similar solvent composition as the liquid photoresist being applied. By using these other coatings, the viscosity of the liquid photoresist can be further adjusted, thereby further improving the size, filling properties, and release properties of the second etched portion 401.

[0053] Those skilled in the art will further understand that before electroplating the first metal layer 501 in the second etching section 401, a non-metallic protective layer can be formed on the sidewall of the second etching section 401. This non-metallic protective layer can be, for example, silicon nitride or silicon oxide. The non-metallic protective layer helps prevent damage to the metal layer when the photoresist layer 400 on the sidewall of the electroplated metal structure is removed using a wet process.

[0054] In this embodiment, through improvements in the fabrication process, particularly the introduction of dry film materials in the mask fabrication process before metal plating, a composite electroplating mask layer composed of a patterned dry film layer and a patterned photoresist layer successfully replaces the photoresist electroplating mask layer in the prior art. This fabrication process achieves a thickness that, due to the use of dry film materials, allows the composite electroplating mask layer of this disclosure to meet the requirements of the electroplating bath for a thicker, more robust material. Furthermore, the use of photoresist films at the pattern boundaries enables the fabrication process to meet the high-precision requirements of very small linewidths in chip manufacturing. Therefore, costs are significantly reduced.

[0055] Second Implementation Plan

[0056] The main difference between the second and first embodiments of this disclosure lies in the following: the composite electroplating mask layer uses other highly corrosion-resistant and dense material layers to replace the dry film layer in the first embodiment, so that the other highly corrosion-resistant and dense material layers and the high-precision photoresist layer can work together to form the composite electroplating mask layer. In this embodiment, the other highly corrosion-resistant and dense material layer is, for example, a silicon oxide thin film made of silica sol.

[0057] Specifically, a silica sol solution is applied to the metal layer under the bump, and then a silicon oxide layer is formed through a baking process. The thickness of the silicon oxide layer is approximately equal to the thickness of the desired metal plating layer. The silicon oxide layer is then etched to form the first etched area. The first etched area can be formed on the silicon oxide layer by laser drilling, or by photolithography combined with dry or wet etching.

[0058] Then, a liquid photoresist is applied to the patterned silicon oxide layer. The liquid photoresist can be, for example, a photosensitive polymer material based on epoxy acrylate, and the line resolution of the material meets the chip packaging accuracy. After the liquid photoresist is applied, it is left to stand and shaken, so that the photoresist flows in and fills the first etched part.

[0059] Based on the material properties of the liquid photoresist, a suitable temperature is selected for low-temperature baking to evaporate its organic solvents, thereby solidifying the liquid photoresist and forming a photoresist layer. Then, a portion of the photoresist layer is removed using a photolithography process, leaving only the photoresist layer on the sidewall of the first etched section. The first etched section is then shaped to obtain a second etched section that conforms to the critical dimensions of the conductive pillar.

[0060] The package is placed in an electroplating tank, and the first, second, and third metal layers are electroplated sequentially in the second etching section.

[0061] After electroplating is completed, a protective layer can be formed on the second etched part to protect the third metal layer in the second etched part. Then, a fluorine-containing solution, such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BOE), is used to remove the silicon oxide layer.

[0062] The photoresist layer on the sidewalls of the electroplated metal structure is then removed using a wet process, such as immersion in a polar aprotic solvent like an n-methylpyrrolidone solution or a photoresist edge cleaner. Those skilled in the art will understand that a dry process can also be used in conjunction with a wet process to remove the photoresist from the sidewalls of the conductive pillars. For example, a dry ashing process using a plasma gas containing oxygen or oxygen ions at 80-300 degrees Celsius, combined with immersion in a polar aprotic solvent like an n-methylpyrrolidone solution or a photoresist edge cleaner, can remove the photoresist.

[0063] Those skilled in the art will further understand that the protective layer can be made of the same material as the photoresist formed on the sidewall of the first etched portion. This allows the protective layer to be removed simultaneously with the photoresist layer on the sidewall of the electroplated metal structure using a wet process.

[0064] Then the package is reflowed to form conductive pillars and solder bumps.

[0065] Those skilled in the art will further understand that plasma bombardment of the surface of the under-bump metal layer can be used before forming the composite electroplating mask layer. While removing the natural oxide layer on the surface of the under-bump metal layer, the surface of the under-bump metal layer can be roughened to increase the adhesion between the composite electroplating mask layer and the under-bump metal layer.

[0066] Those skilled in the art will further understand that, before electroplating the first metal layer in the second etching section, a non-metallic protective layer, such as silicon nitride or silicon oxide, can be formed on the sidewall of the second etching section to avoid damage to the metal layer when removing the photoresist layer on the sidewall of the electroplated metal structure using a wet process.

[0067] The process described in this disclosure can be used in any chip-level manufacturing process that requires a composite electroplating mask layer, in packages that employ the aforementioned composite electroplating mask layer, in various semiconductor devices that include the package, and in various microelectromechanical systems devices that include the package.

[0068] The foregoing description of this disclosure in conjunction with specific implementation schemes is exemplary and not intended to limit the scope of protection of this disclosure. Those skilled in the art can make various modifications and variations to this disclosure based on its spirit and principles, and such modifications and variations are also within the scope of this disclosure.

Claims

1. A mask manufacturing process, characterized in that, include: A carrier is provided on which an electroplating electrode layer that can be used in an electroplating process is formed; A composite electroplating mask layer consisting of at least a first material layer and a second material layer is formed on the electroplated electrode layer; wherein, the first material layer has a first etched portion, the first etched portion having a first critical dimension; the second material layer at least covers the sidewall of the first etched portion to shape the first etched portion into a second etched portion having a second critical dimension; Wherein, the minimum line width that the first material layer can distinguish is greater than the minimum line width that the second material layer can distinguish; The first material layer is a dense material to withstand the corrosion of the plating solution during the electroplating process; The second material layer is formed by coating and curing a photoresist that meets chip-level precision requirements.

2. The mask manufacturing process as described in claim 1, characterized in that: The electroplated electrode layer is a metal layer under the bump.

3. The mask manufacturing process as described in claim 1, characterized in that: The first material layer is a dry film or a silicon oxide layer.

4. The mask manufacturing process as described in claim 1, characterized in that: One or more coatings with the same or similar solvent components as those in the photoresist are formed between the first material layer and the photoresist to further adjust the viscosity of the photoresist.

5. The mask manufacturing process according to any one of claims 2-4, characterized in that: A non-metallic protective layer is formed on the inner sidewall of the second etched portion.

6. The mask manufacturing process as described in claim 5, characterized in that: The surface of the electroplated electrode layer is roughened.

7. A packaging process, characterized in that, include: The mask manufacturing process described in any one of claims 3-6 is employed.

8. The packaging process as described in claim 7, characterized in that: A metal layer is formed by electroplating within the second etched section.

9. The packaging process as described in claim 8, characterized in that: Further remove the first material layer and the second material layer.

10. The packaging process as described in claim 9, characterized in that, When the first material layer is a silicon oxide layer, a protective layer is formed on the metal layer before the first material layer is removed.

11. The packaging process as described in claim 10, characterized in that: The material of the protective layer is the same as that of the second material layer.

12. A packaged device, characterized in that: The packaged device is manufactured using the packaging process of any one of claims 7-11.

13. An electronic device, characterized in that: The electronic device is manufactured using any one of the manufacturing processes described in claims 1-6.

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