Task processing system and method for intelligent processor

Abstract

The application discloses a task processing system and a task processing method suitable for an intelligent processor. The task processing system comprises an intelligent processor and an instruction processor. The instruction processor receives a task from the intelligent processor and starts the intelligent processor in response to the task. The intelligent processor selects a corresponding firmware code from a plurality of firmware codes according to the task and restarts the instruction processor to make the instruction processor run the corresponding firmware code and cooperatively complete the first task with the instruction processor. Thus, the task processing time can be reduced, and the operation efficiency of the task processing system is improved.

Description

Technical Field

[0001] This application relates to task scheduling technology for intelligent processors, and in particular to task processing systems and methods applicable to intelligent processors. Background Technology

[0002] In existing processing systems, the task scheduling mode between the intelligent processor and the main processor is serial. For example, the main processor uses its kernel thread to assign multiple tasks to be executed and instructs the intelligent processor to execute one of those tasks. After the intelligent processor completes a task, it reports the result to the kernel thread. Upon receiving the result, the kernel thread then assigns the next task to the intelligent processor. In this scheduling mode, if the workload of the main processor increases, causing the kernel thread's response time to slow down, it will delay the task scheduling of the intelligent processor, significantly increasing the overall uptime. Summary of the Invention

[0003] In some embodiments, one of the objectives of this invention is to provide a task processing system and a task processing method that can improve upon the shortcomings of prior art.

[0004] In some embodiments, the task processing system includes a first intelligent processor; and a first instruction processor, configured to receive a first task from a main processor and, in response to the first task, start the first intelligent processor, wherein the first intelligent processor selects a corresponding firmware code from a plurality of firmware codes according to the first task, restarts the first instruction processor to run the corresponding firmware code, and works in cooperation with the first instruction processor to complete the first task.

[0005] In some embodiments, the task processing method includes the following operations: starting an intelligent processor in response to a task from a main processor via an instruction processor; selecting a corresponding firmware code from a plurality of firmware codes according to the task via the intelligent processor, and restarting the instruction processor to run the corresponding firmware code; and cooperating with the instruction processor via the intelligent processor to complete the task.

[0006] The solution provided in this application reduces the dependence on the main processor, thereby reducing the load on the main processor, resulting in low-latency processing time, which in turn shortens the overall operating time and improves processing efficiency. Attached Figure Description

[0007] Regarding the features, implementation, and effects of this case, the preferred embodiments are described in detail below with reference to the drawings.

[0008] Figure 1A schematic diagram of a task processing system is provided based on some embodiments of this case. Figure 2A Drawing based on some embodiments of this case Figure 1 A schematic diagram of an instruction processor; Figure 2B Drawing based on some embodiments of this case Figure 2A A data diagram of the task queue; Figure 3A Drawings based on some embodiments of this case Figure 1 A timing diagram illustrating the operation between the main processor, intelligent processor, and instruction processor; Figure 3B Drawing based on some embodiments of this case Figure 1 A timing diagram illustrating the operation between the main processor and multiple instruction processors; and Figure 4 This is a flowchart illustrating a task processing method based on some embodiments of this case. Detailed Implementation

[0009] All terms used herein have their common meanings. The definitions of the terms mentioned above in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not limit the scope or meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0010] As used herein, "coupling" or "connection" can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or moving together. As used herein, the term "circuit" can refer to a device that processes signals by connecting at least one transistor and / or at least one active or passive component in a certain manner.

[0011] Figure 1 A schematic diagram of a task processing system 100 is provided according to some embodiments of this invention. In some embodiments, the task processing system 100 includes a main processor 110, a memory 120, an instruction processor 130, an instruction processor 135, an intelligence processing unit (IPU) 140, and an intelligence processor 145. The aforementioned hardware components may be coupled to each other via one or more buses or data lines.

[0012] The main processor 110 is the primary processor in the task processing system 100, and it has relatively high computing power (compared to the instruction processor 130 and / or instruction processor 135). For example, the main processor 110 can run an operating system (e.g., but not limited to, Linux) on the task processing system 100.

[0013] In some embodiments, memory 120 may be, but is not limited to, dynamic random access memory. Memory 120 stores multiple firmware codes D1 to DM. Intelligent processor 140 can select a corresponding firmware code (hereinafter referred to as firmware code Di) from the multiple firmware codes D1 to DM according to the task to be executed, and transmit this firmware code Di to instruction processor 130 so that instruction processor 130 runs firmware code Di. Thus, instruction processor 130 can run a specific firmware code (i.e., the firmware code corresponding to firmware code Di) to cooperate with intelligent processor 140 to complete the task to be executed.

[0014] For example, the task to be executed is a computation using a specific neural network model, and the data format of some of the data used is more suitable for computation using the instruction processor 130 (compared to using the intelligent processor 140). By parsing the relevant data describing the specific neural network model, the main processor 110 can determine the correspondence between the specific neural network model and at least one of multiple firmware codes D1 to DM, and determine the firmware code Di suitable for the task based on this correspondence. The main processor 110 can transmit the above-mentioned relevant information to the task queue of the instruction processor 130 (e.g., ...). Figure 2B The firmware code is stored in the task queue (TQ) in the memory. Thus, based on the triggering of the instruction processor 130, the intelligent processor 140 can select firmware code Di from multiple firmware codes D1 to DM according to the aforementioned relevant information. The intelligent processor 140 can transfer firmware code Di to the instruction processor 130 and restart the instruction processor 130 to run firmware code Di. Specifically, the intelligent processor 140 retrieves firmware code Di from the memory 120 and transfers the retrieved firmware code Di to the instruction processor 130. The above operations also apply to the instruction processor 135 and the intelligent processor 145, and therefore will not be repeated here.

[0015] In some embodiments, each of instruction processors 130 and 135 may be a reduced instruction set processor (RISC-V). In some embodiments, each of instruction processors 130 and 135 may be a processor based on an open standard instruction set architecture (OSA). For example, each of instruction processors 130 and 135 may be, but is not limited to, a fifth-generation RISC-V processor. Each of instruction processors 130 and 135 has relatively low computational power (compared to the main processor 110). For example, instruction processors 130 and 135 do not execute the operating system of the task processing system 100, and their main function is to receive tasks assigned to intelligent processors 140 and / or 145 from the main processor 110 for processing, and then perform task scheduling for intelligent processors 140 and / or 145.

[0016] Each of intelligent processor 140 and / or intelligent processor 145 is a dedicated processor for executing an artificial intelligence technique, which can be used to process applications and / or operations related to neural networks (e.g., including, but not limited to, convolutional neural networks). As previously described, instruction processor 130 is used to handle task scheduling of intelligent processor 140, and instruction processor 135 is used to handle task scheduling of intelligent processor 145. In other words, instruction processor 130 is configured corresponding to intelligent processor 140, and instruction processor 135 is configured corresponding to intelligent processor 145. In the embodiments of this application, one instruction processor corresponds to one intelligent processor. Detailed operation regarding task scheduling will be referred to later. Figure 3A illustrate.

[0017] In some embodiments, each of the plurality of intelligent processors 140 and 145 may be a processing unit in a multi-core intelligent processor. Similarly, in some embodiments, each of the plurality of instruction processors 130 and 135 may be a processing unit in a multi-core reduced instruction set processor. The above-described arrangements and / or types of the plurality of instruction processors 130 and 135 and the plurality of intelligent processors 140 and 145 are for illustrative purposes and are not intended to limit the scope of this invention. Furthermore, Figure 1 This example uses two instruction processors 130 and 135 and two intelligent processors 140 and 145, but it is not limited to this. The number of instruction processors and intelligent processors used in the task processing system 100 can be adjusted according to actual application requirements.

[0018] Figure 2A Drawing based on some embodiments of this case Figure 1A schematic diagram of instruction processor 130 is shown. Instruction processor 130 has the same architecture as instruction processor 135. Taking instruction processor 130 as an example, instruction processor 130 includes arithmetic circuitry 210 and tightly coupled memory (TCM) circuitry 220. (The following...) Figure 3A The computing circuit 210 can start (or trigger) the intelligent processor 140 according to the corresponding task, and after the intelligent processor 140 starts, it runs the firmware code Di transmitted by the intelligent processor 140 to work in coordination with the intelligent processor 140 to execute the corresponding task. Furthermore, after the intelligent processor 140 reports that the task has been completed, the computing circuit 210 will report to the main processor 110 that the task has been completed.

[0019] The tightly coupled memory circuit 220 can be used to store firmware code Di and a task queue TQ, wherein the task queue TQ includes at least one first task assigned by the main processor 110. Specifically, the tightly coupled memory circuit 220 includes instruction tightly coupled memory (ITCM) 222 and data tightly coupled memory (DTCM) 224. The instruction tightly coupled memory 222 stores the instruction data ID of the firmware code Di. The data tightly coupled memory 224 includes data areas 224A and 224B, wherein data area 224A stores the processing data PD of the firmware code Di, and data area 224B stores the task queue TQ. Generally, the data transfer rate of the tightly coupled memory circuit 220 is higher than that of the memory 120. Therefore, compared to running the firmware code Di on the memory 120, the arithmetic circuit 210 can run the firmware code Di stored in the tightly coupled memory circuit 220 to achieve a faster processing speed. In some embodiments, the main processor 110 has the ability to write data into the tightly coupled memory circuit 220. When assigning a task, the main processor 110 can directly write task-related information into the task queue TQ within the tightly coupled memory circuit 220, thereby improving the efficiency of task assignment.

[0020] Figure 2B Drawing based on some embodiments of this case Figure 2AA schematic diagram of the task queue TQ is provided. In some embodiments, the task queue TQ can be used to indicate the processing order of multiple tasks. In some embodiments, the data area 224B can be operated as a ring buffer, which stores a header H and multiple tasks TK1 to TKn, etc. The header H records the read pointer signal RP and the write pointer signal WP. The read pointer signal RP indicates the start position of multiple valid data (i.e., the relevant information of multiple tasks TK1 to TKn) stored in the data area 224B, and the write pointer signal WP indicates the end position of multiple valid data stored in the data area 224B. The main processor 110 can determine the remaining data capacity of the data area 224B based on the difference between the read pointer signal RP and the write pointer signal WP. For example, the smaller the difference and the positive number, the more available capacity the data area 224B has (i.e., the fewer tasks to be processed).

[0021] In some embodiments, the main processor 110 may determine, based on a first difference (corresponding to the instruction processor 130) and a second difference (corresponding to the instruction processor 135), which will determine the assignment of tasks to be processed to the task queue of the instruction processor 130 (e.g., ...). Figure 2B The task queue (TQ) in the instruction processor 130 or the task queue assigned to the instruction processor 135 is defined by a first difference determined by the difference between the read indicator signal RP and the write indicator signal WP of the instruction processor 130, and a second difference determined by the difference between the read indicator signal and the write indicator signal of the instruction processor 135. For example, if the first difference corresponding to the instruction processor 130 is lower than the second difference corresponding to the instruction processor 135, it means that the number of tasks in the task queue of the instruction processor 130 is smaller (compared to the instruction processor 135). Under this condition, the main processor 110 may preferentially assign the task to be processed as the first task scheduled by the instruction processor 130. Alternatively, if the second difference corresponding to the instruction processor 135 is lower than the first difference corresponding to the instruction processor 135, it means that the number of tasks in the task queue of the instruction processor 135 is smaller (compared to the instruction processor 130). Under this condition, the main processor 110 may preferentially assign the task to be processed as the second task scheduled by the instruction processor 135. Furthermore, when the task processing system 100 includes multiple sets of instruction processors and intelligent processors, the main processor 110 allocates tasks by comparing the difference between the read indicator signal RP and the write indicator signal WP corresponding to each instruction processor.

[0022] The information related to multiple tasks TK1 to TKn includes information written to multiple temporary registers in the intelligent processor 140. Taking task TK1 as an example, the information related to task TK1 may include, but is not limited to, the storage address of the intelligent processor's instructions (labeled as IPU instructions), the storage address of the intelligent processor's data (labeled as IPU data), the storage address of the memory management unit (MMU) table, and the storage address of the firmware code Di. In this embodiment, the aforementioned storage addresses refer to addresses in the memory 120. That is, the task processing system 100 or the main processor 110 stores the instructions and data related to each task in the memory 120 in advance, and includes the storage addresses of the relevant instructions and data in the task information of tasks TK1 to TKn when assigning tasks. When the arithmetic circuit 210 reads task TK1 according to the read indicator signal RP, the arithmetic circuit 210 can start the intelligent processor 140 and write the information related to task TK1 into the intelligent processor 140.

[0023] In this way, the intelligent processor 140 can obtain the storage address of the firmware code Di from the memory 120, and obtain the instructions and data required to execute task TK1 based on other information. Thus, the intelligent processor 140 can perform the aforementioned operations to restart the instruction processor 130, so as to cooperate with the instruction processor 130 to complete the relevant calculations of task TK1.

[0024] Figure 3A Drawings based on some embodiments of this case Figure 1 A schematic diagram of the operating timing between the main processor 110, the intelligent processor 140, and the instruction processor 130.

[0025] In operation S301, after the system is powered on, the main processor 110 starts the intelligent processor 140 to execute the initial task. In operation S302, the intelligent processor 140 can optionally select firmware code corresponding to the initial task and start the instruction processor 130 to cooperate in executing the initial task. For example, after the task processing system 100 is powered on, the main processor 110 can respond to the initial task issued by the software application in the user layer, write task-related information into the temporary register of the intelligent processor 140, and start the intelligent processor 140. The intelligent processor 140 can retrieve the corresponding firmware code (assuming it is firmware code D1) from the memory 120 according to the information of the initial task. The intelligent processor 140 can transmit firmware code D1 to the instruction processor 130 and start the instruction processor 130 so that the instruction processor 130 runs firmware code D1 to cooperate with the intelligent processor 140 to execute the initial task.

[0026] In operation S303, the intelligent processor 140 notifies the instruction processor 130 that the first task has been completed and enters sleep mode. In operation S304, the instruction processor 130 notifies the main processor 110 that the first task has been completed. For example, after the first task is completed, the intelligent processor 140 can notify the instruction processor 130 that the first task has been completed by issuing an interrupt request. Similarly, after receiving a response from the intelligent processor 140, the instruction processor 130 can notify the main processor 110 that the first task has been completed by issuing an interrupt request. In some embodiments, the intelligent processor 140 enters sleep mode after completing each task to save power. The sleep mode can be a shutdown mode, a power-saving mode, a standby mode, or other low-power operating modes. In some embodiments, the instruction processor 130 also feeds back the execution results of the task to the main processor 110.

[0027] In operation S305, instruction processor 130 responds to a task by restarting intelligent processor 140. In operation S306, intelligent processor 140 selects firmware code corresponding to the task and restarts instruction processor 130 to run the firmware code to execute the task. For example, instruction processor 130 may, according to... Figure 2BThe instruction processor 130 reads an unexecuted task (e.g., task TK1) from the task queue TQ (which includes one or more tasks allocated by the main processor 110), and restarts the intelligent processor 140, transferring the relevant information of task TK1 to the instruction processor 140 (i.e., writing the task-related information to the temporary register of the intelligent processor 140). Since the intelligent processor 140 is in sleep mode at this time, this restart includes waking up the intelligent processor 140. In other words, the instruction processor 130 can restart the intelligent processor 140 to execute the next task (e.g., task TK1) in response to a task without receiving an instruction from the main processor 110. The intelligent processor 140 can confirm the firmware code (let's say firmware code D2) corresponding to task TK1 in the memory 120 based on the relevant information of task TK1. Thus, the intelligent processor 140 can transfer firmware code D2 to the instruction processor 130 and restart the instruction processor 130, so that the instruction processor 130 runs firmware code D2 to cooperate with the intelligent processor 140 to execute task TK1. In some embodiments, the intelligent processor 140 may include a direct memory access circuit coupled to the memory 120 and the tightly coupled memory circuit 220 within the instruction processor 130. The intelligent processor 140 may use this direct memory access circuit to write firmware code D2 from the memory 120 into the tightly coupled memory circuit 220 of the instruction processor 130. In operation S307, the intelligent processor 140 notifies the instruction processor 130 that the task (e.g., task TK1) has been completed and enters a sleep mode. In operation S308, the instruction processor 130 notifies the main processor 110 that the task (e.g., task TK1) has been completed.

[0028] When there are unexecuted tasks in the task queue TQ, operations S309 to S312 are performed. The details of operations S309 to S312 are similar to those of operations S305 to S308, and will not be repeated here.

[0029] Similarly, it should be understood that in some embodiments, during the first task after the task processing system 100 is powered on, the intelligent processor 140 is started via the main processor 110. In subsequent operations, the intelligent processor 140 is started via the instruction processor 130 to execute subsequent tasks. Furthermore, during task execution, the intelligent processor 140 and the instruction processor 130 mutually start each other. After each task is completed, the intelligent processor 140 enters a sleep mode to reduce power consumption until it is restarted via the instruction processor 130. During each task execution, the intelligent processor 140 selects appropriate firmware code, transmits this firmware code to the instruction processor 130, and restarts the instruction processor 130. The restarted instruction processor 130 can run the firmware code stored in the tightly coupled memory circuit 220 to work in conjunction with the intelligent processor 140 to complete the task. By selecting corresponding firmware code for each task, each firmware code can be very concise and meet the needs of the task, thereby reducing the resources consumed by the instruction processor 130 when executing the firmware code and reducing the capacity requirements of the tightly coupled memory circuit 220. During the task scheduling process described above, the main processor 110 releases the relevant kernel thread after each task assignment. The intelligent processor 140 and the instruction processor 130 do not use the kernel thread of the main processor 110 when executing tasks. In this way, the dependence on the main processor 110 can be reduced, and the load on the main processor 110 can be reduced, thereby achieving low-latency processing time.

[0030] Figure 3A This explanation uses the main processor 110, intelligent processor 140, and instruction processor 130 as an example. The timing diagram of the operation between the main processor 110, intelligent processor 145, and instruction processor 135 can be found in [reference needed]. Figure 3A This is understood, so it will not be repeated. In addition, since the task processing system 100 has a parallel architecture, the operation between the intelligent processor 140 and the instruction processor 130 can be processed in parallel with the operation between the intelligent processor 145 and the instruction processor 135.

[0031] Figure 3B Drawing based on some embodiments of this case Figure 1 The diagram illustrates the timing of operation between the main processor 110, instruction processor 130, and instruction processor 135. As previously described, the main processor 110 can determine, based on a first difference and a second difference, which task to be processed will be assigned to the task queue of the instruction processor 130 (e.g., for...). Figure 2B The task queue (TQ) in the instruction processor 135, or the task queue assigned to the instruction processor 135. The first difference is determined by the read indicator signal RP and the write indicator signal WP of the instruction processor 130 (e.g., ...). Figure 2BThe difference between the two signals is determined by the difference between the read indicator signal and the write indicator signal of the instruction processor 135. Similarly, the second difference is determined by the difference between the read indicator signal and the write indicator signal of the instruction processor 135.

[0032] exist Figure 3B In the example, assuming the task queue of instruction processor 135 is relatively full, in operations S320 and S321, main processor 110 can assign tasks to the task queue of instruction processor 130 based on a first difference with a lower value. Next, in operation S322, main processor 110 can assign tasks to the task queue of instruction processor 135 based on a second difference with a lower value. Similarly, in operation S323, main processor 110 can assign tasks to the task queue of instruction processor 130 based on a first difference with a lower value. In operation S324, main processor 110 can assign tasks to the task queue of instruction processor 135 based on a second difference with a lower value. Through these operations, main processor 110 can assign new tasks to instruction processors with fewer pending tasks, thereby reducing overall operational latency (or waiting time).

[0033] In some embodiments, Figure 3A The operating sequence shown is Figure 3B The illustrated timing sequence can be performed in parallel. In other words, the timing sequence of the task received by the instruction processor 130 (i.e., Figure 3B The timing shown can be independent of the intelligent processor 140 to execute the corresponding task's operating timing (i.e., Figure 3A (The timing diagram is shown). Specifically, the intelligent processor 140 can execute tasks according to the task queue TQ of the instruction processor 130, without relying on or waiting for instructions and / or responses from the main processor 110. Similarly, the main processor 110 can allocate tasks according to the aforementioned first and second differences, without relying on or waiting for responses from the intelligent processor 140 and / or the intelligent processor 145. Thus, the main processor 110, intelligent processor 140, and / or intelligent processor 145 can execute their respective operations independently and in parallel to improve overall processing efficiency.

[0034] Figure 4 This is a flowchart illustrating a task processing method 400 according to some embodiments of this invention. In operation S410, the instruction processor responds to a task from the main processor and starts the intelligent processor. In operation S420, the intelligent processor selects the corresponding firmware code from multiple firmware codes according to the task and restarts the instruction processor to run the corresponding firmware code. In operation S430, the intelligent processor and the instruction processor work together to complete the task.

[0035] The descriptions of the above operations can be found in the foregoing embodiments, and therefore will not be repeated. The operations of the task processing method 400 described above are merely examples and are not limited to being executed in the order shown in this example. Without departing from the operation mode and scope of the embodiments of this case, the various operations in the task processing method 400 may be appropriately added, replaced, omitted, or executed in a different order (for example, they may be executed simultaneously or partially simultaneously).

[0036] In summary, the task processing system and method in some embodiments of this case can utilize an instruction processor to implement parallel task scheduling and a system architecture capable of independently executing each operation. This reduces the load on the main processor and achieves lower latency task processing times, thereby improving the overall system efficiency.

[0037] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the express or implied content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification.

[0038] [Symbol Explanation] 100: Task processing system; 110: Main processor; 120: Memory; 130, 135: Instruction processor; 140, 145: Intelligent processor; 210: Operational circuit; 220: Tightly coupled memory circuit; 222: Instruction-Tightly Coupled Memory; 224: Tightly Coupled Data Memory; 224A, 224B: Data area; 400: Task processing method; D1-DM, Di: Firmware code; H: Header; ID: Command data; PD: Data processing; RP: Read indicator signals; S301-S312, S320-S234, S410, S420, S430: Operation; TK1-TKn: Tasks; TQ: Task Queue; WP: Write indicator signal.

Claims

1. A task processing system, comprising: First intelligent processor; as well as A first instruction processor is configured to receive a first task from the main processor and, in response to the first task, launch the first intelligent processor. The computing power of the first instruction processor is lower than that of the main processor. The first intelligent processor selects a corresponding firmware code from multiple firmware codes according to the first task, restarts the first instruction processor to run the corresponding firmware code, and works in conjunction with the first instruction processor to complete the first task.

2. The task processing system as described in claim 1, characterized in that, The first instruction processor includes: A computing circuit, configured to start the first intelligent processor according to the first task, and run the corresponding firmware code to cooperate with the first intelligent processor to execute the first task; and Tightly coupled memory circuits; The first intelligent processor stores the corresponding firmware code in the tightly coupled memory circuit.

3. The task processing system as described in claim 1, characterized in that, The information for the first task includes the storage address of the instructions of the first intelligent processor in the memory and the storage address of the corresponding firmware code in the memory.

4. The task processing system as described in claim 1, characterized in that, The first instruction processor includes a tightly coupled memory circuit, and the main processor is used to store information of the first task in the tightly coupled memory circuit.

5. The task processing system as described in claim 1, characterized in that, After the task processing system is powered on, the first intelligent processor is directly started by the main processor to execute the first task, and after the first task is executed, the first intelligent processor is restarted by the first instruction processor.

6. The task processing system as described in claim 1, characterized in that, After the first intelligent processor executes the first task, the first intelligent processor enters a hibernation mode until it is restarted by the first instruction processor.

7. The task processing system as described in claim 1, characterized in that, When the first instruction processor starts the first intelligent processor, it does not occupy the kernel thread of the main processor.

8. The task processing system as described in claim 1, characterized in that, Also includes: Second intelligent processor; as well as A second instruction processor is configured to receive a second task from the main processor and, in response to the second task, initiate a second intelligent processor to execute the second task. The first instruction processor stores a first task queue including the first task, and the second instruction processor stores a second task queue including the second task. The main processor determines whether to write the task to be processed into the first task queue or the second task queue based on a first difference and a second difference. The first difference is determined based on a first read indicator signal and a first write indicator signal corresponding to the first instruction processor, and the second difference is determined based on a second read indicator signal and a second write indicator signal corresponding to the second instruction processor.

9. The task processing system as described in claim 1, characterized in that, The operating system of the task processing system is executed by the main processor.

10. The task processing system as described in claim 1, characterized in that, The first instruction processor is a processor based on an open-source instruction set architecture.

11. A task processing method, applied to a processing system, characterized in that, include: The intelligent processor is activated by responding to a task from the main processor via an instruction processor, wherein the computing power of the instruction processor is lower than that of the main processor. The intelligent processor selects the corresponding firmware code from multiple firmware codes according to the task, and restarts the instruction processor to make the instruction processor run the corresponding firmware code; as well as The task is accomplished by the intelligent processor working in conjunction with the instruction processor.

12. The task processing method as described in claim 11, characterized in that, The intelligent processor stores the corresponding firmware code in the tightly coupled memory circuit of the instruction processor.

13. The task processing method as described in claim 11, characterized in that, The main processor stores the task information in the tightly coupled memory circuit of the instruction processor.

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