Semiconductor device

Abstract

A semiconductor device. As non-limiting examples, various features of this summary are provided for various semiconductor package structures, and methods for making the same, including a thin fine pitch redistribution structure.

Description

[0001] This application is a divisional application of the invention entitled "Semiconductor Device", filed on August 9, 2016, with application number 201610648773.X. Technical Field

[0002] This invention relates to a semiconductor device.

[0003] Cross-referencing / inclusion of related applications as a reference

[0004] This application relates to U.S. Patent Application Serial No. 13 / 753,120, filed January 29, 2013, entitled "Semiconductor Device and Method of Manufacturing a Semiconductor Device"; U.S. Patent Application Serial No. 13 / 863,457, filed April 16, 2013, entitled "Semiconductor Device and Method of Manufacturing the Same"; U.S. Patent Application Serial No. 14 / 083,779, filed November 19, 2013, entitled "Semiconductor Device with Through-Silicon Vias - A Less Deep Well"; U.S. Patent Application Serial No. 14 / 218,265, filed March 18, 2014, entitled "Semiconductor Device and Method of Manufacturing the Same"; and U.S. Patent Application Serial No. 14 / 313,724, filed June 24, 2014, entitled "Semiconductor Device and Method of Manufacturing the Same". U.S. Patent Application Serial No. 14 / 444,450, filed July 28, 2014, entitled "Semiconductor Device Having a Thin Redistribution Layer"; U.S. Patent Application Serial No. 14 / 524,443, filed October 27, 2014, entitled "Semiconductor Device Having Reduced Thickness"; U.S. Patent Application Serial No. 14 / 532,532, filed November 4, 2014, entitled "Intermediate, Method of Manufacturing Thereof, Semiconductor Package Using Thereof, and Method for Manufacturing the Semiconductor Package"; U.S. Patent Application Serial No. 14 / 546,484, filed November 18, 2014, entitled "Semiconductor Device Having Reduced Warpage"; and U.S. Patent Application Serial No. 14 / 671,095, filed March 27, 2015, entitled "Semiconductor Device and Method of Manufacturing Thereof"; the contents of each of these U.S. patent applications are incorporated herein by reference in their entirety. Background Technology

[0005] Current semiconductor packaging methods are inadequate, resulting in, for example, excessive costs, lower reliability, or excessively large package sizes. Further limitations and disadvantages of these existing and conventional methods will become apparent to those skilled in the art upon comparison with the present invention as set forth in the remainder of the reference drawings of this application. Summary of the Invention

[0006] The various features of this invention include providing a semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, the various features of this invention include providing various semiconductor package structures and methods for manufacturing them, which include a thin, fine-pitch redistribution structure.

[0007] One embodiment of the present invention is a semiconductor device comprising: a redistribution structure comprising: a first redistribution layer comprising: a first dielectric layer comprising: a first dielectric material; and a first conductive line; and a second redistribution layer comprising: a second dielectric layer comprising: a second dielectric material different from the first dielectric material; and a second conductive line electrically coupled to the first conductive line; a first semiconductor die attached to the first redistribution layer; a second semiconductor die attached to the first redistribution layer; and a conductive interconnect structure attached to the second redistribution layer.

[0008] Another embodiment of the present invention is a semiconductor device comprising: a redistribution structure including: an upper redistribution layer including: a first dielectric layer including a first dielectric material; and a first conductive line; and a lower redistribution layer including: a second dielectric layer including a second dielectric material; and a second conductive line electrically coupled to the first conductive line; a first semiconductor die attached to an upper side of the redistribution structure; a second semiconductor die attached to the upper side of the redistribution structure; a first molding material covering at least the upper side of the redistribution structure and a further lateral side of each of the first and second semiconductor dies; a substrate including a substrate side attached to a lower side of the redistribution structure; and a second molding material covering at least the upper substrate side, a lateral side of the first molding material, and a lateral side of the redistribution structure.

[0009] Another embodiment of the present invention is a semiconductor device comprising: a redistribution structure including: an upper redistribution layer including: a first dielectric layer including a first dielectric material; and a first conductive line; a lower redistribution layer including: a second dielectric layer including a second dielectric material; and a second conductive line electrically coupled to the first conductive line; and a plurality of conductive pillars extending from the lower redistribution layer and attached to the second conductive line; a first semiconductor die attached to an upper side of the redistribution structure; and a second semiconductor die attached to the upper side of the redistribution structure. Attached Figure Description

[0010] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. These drawings are examples depicting the invention and, together with the description, serve to explain the various principles of the invention. In the drawings:

[0011] Figure 1A-1J This is a cross-sectional view illustrating an example of a semiconductor package depicting various features of the present invention, and an example of a method for manufacturing a semiconductor package.

[0012] Figure 2 This is a flowchart illustrating an exemplary method for manufacturing a semiconductor package according to various features of the present invention.

[0013] Figures 3A-3B This is a cross-sectional view illustrating an example of a semiconductor package depicting various features of the present invention, and an example of a method for manufacturing a semiconductor package.

[0014] Figures 4A-4D This is a cross-sectional view illustrating an example of a semiconductor package depicting various features of the present invention, and an example of a method for manufacturing a semiconductor package.

[0015] Figures 5A-5F This is a cross-sectional view illustrating an example of a semiconductor package depicting various features of the present invention, and an example of a method for manufacturing a semiconductor package.

[0016] Figures 6A-6D This is a cross-sectional view illustrating an example of a semiconductor package depicting various features of the present invention, and an example of a method for manufacturing a semiconductor package.

[0017] Figure 7A-7L This is a cross-sectional view illustrating an example of a semiconductor package depicting various features of the present invention, and an example of a method for manufacturing a semiconductor package.

[0018] Figure 8 This is a flowchart illustrating an exemplary method for manufacturing a semiconductor package according to various features of the present invention.

[0019] Figure 9 This is a cross-sectional view illustrating an example of a semiconductor package depicting various features of the present invention, and an example of a method for manufacturing a semiconductor package.

[0020] Figures 10A-10B This is a cross-sectional view illustrating an example of a semiconductor package depicting various features of the present invention, and an example of a method for manufacturing a semiconductor package.

[0021] Figure 11A-11D This is a cross-sectional view illustrating an example of a semiconductor package depicting various features of the present invention, and an example of a method for manufacturing a semiconductor package.

[0022] Figure 12A-12B This is a cross-sectional view illustrating an example of a semiconductor package depicting various features of the present invention, and an example of a method for manufacturing a semiconductor package.

[0023] Figure 13 This is a cross-sectional view illustrating an example of a semiconductor package depicting various features of the present invention, and an example of a method for manufacturing a semiconductor package.

[0024] Figure 14 This is a cross-sectional view illustrating an example of a semiconductor package depicting various features of the present invention, and an example of a method for manufacturing a semiconductor package.

[0025] Figure 15 This is a cross-sectional view illustrating an example of a semiconductor package depicting various features of the present invention, and an example of a method for manufacturing a semiconductor package.

[0026] Figure 16 This is a cross-sectional view illustrating an example of a semiconductor package depicting various features of the present invention, and an example of a method for manufacturing a semiconductor package. Detailed Implementation

[0027] The following discussion is presented by way of various examples that provide various features of the present invention. These examples are not limiting, and therefore the scope of the various features of the present invention should not necessarily be limited to any particular feature of the examples provided. In the following discussion, the terms "for example," "for instance," and "exemplary" are not limiting and are generally synonymous with "illustrated but not limiting," "for example but not limiting," and the like.

[0028] As used herein, "and / or" indicates any one or more of the items added to a table column by "and / or". For example, "x and / or y" indicates any element in the set of three elements {(x), (y), (x,y)}. In other words, "x and / or y" indicates "one or both of x and y". As another example, "x, y and / or z" indicates any element in the set of seven elements {(x), (y), (z), (x,y), (x,z), (y,z), (x,y,z)}. In other words, "x, y and / or z" indicates "one or more of x, y and z".

[0029] The terminology used herein is for the purpose of describing particular examples only and is not intended to limit the scope of the invention. As used herein, the singular form is intended to include multiple forms unless the context clearly indicates otherwise. It will further be understood that when the terms "comprising," "including," "having," and the like are used in this specification, they indicate the presence of the stated features, integers, steps, operations, components, and / or elements, but do not exclude the presence or addition of one or more other features, integers, steps, operations, components, elements, and / or groups thereof.

[0030] It will be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are merely used to distinguish one component from another. Thus, for example, a first component, a first member, or a first segment discussed below may be referred to as a second component, a second member, or a second segment without departing from the teachings of the invention. Similarly, various spatial terms such as "above," "below," "side," and the like may be used in a relative manner to distinguish one component from another. However, it should be understood that components may be oriented in different ways; for example, a semiconductor device may be turned to the side so that its "top" surface is horizontal and its "side" surface is vertical, without departing from the teachings of the invention.

[0031] The various features of this invention include providing a semiconductor device or package and a method of manufacturing (or fabricating) the same, which can reduce costs, improve reliability, and / or improve the manufacturability of the semiconductor device.

[0032] The above-described features and other features of the present invention will be apparent from the following description of various exemplary embodiments. The various features of the present invention will now be presented with reference to the accompanying drawings, enabling those skilled in the art to easily implement these features.

[0033] Figure 1A-1J This is a cross-sectional view illustrating an exemplary semiconductor package and an exemplary method of manufacturing a semiconductor package, depicting various features according to the present invention. Figure 1A-1J The structure shown in the document can be compared with that in Figures 3A-3B Similar structures shown in 4A-4D, 5A-5F, 6A-6D, 7A-7L, 9, 10A-10B, 11A-11D, 12A-12B, 13, 14, 15, and 16 share any or all of the features. Figure 2 is a flowchart of an exemplary method 200 for manufacturing a semiconductor package according to various features of the present invention. Figure 1A-1J For example, it can be depicted in Figure 2 Method 200 is an example of various steps (or blocks) in semiconductor packaging. Figure 1A-1J as well as Figure 2 They will now be discussed together. It should be noted that the order of the blocks in the example of method 200 can be changed without departing from the scope of this invention.

[0034] The method 200 of this example, in block 205, may include preparing a logic wafer for processing (e.g., for packaging). Block 205 may include preparing a logic wafer for processing in any of a variety of ways, the non-limiting of which is shown herein.

[0035] For example, block 205 may include receiving a logic wafer, for example, from a supplier, from an upstream process at a manufacturing location, etc. The logic wafer may include, for example, a semiconductor wafer comprising a plurality of active semiconductor dies. The semiconductor dies may include, for example, a processor die, a memory die, a programmable logic die, an application-specific integrated circuit die, a general logic die, etc.

[0036] Block 205 may include, for example, forming conductive interconnect structures on the logic wafer. Such conductive interconnect structures may include, for example, conductive pads, planes, bumps or balls, conductive pillars, etc. The forming process may include, for example, attaching a pre-formed interconnect structure to the logic wafer, electroplating the interconnect structure on the logic wafer, etc.

[0037] In one exemplary embodiment, the conductive structures may include conductive pillars (which comprise copper and / or nickel) and may include a solder cap (e.g., which comprises tin and / or silver). For example, a conductive structure including conductive pillars may include: (a) a bump bottom metallization ("UBM") structure comprising (i) a titanium-tungsten (TiW) layer (which may be referred to as a "seed layer") formed by sputtering, and (ii) a copper (Cu) layer formed on the titanium-tungsten layer by sputtering; (b) a copper pillar formed on the UBM by electroplating; and (c) a solder layer formed on the copper pillar, or a nickel layer formed on the copper pillar and a solder layer formed on the nickel layer.

[0038] Furthermore, in an exemplary embodiment, the conductive structures may include a lead and / or lead-free wafer bump. For example, the lead-free wafer bump (or interconnect structure) may be formed at least in part by: (a) forming a bump bottom metallization (UBM) structure by (i) sputtering to form a titanium (Ti) or titanium-tungsten (TiW) layer, (ii) sputtering to form a copper (Cu) layer on the titanium or titanium-tungsten layer, (iii) electroplating to form a nickel (Ni) layer on the copper layer; and (b) electroplating to form a lead-free solder material on the nickel layer of the UBM structure, wherein the lead-free solder material has a composition of 1% to 4% silver (Ag) by weight, and the remainder of the composition by weight is tin (Sn).

[0039] Block 205 may include, for example, performing partial or complete thinning of the logic wafer (e.g., grinding, etching, etc.). Block 205 may also include, for example, dicing the logic wafer into individual dies or groups of dies for subsequent mounting. Block 205 may also include receiving the logic wafer from an adjacent or upstream manufacturing station in a manufacturing facility, from another geographical location, etc. The received logic wafer may be, for example, already fabricated, or additional fabrication steps may be performed.

[0040] Generally, block 205 may include the fabrication of a logic wafer for processing (e.g., for packaging). Therefore, the scope of this invention should not be limited to the characteristics of a particular type of logic wafer and / or die processing.

[0041] The method 200 of this example, in block 210, may include the fabrication of a carrier, substrate, or wafer. The fabricated (or received) wafer may be referred to as a redistributed structure wafer or an RD wafer. Block 210 may include the fabrication of an RD wafer for processing in any of a variety of ways, non-limiting examples of which are shown herein.

[0042] The RD wafer may include, for example, an intermediate wafer, a packaging substrate wafer, etc. The RD wafer may include, for example, a redistribution structure formed (e.g., die-by-die) on a semiconductor (e.g., silicon) wafer. The RD wafer may include only electrical paths and not electronic devices (e.g., semiconductor devices). The RD wafer may also include passive electronic devices but not active semiconductor devices. For example, the RD wafer may include one or more conductive layers or lines formed on or coupled to a substrate or carrier (e.g., directly or indirectly thereon). Examples of the carrier or substrate may include a semiconductor (e.g., silicon) wafer or a glass substrate. Examples of processes used to form conductive layers (e.g., copper, aluminum, tungsten, etc.) on a semiconductor wafer include semiconductor wafer fabrication processes, which may also be referred to herein as back-end processes (BEOL). In an exemplary embodiment, the conductive layers may be deposited on or on a substrate using a sputtering and / or electroplating process. These conductive layers may be referred to as redistribution layers. These redistribution layers can be used to wire an electrical signal between two or more electrical connections, and / or to wire an electrical connection with a wider or narrower pitch.

[0043] In one exemplary embodiment, various portions of the redistributed structure (e.g., an interconnect structure that can be attached to an electronic device (e.g., a plane, a line, etc.)) may be formed with a pitch of one sub-micrometer (or a center-to-center spacing) and / or less than one 2-micrometer pitch. In various other embodiments, a pitch of 2-5 micrometers may be used.

[0044] In one exemplary embodiment, a silicon wafer on which the redistribution structure is formed may include a lower grade of silicon than that which can be fully utilized to form the semiconductor die ultimately attached to the redistribution structure. In another exemplary embodiment, the silicon wafer may be a recycled silicon wafer manufactured from a failed semiconductor device wafer. In yet another exemplary embodiment, the silicon wafer may include a thinner silicon layer than that which can be fully utilized to form the semiconductor die ultimately attached to the redistribution structure. Block 210 may also include receiving the RD wafer from an adjacent or upstream manufacturing station in a manufacturing facility, from another geographical location, etc. The received RD wafer may, for example, be already fabricated or may require additional fabrication steps.

[0045] Figure 1A This is an icon that provides an example of the various features of block 210. (See reference...) Figure 1AThe RD wafer 100A may include, for example, a support layer 105 (e.g., a silicon or other semiconductor layer, a glass layer, etc.). A redistribution (RD) structure 110 may be formed on the support layer 105. The RD structure 110 may include, for example, a substrate dielectric layer 111, a first dielectric layer 113, a first conductive line 112, a second dielectric layer 116, a second conductive line 115, and an interconnect structure 117.

[0046] The substrate dielectric layer 111 may, for example, be on the support layer 105. The substrate dielectric layer 111 may, for example, include an oxide layer, a nitride layer, etc. The substrate dielectric layer 111 may, for example, be formed according to specifications and / or may be natural. The dielectric layer 111 may be referred to as a protective layer. For example, the dielectric layer 111 may be a silicon dioxide layer formed using a low-pressure chemical vapor deposition (LPCVD) process, or may include the silicon dioxide layer.

[0047] The RD wafer 100A may, for example, include first conductive lines 112 and a first dielectric layer 113. The first conductive lines 112 may, for example, include deposited conductive metals (e.g., copper, aluminum, tungsten, etc.). The conductive lines 112 may be formed by sputtering and / or electroplating. The conductive lines 112 may, for example, be formed at a spacing of one or two micrometers (or a center-to-center spacing). The first dielectric layer 113 may, for example, include an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). It is noted that in various embodiments, the dielectric layer 113 may be formed prior to the first conductive lines 112, for example, by forming vias that are then filled into the first conductive lines 112 or a portion thereof. In an embodiment, for example, including copper conductive lines, a dual damascene process may be used to deposit these lines.

[0048] In an alternative component, the first dielectric layer 113 may comprise an organic dielectric material. For example, the first dielectric layer 113 may comprise bismaleimidetriazine (BT), phenolic resin, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), epoxy resin, and equivalents and compounds thereof, but the scope of this invention is not limited thereto. The organic dielectric material may be formed using any of a variety of methods (e.g., chemical vapor deposition, CVD). In this alternative component, the first conductive lines 112 may, for example, be spaced at a 2-5 micrometer pitch (or center-to-center spacing).

[0049] The RD wafer 100A may, for example, include a second conductive line 115 and a second dielectric layer 116. The second conductive lines 115 may, for example, include deposited conductive metal (e.g., copper, etc.). The second conductive lines 115 may, for example, be connected to individual first conductive lines 112 through individual conductive vias 114 (e.g., in the first dielectric layer 113). The second dielectric layer 116 may, for example, include an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In an alternative embodiment, the second dielectric layer 116 may include an organic dielectric material. For example, the second dielectric layer 116 may include bis(cis-butenedioic acid)imide / trinitrogen trap (BT), phenolic resin, polyimide (PI), phenylcyclobutene (BCB), polybenzoxazole (PBO), epoxy resin, and equivalents and compounds thereof, but the scope of this invention is not limited thereto. The second dielectric layer 116 may, for example, be formed using a CVD process, but the scope of this invention is not limited thereto.

[0050] Although the dielectric layers and conductive lines of the two groups are depicted in Figure 1A However, it should be understood that the RD structure 110 of the RD wafer 100A may include any number of such layers and lines. For example, the RD structure 110 may include only one dielectric layer and / or multiple sets of conductive lines, three sets of dielectric layers and / or conductive lines, etc.

[0051] Similar to the logic wafer fabrication in block 205, block 210 may include interconnect structures (e.g., conductive bumps, conductive balls, conductive pillars, conductive planes or pads, etc.) formed on one surface of the RD structure 110. An example of such an interconnect structure 117 is shown in... Figure 1AIn this embodiment, the RD structure 110 includes an interconnect structure 117, which is shown to be formed on the front (or top) side of the RD structure 110 and electrically connected to individual second conductive lines 115 through conductive vias in the second dielectric layer 116. Such an interconnect structure 117 can be used, for example, to couple the RD structure 110 to various electronic components (e.g., active semiconductor components or chips, passive components, etc.).

[0052] These interconnect structures 117 may include, for example, any of a variety of conductive materials (e.g., any one or a combination of copper, nickel, gold, etc.). These interconnect structures 117 may also include, for example, solder.

[0053] Generally, block 210 may include the fabrication of a redistributed structure wafer (RD wafer). Therefore, the scope of this invention should not be limited to the features of any particular method of performing such fabrication.

[0054] Method 200 of this example may include forming an interconnect structure (e.g., a through-mold via (TMV) interconnect structure) on the RD wafer in block 215. Block 215 may include forming such an interconnect structure in any of a variety of ways.

[0055] These interconnect structures may include any of a variety of features. For example, these interconnect structures may include solder balls or bumps, multi-spherical solder pillars, elongated solder balls, metal (e.g., copper) core balls with a solder layer on a metal core, electroplated pillar structures (e.g., copper pillars, etc.), wire structures (e.g., wire-jointed wires), etc.

[0056] These interconnect structures can include any of various sizes. For example, these interconnect structures can extend from the RD wafer to a height less than the height of the electronic component coupled to the RD wafer (e.g., in block 220). Similarly, these interconnect structures can extend from the RD wafer to a height greater than or equal to the height of the electronic component coupled to the RD wafer. The importance of this relative height will become apparent in the discussion herein (e.g., in discussions of molding thinning, package stacking, top substrate attachment, top redistribution structure formation, etc.). These interconnect structures can also be formed, for example, at various pitches (or center-to-center spacing). For example, these interconnect structures (e.g., conductive pillars or columns) can be plated and / or bonded at a pitch of 150-250 micrometers or less. Similarly, these interconnect structures (e.g., elongated and / or metal-filled solder structures) can be attached at a pitch of 250-350 micrometers or less. Similarly, for example, these interconnect structures (e.g., solder balls) can be attached at a pitch of 350-450 micrometers or less.

[0057] Block 215 may include attaching the interconnect structures in any of a variety of ways. For example, block 215 may include reflowing the interconnect structures onto the RD wafer, electroplating the interconnect structures onto the RD wafer, wire bonding the interconnect structures onto the RD wafer, using conductive epoxy resin to attach pre-formed interconnect structures to the RD wafer, and so on.

[0058] Figure 1B This is an illustration of an example of the various features of block 215 (e.g., the features of interconnect structure formation). In the example component 100B, interconnect structure 121 (e.g., solder ball) is attached (e.g., reflow attachment, attachment using a solder ball drop process, etc.) to RD structure 110 of the RD wafer 100A.

[0059] Although the interconnection structure 121 of two columns is shown, various implementations may include a single column, three columns, or any number of columns. As will be discussed herein, various exemplary implementations may not have this interconnection structure 121, and therefore block 215 may be included in exemplary method 200.

[0060] It is noted that, although in method 200 of this example, block 215 is performed before the wafer molding operation of block 230, the interconnect structures can alternatively be formed after the wafer molding operation (e.g., forming through-holes in the molding material and then filling such holes with a conductive material). It is also noted that, as in... Figure 2As shown, block 215 can be executed, for example, after the die attachment operation of block 220, rather than before the die attachment.

[0061] Generally, block 215 may include an interconnect structure formed on the RD wafer. Therefore, the scope of this invention should not be limited to the characteristics of a particular type of interconnect structure or to the characteristics of any particular manner in which such an interconnect structure is formed.

[0062] The method 200 of this example may include attaching one or more semiconductor dies to the RD structure (e.g., the RD structure of the RD wafer) in block 220. Block 220 may include attaching the dies to the RD structure in any of a variety of ways, non-limiting examples of which are provided herein.

[0063] The semiconductor die may include features of any of various types of semiconductor dies. For example, the semiconductor die may include a processor die, a memory die, an application-specific integrated circuit die, a general logic die, an active semiconductor device, etc. It should be noted that passive devices may also be attached to block 220.

[0064] Block 220 may include attaching the semiconductor die using any of a variety of methods (e.g., as prepared in block 205). For example, block 220 may include attaching the semiconductor die using mass reflow, thermocompression bonding (TCB), conductive epoxy, etc.

[0065] Figure 1B This is an illustration illustrating an example of various features of block 220, such as die attachment features. For example, a first die 125 (e.g., which may have been diced from a logic wafer prepared in block 205) is electrically and mechanically attached to the redistribution structure 110. Similarly, a second die 126 (e.g., which may have been diced from a logic wafer prepared in block 205) is electrically and mechanically attached to the redistribution structure 110. For example, as explained in block 205, the logic wafer (or its dies) may have been prepared with various interconnect structures formed thereon (e.g., conductive pads, planes, bumps, balls, wafer bumps, conductive pillars, etc.). This structure is... Figure 1B The middle section is generally shown as item 119. Block 220 may include, for example, any of a variety of attachment processes (e.g., batch reflow, thermocompression bonding (TCB), conductive epoxy, etc.) to electrically and mechanically attach such an interconnect structure to the redistribution structure 110.

[0066] The first die 125 and the second die 126 may include any of a variety of die features. In one example scenario, the first die 125 may include a processor die, and the second die 126 may include a memory die. In another example scenario, the first die 125 may include a processor die, and the second die 126 may include a coprocessor die. In yet another example scenario, the first die 125 may include a sensor die, and the second die 126 may include a sensor processing die. Although in Figure 1B Component 100B is shown as having two grains 125 and 126, but it can have any number of grains. For example, it can have only one grain, three grains, four grains, or more than four grains.

[0067] Furthermore, although the first die 125 and the second die 126 are shown attached laterally to the redistribution structure 110 relative to each other, they can also be configured with a vertical assembly. Various non-limiting examples of this structure are shown and discussed herein (e.g., die stacking on dies, dies attached to opposite substrate sides, etc.). Moreover, although the first die 125 and the second die 126 are shown to have substantially similar dimensions, these dies 125, 126 may include different individual features (e.g., die height, coverage area, interconnection spacing, etc.).

[0068] The first die 125 and the second die 126 are depicted as having a generally uniform pitch, but this is not necessarily the case. For example, most or all of the contacts 119 of the first die 125 in a region of the first die coverage area adjacent to the second die 126 and / or most of the contacts 119 of the second die 126 in a region of the second die coverage area adjacent to the first die 125 may have a substantially finer pitch than most or all of the other contacts 119. For example, the first 5, 10, or n columns of contacts 119 of the first die 125 closest to the second die 126 (and / or the second die 126 closest to the first die 125) may have a pitch of 30 micrometers, while other contacts 119 may have a pitch of approximately 80 micrometers and / or 200 micrometers. The RD structure 110 can therefore have corresponding contact structures and / or circuitry at these corresponding pitches.

[0069] Generally, block 220 includes attaching one or more semiconductor dies to the redistribution structure (e.g., a redistribution structure of a redistribution wafer). Therefore, the scope of this invention should not be limited to the characteristics of any particular die, or to the characteristics of any particular layout of the polydies, or to the characteristics of any particular manner in which such dies are attached, etc.

[0070] Method 200 of this example may include underfilling in block 225 of attaching semiconductor dies and / or other components to the RD structure in block 220. Block 225 may include performing such underfilling in any of a variety of ways, non-limiting examples of which are shown herein.

[0071] For example, after the die attachment in block 220, block 225 may include underfilling the semiconductor die with a capillary underfill. For example, the underfill may include a sufficiently viscous reinforcing polymeric material that flows between the attached die and the RD wafer in a capillary action.

[0072] Similarly, for example, block 225 may include filling the semiconductor die with a non-conductive paste (NCP) and / or a non-conductive film (NCF) or adhesive tape while the die is being attached to block 220 (e.g., using a thermosetting bonding process). For example, such adhesive filling material may be deposited (e.g., printed, sprayed, etc.) before the semiconductor die is attached.

[0073] As with all the blocks depicted in method 200 of this example, block 225 can be executed at any point in the process of method 200, provided that the space between the grain and the redistributed structure is accessible.

[0074] The underfill can also occur in a different block of method 200 in this example. For example, the underfill can be performed as part of the wafer molding block 230 (e.g., using a molding underfill).

[0075] Figure 1B This is an icon illustrating an example of various features of block 225 (e.g., the features of the underfill). The underfill 128 is disposed between the first semiconductor die 125 and the redistribution structure 110, and between the second semiconductor die 126 and the redistribution structure 110, for example, around the contacts 119.

[0076] Although the underfill 128 is generally depicted as flat, it may be raised and form fillets on the sides of the semiconductor dies and / or other components. In one example, at least one-quarter or at least half of the die side surfaces may be covered by the underfill material. In another example, one or more or all of the entire side surfaces may be covered by the underfill material. Similarly, for example, a substantial portion of the space directly between the semiconductor dies, between the semiconductor dies and other components, and / or between other components may be filled with the underfill material. For example, at least half or all of the space between laterally adjacent semiconductor dies, between the dies and other components, and / or between other components may be filled with the underfill material. In one example embodiment, the underfill 128 may cover the entire redistribution structure 110 of the RD wafer. In this example embodiment, when the RD wafer is subsequently diced, such dicing may also cut through the underfill 128.

[0077] Generally, block 225 may include an underfill material attached to the semiconductor die and / or other components of the RD structure in block 220. Therefore, the scope of this invention should not be limited to any particular type of underfill or any particular method of performing such underfill.

[0078] The method 200 of this example may include molding the RD wafer (e.g., or an RD structure) in block 230. Block 230 may include molding the RD wafer in any of a variety of ways, of which non-limiting examples are shown herein.

[0079] For example, block 230 may include molded on the top surface of the RD wafer, on the dies and / or other components attached to block 220, on the interconnect structure formed in block 215 (e.g., conductive spheres, ellipsoids, pillars or columns (e.g., electroplated pillars, lines or bonding lines, etc.), etc.), on the underfill formed in block 225, etc.

[0080] Block 230 may include compression molding (e.g., using liquid, powder, and / or film) or vacuum molding. Similarly, block 230 may include a transfer molding process (e.g., a wafer-level transfer molding process).

[0081] The molding material may include, for example, any of a variety of characteristics. For instance, the molding material (e.g., epoxy molding compound (EMC), epoxy resin molding compound, etc.) may include a relatively high modulus, for example, to provide wafer support in a subsequent process. Similarly, for example, the molding material may include a relatively low modulus to provide wafer flexibility in a subsequent process.

[0082] As explained herein, for example, with respect to block 225, the molding process of block 230 can provide an underfill material between the die and the RD wafer. In this example, there can be a uniform material between the molding underfill material and the molding material encapsulating the semiconductor die.

[0083] Figure 1C This is an illustration of an example of various features (e.g., molding features) of block 230. For example, molding assembly 100C is shown where molding material 130 covers the top surfaces of interconnect structures 121, first semiconductor die 125, second semiconductor die 126, primer filler 128, and redistribution structure 110. Although the molding material 130 (which may also be referred to herein as encapsulating material) is shown to completely cover the sides and tops of the first semiconductor die 125 and the second semiconductor die 126, this is not necessary. For example, block 230 may include molding techniques using a film-assisted or die-sealing method to keep the tops of the dies free of molding material.

[0084] Generally, the molding material 130 can, for example, directly contact and cover the portions of the grains 125, 126 that are not covered by the primer filler 128. For example, in a scenario where at least a first portion of the sides of the grains 125, 126 is covered by the primer filler 128, the molding material 130 can directly contact and cover a second portion of the sides of the grains 125, 126. The molding material 130 can also, for example, fill the spaces between the grains 125, 126 (e.g., at least a portion of the spaces not yet filled by the primer filler 128).

[0085] Generally, block 230 may include molding the RD wafer. Therefore, the scope of this invention should not be limited to the characteristics of any particular molding material, structure, and / or technology.

[0086] Method 200 of this example may include grinding (or thinning) the molding material applied in block 235. Block 235 may include grinding (or thinning) the molding material in any of a variety of ways, non-limiting examples of which are presented herein.

[0087] Block 235 may include, for example, mechanically grinding the molding material to thin it. Such thinning may, for example, preserve the grains and / or interconnect structures as overmolded, or may expose one or more grains and / or one or more interconnect structures.

[0088] Block 235 may include grinding other components besides the molding compound. For example, block 235 may include grinding the tip side (e.g., the back side or non-active side) of the die to which block 220 is attached. Block 235 may also include grinding the interconnect structure formed in block 215. Furthermore, in a scenario where the primer filler applied to block 225 or block 230 extends upward sufficiently, block 235 may also include grinding such primer filler material. Such grinding may, for example, create a flat planar surface at the tip of the material being ground.

[0089] Block 235 could be, for example, a section in which the height of the molding material was originally formed in a plot of desired thickness and is skipped.

[0090] Figure 1D This is an icon that provides an example of various features of block 235 (e.g., the molding and grinding features). Component 100D is depicted as wherein the molding material 130 (e.g., relative to the molding material 130) is used. Figure 1C The molded material 130 depicted is thinned to expose the top surfaces of the grains 125 and 126. In this example, the grains 125 and 126 may also have been ground (or thinned).

[0091] Although as in Figure 1D As shown in the illustration, the top surface of the molding material is over the interconnect structures 121, and therefore the interconnect structures 121 are not ground, although they could be ground. This exemplary embodiment may, for example, produce a top surface at this stage that includes grains 125, 126, a top surface of the molding material 130, and a top surface of the interconnect structures 121, all on a common plane.

[0092] As explained herein, the molding material 130 can be retained in an overmold configuration to cover the grains 125, 126. For example, the molding material 130 may not be ground, or the molding material 130 may be ground, but not to a height that exposes the grains 125, 126.

[0093] Generally, block 235 may include grinding (or thinning) the molding material applied to block 230. Therefore, the scope of this invention should not be limited to the characteristics of any particular amount or type of grinding (or thinning).

[0094] Method 200 of this example may include stripping the molding material applied in block 230 in block 240. Block 240 may include stripping the molding material in any of a variety of ways, non-limiting examples of which are provided herein.

[0095] As discussed herein, the molding material may cover the interconnect structures formed in block 215. If the molding material covers the interconnect structures and those interconnect structures need to be exposed (e.g., for subsequent package attachment, top-side redistribution layer formation, top-side multilayer substrate attachment, electrical connections, heat sink connections, electromagnetic shielding connections, etc.), then block 240 may include eroding the molding material to expose those interconnect structures.

[0096] Block 240 may include, for example, using laser ablation to expose the interconnect structures through the molding material. Similarly, block 240 may include methods such as soft beam drilling, mechanical drilling, chemical drilling, etc.

[0097] Figure 1D The illustration is an example of various features of block 240 (e.g., the erosion feature). For example, component 100D is shown to include eroded through-holes 140 extending through the molding material 130 to the interconnect structure 121. Although these eroded through-holes 140 are shown to have vertical sidewalls, it should be understood that the through-holes 140 can include any of a variety of shapes. For example, the sidewalls can be sloping (e.g., having a larger opening on the top surface of the molding material 130 than in the interconnect structure 121).

[0098] Although block 240 is Figure 2 The process is described as immediately following wafer molding in block 230 and molding and polishing in block 235, but block 240 can be performed at any point after the process 200. For example, block 240 can be performed after the wafer support structure (e.g., to which block 245 is attached) has been removed.

[0099] Generally, block 240 may include the molding material applied to block 230 (e.g., to expose the interconnect structure formed in block 215). Therefore, the scope of this invention should not be limited to the characteristics of any particular manner in which such erosion is performed, or to the characteristics of any particular eroded through-hole structure.

[0100] The method 200 of this example, in block 245, may include attaching the molded RD wafer (e.g., its top or molded side) to a wafer support structure. Block 245 may include attaching the molded RD wafer to the wafer support structure in any of a variety of ways, non-limiting examples of which are provided herein.

[0101] The wafer support structure may include, for example, a wafer or fixture formed of silicon, glass, or various other materials (e.g., dielectric materials). Block 245 may include, for example, using an adhesive, a vacuum fixture, etc., to attach the molded RD wafer to the wafer support structure. Note that, as depicted and explained herein, a redistribution structure may be formed on the top (or back) side of the die and molding material prior to attachment of the wafer support.

[0102] Figure 1E This is an illustration of an example of various features of block 245 (e.g., wafer support attachment features). The wafer support structure 150 is attached to the molding material 130 and the top sides of the dies 125, 126. The wafer support structure 150 may be attached, for example, using an adhesive, which may also be formed in the vias 140 and contact the interconnect structures 121. In another example assembly, the adhesive does not enter the vias 140 and / or does not contact the interconnect structures 121. It should be noted that in an assembly where the tops of the dies 125, 126 are covered by the molding material 130, the wafer support structure 150 may only be directly coupled to the top of the molding material 130.

[0103] Generally, block 245 may include attaching the molded RD wafer (e.g., its top or molded side) to a wafer support structure. Therefore, the scope of this invention should not be limited to the characteristics of any particular type of wafer support structure, or to the characteristics of any particular manner of attaching a wafer support structure.

[0104] Method 200 of this example may include removing a support layer from the RD wafer in block 250. Block 250 may include removing the support layer in any of a variety of ways, of which non-limiting examples are shown herein.

[0105] As discussed herein, the RD wafer may include a support layer on which an RD structure is formed and / or supported. The support layer may, for example, include a semiconductor material (e.g., silicon). In an exemplary scenario where the support layer comprises a silicon wafer layer, block 250 may include removing the silicon (e.g., removing all of the silicon from the RD wafer, removing almost all (e.g., at least 90% or 95%) of the silicon from the RD wafer, etc.). For example, block 250 may include mechanically grinding almost all of the silicon, followed by a dry or wet chemical etching to remove the remainder (or almost all of the remainder). In an exemplary scenario where the support layer is loosely attached to the RD structure formed (or supported) thereon, block 250 may include pulling or peeling to separate the support layer from the RD structure.

[0106] Figure 1F This is an icon that provides an example of various features of block 250 (e.g., the support layer removal feature). For example, the support layer 105 (in...) Figure 1E The RD structure 110 shown is removed from the RD structure 110. In the example illustrated, the RD structure 110 may still include a substrate dielectric layer 111 as discussed herein (e.g., an oxide, nitride, etc.).

[0107] Generally, block 250 may include the removal of a support layer from the RD wafer. Therefore, the scope of this invention should not be limited to the characteristics of any particular type of wafer material or to the characteristics of any particular method of wafer material removal.

[0108] The method 200 of this example may include forming and patterning a dielectric layer of a first redistribution layer (RDL) in block 255 for etching an oxide layer of the RD structure. Block 255 may include forming and patterning the first RDL dielectric layer in any of a variety of ways, of which non-limiting examples are shown herein.

[0109] In an example roughly described here, the RD structure of the RD wafer is generally formed on an oxide layer (or nitride or other dielectric). To enable metal-to-metal attachments to the RD structure, the portion of the oxide layer covering the wiring (or pads or planes) of the RD structure can be removed, for example, by etching. It should be noted that the oxide layer does not necessarily need to be removed or completely removed, as long as it has acceptable conductivity.

[0110] The first RDL dielectric layer may, for example, comprise a polyimide or a polybenzoxazole (PBO) material. The first RDL dielectric layer may, for example, comprise a laminated film or other materials. The first RDL dielectric layer may, for example, comprise a generally organic material. However, in various exemplary embodiments, the first RDL dielectric layer may comprise an inorganic material.

[0111] In one exemplary embodiment, the first RDL dielectric layer may include an organic material (e.g., polyimide, PBO, etc.) formed on a first side of a base dielectric layer of the RD structure, and the base dielectric layer may include an oxide or nitride or other dielectric material.

[0112] The first RDL dielectric layer can be used, for example, as a shield for etching a base dielectric layer, such as an oxide or nitride layer (e.g., in block 260). Similarly, for example, after etching, the first RDL dielectric layer can be retained, for example, to form conductive RDL lines thereon.

[0113] In an alternative scenario (not shown), a temporary shielding layer (e.g., a temporary photoresist layer) may be used. For example, after etching, this temporary shielding layer may be removed and replaced by a permanent RDL dielectric layer.

[0114] Figure 1G This is an example icon illustrating various features of block 255. For example, the first RDL dielectric layer 171 is formed and patterned on the base dielectric layer 111. The patterned first RDL dielectric layer 171 may, for example, include vias 172 passing through the first RDL dielectric layer 171, and the base dielectric layer 111 may, for example, be etched through the vias 172 (e.g., in block 260), and a first line (or a portion thereof) may be formed in the vias 172 (e.g., in block 265).

[0115] Generally, block 255 may include, for example, forming and patterning a first dielectric layer (e.g., a first RDL dielectric layer) on the substrate dielectric layer. Therefore, the scope of this invention should not be limited to the characteristics of a particular dielectric layer or to the characteristics of a particular manner in which a dielectric layer is formed.

[0116] The method 200 of this example, in block 260, may include etching the substrate dielectric layer (e.g., oxide layer, nitride layer, etc.) from the RD structure, such as the unshielded portion thereof. Block 260 may include performing the etching in any of a variety of ways, of which non-limiting examples are shown herein.

[0117] For example, block 260 may include performing a dry etching process (or a wet etching process) to etch the portion of the substrate dielectric layer (e.g., oxide, nitride, etc.) exposed by a via through the first dielectric layer, which acts as a shield for the etching.

[0118] Figure 1G This is an icon illustrating an example of various features of block 260 (e.g., dielectric etch characteristics). For example, the substrate dielectric layer 111 in... Figure 1F The portion shown below the first conductive line 112 is self- Figure 1G Removed. This, for example, enables a metal-to-metal contact between the first conductive line 112 and the first RDL line formed in block 265.

[0119] Generally, block 260 may include, for example, etching the substrate dielectric layer. Therefore, the scope of this invention should not be limited to any particular method of performing such etching.

[0120] Method 200 of this example may include forming a first redistribution layer (RDL) line in block 265. Block 265 may include forming the first RDL line in any of a variety of ways, non-limiting examples of which are presented herein.

[0121] As discussed herein, the first RDL dielectric layer (e.g., formed in block 255) can be used for etching (e.g., in block 260) and then retained for the formation of the first RDL lines. Alternatively, the first RDL dielectric layer can be formed and patterned after the etching process. In yet another alternative embodiment discussed herein, the etching process for the substrate dielectric layer can be skipped, for example in an embodiment where the substrate dielectric layer (e.g., a thin oxide or nitride layer) is sufficiently conductive to adequately serve as a conductive path between metal lines.

[0122] Block 265 may include a first conductive line exposed through the patterned first RDL dielectric layer to form the first RDL line for attachment to the RD structure. The first RDL line may also be formed on the first RDL dielectric layer. Block 265 may include forming the first RDL line in any of a variety of ways (e.g., by electroplating), but the scope of this invention is not limited to any particular feature of forming such a line.

[0123] These first RDL lines may comprise any of various materials (e.g., copper, gold, nickel, etc.). The first RDL lines may, for example, comprise any of various dimensional features. For example, a typical pitch for the first RDL lines may be 5 micrometers. In an exemplary embodiment, the first RDL lines may be formed at a pitch (e.g., a sub-micrometer pitch, approximately 0.5 micrometers, etc.) where the various lines of the RD structure are formed with a center-to-center spacing approximately or at least an order of magnitude larger than that of the RD wafer.

[0124] Figure 1G and 1H This is an illustration of an example of various features of block 265 (e.g., RDL line formation features). For example, a first portion 181 of the first RDL line may be formed in a via 172 of the first RDL dielectric layer 171 and contact the first conductive line 112 exposed by the via 172 of the RD structure 110. Similarly, for example, a second portion 182 of the first RDL line may be formed on the first RDL dielectric layer 171.

[0125] Generally, block 265 may include a first redistribution layer (RDL) line. Therefore, the scope of this invention should not be limited to the characteristics of any particular RDL line or to the characteristics of any particular manner in which such an RDL line is formed.

[0126] The method 200 of this example may include forming and patterning a second RDL dielectric layer on the first RDL lines (e.g., formed in block 265) and the first RDL dielectric layer (e.g., formed in block 255) in block 270. Block 270 may include forming and patterning the second dielectric layer in any of a variety of ways, of which non-limiting examples are shown herein.

[0127] For example, block 270 may share any or all of the features with block 255. The second RDL dielectric layer may, for example, be formed using the same material as the first RDL dielectric layer formed in block 255.

[0128] The second RDL dielectric layer may, for example, comprise a polyimide or a polybenzoxazole (PBO) material. The second RDL dielectric layer may, for example, comprise a generally organic material. However, in various exemplary embodiments, the first RDL dielectric layer may comprise an inorganic material.

[0129] Figure 1HThis is an example icon providing various features of block 270. For example, the second RDL dielectric layer 183 is formed on the first RDL lines 181, 182 and on the first RDL dielectric layer 171. As in Figure 1H As shown, via 184 is formed in the second RDL layer 183, and conductive contact can be made through via 184 to the first RDL line 182 exposed by such via 184.

[0130] Generally, block 270 may include forming and / or patterning a second RDL dielectric layer. Therefore, the scope of this invention should not be limited to the characteristics of any particular dielectric layer or to the characteristics of any particular manner in which a dielectric layer is formed.

[0131] Method 200 of this example may include forming a second redistribution layer (RDL) line in block 275. Block 275 may include forming the second RDL line in any of a variety of ways, non-limiting examples of which are shown herein. Block 275 may, for example, share any or all of the features with block 265.

[0132] Block 275 may include forming second RDL lines attached to the first RDL lines (e.g., formed in block 265), which are exposed through vias in the patterned second RDL dielectric layer (e.g., formed in block 270). The second RDL lines may also be formed on the second RDL dielectric layer. Block 275 may include forming the second RDL lines using any of a variety of methods (e.g., by electroplating), but the scope of this invention is not limited to any particular method.

[0133] Like the first RDL lines, these second RDL lines can include any of various materials (e.g., copper, etc.). Furthermore, the second RDL lines can, for example, include any of various dimensional features.

[0134] Figure 1H and 1I This is an example icon illustrating various features of block 275. For instance, the second RDL lines 191 may be formed within vias 184 in the second RDL dielectric layer 183 to contact the first RDL lines 181 exposed through such vias 184. Furthermore, the second RDL lines 191 may be formed on the second RDL dielectric layer 183.

[0135] Generally, block 275 may include a second redistribution layer (RDL) line. Therefore, the scope of this invention should not be limited to the characteristics of any particular RDL line or to the characteristics of any particular manner in which such an RDL line is formed.

[0136] The method 200 of this example may include forming and patterning a third RDL dielectric layer on the second RDL line (e.g., formed in block 275) and the second RDL dielectric layer (e.g., formed in block 270). Block 280 may include forming and patterning the third dielectric layer in any of a variety of ways, non-limiting examples of which are shown herein.

[0137] For example, block 280 may share any or all of the features with blocks 270 and 255. The third RDL dielectric layer may be formed, for example, using the same material as the first RDL dielectric layer formed in block 255 (and / or after etching of block 260 and removal of a temporary shielding layer), and / or using the same material as the second RDL dielectric layer formed in block 270.

[0138] The third RDL dielectric layer may, for example, comprise a polyimide or a polybenzoxazole (PBO) material. The third RDL dielectric layer may, for example, comprise a generally organic material. However, in various exemplary embodiments, the third RDL dielectric layer may comprise an inorganic material.

[0139] Figure 1I This is an example icon providing various features of block 280. For example, the third RDL layer 185 can be formed on the second RDL lines 191 and on the second RDL layer 183. As in Figure 1I As shown, vias are formed in the third RDL layer 185, and conductive contacts can be made through these vias to the second RDL lines 191 exposed by these vias.

[0140] Generally, block 280 may include forming and / or patterning a third RDL dielectric layer. Therefore, the scope of this invention should not be limited to the characteristics of any particular dielectric layer or to the characteristics of any particular manner in which a dielectric layer is formed.

[0141] The method 200 of this example may include forming interconnect structures on the second RDL lines and / or on the third RDL dielectric layer in block 285. Block 285 may include forming the interconnect structures in any of a variety of ways, of which non-limiting examples are shown herein.

[0142] Block 285 may, for example, include forming an underbump metal on a portion of the second RDL line exposed through a via in the third dielectric layer. Block 285 may then, for example, include attaching conductive bumps or balls to the underbump metal. Other interconnect structures may also be used, examples of which are shown herein (e.g., conductive pillars or columns, solder balls, solder bumps, etc.).

[0143] Figure 1I This is an illustration of an example of various features of block 285 (e.g., features of interconnect structure formation). For example, interconnect structure 192 is attached to the second RDL lines 191 through vias formed in the third RDL dielectric layer 185. It should be noted that although interconnect structures 192 are depicted as smaller than interconnect structure 121, the invention is not so limited. For example, interconnect structures 192 may be the same size as interconnect structure 121 or larger than interconnect structure 121. Furthermore, interconnect structures 192 may be the same type of interconnect structure as interconnect structure 121 or may be a different type.

[0144] Although the redistribution layer formed in blocks 255-285 (which can also be called the positive redistribution layer (RDL)) Figure 1A-1J The interconnects are generally depicted as fan-out components (e.g., extending beyond the coverage areas of dies 125, 126), but they can also be formed as fan-in components, for example, where interconnect structure 192 does not generally extend beyond the coverage areas of dies 125, 126. Non-limiting examples of such components are shown herein.

[0145] Generally, block 285 may include interconnect structures formed on the second RDL lines and / or on the third RDL dielectric layer. Therefore, the scope of this invention should not be limited to the characteristics of any particular interconnect structure or to any particular manner in which the interconnect structure is formed.

[0146] Method 200 of this example may include debonding (or separating) the wafer support attached in block 245 in block 290. Block 290 may include performing such debonding in any of a variety of ways, the non-limiting nature of which is presented herein.

[0147] For example, in an embodiment where the wafer support is adhesively attached, the adhesive can be released (e.g., by heat and / or force). Similarly, a chemical release agent can be used. In another embodiment where the wafer support is attached using a vacuum force, the vacuum force can be released. It should be noted that in an embodiment involving adhesives or other substances to facilitate the mounting of the wafer support, block 285 may include removing residues from the electrical components and / or from the wafer support after the debonding process.

[0148] Figure 1I and 1J This is an example icon that provides various features of block 290. For example, in Figure 1I The wafer support 150 depicted in the image is... Figure 1J It was removed from the text.

[0149] Generally, block 290 may include debonding the wafer support. Therefore, the scope of this invention should not be limited to the characteristics of any particular type of wafer support, or to any particular manner of debonding a wafer support.

[0150] Method 200 of this example may include dicing the wafer in block 295. Block 295 may include dicing the wafer in any of a variety of ways, of which non-limiting examples are presented herein.

[0151] The discussion here has largely focused on the processing of a single die on the RD wafer. This focus on a single die on the RD wafer is merely for illustrative purposes. It should be understood that all the process steps discussed here can be performed on an entire wafer. For example, in Figure 1A-1J Each of the illustrations presented in the other figures herein can be replicated dozens or hundreds of times on a single wafer. For example, before dicing, one component of the exemplified components on the wafer may not be separated from an adjacent component.

[0152] Block 295 may, for example, include individual packages cut from the wafer (e.g., mechanical punching, mechanical sawing, laser cutting, flexible beam cutting, plasma cutting, etc.). The final result of such cutting may be, for example, in... Figure 1J The package shown is an example of a package where the cut can form a side surface that is a coplanar side surface comprising a plurality of components of the package. For example, any or all of the side surfaces of the molding material 130, the dielectric layer of the RD structure 110, various RDL dielectric layers, the underfill filler 128, etc., can be coplanar.

[0153] Generally, block 295 may include dicing the wafer. Therefore, the scope of this invention should not be limited to the characteristics of any particular method of dicing a wafer.

[0154] Figure 1A-1J and Figure 2 This section presents the characteristics of various exemplary methods and their variations. The characteristics of other exemplary methods will now be presented with reference to a separate diagram.

[0155] As discussed here, in Figure 1A-1J and Figure 2 In the discussion, block 235 may include grinding (or thinning) the molding material 130 to expose one or more of the grains 125, 126. An example is... Figure 1D Provided.

[0156] As discussed, molding and polishing (or thinning) of block 235 does not need to be performed, or can be performed to a extent that the tops of grains 125 and 126 are still covered with molding material 130. An example is shown in Figure 3. Figures 3A-3B Provided. As in Figure 3A As shown, the molding material 130 covers the tops of semiconductor dies 125 and 126. It is noted that the interconnect structures 121 can be shorter or taller than the dies 125 and 126. Continuing this comparison, it is not as shown in... Figure 1J The resulting package shown is 100J, but the resulting package 300B can appear as in... Figure 3B As shown in the image.

[0157] Furthermore, as discussed herein, in Figure 1A-1J and Figure 2 In the discussion, block 215 forming the TMV interconnect structure and block 240 of TMV molding erosion can be skipped. An example is... Figures 4A-4D Provided. As in Figure 4A As shown, relative to block 215 and Figure 1B It did not form a TMV interconnect structure 121. As in... Figure 4B As shown, relative to block 230 and Figure 1C The molding material 130 does not cover the interconnect structure.

[0158] Continuing the comparison, as explained herein, the molding grinding (or thinning) of block 235 can be performed to a range from one or more of the tips of the grains 125, 126 exposed from the molding material 130. Figure 4C This is an icon that provides an example of this type of processing. Generally speaking, Figure 4C Component 400C is similar to Figure 1JThe component 100J is then subtracted from the interconnect structure 121 and the etched through-holes that expose the interconnect structure through the molding material 130.

[0159] Similarly, as explained here, the molding grinding (or thinning) in block 235 can be skipped or performed to a extent that the tops of the grains 125, 126 are covered with molding material 130. Figure 4D This is an icon that provides an example of this type of processing. Generally speaking, Figure 4D The 400D component is similar to Figure 1J The component 100J, minus the interconnect structure 121 and the etched through-holes through the molding material 130 to expose the interconnect structure, wherein the molding material 130 covers the grains 125, 126.

[0160] In another example, as explained here, in the discussion of block 215, these TMV interconnects may include any of a variety of structures, such as a conductive post (e.g., an electroplated post or column, a vertical wire, etc.). Figure 5A This is an illustration of an example of conductive posts 521 attached to the RD structure 110. These conductive posts 521 may, for example, be electroplated onto the RD structure 110. These conductive posts 521 may also include, for example, lines (e.g., wire-bonded lines) attached (e.g., wire-bonded attachments, soldering, etc.) to the RD structure 110 and extending vertically. These conductive posts 521 may extend from the RD structure 110 to a height greater than the height of grains 125, 126, equal to the height of one or more of grains 125, 126, less than the height of grains 125, 126, etc. In an exemplary embodiment, the posts may have a height greater than or equal to 200 micrometers and a center-to-center spacing of 100-150 micrometers. It is noted that any number of columns of posts 521 can be formed. Generally, Figure 5A The 500A component is similar to Figure 1B Component 100B, wherein conductive post 521 is used as an interconnect structure instead of conductive ball 121.

[0161] Continuing with this example, Figure 5B This describes the RD structure 110, conductive pillars 521, semiconductor chips 125 and 126, and primer filler 128 of the covered molding material 130. This molding can be performed, for example, according to block 230 of the method 200 of this example. Generally speaking, Figure 5B Component 500B is similar to Figure 1C Component 100C, wherein conductive post 521 is used as an interconnect structure instead of conductive ball 121.

[0162] Continuing with this example, Figure 5C This describes the molding material 130 being thinned (e.g., ground) to a desired thickness. This thinning can be performed, for example, according to block 235 of the method 200 of this example. For example, it is noted that the conductive pillars 521 and / or semiconductor grains 125, 126 can also be thinned. Generally speaking, Figure 5D The 500D component is similar to Figure 1D Component 100D, wherein the conductive post 521 serves as an interconnect structure, rather than the conductive ball 121, and also does not have Figure 1D The through-hole 140 is etched. For example, thinning of the molding material 130 may expose the top of the conductive pillar 521. However, if the thinning of the molding material 130 does not expose the top of the conductive pillar 521, a molding etch operation (e.g., according to block 240) may be performed. It should be noted that although the component is shown with the tops of the semiconductor dies 125, 126 exposed, these tops do not necessarily need to be exposed. For example, the pillars 521 may be higher than the semiconductor dies 125, 126. This exemplary configuration may, for example, allow the pillars 521 to be exposed and / or protrude from the molding material 130 while the molding material 130 continuously covers the back surface of the semiconductor dies 125, 126, which may, for example, provide protection to the semiconductor dies 125, 126, preventing or reducing warpage, etc.

[0163] In one embodiment where the pillars 521 are formed to have a height smaller than that of the grains 125, 126, the thinning may include first grinding the molding material 130, followed by grinding the back (or non-active) side of the molding material 130 and the grains 125, 126 until the pillars 521 are exposed. At this point, the thinning may be stopped or may continue, for example, by grinding the molding material 130, the grains 125, 126, and the pillars 521.

[0164] Continuing with this example, in Figure 5C The component 500C shown can be further processed by forming a redistribution layer (RDL) 532 on the molding material 130 and the grains 125, 126. Figure 5DThis is an example illustrating this process. The redistribution layer 532 may also be referred to herein as a backside redistribution (RDL) layer 532. Although the formation of this backside RDL is not explicitly shown in any block of method 200 of this example, this operation can be performed in any of these blocks, for example, after the molding and polishing operation of block 235 and before the wafer support attachment of block 245 (e.g., in block 235, in block 240, in block 245, or between any of these blocks).

[0165] As in Figure 5D As shown, a first back dielectric layer 533 can be formed and patterned on the molding material 130 and the dies 125, 126. The first back dielectric layer 533 can be formed and patterned, for example, in the same or similar manner as the first RDL dielectric layer 171 formed in block 260, although the first RDL dielectric layer 171 is on a different surface. For example, the first back dielectric layer 533 can be formed on the molding material 130 and on the semiconductor dies 125, 126 (e.g., directly above the exposed back surfaces of the dies 125, 126, on the molding material 130 covering the back surfaces of the dies 125, 126, etc.), and vias 534 can be formed in the first back dielectric layer 533 (e.g., by etching, stripping, etc.) to at least expose the tops of the conductive pillars 521. It should be noted that in an exemplary configuration in which the molding material 130 covers the back surface of the semiconductor dies 125, 126, the first back dielectric layer 533 may still be formed, but it is not necessary to do so (for example, the back line 535 discussed below may be formed directly on the molding material 130 instead of on the first back dielectric layer 533).

[0166] Backside traces 535 may be formed on the first backside dielectric layer 533 and in vias 534 of the first backside dielectric layer 533. These backside traces 535 can therefore be electrically connected to the conductive posts 521. These backside traces 535 may be formed, for example, in a manner similar to or the same as the first RDL traces formed in block 265. At least some (if not all) of these backside traces 535 may extend horizontally from the conductive posts 521 to a position directly above the semiconductor dies 125, 126. At least some of these backside traces 535 may also extend from the conductive posts 521 to a position not directly above the semiconductor dies 125, 126.

[0167] A second back dielectric layer 536 may be formed and patterned on the first back dielectric layer 533 and the back traces 535. The second back dielectric layer 536 may be formed and patterned, for example, in the same or similar manner as the second RDL dielectric layer 183 formed in block 270, although the second RDL dielectric layer 183 is on a different surface. For example, the second back dielectric layer 536 may be formed on the first back dielectric layer 533 and on the back traces 535, and vias 537 may be formed in the second back dielectric layer 536 (e.g., by etching, stripping, etc.) to expose the contact areas of the back traces 535.

[0168] Backside interconnect pads 538 (e.g., ball contact pads) may be formed on the second backside dielectric layer 536 and / or in vias 537 of the second backside dielectric layer 536. These backside interconnect pads 538 can thus be electrically connected to the backside lines 535. These backside interconnect pads 538 may be formed, for example, in the same or similar manner as the second RDL lines formed in block 275. These backside interconnect pads 538 may be formed, for example, by forming metal contact pads and / or forming bump bottom metallization (e.g., to reinforce subsequent attachment to the backside lines 535 via the interconnect structure).

[0169] Although the back RDL layer 532 is shown as having two back dielectric layers 533, 536 and one back line 535, it should be understood that any number of dielectric layers and / or line layers can be formed.

[0170] For example, in Figure 5E As shown, after the back RDL layer 532 is formed, a wafer support structure 150 can be attached to the back RDL layer 532 (e.g., directly, using an intermediate adhesive layer, using vacuum force, etc.). The wafer support 150 can be attached, for example, in the same or similar manner as the wafer support 150 attached to block 245. Figure 5E This demonstrates the wafer support 150 in a manner similar to... Figure 1E The attachment method is such that it is attached to the RDL layer 532, but not to the molding layer 130 and the semiconductor chips 125, 126.

[0171] For example, in Figure 5F As depicted, the support layer 105 (in) Figure 5EAs shown, the wafer support 150 can be removed from the RD wafer, a front redistribution layer can be formed on a side of the RD structure 110 opposite to the dies 125, 126, an interconnect structure 192 can be formed, and the wafer support 150 can be removed.

[0172] For example, the support layer 105 can be used in conjunction with the relevant block 250 and Figure 1E-1F The same or similar methods discussed can be used for removal. For example, a positive redistribution layer can be removed using a method similar to that described in blocks 255-280. Figure 1G-1H The same or similar methods discussed herein can be used to form it. Furthermore, for example, the interconnect structure 192 can be formed using a method similar to that described in block 285 and... Figure 1I It can be formed in the same or similar manner as described above. For example, the wafer support 150 can be formed using a method similar to that described in the relevant block 290. Figure 1J The same or similar methods discussed were removed.

[0173] In another exemplary embodiment, a substrate (e.g., a multilayer substrate, a packaging substrate, etc.) may be attached to the semiconductor dies 125, 126, for example, in the relevant context. Figures 5A-5F The alternatives or additional ones to the backside RDL discussed. For example, as in Figure 6A As illustrated, interconnect structure 621 can be formed at a height that extends to the height of grains 125 and 126. It should be noted that this height is not necessarily present, for example, in a case where the back substrate has its own interconnect structure, or where additional interconnect structures are utilized in the context between these interconnect structures 621 and the back substrate. These interconnect structures 621 can, for example, be a type of interconnect structure used in the associated block 215 and... Figure 1B Attached in the same or similar manner as described.

[0174] Continuing with this example, as in Figure 6B As illustrated, component 600B can be molded, and if necessary, the molded product can be thinned. Such molding and / or thinning can, for example, be achieved using a method described in the relevant blocks 230 and 235. Figure 1C and 1D It shall be carried out in the same or similar manner as described herein.

[0175] As in Figure 6C As shown, a wafer support 150 can be attached, a support layer 105 can be removed, and a front-side RDL can be formed. For example, a wafer support 150 can be used with a method described in the relevant block 245 and Figure 1EAttached in the same or similar manner as described above. For example, support layer 105 can be attached in a manner consistent with that of the relevant block 250 and... Figure 1F The same or similar methods discussed above can be used for removal. For example, a positive RDL can be removed using a method similar to that described in blocks 255-280. Figure 1G-1H It is formed in the same or similar ways as described.

[0176] As in Figure 6D As illustrated, interconnect structure 192 can be attached, wafer support 150 can be removed, and back substrate 632 can be attached. For example, interconnect structure 192 can be used with a method described in relation to block 285 and... Figure 1I Attached in the same or similar manner as described herein. Again, for example, the wafer support 150 can be attached using a method similar to that described in the relevant block 290 and... Figure 1J The same or similar methods discussed herein may be used for removal. For example, the back substrate 632 may be electrically attached to the interconnect structure 621 and / or mechanically attached to the molding material 130 and / or the dies 125, 126. The back substrate 632 may be attached, for example, in wafer (or panel) form and / or in a single package form, and may be attached, for example, before or after dicing (e.g., as discussed in block 295).

[0177] exist Figure 1A-1J to Figure 7A-7LThe methods and components shown and discussed herein are merely non-limiting examples, presented to illustrate various features of the invention. This method and component may also share any or all of the features with the methods and components shown and discussed in the following co-filed U.S. patent applications: U.S. Patent Application Serial No. 13 / 753,120, filed January 29, 2013, entitled "Semiconductor Device and Method of Manufacturing a Semiconductor Device"; U.S. Patent Application Serial No. 13 / 863,457, filed April 16, 2013, entitled "Semiconductor Device and Method of Manufacturing the Thereof"; U.S. Patent Application Serial No. 14 / 083,779, filed November 19, 2013, entitled "Semiconductor Device with Through-Silicon Vias - Less Deep Well"; U.S. Patent Application Serial No. 14 / 218,265, filed March 18, 2014, entitled "Semiconductor Device and Method of Manufacturing the Thereof"; and U.S. Patent Application Serial No. 14 / 313,724, filed June 24, 2014, entitled "Semiconductor Device and Method of Manufacturing the Thereof". U.S. Patent Application Serial No. 14 / 444,450, filed July 28, 2014, entitled "Semiconductor Device Having a Thin Redistribution Layer"; U.S. Patent Application Serial No. 14 / 524,443, filed October 27, 2014, entitled "Semiconductor Device Having Reduced Thickness"; U.S. Patent Application Serial No. 14 / 532,532, filed November 4, 2014, entitled "Intermediate, Method of Manufacturing Thereof, Semiconductor Package Using Thereof, and Method for Manufacturing the Semiconductor Package"; U.S. Patent Application Serial No. 14 / 546,484, filed November 18, 2014, entitled "Semiconductor Device Having Reduced Warpage"; and U.S. Patent Application Serial No. 14 / 671,095, filed March 27, 2015, entitled "Semiconductor Device and Method of Manufacturing Thereof"; the contents of each of these U.S. patent applications are incorporated herein by reference in their entirety.

[0178] It should be noted that any or all of the semiconductor packages discussed herein may (but are not necessarily) be attached to a package substrate. Various non-limiting examples of such semiconductor device packages and methods of manufacturing them will now be discussed.

[0179] Figure 7A-7L This is a cross-sectional view illustrating an exemplary semiconductor package and an exemplary method of manufacturing a semiconductor package, depicting various features according to the present invention. Figure 7A-7L The structures shown in the example can be combined with those in Figure 1A-1JSimilar structures shown in 3A-3B, 4A-4D, 5A-5F, 6A-6D, 9, 10A-10B, 11A-11D, 12A-12B, 13 and 14 share any or all of the features. Figure 8 This is a flowchart of an exemplary method 800 for manufacturing a semiconductor package according to various features of the present invention. This exemplary method 800 can, for example, be used in... Figure 2 Method 200, as described herein and discussed in the examples, shares any or all of the features with any method discussed herein. Figure 7A-7L For example, it can be depicted in Figure 8 Examples of semiconductor packaging manufacturing methods 800, including various steps (or blocks). Figure 7A-7L as well as Figure 8 We will now discuss them together.

[0180] The method 800 of this example, in block 805, may include preparing a logic wafer for processing (e.g., for packaging). Block 805 may include preparing a logic wafer for processing in any of a variety of ways, non-limiting examples of which are shown herein. Block 805 may, for example, be combined with... Figure 2 Block 205 of method 200 shown and discussed herein shares any or all of the features.

[0181] The method 800 of this example, in block 810, may include the fabrication of a redistributed structure wafer (RD wafer). Block 810 may include fabricating an RD wafer for processing using any of various methods, non-limiting examples of which are provided herein. Block 810 may, for example, be combined with... Figure 2 Block 210 of method 200 shown and in the examples discussed herein share any or all of the features.

[0182] Figure 7A This is an example icon providing various features of block 810. (See reference...) Figure 7A The RD wafer 700A may include, for example, a support layer 705 (e.g., a silicon layer). A redistribution (RD) structure 710 may be formed on the support layer 705. The RD structure 710 may include, for example, a substrate dielectric layer 711, a first dielectric layer 713, a first conductive line 712, a second dielectric layer 716, a second conductive line 715, and an interconnect structure 717.

[0183] The substrate dielectric layer 711 may, for example, be on the support layer 705. The substrate dielectric layer 711 may, for example, include an oxide layer, a nitride layer, etc. The substrate dielectric layer 711 may, for example, be formed according to specifications, and / or may be natural.

[0184] The RD wafer 700A may, for example, include a first conductive line 712 and a first dielectric layer 713. The first conductive line 712 may, for example, include a deposited conductive metal (e.g., copper, etc.). The first dielectric layer 713 may, for example, include an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In an alternative embodiment, the first dielectric layer 713 may include an organic dielectric material.

[0185] The RD wafer 700A may, for example, include a second conductive line 715 and a second dielectric layer 716. The second conductive line 715 may, for example, include a deposited conductive metal (e.g., copper, etc.). The second conductive line 715 may, for example, be connected to a separate first conductive line 712 through a separate conductive via 714 (e.g., in the first dielectric layer 713). The second dielectric layer 716 may, for example, include an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In an alternative embodiment, the second dielectric layer 716 may include an organic dielectric material.

[0186] Although the two sets of dielectric layers and conductive lines are depicted in Figure 7A However, it should be understood that the RD structure 710 of the RD wafer 700A may include any number of such layers and lines. For example, the RD structure 710 may include only one dielectric layer and / or one set of conductive lines, three sets of dielectric layers and / or conductive lines, etc.

[0187] Similar to the logic wafer fabrication in block 805, block 810 may include interconnect structures (e.g., conductive bumps, conductive balls, conductive pillars, conductive planes or pads, etc.) formed on one surface of the RD structure 710. An example of such an interconnect structure 717 is shown in... Figure 7A In this embodiment, the RD structure 710 includes an interconnect structure 717, which is shown to be formed on the front (or top) side of the RD structure 710 and electrically connected to individual second conductive lines 715 through conductive vias in the second dielectric layer 716. Such an interconnect structure 717 can be used, for example, to couple the RD structure 710 to various electronic components (e.g., active semiconductor components or chips, passive components, etc.).

[0188] These interconnect structures 717 may include, for example, any of a variety of conductive materials (e.g., any one or a combination of copper, nickel, gold, etc.). These interconnect structures 717 may also include, for example, solder.

[0189] Generally, block 810 may include the fabrication of a redistributed structure wafer (RD wafer). Therefore, the scope of this invention should not be limited to the features of any particular method of performing such fabrication.

[0190] The method 800 of this example may include attaching one or more semiconductor dies to the RD structure (e.g., the RD structure of the RD wafer) in block 820. Block 820 may include attaching the dies to the RD structure in any of a variety of ways, non-limiting examples of which are provided herein. Block 820 may, for example, be in... Figure 2 Block 220 of method 200 shown and discussed herein shares any or all of the features.

[0191] Figure 7B This is an illustration of an example of various features of block 820 (e.g., the die attachment). For example, a first die 725 (e.g., which may have been diced from a logic wafer prepared in block 805) is electrically and mechanically attached to the redistribution structure 710. Similarly, a second die 726 (e.g., which may have been diced from a logic wafer prepared in block 805) is electrically and mechanically attached to the redistribution structure 710.

[0192] The first die 725 and the second die 726 may include any of a variety of die features. In one example scenario, the first die 725 may include a processor die, and the second die 726 may include a memory die. In another example scenario, the first die 725 may include a processor die, and the second die 726 may include a coprocessor die. In yet another example scenario, the first die 725 may include a sensor die, and the second die 726 may include a sensor processing die. Although in Figure 7B The component 700B is shown to have two dies 725 and 726, but it can have any number of dies. For example, it can have only one die, three dies, four dies, or more than four dies.

[0193] Furthermore, although the first die 725 and the second die 726 are shown attached laterally to the redistribution structure 710 relative to each other, they can also be arranged in a vertical assembly. Various non-limiting examples of such an assembly are shown and discussed herein (e.g., die stacking on dies, dies attached to opposite substrate sides, etc.). Moreover, although the first die 725 and the second die 726 are shown to have substantially similar dimensions, such dies 725, 726 may include different individual features (e.g., die height, coverage area, interconnection spacing, etc.).

[0194] The first die 725 and the second die 726 are depicted as having a generally uniform pitch, but this is not necessarily the case. For example, most or all of the contacts of the first die 725 in a region of the first die coverage area adjacent to the second die 726 and / or most of the contacts of the second die 726 in a region of the second die coverage area adjacent to the first die 725 may have a substantially finer pitch than most or all of the other contacts. For example, the first 5, 10, or n columns of contacts of the first die 725 closest to the second die 726 (and / or the second die 726 closest to the first die 725) may have a pitch of 30 micrometers, while other contacts may have a pitch of approximately 80 micrometers and / or 200 micrometers. The RD structure 710 can therefore have corresponding contact structures and / or circuitry at these corresponding pitches.

[0195] Generally, block 820 includes attaching one or more semiconductor dies to the redistribution structure (e.g., a redistribution structure of a redistribution wafer). Therefore, the scope of this invention should not be limited to the characteristics of any particular die, or to the characteristics of any particular arrangement of the polydies, or to the characteristics of any particular manner in which such dies are attached, etc.

[0196] The method 800 of this example in block 825 may include underfilling the semiconductor die and / or other components attached to the RD structure in block 820. Block 825 may include performing such underfilling in any of a variety of ways, of which non-limiting examples are shown herein. Block 825 may, for example, be combined with... Figure 2 Block 225 of method 200 shown and discussed herein shares any or all of the features.

[0197] Figure 7B This is an icon illustrating an example of various features of block 825 (e.g., the underfill). The underfill 728 is disposed between the first semiconductor die 725 and the redistribution structure 710, and between the second semiconductor die 726 and the redistribution structure 710.

[0198] Although the underfill 728 is generally depicted as flat, it may be raised and form rounded corners on the sides of the semiconductor dies and / or other components. In one example, at least one-quarter or at least half of the die side surfaces may be covered by the underfill material. In another example, one or more or all of the entire side surfaces may be covered by the underfill material. Similarly, for example, a substantial portion of the space directly between the semiconductor dies, between the semiconductor dies and other components, and / or between other components may be filled with the underfill material. For example, at least half or all of the space between laterally adjacent semiconductor dies, between the semiconductor dies and other components, and / or between other components may be filled with the underfill material. In one example embodiment, the underfill 728 may cover the entire redistribution structure 710 of the RD wafer. In this example embodiment, when the RD wafer is subsequently diced, such dicing may also cut through the underfill 728.

[0199] Generally, block 825 may include an underfill material attached to the semiconductor die and / or other components of the RD structure in block 820. Therefore, the scope of this invention should not be limited to any particular type of underfill material or any particular manner in which such underfill material is performed.

[0200] The method 800 of this example may include molding the RD wafer (or RD structure) in block 830. Block 830 may include molding the RD wafer in any of a variety of ways, non-limiting examples of which are shown herein. Block 830 may, for example, be combined with... Figure 2 Block 230 of method 200 shown and discussed herein shares any or all of the features.

[0201] Figure 7C This is an illustration illustrating an example of various features (e.g., molding features) of block 830. For example, the molding assembly 700C is shown where the molding material 730 covers the first semiconductor die 725, the second semiconductor die 726, the underfill 728, and the top surface of the redistribution structure 710. Although the molding material 730 (which may also be referred to herein as encapsulating material) is shown to completely cover the sides and tops of the first semiconductor die 725 and the second semiconductor die 726, this is not necessary. For example, block 830 may include molding techniques utilizing a film-assisted or die-sealing method to keep the tops of the dies free of molding material.

[0202] Generally, the molding material 730 can, for example, directly contact and cover the portions of the grains 725, 726 that are not covered by the primer filler 728. For example, in a scenario where at least a first portion of the sides of the grains 725, 726 is covered by the primer filler 728, the molding material 730 can directly contact and cover a second portion of the sides of the grains 725, 726. The molding material 730 can also, for example, fill the space between the grains 725, 726 (e.g., at least a portion of the space not yet filled by the primer filler 728).

[0203] Generally, block 830 may include molding the RD wafer. Therefore, the scope of this invention should not be limited to the characteristics of any particular molding material, structure, and / or technology.

[0204] The method 800 of this example may include grinding (or thinning) the molding material applied in block 835. Block 835 may include grinding (or thinning) the molding material in any of a variety of ways, non-limiting examples of which are shown herein. Block 835 may, for example, be combined with... Figure 2 Block 235 of method 200 shown and discussed herein shares any or all of the features.

[0205] Figure 7D This is an icon that provides an example of the various features of block 835 (e.g., the molding and grinding features). Component 700D is depicted as the molding material 730 (e.g., relative to...). Figure 7C The molded material 730 is thinned to expose the top surfaces of the grains 725 and 726. In this example, the grains 725 and 726 may also have been ground (or thinned).

[0206] As explained herein, the molding material 730 can be retained in an overmolded assembly to cover the grains 725, 726. For example, the molding material 730 may be unpolished, or the molding material 730 may be polished, but not to a height that exposes the grains 725, 726.

[0207] Generally, block 835 may include grinding (or thinning) the molding material applied to block 830. Therefore, the scope of this invention should not be limited to any particular amount or type of grinding (or thinning).

[0208] The method 800 of this example, in block 845, may include attaching the molded RD wafer (e.g., its top or molded side) to a wafer support structure. Block 845 may include attaching the molded RD wafer to the wafer support structure in any of various manners, non-limiting examples of which are provided herein. Block 845 may, for example, be consistent with... Figure 2 Block 245 of method 200 shown and discussed herein shares any or all of the features.

[0209] Figure 7E This is an illustration of an example of various features of block 845 (e.g., the feature of wafer support attachment). The wafer support structure 750 is attached to the molding material 730 and the top sides of the dies 725, 726. The wafer support structure 750 may be attached, for example, using an adhesive. It is noted that in an assembly in which the tops of the dies 725, 726 are covered by the molding material 730, the wafer support structure 750 may only be directly coupled to the top of the molding material 730.

[0210] Generally, block 845 may include attaching the molded RD wafer (e.g., its top or molded side) to a wafer support structure. Therefore, the scope of this invention should not be limited to the characteristics of any particular type of wafer support structure, or to the characteristics of any particular manner of attaching a wafer support structure.

[0211] The method 200 of this example, in block 850, may include removing a support layer from the RD wafer. Block 850 may include removing the support layer in any of a variety of ways, of which non-limiting examples are shown herein. Block 850 may, for example, be combined with... Figure 2 Blocks 250 of method 200 shown and in the examples discussed herein share any or all of the features.

[0212] As discussed herein, the RD wafer may include a support layer on which an RD structure is formed and / or supported. The support layer may, for example, include a semiconductor material (e.g., silicon). In an exemplary scenario where the support layer comprises a silicon wafer layer, block 850 may include removing the silicon (e.g., removing all of the silicon from the RD wafer, removing almost all (e.g., at least 90% or 95%) of the silicon from the RD wafer, etc.). For example, block 850 may include mechanically grinding almost all of the silicon, followed by a dry or wet chemical etching to remove the remainder (or almost all of the remainder). In an exemplary scenario where the support layer is loosely attached to the RD structure formed (or supported) thereon, block 850 may include pulling or peeling to separate the support layer from the RD structure.

[0213] Figure 7F This is an icon that provides an example of various features of block 850 (e.g., the support layer removal feature). For example, the support layer 705 (in...) Figure 7E The RD structure 710 shown is removed from the RD structure 710. In the illustrative example, the RD structure 710 may still include a substrate dielectric layer 711 (e.g., an oxide, nitride, etc.) as discussed herein.

[0214] Generally, block 850 may include the removal of a support layer from the RD wafer. Therefore, the scope of this invention should not be limited to the characteristics of any particular type of wafer material or to the characteristics of any particular method of wafer material removal.

[0215] The method 800 of this example may include forming and patterning a redistribution layer (RDL) dielectric layer in block 855 for etching an oxide layer of the RD structure. Block 855 may include forming and patterning the RDL dielectric layer in any of various ways, non-limiting examples of which are shown herein. Block 855 may, for example, be combined with... Figure 2 Block 255 of method 200 shown and discussed herein shares any or all of the features.

[0216] Figure 7G This is an example icon illustrating various features of block 855. For example, the RDL dielectric layer 771 is formed and patterned on the substrate dielectric layer 711. The patterned RDL dielectric layer 771 may include, for example, vias 772 through the RDL dielectric layer 771, through which the substrate dielectric layer 711 may be etched (e.g., in block 860), and conductive lines (or portions thereof) may be formed (e.g., in block 865) in the vias 772.

[0217] Generally, block 855 may include, for example, forming and patterning a dielectric layer (e.g., an RDL dielectric layer) on the substrate dielectric layer. Therefore, the scope of this invention should not be limited to the characteristics of a particular dielectric layer or to the characteristics of a particular manner in which a dielectric layer is formed.

[0218] The method 800 of this example, in block 860, may include etching the substrate dielectric layer (e.g., oxide layer, nitride layer, etc.) from the RD structure, such as the unshielded portion thereof. Block 860 may include performing the etching in any of a variety of ways, of which non-limiting examples are shown herein. Block 860 may, for example, be combined with... Figure 2 Block 260 of method 200 shown and discussed herein shares any or all of the features.

[0219] Figure 7G This is an icon illustrating various features of block 860. For example, the substrate dielectric layer 711 is shown in... Figure 7F The portion below the first conductive line 712 in the middle is from Figure 7G Removed. For example, this enables metal-to-metal contact between the first conductive lines 712 and the RDL lines formed in block 865.

[0220] Generally, block 860 may include, for example, etching the substrate dielectric layer. Therefore, the scope of this invention should not be limited to any particular method of performing such etching.

[0221] The method 800 of this example in block 865 may include forming a redistribution layer (RDL) line. Block 865 may include forming the RDL line in any of a variety of ways, of which non-limiting examples are shown herein. Block 865 may, for example, be combined with... Figure 2 Block 265 of method 200 shown and discussed herein shares any or all of the features.

[0222] Figure 7G and 7H This is an illustration of an example of various features of block 865 (e.g., features of RDL line formation). For example, a first portion 781 of these RDL lines may be formed in a via 772 of the RDL dielectric layer 771 and contact the first conductive line 712 exposed by this via 772 of the RD structure 710. Similarly, for example, a second portion 782 of the first RDL line may be formed on the first RDL dielectric layer 771.

[0223] Generally, block 865 may include a redistribution layer (RDL) circuit. Therefore, the scope of this invention should not be limited to the characteristics of any particular RDL circuit or to the characteristics of any particular manner in which such an RDL circuit is formed.

[0224] It should be noted that although the method 800 of this example only shows an RDL dielectric layer at block 855 and only shows an RDL line at block 865, such blocks can be repeated as desired.

[0225] Method 800 of this example allows block 885 to form an interconnect structure on the RDL line. Block 885 can include any of a variety of methods for forming these interconnect structures, non-limiting examples of which are shown herein. For example, block 885 can be connected to... Figure 2Block 285 of method 200 shown and discussed herein shares any or all of the features.

[0226] Block 885 may, for example, form conductive pillars (e.g., metal pillars, copper pillars, solder-capped pillars, etc.) and / or conductive bumps (e.g., solder, etc.) on the RDL line. For example, block 885 may include electroplating conductive pillars, setting or coating conductive bumps, etc.

[0227] Figure 7I This is an icon that provides an example of various features of block 885 (e.g., the feature of bump formation). For example, interconnect structure 792 (e.g., which is shown as a solder-capped pillar, such as a copper pillar) is attached to these RDL lines 782.

[0228] Although the redistribution layer formed in blocks 855-885 (which can also be called the positive redistribution layer (RDL)) Figure 7A-7L The interconnects are generally depicted as fan-in components (e.g., generally contained within the coverage areas of dies 725, 726), but they can also be formed as fan-out components, for example, in which at least a portion of the interconnect structure 792 extends generally beyond the coverage areas of dies 725, 726. Non-limiting examples of such components are shown herein.

[0229] Generally, block 885 may include, for example, interconnect structures formed on the RDL lines and / or on the RDL dielectric layer. Therefore, the scope of this invention should not be limited to the characteristics of any particular interconnect structure or to any particular manner in which the interconnect structure is formed.

[0230] The method 800 of this example may include debonding (or separating) the wafer support attached to block 845 in block 890. Block 890 may include performing such debonding in any of a variety of ways, the non-limiting nature of which is shown herein. For example, block 890 may be combined with... Figure 2 Block 290 of method 200 shown and discussed herein shares any or all of the features.

[0231] Figure 7H and 7I This is an example icon that provides various features of block 890. For example, in Figure 7H The wafer support 750 depicted in the image is... Figure 7I It was removed from the text.

[0232] Generally, block 890 may include debonding the wafer support. Therefore, the scope of this invention should not be limited to the characteristics of any particular type of wafer support, or to any particular manner of debonding a wafer support.

[0233] The method 800 of this example, in block 895, may include dicing the wafer. Block 895 may include dicing the wafer in any of a variety of ways, of which non-limiting examples are shown herein. Block 895 may, for example, be used in... Figure 2 Block 295 of method 200, as shown and discussed herein, shares any or all of the features.

[0234] The discussion here has largely focused on the processing of a single die on the RD wafer. This focus on a single die on the RD wafer is merely for illustrative purposes. It should be understood that all process steps (or blocks) discussed here can be performed on an entire wafer. For example, in Figure 7A-7L Each of the illustrations presented in the other figures herein can be replicated dozens or hundreds of times on a single wafer. For example, before dicing, one component of the illustrated device assembly on the wafer may be inseparable from an adjacent device assembly.

[0235] Block 895 may, for example, include individual packages cut from the wafer (e.g., mechanical punching, mechanical sawing, laser cutting, flexible beam cutting, plasma cutting, etc.). The final result of such cutting may be, for example, in... Figure 7I The package shown is an example of a package where the cut can form a side surface that is a coplanar side surface comprising a plurality of components of the package. For example, any or all of the side surfaces of the molding material 730, the dielectric layer of the RD structure 710, the RDL dielectric layer 771, the underfill filler 728, etc., may be coplanar.

[0236] Generally, block 895 may include dicing the wafer. Therefore, the scope of this invention should not be limited to the characteristics of any particular method of dicing a wafer.

[0237] The method 800 of this example, in block 896, may include fabricating a substrate, or a wafer or panel thereof, for attachment of the component 700I to it. Block 896 may include fabricating a substrate in any of various ways, non-limiting examples of which are shown herein. Block 896 may, for example, be combined with... Figure 2 Blocks 205 and 210 of method 200 shown and in the examples discussed herein share any or all of the features.

[0238] The substrate may include features of any of various substrates. For example, the substrate may include a packaging substrate, a motherboard substrate, a multilayer substrate, a molded substrate, a semiconductor substrate, a glass substrate, etc. Block 896 may include, for example, preparing the front and / or back surfaces of the substrate for electrical and / or mechanical attachment. Block 896 may, for example, allow a panel substrate to remain in panel form and subsequently cut into individual packages, or allow individual substrates to be cut from a panel at this stage.

[0239] Block 896 may also include receiving the substrate from a manufacturing station adjacent to or upstream of one of the manufacturing facilities, from another geographical location, etc. The received substrate may be, for example, already prepared, or additional preparation steps may be performed.

[0240] Figure 7J This is an icon illustrating an example of the various features provided by block 896. For example, component 700J includes a substrate 793 prepared for attachment.

[0241] Generally, block 896 may include the fabrication of a substrate, or a wafer or panel thereof, for attachment of the component 700I to it. Therefore, the scope of the various features of this invention should not be limited to the characteristics of a particular substrate or to any particular manner of fabricating a substrate.

[0242] The method 800 of this example may include attaching a component to the substrate in block 897. Block 897 may include attaching a component in any of a variety of ways (e.g., a component in...). Figure 7I The exemplified component 700I (or other components) is presented herein as a non-limiting example. Block 897, for example, can be combined with... Figure 2 Block 220 of method 200 shown and discussed herein shares any or all of the features.

[0243] The component may include any of the features of various components, non-limiting examples of which are presented herein, for example, in all the figures and / or in the related discussion. Block 897 may include attaching the component in any of a variety of ways. For example, block 897 may include attaching the component to the substrate using batch reflow soldering, thermocompression bonding (TCB), conductive epoxy resin, etc.

[0244] Figure 7J This is an icon that provides an example of the various features of block 897 (such as component attachment features). For example, in Figure 7I The component 700I shown is attached to the substrate 793.

[0245] Although not displayed Figure 7J In various exemplary implementations (e.g., as in...), Figure 7K and 7L As shown in the diagram, an interconnect structure, such as a through-hole interconnect structure, can be formed on the substrate 793. In this exemplary embodiment, block 897 can be connected to... Figure 2 Block 215 of method 200 shown and discussed herein shares any or all of the features, although relating to the formation of these interconnect structures on the substrate 793. It should be noted that such interconnect structures may be performed before or after the component is attached, or may be performed before or after the underfill of block 898.

[0246] Generally speaking, block 897 includes attaching a component to the substrate. Therefore, the scope of this invention should not be limited to any particular component, substrate, or the characteristics of the manner in which a component is attached to a substrate.

[0247] The method 800 of this example may include, in block 898, an assembly with an adhesive filler on the substrate. Block 898 may include any of various types of adhesive filler, of which non-limiting examples are shown herein. Block 898 may, for example, be combined with block 825 and / or... Figure 2 Block 225 of method 200 shown and discussed herein shares any or all of the features.

[0248] For example, after the component is attached in block 897, block 898 may include underfilling the attached component with a capillary underfill. For example, the underfill may include a sufficiently viscous, reinforced polymeric material to flow between the component and the substrate in a capillary action.

[0249] Similarly, for example, block 897 may include filling the semiconductor die with a non-conductive paste (NCP) and / or a non-conductive film (NCF) or tape as the component is being attached (e.g., using a thermosetting bonding process). For example, such a primer filling material may be deposited (e.g., printed, sprayed, etc.) before the component is attached.

[0250] As with all the blocks depicted in method 800 of this example, block 898 can be executed at any point in the process of method 800, provided that the space between the component and the substrate is accessible.

[0251] The underfill can also occur at different sections of method 800 in this example. For example, the underfill can be performed on a portion of the substrate molding section 899 (e.g., using a molding underfill).

[0252] Figure 7K This is an icon illustrating an example of the various features of block 898 (e.g., the underfill feature). The underfill 794 is disposed between the component 700I and the substrate 793.

[0253] Although the underfill 794 is depicted as generally flat, it may be raised and form rounded corners on the sides of the component 700I and / or other components. In one example scenario, at least one-quarter or at least half of the side surface of the component 700I may be covered with the underfill material. In another example scenario, one or more or all of the entire side surface of the component 700I may be covered with the underfill material. Similarly, for example, a substantial portion of the space directly between the component 700I and other components, and / or between other components (shown in the various figures) may be filled with the underfill material 794. For example, at least half or all of the space between the component 700I and a laterally adjacent component may be filled with the underfill material.

[0254] As in Figure 7J As shown, the component 700J may include a first primer filler 728 between the dies 725, 726 and the RD structure 710, and a second primer filler 794 between the RD structure 710 and the substrate 793. These primer fillers 728 and 794 may be different, for example. For instance, in an exemplary scenario where the distance between the dies 725, 726 and the RD structure 710 is less than the distance between the RD structure 710 and the substrate 793, the first primer filler 728 may comprise a substantially smaller filler size (or have a higher viscosity) compared to the second primer filler 794. In other words, the second primer filler 794 may be less expensive than the first primer filler 728.

[0255] Furthermore, the individual primer filling processes performed in blocks 898 and 825 can be different. For example, block 825 may include a capillary primer filling process, while block 898 may include a non-conductive paste (NCP) primer filling process.

[0256] In another example, blocks 825 and 898 may be performed simultaneously in the same underfill process, for example, after block 897. Furthermore, as discussed herein, a molded underfill may also be used. In this example scenario, block 899 may include performing underfill of any or both of blocks 825 and / or 898 during the substrate molding process. For example, block 825 may include performing a capillary underfill, while block 898 is performed as a molded underfill process in block 899.

[0257] Generally, block 898 may include components and / or other elements for which the primer is applied to the substrate in block 897. Therefore, the scope of this invention should not be limited to any particular type of primer application or any particular method of performing primer application.

[0258] The method 800 of this example may include molding the substrate in block 899. Block 899 may include performing such molding in any of a variety of ways, non-limiting examples of which are shown herein. Block 899 may, for example, be combined with block 830 and / or Figure 2 Block 230 of method 200 shown and discussed herein shares any or all of the features.

[0259] For example, block 899 may include being molded on the top surface of the substrate, on the components attached to block 897, on the TMV interconnect structure (if it is formed on the substrate, such as a conductive ball, ellipsoid, pillar or column (e.g., an electroplated pillar, line or bonding line, etc.)).

[0260] Block 899 may include, for example, transfer molding, compression molding, etc. Block 899 may include, for example, a panel molding process in which multiple substrates are connected in a panel and molded together, or Block 899 may include individually molding the substrates. In a panel molding process, after the panel is molded, Block 899 may include performing a separation process in which the individual substrates are separated from the substrate panel.

[0261] The molding material may include any of a variety of characteristics. For example, the molding material (e.g., epoxy molding compound (EMC), epoxy resin molding compound, etc.) may include a relatively high modulus, for example, to provide encapsulation support in a subsequent process. Similarly, the molding material may include a relatively low modulus to provide encapsulation flexibility in a subsequent process.

[0262] Block 899 may, for example, include using a molding material that is different from the molding material used in block 830. For example, block 899 may use a molding material having a lower modulus than the molding material used in block 830. In this scenario, the central region of the component may be relatively rigid compared to the peripheral region of the component, which provides absorption of various forces in the stronger region of the component.

[0263] In an exemplary scenario where the molding material 735 of component 700K and the molding material 730 of component 700I are different and / or formed at different stages and / or formed using different types of processes, block 899 (or another block) may include preparing the molding material 730 for adhesion to the molding material 735. For example, the molding material 730 may be physically or chemically etched. The molding material 730 may, for example, be plasma etched. Similarly, trenches, notches, protrusions, or other physical features may be formed on the molding material 730. As another example, an adhesive may be applied to the molding material 730.

[0264] Block 899 may, for example, utilize a molding process of a different type than that used in block 830. In one example scenario, block 830 may utilize a compression molding process, while block 899 utilizes a transfer molding process. In this example scenario, block 830 may utilize a molding material specifically adapted to compression molding, and block 899 may utilize a molding material specifically adapted to transfer molding. Such molding materials may, for example, have significantly different material characteristics (e.g., flow characteristics, curing characteristics, hardness characteristics, particle size characteristics, chemical compound characteristics, etc.).

[0265] As explained herein, for example, regarding block 898, the molding process of block 899 can provide underfill between the component 700I and the substrate 793, and / or can provide underfill between the dies 725, 726 and the RD structure 710. In this example, there can be material uniformity between the molding underfill material and the molding materials of the encapsulating substrate 793 and component 700I and / or the molding materials of the encapsulating RD structure 710 and semiconductor dies 725, 726.

[0266] Figure 7KThis is an icon illustrating an example of the various features of block 899 (e.g., these molding features). For example, the molded component 700K is shown where the molding material 735 covers the interconnect structure 795 and component 700I. Although the molding material 735 (which may also be referred to herein as encapsulating material) is shown to expose the top of component 700I, this is not necessary. For example, block 899 could completely cover component 700I, and a subsequent thinning (or polishing) operation to expose the top of component 700I is not required.

[0267] Generally, the molding material 735 can, for example, directly contact and cover the portion of component 700I not covered by the primer filler 794. For example, in a scenario where at least a first portion of the side of component 700I is covered by the primer filler 794, the molding material 735 can directly contact and cover a second portion of the side of component 700I. Furthermore, the molding material 735 can extend laterally to the edge of the substrate 793, thus forming a side surface coplanar with the substrate 793. Such a component can, for example, be formed using panel molding, followed by individual encapsulation from the panel.

[0268] Generally, block 899 may include molding the substrate. Therefore, the scope of this invention should not be limited to the characteristics of any particular molding material, structure, and / or technique.

[0269] The method 800 of this example may include forming interconnect structures on the substrate in block 886, for example, on the side of the substrate opposite to the side to which the component is attached in block 897. These interconnect structures may include features of any of various types of interconnect structures, such as structures that can be used to connect a semiconductor package to another package or a motherboard. For example, these interconnect structures may include conductive balls (e.g., solder balls) or bumps, conductive pillars, etc.

[0270] Figure 7K The icon is an example of providing various features of block 886 (e.g., the features that form interconnects). For example, the interconnect structure 792 is depicted as a plane 791 attached to the substrate 793.

[0271] Generally, block 886 may include an interconnect structure formed on the substrate. Therefore, the scope of this invention should not be limited to the characteristics of a particular interconnect structure or to any particular manner in which such a structure is formed.

[0272] As discussed herein, the underfill 728 may cover at least a portion of the sides of the grains 725, 726, and / or the underfill 794 may cover at least a portion of the sides of the component 700I. Figure 7L This is an illustrative example of providing such coverage. For example, component 700I is shown in which the underfill 728 is part of the side of the contact grains 725, 726. As discussed herein, the underfill 728 can also be cut during a cutting process, resulting in component 700I comprising a flat side surface that includes one side surface of the RD structure 710, one side surface of the molding material 730, and one side surface of the underfill 728.

[0273] The component 700L (which may also be referred to as a package) is shown as having a base filler 794 contacting a portion of the side of the component 700I (e.g., the side of the RD structure 710, the side of the base filler 728, and the side of the molding material 730). It should be noted that, as discussed herein, in various exemplary embodiments, the base filler 794 may include a molded base filler of the same material as the molding material 735. The molding material 735 is shown as encapsulating the substrate 793, interconnect structure 795, base filler 794, and component 700I. Although in the illustration of this example, the tops of component 700I and interconnect structure 795 are exposed from the molding material 735, this is not necessarily the case.

[0274] Figure 7A-7L and Figure 8 This presents the methodological characteristics of various paradigms and their variations. The methodological characteristics of other paradigms will now be presented with reference to additional diagrams.

[0275] As discussed here, in Figure 7A-7L and Figure 8 In the discussion, block 835 may include grinding (or thinning) the molding material 730 to expose one or more of the grains 725, 726. An example is provided in Figure 7D.

[0276] As discussed, molding and polishing (or thinning) of block 835 does not need to be performed, or can be performed to a extent that the tops of the grains 725 and 726 are still covered with molding material 730. An example is... Figure 9 It is provided in which the molding material 735 is the top of the grains 725, 726 covering the component 700I.

[0277] As discussed here, for example, it relates to block 897 and Figure 7K and 7LIn various exemplary embodiments, interconnect structures can be formed on this substrate. One example is... Figure 9 Provided. For example, although the tops of the grain interconnect structures 795 are initially covered by the molding material 735, the through holes 940 are etched in the molding material 735 to expose the interconnect structures 795.

[0278] Furthermore, as in this case Figure 7A-7L and Figure 8 As discussed in the previous discussion, in various exemplary implementations, the TMV interconnect structure does not need to be formed on the substrate. One example is... Figure 10A Provided. As in Figure 10A As shown, relative to Figure 7K It does not have a TMV interconnect structure 795 formed. Similarly, as in... Figure 10A As shown, relative to Figure 7K The molding material 735 does not cover the interconnect structure.

[0279] Similarly, as explained herein, the molding grinding (or thinning) in block 899 may be skipped or may be performed to the extent that the top of at least one of the components 700I and / or the grains 725, 726 is covered with molding material 735. Figure 10A This is an icon that provides an example of this type of processing. Generally speaking, Figure 10A Component 1000A is similar to Figure 7K The component 700K is subtracted from the interconnect structure 795, and the molding material 735 is used to cover the component 700I.

[0280] Furthermore, as explained herein, molding grinding (or thinning) in block 899 may be performed to the extent that the top of one or more of the components 700I and / or grains 725, 726 are exposed from the molding material 735 (and / or molding material 730). Figure 10B This is an icon providing an example of this processing. Generally speaking, component 1000B in Figure 10B is similar to... Figure 7K The components are 700K, minus the interconnect structure of 795.

[0281] In another example, as explained here, in the discussion of block 897, these TMV interconnects may include any of a variety of structures, such as a conductive pillar (e.g., an electroplated pillar or column, a vertical wire, etc.). Figure 11AThis is an illustration of an example of conductive posts 1121 attached to the substrate 793. These conductive posts 1121 may, for example, be electroplated onto the substrate 793. These conductive posts 1121 may also include, for example, wires (e.g., wire-bonded wires) attached (e.g., wire-jointed attachments, soldering, etc.) to the substrate 793 and extending vertically. These conductive posts 1121 may extend from the substrate 793 to a height greater than the height of the grains 725, 726, equal to the height of one or more of the grains 725, 726, less than the height of the grains 725, 726, etc. It should be noted that any number of posts 1121 can be formed. Generally speaking, Figure 11A Component 1100A is similar to Figure 7K The component 700K (minus the molding compound 735) has conductive pillars 1121 as interconnect structures, instead of elongated conductive balls 795.

[0282] Continuing with this example, Figure 11B This describes the substrate 793 covered by molding material 735, conductive pillars 1121, components 700I (e.g., semiconductor dies 725, 726), and primer filler 794. This molding can be performed, for example, according to block 899 of the method 800 of this example. Generally, Figure 11B Component 1100B is similar to Figure 7K The component 700K has conductive pillars 1121 as interconnect structures instead of elongated conductive balls 795, and has molding material 735 that has not been thinned or has not been thinned sufficiently to expose the component 700I.

[0283] Continuing with this example, Figure 11C This describes the molding material 735 being thinned (e.g., ground) to a desired thickness. This thinning can be performed, for example, according to block 899 of the method 800 of this example. For example, it is noted that the conductive pillars 1121 and / or components 700I (e.g., comprising molding material 730 and / or semiconductor dies 725, 726) can also be thinned. For example, thinning of the molding material 735 may expose the tips of the conductive pillars 1121. However, if thinning of the molding material 735 does not expose the tips of the conductive pillars 1121, a molding etch operation can be performed. It is noted that although component 1100C is shown as having exposed tips of the semiconductor dies 725, 726 of component 700I, these tips are not necessarily exposed.

[0284] Generally speaking, Figure 11C Component 1100C is similar to Figure 7KThe component 700K has conductive pillars 1121 as an interconnect structure, instead of elongated conductive balls 795.

[0285] Continuing with this example, in Figure 11C The component 1100C shown can be further processed by forming a redistribution layer (RDL) 1132 on the molding material 735 and the component 700I (e.g., including the molding material 730 and / or its semiconductor dies 725, 726). Figure 11D This is an example illustrating this process. The redistribution layer 1132 may also be referred to herein as the backside redistribution (RDL) layer 1132. Although the formation of this backside RDL is not explicitly shown in one of the blocks of method 800 in this example, this operation can be performed in any of those blocks, for example, after the molding and grinding operation in block 899 (if performed).

[0286] As in Figure 11D As shown, a first back dielectric layer 1133 can be formed and patterned on the molding material 735 and the component 700I (e.g., comprising the molding material 730 and / or its semiconductor dies 725, 726). The first back dielectric layer 1133 can be formed and patterned, for example, in the same or similar manner as the RDL dielectric layer 771 formed in block 855, although on a different surface. For example, the first back dielectric layer 1133 may be formed on the molding material 735 and / or on the component 700I (e.g., including the molding material 730 and / or its semiconductor dies 725, 726), for example, directly formed on the exposed back surface of the dies 725, 726, on the molding material 730 and / or 735 covering the back surface of the dies 725, 726, etc., and the through hole 1134 may be formed in the first back dielectric layer 1133 (e.g., by etching, stripping, etc.) to at least expose the top of the conductive post 1121.

[0287] Backside traces 1135 may be formed on the first backside dielectric layer 1133 and in vias 1134 of the first backside dielectric layer 1133. These backside traces 1135 can therefore be electrically connected to the conductive posts 1121. These backside traces 1135 may be formed, for example, in the same or similar manner as the RDL traces 782 formed in block 865. At least some (if not all) of these backside traces 1135 may extend from the conductive posts 1121 to a position directly above the component 700I (e.g., containing the molding material 730 and / or its semiconductor dies 725, 726). At least some of these backside traces 1135 may also extend from the conductive posts 1121 to a position not directly above the component 700I (e.g., containing the molding material 730 and / or its semiconductor dies 725, 726).

[0288] A second back dielectric layer 1136 may be formed and patterned on the first back dielectric layer 1133 and the back traces 1135. The second back dielectric layer 1136 may be formed and patterned, for example, in the same or similar manner as the RDL dielectric layer 771 formed in block 855, although on a different surface. For example, the second back dielectric layer 1136 may be formed over the first back dielectric layer 1133 and the back traces 1135, and vias 1137 may be formed in the second back dielectric layer 1136 (e.g., by etching, stripping, etc.) to expose the contact areas of the back traces 1135.

[0289] Backside interconnect pads 1138 (e.g., ball contacts, planes, terminals, etc.) may be formed on the second backside dielectric layer 1136 and / or in vias 1137 of the second backside dielectric layer 1136. These backside interconnect pads 1138 can thus be electrically connected to the backside wiring 1135. These backside interconnect pads 1138 may be formed, for example, in the same or similar manner as the RDL wiring formed in block 865. These backside interconnect pads 1138 may be formed, for example, by forming metal contact pads and / or forming bump bottom metallization (e.g., to reinforce subsequent attachment to the backside wiring 1135 via other interconnect structures).

[0290] Although the back RDL layer 1132 is shown as having two back dielectric layers 1133, 1136 and a back wiring layer 1135, it should be understood that any number of dielectric and / or wiring layers can be formed.

[0291] Although not displayed Figure 11DInterconnect structures can be formed on the substrate 793, for example, on a side of the substrate 793 opposite to the component 700I and the molding material 735, as in this example, related to block 886 and Figure 7K The subject of discussion.

[0292] In another exemplary embodiment, a substrate (e.g., a multilayer substrate, a packaging substrate, etc.) may be attached to the component 700I (e.g., including the semiconductor dies 725, 726 and the molding material 730) and the molding material 735, for example as in the relevant context. Figure 11A-11D The backside RDL discussed is either an alternative or an additional one.

[0293] For example, as in Figure 12A As illustrated, these interconnect structures 795 may be formed at a height that will extend at least to the height of the component 700I. It should be noted that this height is not necessarily present, for example, in a scenario where the back substrate has its own interconnect structure, or where additional interconnect structures are utilized between the interconnect structures 795 and the back substrate. These interconnect structures 795 may, for example, be a type of interconnect structure used in the relevant block 897 and... Figure 7K Attached in the same or similar manner as described.

[0294] Continuing with this example, as in Figure 12A As illustrated, component 1200A can be molded using a molding material 735, and if necessary, the molding material 735 can be thinned. Such molding and / or thinning can, for example, be performed using a material as shown in the relevant block 899. Figure 7K It shall be carried out in the same or similar manner as described herein.

[0295] As in Figure 12B As shown, a back substrate 1232 can be attached. For example, the back substrate 1232 can be electrically connected to the interconnect structure 795 and / or mechanically attached to the molding material 735 and / or component 700I (e.g., molding material 730 and / or semiconductor dies 725, 726). The back substrate 1232 can be attached, for example, in a panel form and / or a single package form, and can be attached, for example, before or after monolithization.

[0296] As discussed herein, after the component 700I is attached to the substrate 793, the substrate 793 and / or component 700I may be covered with a molding material. Alternatively or additionally, the substrate 793 and / or component 700I may be covered with a cap or a stiffener. Figure 13 This is an example to illustrate the point. Figure 13It is roughly a display Figure 7J The component 700J, with an additional cover 1310 (or a reinforcing component).

[0297] The cover 1310 may include, for example, metal and provide electromagnetic shielding and / or heat dissipation. For example, the cover 1310 may be electrically coupled to a ground line on the substrate 793 to provide shielding. The cover 1310 may be coupled to the substrate 793, for example, using solder and / or conductive epoxy. Although not shown, a thermal interface material may be formed in a gap 1315 between the component 700I and the cover 1310.

[0298] Although most of the examples shown and discussed herein only demonstrate that component 700I is attached to substrate 793, other components (e.g., active and / or passive components) may also be attached to substrate 793. For example, as in Figure 14 As shown, a semiconductor die 1427 can be attached (e.g., flip-chip bonding, wire bonding, etc.) to the substrate 793. The semiconductor die 1427 is attached to the substrate 793 in a manner laterally adjacent to the component 700I. After this attachment, any of the packaging structures discussed herein (e.g., interconnect structures, molding, caps, etc.) can then be formed.

[0299] In another exemplary implementation, other components may be coupled to the top side of component 700I in a vertically stacked assembly. Figure 15 This is an example illustrating such a component 1500C. A third die 1527 and a fourth die 1528 (e.g., their non-active sides) can be attached to the top of the component 700I. This attachment can be performed, for example, using an adhesive. Bonding pads on the active sides of the third die 1527 and the fourth die 1528 can then be wire-bonded to the substrate 793. Note that in a scenario where one RDL and / or substrate is attached to the component 700I, the third die 1527 and / or the fourth die 1528 can be flip-chip bonded to this RDL and / or substrate. After this attachment, any of the packaging structures discussed herein (e.g., interconnect structures, molding, caps, etc.) can then be formed.

[0300] In yet another exemplary embodiment, another component may be coupled to the bottom side of the substrate. Figure 16 This is an example illustrating such a component. A third die 1699 is attached to the bottom side of the substrate 793, for example, in a gap between interconnect structures on the bottom side of the substrate 793. After this attachment, any of the packaging structures discussed herein (e.g., interconnect structures, molding, caps, etc.) can then be formed.

[0301] exist Figure 8-16 The methods and components shown and discussed herein are merely non-limiting examples, presented to depict various features of the invention. Such methods and components may also share any or all of the features shown and discussed in the following co-filed U.S. patent applications: U.S. Patent Application Serial No. 13 / 753,120, filed January 29, 2013, entitled "Semiconductor Device and Method of Manufacturing a Semiconductor Device"; U.S. Patent Application Serial No. 13 / 863,457, filed April 16, 2013, entitled "Semiconductor Device and Method of Manufacturing the Same"; and others. U.S. Patent Application Serial No. 14 / 083,779, filed on March 18, 2014, entitled "Semiconductor Device with Through-Silicon Vias - Less Deep Well"; U.S. Patent Application Serial No. 14 / 218,265, filed on June 24, 2014, entitled "Semiconductor Device and Method of Manufacturing Thereof"; U.S. Patent Application Serial No. 14 / 313,724, filed on July 28, 2014, entitled "Semiconductor Device with Thin Redistribution Layer"; U.S. Patent Application Serial No. 14 / 444,450, filed on October 27, 2014, entitled "Semiconductor Device with Reduced Thickness". The contents of each of these U.S. patent applications are incorporated herein by reference in their entirety: U.S. Patent Application Serial No. 14 / 524,443, entitled “Mechanism”; U.S. Patent Application Serial No. 14 / 532,532, entitled “Intermediate, Method of Manufacturing Thereof, Semiconductor Package Using Thereof, and Method of Manufacturing The Semiconductor Package”, filed November 4, 2014; U.S. Patent Application Serial No. 14 / 546,484, entitled “Semiconductor Device with Reduced Warpage”, filed November 18, 2014; and U.S. Patent Application Serial No. 14 / 671,095, entitled “Semiconductor Device and Method of Manufacturing Thereof”, filed March 27, 2015; the contents of each of these U.S. patent applications are incorporated herein by reference.

[0302] The discussion herein includes numerous illustrative diagrams illustrating various parts of a semiconductor package assembly. For clarity of illustration, these diagrams do not show all features of each exemplary assembly. Any of the exemplary components presented herein may share any or all of the features with any or all of the other components presented herein. For example, and without limitation, any or any part of the components relating to the examples shown and discussed in Figures 1-7 may be included in relation to… Figure 8-16 Any of the components of the paradigm discussed. Conversely, related to Figure 8-16Any of the components shown and discussed can be included in relation to the components shown and discussed in Figures 1-7.

[0303] In summary, the various features of this invention are to provide a semiconductor device or package structure and a method for manufacturing it. Although the foregoing description has been illustrated with reference to certain features and examples, it will be understood by those skilled in the art that various changes can be made and equivalents can be substituted without departing from the scope of this invention. Furthermore, many modifications can be made to adapt a particular situation or material to the teachings of this invention without departing from its scope. Therefore, it is intended that this invention is not limited to the specific examples disclosed, but rather encompasses all examples falling within the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: The first redistribution structure includes: First dielectric layer; and A first conductive line, embedded in the first dielectric layer, includes: The top side of the first line is at least partially covered by the first dielectric layer; The bottom side of the first line is exposed on the bottom side of the first dielectric layer; and The first line's lateral side is covered by the first dielectric layer; and A first conductive via, buried in the first dielectric layer, includes: The top side of the first conductive via is exposed on the top side of the first dielectric layer; The bottom side of the first conductive via is directly coupled to the top side of the first line; and The first conductive via is covered by the first dielectric layer on its lateral side. The second redistribution structure is located on the bottom side of the first redistribution structure and includes: The second dielectric layer is coupled to the bottom side of the first dielectric layer below; The third dielectric layer is coupled to the bottom side of the second dielectric layer; The second conductive line is embedded in the third dielectric layer; and The second via extends through the second dielectric layer, wherein: The second conductive line includes a first portion, the first portion of the second conductive line extending along the bottom side of the second dielectric layer; The first conductive line includes a first portion and a second portion, the first portion of the first conductive line being along the top side of the second dielectric layer and the second portion of the first conductive line being above the second via extending through the second dielectric layer; and The second conductive line includes a second portion that extends through the second via and contacts the second portion of the first conductive line above the second via that extends through the second dielectric layer. Semiconductor grains are attached to the top side of the first redistribution structure; and Molding material covers at least a portion of the first redistributed structure and the lateral sides of the semiconductor grain. The first dielectric layer, the second dielectric layer, and the third dielectric layer all comprise the same dielectric material.

2. The semiconductor device as claimed in claim 1, characterized in that, No wiring is buried in the second dielectric layer.

3. The semiconductor device as claimed in claim 1, characterized in that, The same dielectric material includes organic dielectric materials.

4. The semiconductor device as claimed in claim 1, characterized in that, The first conductive line and the other conductive lines of the first redistribution structure have a submicron spacing.

5. The semiconductor device as claimed in claim 1, characterized in that, Also includes: substrate; A conductive interconnect structure electrically connects the bottom side of the semiconductor die to the top side of the substrate; as well as An encapsulating material covers at least a portion of the upper side of the substrate and laterally surrounds the semiconductor die, the first redistribution structure, the second redistribution structure, and the conductive interconnect structure, while leaving the upper side of the semiconductor die uncovered by the encapsulating material.

6. The semiconductor device as claimed in claim 1, characterized in that, The first portion and the second portion of the second conductive line are portions of the same continuous metal layer.

7. The semiconductor device as claimed in claim 1, characterized in that, The first conductive line does not have a seed layer.

8. The semiconductor device as claimed in claim 1, characterized in that, It also includes a base filler that extends to at least one lateral edge in the first redistribution structure and the second redistribution structure.

9. A semiconductor device, characterized in that, include: The first redistribution structure includes: First dielectric layer; The first conductive circuit includes: The top side of the first line is at least partially covered by the first dielectric layer; The bottom side of the first line is exposed from the first dielectric layer; and The first line lateral side is at least partially covered by the first dielectric layer; The first conductive via includes: The top side of the first conductive via is exposed from the first dielectric layer; The bottom side of the first conductive via is directly coupled to the top side of the first line; and The first conductive via's lateral side is at least partially covered by the first dielectric layer; and A grain interconnect structure, wherein at least a portion of the grain interconnect structure is above the top side of the first conductive via; The second redistribution structure includes: The second dielectric layer is coupled to the bottom side of the first dielectric layer below it, and the first conductive line includes a first portion that extends along the top side of the second dielectric layer. The second conductive line includes a first portion, the first portion of the second conductive line extending along the bottom side of the second dielectric layer; A second via extends through the second dielectric layer, wherein a second portion of the second conductive line extends through the second via and couples the second conductive line to the first conductive line; and The third dielectric layer is coupled to the bottom side of the second dielectric layer; Semiconductor die, attached to the top side of the die interconnect structure; Conductive pillars, coupled to the top side of the first redistribution structure; and A molding material covers at least a portion of the first redistributed structure and laterally surrounds the semiconductor grain; The top side of the conductive pillar, the top side of the molding material, and the top side of the semiconductor grain are substantially coplanar; The bottom side of the conductive post is perpendicular to at least a portion of the conductive post; and The first dielectric layer, the second dielectric layer, and the third dielectric layer all comprise the same dielectric material.

10. The semiconductor device as claimed in claim 9, characterized in that, No wiring is buried in the second dielectric layer.

11. The semiconductor device as claimed in claim 9, characterized in that, The first dielectric layer, the second dielectric layer, and the third dielectric layer each comprise a polyimide or polybenzoxazole dielectric material.

12. The semiconductor device as claimed in claim 9, characterized in that, The semiconductor die includes conductive bumps that are soldered to the die interconnect structure.

13. The semiconductor device as claimed in claim 9, characterized in that, It also includes an oxide layer between the first dielectric layer and the second dielectric layer.

14. The semiconductor device as claimed in claim 9, characterized in that, Also includes: substrate; A conductive interconnect structure electrically connects the bottom side of the semiconductor die to the top side of the substrate; as well as An encapsulating material covers at least a portion of the upper side of the substrate and laterally surrounds the semiconductor die, the first redistribution structure, the second redistribution structure, and the conductive interconnect structure, while leaving the upper side of the semiconductor die uncovered by the encapsulating material.

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