Chip package strip, chip and chip packaging method

Abstract

This disclosure provides a chip packaging strip, a chip, and a chip packaging method, belonging to the field of semiconductor technology. The chip packaging strip includes: at least one packaging strip structure disposed around a stacked chip. The packaging strip structure is a structure with vertical logical continuity formed by multiple sequentially stacked metal rings and through-holes disposed between adjacent metal rings, but the vertical logical continuity between adjacent stacked packaging strip structures is not achieved. The multiple metal rings in the at least one packaging strip structure are discontinuous, and the broken arc segments of each metal ring are vertically connected to the corresponding broken arc segments of adjacent metal rings in the packaging strip structure through through-holes, forming multiple packaging strip substructures. At least one packaging strip substructure is connected to at least one functional unit and at least one active unit in the chip, establishing a first logical connection between the functional unit and the active unit. Embodiments of this disclosure can improve chip footprint, enhance trace routing, and reduce voltage drop.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a chip packaging strip, a chip, and a chip packaging method. Background Technology

[0002] A seal ring (also known as a sealing ring, protective ring, etc.) is a protective ring located between the core area of ​​a chip and the scribe line. Summary of the Invention

[0003] This disclosure provides a chip packaging strip, a chip, and a chip packaging method.

[0004] In a first aspect, this disclosure provides a chip packaging strip, comprising: at least one packaging strip structure disposed around a stacked chip, wherein the packaging strip structure is a structure with vertical logical continuity formed by a plurality of sequentially stacked metal rings and through holes disposed between adjacent metal rings, and the vertical logical continuity between adjacent stacked packaging strip structures is not achieved; wherein, the plurality of metal rings in at least one packaging strip structure are discontinuous metal rings, and the broken arc segments of each metal ring are vertically connected to the corresponding broken arc segments in adjacent metal rings in the packaging strip structure through the through holes to form a plurality of packaging strip substructures, and at least one packaging strip substructure is connected to at least one functional unit and at least one active unit in the chip, thereby establishing a first logical connection between the functional unit and the active unit.

[0005] Secondly, this disclosure provides a chip comprising: a substrate; a circuit module disposed on the substrate; and a chip packaging strip disposed around the circuit module; wherein the chip packaging strip is a chip packaging strip as described in any one of the embodiments of this disclosure.

[0006] Thirdly, this disclosure provides a chip packaging method, which includes: providing a chip to be packaged, the chip to be packaged including a substrate and a circuit module disposed on the substrate; and disposing of a chip packaging strip as described in any one of the embodiments of this disclosure around the circuit module.

[0007] The embodiments provided in this disclosure reuse the area occupied by the chip package strip when setting the chip package strip for each chip. Based on the chip package strip with a breakpoint method, the logical connection between the functional unit and the active unit in the chip is realized without occupying additional area outside the chip, thereby improving the area utilization of the chip. At the same time, the chip package strip also takes into account the protection function of the package strip structure for the chip. In addition, by dividing the package strip structure into multiple package strip substructures through the breakpoint method, and establishing the first logical connection between the functional unit and the active unit in the chip through the package strip substructures, the functional unit can obtain power and / or grounding function based on the first logical connection, thereby enhancing the routing of the chip's bus and reducing voltage drop.

[0008] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0009] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 A schematic diagram of an encapsulation strip provided for related technologies;

[0011] Figure 2 A schematic diagram of a chip packaging strip provided in an embodiment of this disclosure;

[0012] Figure 3 A schematic diagram of a chip packaging strip provided in an embodiment of this disclosure;

[0013] Figure 4 A schematic diagram of a chip packaging strip provided in an embodiment of this disclosure;

[0014] Figure 5 A schematic diagram of a chip packaging strip provided in an embodiment of this disclosure;

[0015] Figure 6 A schematic diagram of a chip packaging strip provided in an embodiment of this disclosure;

[0016] Figure 7 A schematic diagram of a chip packaging strip provided in an embodiment of this disclosure;

[0017] Figure 8 A schematic diagram of a chip packaging strip provided in an embodiment of this disclosure;

[0018] Figure 9 A schematic diagram of a chip packaging strip provided in an embodiment of this disclosure;

[0019] Figure 10 A schematic diagram of a chip packaging strip provided in an embodiment of this disclosure;

[0020] Figure 11 A schematic diagram of a chip packaging strip provided in an embodiment of this disclosure;

[0021] Figure 12 A schematic diagram of a chip provided in an embodiment of this disclosure;

[0022] Figure 13 A flowchart of a chip packaging method provided in this disclosure embodiment;

[0023] Figure 14 A block diagram of an electronic device provided in an embodiment of this disclosure;

[0024] Figure 15 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0026] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0027] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0029] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0030] In through-silicon via (TSV) packaging technology, conductive materials such as copper, tungsten, and polysilicon can be filled into TSVs to achieve vertical electrical interconnection, thereby reducing interconnection length, signal delay, capacitance, and inductance, and enabling low-power, high-speed communication between chips.

[0031] In related technologies, through-silicon via (TSV) packaging requires creating vias in non-functional areas of the chip. This typically occupies a dicing slot or additional area, and the dicing slot incurs area loss during slicing. Therefore, both occupying a dicing slot and additional area reduce the usable area of ​​the chip. Consequently, given the limited chip area, meeting these requirements would reduce the area available for fabricating circuit modules, thus decreasing chip utilization and potentially impacting chip performance and reliability.

[0032] A seal ring (also known as a sealing ring or protective ring) is a protective ring located between the core area of ​​a chip and the scribe line. A seal ring is typically composed of active layers, contacts, vias, and metal layers stacked according to certain rules. Its main function is to prevent mechanical damage to the chip during dicing. Additionally, the seal ring prevents moisture and free ions from entering the chip through the side cut and affecting its functionality. Furthermore, by grounding the seal ring, it can shield against external interference. Therefore, the seal ring is like a Great Wall surrounding the chip, mitigating the impact of dicing on the internal circuitry and preventing external moisture and dust from entering the chip.

[0033] Figure 1 A schematic diagram of an encapsulation strip provided for related technologies. (Refer to...) Figure 1In an uncut chip, the circuit function implementation area 10 of each chip is surrounded by a packaging strip 20, and the area between each packaging strip 20 corresponds to a dicing groove 30 (also called a dicing channel, saw channel, or street). By performing slicing at the dicing groove 30, multiple independent chips can be obtained.

[0034] In this embodiment of the disclosure, corresponding chip packaging strips are stacked around each chip, thereby eliminating the need for perforation processing. Considering that the aperture size required by TSV technology is usually larger than the width of the packaging strip, the chip packaging strip method can reduce the chip's footprint, thereby increasing the usable area of ​​the chip.

[0035] In addition, the packaging strips in related technologies are usually only grounded and not connected to other active devices. Therefore, the functional units in the chip can only obtain power through a preset power bus, making the power supply method relatively simple. In the event of a power bus failure, the chip cannot obtain power, resulting in unstable chip operation and affecting the chip's reliability.

[0036] In this embodiment, by setting the chip packaging strip for each chip, the area occupied by the chip packaging strip is reused. Based on the chip packaging strip with a breakpoint method, the logical connection between the functional units and active units in the chip is realized without occupying additional area outside the chip, thereby improving the chip area utilization rate. At the same time, the chip packaging strip also takes into account the protection function of the packaging strip structure for the chip. In addition, by dividing the packaging strip structure into multiple packaging strip substructures through a breakpoint method, and establishing the first logical connection between the functional units and active units in the chip through the packaging strip substructures, the functional units can obtain power and / or grounding function based on the first logical connection, thereby enhancing the routing of the chip's bus and reducing voltage drop.

[0037] The first aspect of this disclosure provides a chip packaging strip.

[0038] Figure 2 This is a schematic diagram of a chip packaging strip provided in an embodiment of this disclosure. (Refer to...) Figure 2 The chip package bar 100 includes at least one package bar structure 110 / 120 stacked around the chip 200. The package bar structure 110 / 120 is a structure with vertical logical conduction formed by a plurality of sequentially stacked metal rings 1101 and through holes 1102 (through holes 1102 include through holes 1102a and through holes 1102b, which are only used to distinguish between adjacent metal rings 1101 and have no essential difference) and the vertical logical conduction between adjacent stacked package bar structures 110 / 120 is not.

[0039] In this embodiment, at least one of the multiple metal rings 1101 in the package strip structure 110 / 120 are discontinuous metal rings, and the break position and number of metal rings 1101 are determined according to the voltage domain of the chip 200. The break arc segment of each metal ring 1101 is connected vertically to the corresponding break arc segment in the adjacent metal ring 1101 in the package strip structure 110 through the through hole 1102 to form multiple package strip substructures. At least one package strip structure is connected to at least one functional unit and at least one active unit in the chip 200, so that a first logical connection is established between the functional unit and the active unit.

[0040] Therefore, the chip packaging strip in this embodiment is a protective structure surrounding the chip, including a single packaging strip structure or multiple stacked packaging strip structures. Each packaging strip structure is composed of multiple stacked metal rings, and a via is provided between adjacent metal rings. The via can establish a connection between adjacent metal rings, ultimately enabling the packaging strip structure to be logically connected vertically ("vertically" refers to the direction along the vertical direction of the chip, i.e., the direction representing the chip thickness).

[0041] It should be noted that, Figure 2 The chip package strip is shown in the cross-sectional view, and in Figure 2 The image only shows the structure of the chip package strip on one side of the chip. In reality, the right side of the chip also has symmetrically arranged chip package strips. Since the structures of the chip package strips on both sides are basically the same, they are not shown in the image. Figure 2 As shown in the image, this does not mean that the chip packaging strip is not present in the right-side area of ​​the chip.

[0042] In some alternative implementations, the chip package strip includes one or more package strip structures. The upper and lower logic connections between these multiple package strip structures are not conductive.

[0043] In some alternative implementations, when multiple metal rings are stacked consecutively in a chip package strip, if no connection is established between two adjacent stacked metal rings, the consecutively stacked metal rings can be divided into two package strip structures based on these two unconnected metal rings. The bottom layer of the upper package strip structure is the uppermost metal ring of these two metal rings, and the top layer of the lower package strip structure is the lowermost metal ring of these two metal rings.

[0044] For example, in adjacent stacked encapsulation strip structures, the connection between the bottommost metal ring of the upper encapsulation strip structure and the topmost metal ring of the lower encapsulation strip structure is in a disconnected state; wherein, the disconnected state is achieved by not providing through holes or by placing the through holes in an invalid connection state.

[0045] Figure 3This is a schematic diagram of a chip packaging strip provided in an embodiment of this disclosure. (Refer to...) Figure 3 The chip packaging strip includes a packaging strip structure 110 and a packaging strip structure 120. No through-holes are provided between the bottom metal ring of the packaging strip structure 110 and the top metal ring of the packaging strip structure 120, thus ensuring that there is no logical connection between the two parts.

[0046] Figure 4 This is a schematic diagram of a chip packaging strip provided in an embodiment of this disclosure. (Refer to...) Figure 4 The chip packaging strip includes packaging strip structure 110 and packaging strip structure 120. The width of the bottom metal ring of packaging strip structure 110 is less than the distance between through-holes, and the width of the top metal ring of packaging strip structure 120 is also less than the distance between through-holes. This prevents the bottom metal ring of packaging strip structure 110 from connecting to the top metal ring of packaging strip structure 120 through through-holes, thus eliminating any logical connection between the two parts.

[0047] It should be noted that the above implementation of the disconnected state is only an example, and the embodiments disclosed herein are not limited thereto.

[0048] In some alternative implementations, at least one package strip structure exists within the chip package strip, where multiple metal rings have breaks, thus forming discontinuous metal rings. That is, based on the breaks, a closed metal ring is broken, thereby forming multiple corresponding broken arc segments.

[0049] In some alternative implementations, within a package strip structure, the broken arc segments of each metal ring are connected vertically to the corresponding broken arc segments of adjacent metal rings in the package strip structure via through-holes, thereby forming multiple package strip substructures. This is similar to vertically dividing a ring-shaped structure (package strip structure) with a hierarchical structure (metal layers) into multiple substructures (package strip substructures), with each layer of each substructure connected vertically (corresponding broken arc segments connected via through-holes).

[0050] For example, in a packaging strip structure, there is a corresponding relationship between the broken arc segments of each metal ring (for example, there is a corresponding relationship between the broken arc segment a1 of metal ring a and the broken arc segment b1 of metal ring b). These broken arc segments with corresponding relationships are connected vertically through through holes to form corresponding packaging strip substructures, so that the packaging strip structure includes multiple packaging strip structures.

[0051] In some alternative implementations, the location and number of disconnections in the metal rings are determined based on the number and distribution of voltage domains within the chip, with each voltage domain corresponding to at least one package strip structure. A voltage domain is a region divided according to the voltage requirements of various functional units within the chip. Typically, functional units within a voltage domain have relatively consistent voltage requirements. By dividing voltage domains, the chip can utilize electrical energy more rationally and efficiently, thereby reducing chip power consumption.

[0052] In some alternative implementations, all metal rings in an encapsulation strip structure are discontinuous, and the break points and number of breaks in each metal ring are the same. Corresponding break segments are connected vertically by through holes to form corresponding encapsulation strip substructures.

[0053] In some alternative implementations, the through-hole has a strip-like structure and / or a columnar structure. When the through-hole corresponds to a strip-like structure, the through-hole adjacent to the discontinuous metal ring is also broken, becoming multiple discontinuous strip-like through-holes, and the break position of the through-hole corresponds to the break position of the metal ring. When the through-hole corresponds to a columnar structure, it is not necessary to truncate the through-hole at the break position of the metal ring; it is only necessary to ensure that columnar through-holes are not set at the break position of the metal ring.

[0054] It should be noted that for strip-shaped vias, the chip package strip only has gaps at the breaks, while the vias at other locations are continuous. Therefore, strip-shaped vias offer strong structural protection. For columnar vias, due to their relatively abundant porosity, they offer strong protection against moisture and dust adsorption, but relatively weaker structural protection. However, the structural protection function can be enhanced by adjusting the via density and position.

[0055] In some alternative implementations, vias can be used to connect the corresponding broken arc segments of the metal rings in the encapsulation strip structure, thereby forming multiple encapsulation strip substructures. Each encapsulation strip substructure contains a logically connected substructure based on the vias. However, since the various encapsulation strip substructures are not connected by vias, they do not have a direct connection relationship.

[0056] Furthermore, due to Figure 2 This view shows the chip package strip from a cross-sectional perspective, thus clearly illustrating its layer stacking structure. However, it cannot clearly demonstrate the distribution of the package strip structure and its corresponding sub-structures. Therefore, in Figure 5 The chip package strip of this disclosure is shown from the perspective of the front view for further explanation.

[0057] Figure 5 This is a schematic diagram of a chip packaging strip provided in an embodiment of this disclosure. (Refer to...) Figure 5 It shows a front view of one of the package bar structures (e.g., package bar structure 110) in the chip package bar 100.

[0058] like Figure 5 As shown, the central area is chip 200, and at least one packaging strip structure is stacked around chip 200. Figure 5 Only the encapsulation strip structure 110 is shown in the diagram. The encapsulation strip structure 110 includes multiple metal rings 1101, and through holes 1102 have a strip-like structure and are disposed between adjacent metal rings 1101. Moreover, the metal rings 1101 have multiple breaks 1103, such that the metal rings 1101 are divided into multiple broken arc segments by the breaks 1103. Correspondingly, at the positions corresponding to the breaks 1103, the through holes 1102 are also broken to form multiple strip-like through holes.

[0059] It should be noted that "via 1102" is a general term for a through hole used for simplified identification and is not intended to limit it to through holes located only near the outer side of the chip.

[0060] Furthermore, the broken arc segments of each metal ring 1101 in the encapsulation strip structure 110 are connected vertically to the corresponding broken arc segments in the adjacent metal rings through the corresponding strip-shaped through holes, thereby forming multiple encapsulation strip substructures 111 / 112 / 113 / ... / 11n, where n is an integer greater than 1.

[0061] It should be noted that for strip-shaped through holes, they are also truncated at the break points of the metal ring. This is to prevent the establishment of connections between the various broken arc segments of the metal ring through the through hole. For columnar through holes, it is not necessary to truncate them at the break points of the metal ring; it is sufficient to ensure that columnar through holes are not placed at the break points of the metal ring.

[0062] Figure 6 This is a schematic diagram of a chip packaging strip provided in an embodiment of this disclosure. (Refer to...) Figure 6 The through hole 1102 is a columnar through hole, and no through hole is provided at the break 1103. On the one hand, it can ensure that the broken arc segments of each metal ring 1101 in the packaging strip structure are connected vertically to the corresponding broken arc segments in the adjacent metal ring through the through hole 1102, so that the corresponding packaging strip structure is logically connected vertically. On the other hand, it can prevent the through hole 1102 from connecting multiple broken arc segments in a metal ring 1101, thereby keeping the packaging strip structures from having a direct connection relationship.

[0063] In some alternative implementations, the break interface of the metal ring is serrated. This serrated shape increases the cross-sectional area of ​​the break interface and also makes it more difficult for moisture and dust to directly penetrate the chip through the break, thus maintaining the protective function of the chip package strip.

[0064] Figure 7 This is a schematic diagram of a chip packaging strip provided in an embodiment of this disclosure. (Refer to...) Figure 7 The metal ring 1101 is cut off by the break 1103, forming n broken arc segments. Moreover, the break 1103 has a serrated brush shape.

[0065] In some alternative implementations, the disconnection interface of the metal ring can also have a zigzag shape, an irregular curve shape, etc., all of which aim to increase the cross-sectional area of ​​the disconnection interface and prevent moisture and other substances from directly entering the chip.

[0066] It should be noted that the above description of the disconnected interface of the metal ring is merely an example, and the embodiments disclosed herein do not impose any limitations on it.

[0067] As mentioned earlier, in some optional implementations, the break positions and number of breaks in the metal ring can be determined based on the number and distribution of voltage domains in the chip. For example, if the number of voltage domains in the chip is m (m>1), then (m-1) break positions can be set to break the metal ring, forming m broken arc segments. Each broken arc segment is connected vertically to the corresponding broken arc segment in the adjacent metal ring in the package strip structure, ultimately forming m package strip substructures, thus establishing a one-to-one correspondence between the substructures and the voltage domains.

[0068] The following is combined with Figure 8 The correspondence between the voltage domain and the package strip structure is explained in detail.

[0069] Figure 8 This is a schematic diagram of a chip packaging strip provided in an embodiment of this disclosure. (Refer to...) Figure 8 The chip is surrounded by a chip packaging strip, which includes at least one packaging strip structure 110. The chip includes four voltage domains: voltage domain 210, voltage domain 220, voltage domain 230, and voltage domain 240. Correspondingly, at the boundaries of each voltage domain, the metal ring and through-hole in the packaging strip structure 110 are cut off. Furthermore, for each cut-off portion, the corresponding broken arc segments are connected vertically through through-holes to form corresponding packaging strip sub-structures. For example... Figure 8 As shown, the voltage domain 210 corresponds to the package strip structure 111, the voltage domain 220 corresponds to the package strip structure 112, the voltage domain 230 corresponds to the package strip structure 113, and the voltage domain 240 corresponds to the package strip structure 114.

[0070] In some alternative implementations, a voltage domain can correspond to multiple package strip structures. For example, if a certain voltage domain of the chip has a large area and / or a high voltage, multiple package strip structures can be set for that voltage domain.

[0071] It should be noted that the above-described methods and number of voltage domain divisions are merely illustrative examples, and the embodiments disclosed herein do not impose any limitations on them.

[0072] It should also be noted that, considering that the layout and function of different layers of the chip may be different, the voltage domain distribution of the corresponding chip layer may be the same or different for different package structures.

[0073] For example, when multiple package strip structures have the same voltage domain distribution, the break position and number of metal rings in the multiple package strip structures can be the same; when multiple package strip structures have different voltage domain distributions, each package strip structure can determine the break position and number of metal rings according to the voltage domain distribution of its corresponding chip layer. Figure 3 For example, package bar structure 110 and package bar structure 120 correspond to different chip levels. When the number and distribution of voltage domains of the two chip levels are the same, the metal rings in package bar structure 110 and package bar structure 120 can adopt the same disconnection method. When the number and distribution of voltage domains of the two chip levels are different, the metal rings in package bar structure 110 and package bar structure 120 can adopt different disconnection methods according to the voltage domain distribution of their respective chip levels.

[0074] In some alternative implementations, at least one package strip structure is connected to at least one functional unit and at least one active unit in the chip, establishing a first logical connection between the functional unit and the active unit. In other words, the first logical connection between the functional unit and the active unit can be established through the connection function of the package strip structure. The connection function of the package strip structure can be implemented by a metal ring therein, or by a metal ring and a corresponding through-hole.

[0075] In some alternative implementations, the active unit includes a power supply unit (e.g., VDD, AVDD) and / or a ground unit (e.g., GND). The power supply unit provides electrical power to the functional units connected via the package strip structure, and the ground unit provides grounding functionality to the functional units connected via the package strip structure.

[0076] It should be noted that in related technologies, chip packages are typically not connected to a power source. Therefore, the functional units within the chip obtain power in a relatively limited way; for example, they can only obtain power through a power bus. Under these circumstances, if the power bus breaks or experiences poor contact, or if the power supply connected to the power bus fails, the limited power supply method can easily prevent the functional units from obtaining power, thus causing the chip to malfunction.

[0077] In this application, in the packaging strip structure of the chip packaging strip, at least one packaging strip substructure is respectively connected to at least one functional unit and at least one active unit, thereby establishing a first logical connection between the functional unit and the active unit. In other words, for a functional unit, in addition to being connected to the power bus, it can also be connected to the active unit through the packaging strip substructure. Therefore, even if the power bus is broken or has poor contact, or the power supply connected to the power bus fails, the functional unit can still obtain power through the active unit of the first logical connection. In summary, through the first logical connection of the embodiments of this disclosure, the routing enhancement of the bus (including the power bus and / or ground bus) is achieved.

[0078] It should also be noted that, in this embodiment, considering the advantages of the outer ring of the chip, such as wider traces and the ability to execute in parallel on one or more layers, an outer ring line (corresponding to the first logic connection) is added to make the connection of the power supply or ground line more direct. Furthermore, the first logic connection and the second logic connection form a parallel structure, which can reduce impedance, thereby effectively reducing parasitic resistance on the line and thus effectively reducing voltage drop.

[0079] In other words, the outermost ring of the chip is called the outer ring, which has advantages such as wider traces and the ability to execute one or more layers in parallel. In the embodiments of this disclosure, the package strip is set around the chip, and the first logic connection established based on the package strip belongs to the outer ring line, so it also has the advantages of the outer ring line (wider traces and the ability to execute one or more layers in parallel). The functional unit is connected to the active unit through the package strip substructure, and the functional unit is connected to the active unit inside the chip. The two connections are in parallel structure. The parallel structure can reduce resistance, thereby reducing voltage drop.

[0080] In some optional implementations, the functional units that are first logically connected to the package strip structure include: functional units in the voltage domain corresponding to the package strip structure, and / or functional units in voltage domains other than the corresponding voltage domain. In other words, a functional unit in a certain voltage domain can establish a first logical connection with an active unit through a package strip structure corresponding to that voltage domain, or it can establish a first logical connection with an active unit through a package strip structure corresponding to other voltage domains.

[0081] In some optional implementations, the encapsulation strip structure is connected to the functional unit and the active unit respectively through the broken arc segments of the metal ring within it. Furthermore, any functional unit can be connected to one broken arc segment or multiple broken arc segments. When multiple broken arc segments are connected, these multiple broken arc segments can be located within a single encapsulation strip structure or can span across multiple encapsulation strip structures. Within a single encapsulation strip structure, the connected multiple broken arc segments can correspond to one encapsulation strip structure or multiple encapsulation strip structures; this disclosure does not impose any limitation on this.

[0082] It should be noted that, in addition to being connected to active units through the first logic connection, the functional units in the chip can also be connected to active units in the chip's internal regions (e.g., the core region) to improve the chip's reliability.

[0083] In some alternative implementations, the functional unit has a second logical connection with at least one active unit located in the circuit function implementation area of ​​the chip. In other words, while providing external active services (i.e., power and grounding functions provided through the first logical connection) to the functional unit, it is also necessary to provide it with internal active services (i.e., power and grounding functions provided through the second logical connection) as much as possible, thereby increasing the reliability of the chip.

[0084] For example, a functional unit is connected to a package strip structure, establishing a first logical connection between itself and a first active unit through this package strip structure. Simultaneously, the functional unit also establishes a second logical connection with a second active unit located in the chip core region. When the first and second active units are power supply units, under normal circumstances, the functional unit can choose either one to obtain power as needed. If either one fails, power can be obtained promptly from the unfailed power supply unit, thus ensuring a stable power supply for the functional unit. When the first and second active units are grounding units, under normal circumstances, the functional unit can choose either one to obtain grounding functionality as needed. If either one fails, grounding functionality can be obtained promptly from the unfailed grounding unit, thus ensuring a stable grounding service for the functional unit.

[0085] Figure 9 This is a schematic diagram of a chip packaging strip provided in an embodiment of this disclosure. (Refer to...) Figure 9The chip 200 is surrounded by a chip packaging strip, and the chip packaging strip includes at least one packaging strip structure 110 stacked together. The packaging strip structure 110 includes a metal ring 1101 and an adjacent through hole 1102. Moreover, the metal ring 1101 is cut off at the break 1103 to form three broken arc segments 1101a, 1101b and 1101c.

[0086] like Figure 9 As shown, disconnected arc segment 1101a is connected to functional unit 211 and active unit 221 respectively, disconnected arc segment 1101b is connected to active unit 221 and functional unit 212 respectively, and disconnected arc segment 1101c is connected to functional unit 213 and active unit 222 respectively. Therefore, for active unit 221, it can establish a first logical connection with functional unit 211 through disconnected arc segment 1101a, and it can also establish a first logical connection with functional unit 212 through disconnected arc segment 1101b; for active unit 222, it can establish a first logical connection with functional unit 213 through disconnected arc segment 1101c.

[0087] exist Figure 9 In the chip package shown, the functional units and active units are connected by the same metal ring. The following section will further explain... Figure 10 The method for establishing the first logical connection across the metal ring will be explained in detail.

[0088] Figure 10 This is a schematic diagram of a chip packaging strip provided in an embodiment of this disclosure. (Refer to...) Figure 10 The chip 200 is surrounded by a chip packaging strip, which includes metal rings 11011 and 11012 (the two can belong to the same packaging strip structure or to different packaging strip structures). Metal ring 11011 is cut at break 1103, forming three broken arc segments 11011a, 11011b, and 11011c. Similarly, metal ring 11012 is cut at the corresponding position at break 1103, forming three broken arc segments 11012a, 11012b, and 11012c.

[0089] like Figure 10As shown, disconnected arc segment 11011a is connected to functional unit 211 and active unit 221 respectively; disconnected arc segment 11012b is connected to active unit 221 and functional unit 212 respectively; disconnected arc segment 11011c is connected to functional unit 213 and active unit 222 respectively; and disconnected arc segment 11012c is connected to functional unit 214 and active unit 222 respectively (from the perspective of the front view, the functional units establish the first logical connection across layers). Therefore, for active unit 221, it can establish the first logical connection with functional unit 211 through disconnected arc segment 11011a, or it can establish the first logical connection with functional unit 212 through disconnected arc segment 11012b; for active unit 222, it can establish the first logical connection with functional unit 213 through disconnected arc segment 11011c, or it can establish the first logical connection with functional unit 214 through disconnected arc segment 11012c.

[0090] Figure 11 This is a schematic diagram of a chip packaging strip provided in an embodiment of the present disclosure, shown in a cross-sectional view. Figure 10 The chip package strip structure shown clarifies the relative positional relationship between metal ring 11011 and metal ring 11012. Figure 11 (a) shows the case where metal ring 11011 and metal ring 11012 are in the same encapsulation strip structure. Figure 11 (b) shows the case where metal ring 11011 and metal ring 11012 are in different encapsulation strip structures.

[0091] like Figure 11 As shown in (a), the chip packaging strip includes packaging strip structure 110 and packaging strip structure 120, wherein metal ring 11011 and metal ring 11012 are both located in packaging strip structure 110. It should be noted that metal ring 11011 and metal ring 11012 can be adjacent metal rings or non-adjacent metal rings.

[0092] like Figure 11 As shown in (b), the chip packaging strip includes a packaging strip structure 110 and a packaging strip structure 120, wherein a metal ring 11011 is located in the packaging strip structure 110 and a metal ring 11012 is located in the packaging strip structure 120.

[0093] A second aspect of this disclosure provides a chip.

[0094] Figure 12 This is a schematic diagram of a chip provided according to an embodiment of this disclosure. (Refer to...) Figure 12 The chip includes: a substrate 1210; a circuit module 1220 disposed on the substrate; and a chip packaging strip 1230 disposed around the circuit module.

[0095] The chip packaging strip 1230 is a chip packaging strip as described in any one of the embodiments of this disclosure.

[0096] In some alternative implementations, the circuit module is located in the core region of the chip and may include multiple functional units and / or active units.

[0097] In this embodiment of the disclosure, a chip packaging strip is stacked around the chip to protect it. The strip includes one or more packaging strip structures, and at least one packaging strip structure has a breakpoint, thereby forming multiple corresponding packaging strip substructures. The packaging strip substructures can establish a first logical connection between functional units and active units in the chip, so that the functional units can obtain power and / or grounding functions based on the first logical connection. This enhances the bus routing of the chip, reduces voltage drop, and also takes into account the protective function of the packaging strip structure for the chip.

[0098] The third aspect of this disclosure provides a chip packaging method.

[0099] Figure 13 A flowchart illustrating a chip packaging method provided in this disclosure. (Refer to...) Figure 13 The chip packaging method includes:

[0100] Step S131: Provide a chip to be packaged, the chip to be packaged includes a substrate and a circuit module disposed on the substrate.

[0101] Step S132: Set a chip package strip around the circuit module.

[0102] The chip packaging strip used is any one of the chip packaging strips described in the embodiments of this disclosure.

[0103] In this embodiment of the disclosure, the chip to be packaged is packaged based on the chip packaging strip, which reduces the area occupied by the chip and increases the usable area of ​​the chip compared with TSV packaging. At the same time, it can also prevent moisture and other substances from entering the chip. Moreover, since at least one packaging strip structure in the chip packaging strip has a breakpoint, the formed packaging strip substructure can establish a first logical connection between the functional unit and the active unit in the chip, so that the functional unit can obtain power and / or grounding function based on the first logical connection, thereby enhancing the bus of the chip and reducing voltage drop.

[0104] It should be noted that the chip packaged according to the embodiments of this disclosure can be used to further manufacture electronic devices such as terminal devices and servers. The terminal device can be a user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc.; the server can be an independent physical server, a server cluster consisting of multiple servers, or a cloud server capable of cloud computing.

[0105] It is understood that the various embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step and the setting of functional modules should be determined by their functions and possible internal logic.

[0106] Figure 14 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0107] Reference Figure 14 This disclosure provides an electronic device, which includes: at least one processor 1401; at least one memory 1402; and one or more I / O interfaces 1403 connected between the processor 1401 and the memory 1402; wherein the memory 1402 stores one or more computer programs that can be executed by the at least one processor 1401, and the one or more computer programs are executed by the at least one processor 1401 to enable the at least one processor 1401 to perform various pending tasks.

[0108] Figure 15 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0109] Reference Figure 15 This disclosure provides an electronic device that includes multiple processing cores 1501 and an on-chip network 1502. The multiple processing cores 1501 are all connected to the on-chip network 1502, and the on-chip network 1502 is used to exchange data between the multiple processing cores and external data.

[0110] One or more processing cores 1501 store one or more instructions, and the one or more instructions are executed by one or more processing cores 1501 to enable one or more processing cores 1501 to perform various tasks to be processed.

[0111] In some embodiments, the electronic device may be a neuromorphic chip. Since neuromorphic chips can employ vectorized computation and require external memory, such as Double Data Rate (DDR) synchronous dynamic random access memory, to load parameters such as weights of the neural network model, the batch processing method used in this embodiment offers higher computational efficiency.

[0112] In other words, any of the above-mentioned electronic devices is a hardware device made based on the chip of the present disclosure, which can be used to perform corresponding tasks to be processed, including image processing tasks, text processing tasks, etc., and the present disclosure does not limit them.

[0113] This disclosure also provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor / processing core, performs the aforementioned task to be processed. The computer-readable storage medium may be volatile or non-volatile.

[0114] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the aforementioned task to be processed.

[0115] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0116] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A chip package strip, characterized by include: At least one packaging strip structure is arranged around a chip stack. The packaging strip structure is a structure with vertical logical connection formed by a plurality of sequentially stacked metal rings and through holes arranged between adjacent metal rings, and the vertical logical connection between adjacent stacked packaging strip structures is not. In this embodiment, at least one of the multiple metal rings in the packaging strip structure are discontinuous metal rings, and the broken arc segments of each metal ring are connected vertically to the corresponding broken arc segments of the adjacent metal rings in the packaging strip structure through the through holes to form multiple packaging strip substructures. At least one packaging strip substructure is connected to at least one functional unit and at least one active unit in the chip, thereby establishing a first logical connection between the functional unit and the active unit.

2. The chip package strip of claim 1, wherein, include: The location and number of disconnections of the metal ring are determined based on the number and distribution of voltage domains in the chip, and one voltage domain corresponds to at least one of the package strip structures.

3. The chip package strip according to claim 1 or 2, characterized in that, include: The broken interface of the metal ring has a sawtooth shape.

4. The chip package strip of claim 1, wherein, include: The through-hole has a strip-shaped structure; In the case where the metal ring is a discontinuous metal ring, the through holes adjacent to the metal ring include multiple discontinuous strip-shaped through holes, and the break position of the through holes corresponds to the break position of the metal ring.

5. The chip package strip of claim 1, wherein, include: The functional unit that is first logically connected to the package strip structure includes: a functional unit in the voltage domain corresponding to the package strip structure, and / or, a functional unit in a voltage domain other than the corresponding voltage domain; The active unit includes a power supply unit and / or a grounding unit. The power supply unit is used to provide electrical power to the functional units connected through the packaging strip structure, and the grounding unit is used to provide grounding functionality to the functional units connected through the packaging strip structure.

6. The chip package strip according to claim 1 or 5, wherein include: The broken arc segment of at least one metal ring in the encapsulation strip structure is connected to at least one functional unit and at least one active unit respectively, so as to establish a first logical connection between the functional unit and the active unit through the broken arc segment of the metal ring.

7. The chip package strip of claim 6, wherein, include: When the functional unit is connected to multiple disconnected arc segments, the active unit that provides power or grounding function to the functional unit is at least one active unit selected from the active units connected to the multiple disconnected arc segments. The plurality of disconnected arc segments can be a plurality of disconnected arc segments located in a metal ring of a single encapsulation strip structure, or a plurality of disconnected arc segments located in multiple metal rings of a single encapsulation strip structure, or a plurality of disconnected arc segments located in multiple metal rings of different encapsulation strip structures.

8. The chip package strip of claim 1, wherein, include: The functional unit has a second logical connection with at least one active unit located in the circuit function implementation region of the chip.

9. The chip package strip of claim 1, wherein, include: In the adjacent stacked encapsulation strip structures, the connection between the bottommost metal ring of the upper encapsulation strip structure and the topmost metal ring of the lower encapsulation strip structure is broken. The disconnected state is achieved by not setting a through hole or setting the through hole to an invalid connection state.

10. A chip, characterized by include: Substrate; Circuit modules disposed on the substrate; as well as A chip package strip surrounding the circuit module; The chip packaging strip is the chip packaging strip as described in any one of claims 1-9.

11. A chip packaging method, characterized by, include: A chip to be packaged is provided, the chip to be packaged includes a substrate and a circuit module disposed on the substrate; A chip packaging strip as described in any one of claims 1-9 is provided around the circuit module.

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