Packaging structure and electronic device
By setting a protective structure of hot-melt material within the circuit board dielectric layer, the high temperature problem caused by chip short circuits is solved, circuit board damage is avoided, board layout design efficiency is improved, and costs are reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAWEI DIGITAL POWER TECH CO LTD
- Filing Date
- 2022-10-08
- Publication Date
- 2026-07-14
AI Technical Summary
The high temperature caused by a short circuit during chip power-on may cause carbonization or fire of PCB materials, resulting in equipment damage. Existing technologies that add fuses or fuse chip designs will increase costs and occupy PCB area.
A protective structure of hot-melt material is set in the dielectric layer of the circuit board. The melting point is lower than that of the trace layer. This is used to melt the chip first when it is short-circuited, to prevent the temperature from getting too high and to avoid the circuit board from catching fire or carbonizing.
By setting a protective structure of hot-melt material within the dielectric layer, circuit board damage is avoided, additional space is reduced, board layout design efficiency is improved, and costs are lowered.
Smart Images
Figure CN115632047B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip packaging technology, specifically to a packaging structure and electronic device. Background Technology
[0002] After surface-mount chip packages or modules are assembled onto a printed circuit board (PCB), the chip needs to be powered on. During the power-on process, if the internal components of the chip are short-circuited, a large current will be generated. When the large current passes through the PCB traces, it will generate a relatively high temperature, which may cause the PCB material to carbonize or even catch fire.
[0003] In this situation, the PCB will lose its basic functions, which will lead to the scrapping of all components on the PCB, resulting in significant losses. Summary of the Invention
[0004] This application provides a packaging structure and an electronic device. The packaging structure has a protective structure that can self-melt when the chip is short-circuited, thereby reducing losses.
[0005] In a first aspect, this application provides a packaging structure including a protective structure, a circuit board, and a chip packaged on the circuit board. The circuit board includes a first trace layer, a second trace layer, and a dielectric layer, which are stacked. The protective structure is located within the dielectric layer and is used to electrically connect the first trace layer and the second trace layer. When the chip is packaged on the circuit board, the chip is electrically connected to the first trace layer or the second trace layer. During the power-on process of the chip, the current needs to flow through the protective structure to the chip electrically connected to the first trace layer or the second trace layer. When the chip is short-circuited, the current flowing through the protective structure, the first trace layer or the second trace layer, and the chip will increase. The increased current will cause the temperature of the traces used to carry the current and the protective structure to rise. Since the protective structure is made of a hot-melt material, and the melting point of the hot-melt material used in the protective structure is lower than the melting point of the first trace layer and the second trace layer through which the current passes when the chip is powered on, the protective structure will melt first, which can prevent the temperature of the traces from becoming too high, causing the circuit board to catch fire or carbonize, thereby reducing losses.
[0006] The protective structure can be made of a single metal or an alloy, and its melting point is between 260°C and 450°C. More specifically, the material of the protective structure can be, but is not limited to, one of zinc, cadmium, tin-antimony, tin-lead, lead-antimony, aluminum-magnesium, or aluminum-antimony.
[0007] It is worth mentioning that the room temperature resistivity of the protection structure is <120 nΩ*m, to ensure that the temperature generated by the protection structure is low when the current passing through it is normal, so as to avoid affecting the normal operation of the chip. The room temperature resistivity of the protection structure can be, but is not limited to, 110 nΩ*m, 90 nΩ*m, or 85 nΩ*m; no specific limitation is made here.
[0008] In one possible embodiment, a via can be provided on the dielectric layer, the via can extend along the thickness direction of the dielectric layer, a protective structure can be disposed in the via, and the two ends of the protective structure can be connected to the first trace layer and the second trace layer respectively, so as to ensure that the current flowing through the chip can reach the chip connected to the first trace layer or the second trace layer through the protective structure.
[0009] In the above embodiments, in order to ensure that the first wiring layer and the second wiring layer can be stably connected to the protective structure, a first connection terminal can be provided on the first wiring layer, and a second connection terminal can be provided on the second wiring layer. The first connection terminal and the second connection terminal are provided at both ends of the via. The first connection terminal can be electrically connected to one end of the protective structure, and the second connection terminal can be electrically connected to the other end of the protective structure.
[0010] The materials of the first and second connecting terminals can be, but are not limited to, copper, aluminum, or stainless steel.
[0011] In the above embodiments, when specifically setting the protective structure, the shape of the protective structure can be various, such as: the shape of the protective structure is cylindrical, rectangular or triangular.
[0012] In one possible embodiment, the chip can be packaged inside the circuit board. The chip can be electrically connected to the first trace layer, that is, the chip is located on the side of the first trace layer facing the second trace layer. When the chip is powered on, the current enters the chip through the second trace layer, the connection structure, and the first trace layer. When the chip is short-circuited, the current flowing through the connection structure increases. When the temperature of the connection structure increases to the melting point of the connection structure, the connection structure melts, thereby preventing the temperature of the part of the current passing through the first trace layer and the second trace layer from becoming too high, which could cause the circuit board to catch fire or carbonize. This prevents other devices connected to the circuit board from being damaged, thereby reducing losses.
[0013] It should be noted that the chip is packaged inside the circuit board and can be electrically connected to the second trace layer.
[0014] In one possible embodiment, the chip may also be packaged on the outside of the circuit board, with pins on the chip connected to a first or second trace layer. When the chip is connected to the first trace layer, the pins face the first trace layer; when the chip is connected to the second trace layer, the pins face the second trace layer.
[0015] The chip is packaged on the outside of the circuit board. When the chip is connected to the first trace layer, the pins on the chip can face away from the first trace layer, and the pins are electrically connected to the first trace layer through leads. When the chip is connected to the second trace layer, the pins on the chip can face away from the second trace layer, and the pins are connected to the second trace layer through leads.
[0016] In the above embodiments, the first routing layer may have multiple first routing lines, and the second routing layer may have multiple second routing lines. The multiple first routing lines and multiple second routing lines can be configured in a one-to-one correspondence. Specifically, when the chip is packaged on the circuit board, the number of chips can be one or multiple. Correspondingly, one or more vias can be provided on the dielectric layer, and at least one via can be provided between each corresponding first routing line and second routing line. Each corresponding first routing line and second routing line can correspond to one chip.
[0017] Secondly, this application also provides an electronic device, which includes a housing and an encapsulation structure as described in any of the first technical solutions, wherein the encapsulation structure can be disposed within the housing. The electronic device having this encapsulation structure produces the same effect as the encapsulation structure itself, and will not be elaborated further here. Attached Figure Description
[0018] Figure 1 A schematic diagram of the packaging structure provided in the embodiments of this application;
[0019] Figure 2 This is another schematic diagram of the packaging structure provided in the embodiments of this application;
[0020] Figure 3 This is another schematic diagram of the packaging structure provided in the embodiments of this application;
[0021] Figure 4 This is another schematic diagram of the packaging structure provided in the embodiments of this application.
[0022] Reference numerals: 10-Circuit board; 11-First routing layer; 110-First connection terminal; 111-Third connection terminal; 12-Dielectric layer; 13-Second routing layer; 130-Second connection terminal; 20-Protective structure; 30-Chip; 31-Pin. Detailed Implementation
[0023] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.
[0024] Power supply chips are a type of commonly used integrated chip. They can be used to boost or buck voltage. With the continuous development of electronic information technology and the expanding market for analog integrated circuits, the application of power supply chips is becoming more and more widespread. Their main application areas include computers, network communications, consumer electronics, and industrial control.
[0025] Power chips have a packaged structure, which may include a PCB and the chip packaged on the PCB. During the process of supplying power to the chip packaged on the PCB, if a short circuit occurs inside the chip, a large current will be generated. This large current, when passing through the PCB traces, will generate high temperatures, potentially causing the PCB material to carbonize or even catch fire, thus rendering the components on the PCB unusable. Currently, a common solution is to add a fuse or fuse chip to the outside of the PCB to prevent PCB damage caused by chip short circuits. However, this method increases design costs, and the fuse or fuse chip also occupies a significant amount of PCB area.
[0026] Therefore, a new packaging structure is urgently needed to solve the above problems.
[0027] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise.
[0028] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0029] Reference Figure 1This application provides a packaging structure, which includes a protective structure 20, a circuit board 10, and a chip 30 packaged in the circuit board 10. The circuit board 10 may include a dielectric layer 12, a first trace layer 11, and a second trace layer 13. The first trace layer 11 and the second trace layer 13 are located on opposite sides of the dielectric layer 12, that is, the first trace layer 11, the dielectric layer 12, and the second trace layer 13 are stacked. The protective structure 20 is disposed in the dielectric layer 13 and connects the first trace layer 11 and the second trace layer 13. The chip 30 is electrically connected to the first trace layer 11 or the second trace layer 13, and the current flowing through the protective structure 20 flows to the chip through the first trace layer 11 or the second trace layer 13. Specifically, during the power-on process of the chip 30 packaged on the circuit board 10, the current needs to flow through the protection structure 20 to the chip 30 which is electrically connected to the first trace layer 11 or the second trace layer 13. If the chip 30 is short-circuited, the current flowing through the protection structure 20, the first trace layer 11 or the second trace layer 13 and the chip 30 will increase. The increase in current will cause the temperature of the traces used to carry the current and the protection structure 20 to rise. Since the protection structure 20 is a thermoplastic material, the melting point of the thermoplastic material is lower than the melting point of the first trace layer 11 or the second trace layer 13 through which the current passes. In this way, the temperature of the protection structure 20 will reach the melting point first, and the protection structure 20 will melt first. This can prevent the temperature of the traces through which the current passes from continuing to rise, avoid the circuit board 10 from catching fire or carbonizing, and reduce losses.
[0030] The protective structure 20 is disposed within the dielectric layer 12. The protective structure 20 can melt and break when the chip 30 is short-circuited, thereby protecting the circuit board 10. Since the protective structure 20 is disposed within the dielectric layer 12, there is no need to place fuses or fuse chips on the outside of the circuit board 10, which can increase the layout area of the circuit board 10. The increased area is actually the space occupied by fuses or fuse chips. Due to the increased layout area of the circuit board 10, it is easier to place other components on the circuit board 10, thereby reducing the workload of the circuit board 10 layout design and improving the design efficiency of the circuit board 10 layout.
[0031] When specifically setting the protection structure 20, the protection structure 20 can be placed in the via of the dielectric layer 12. The protection structure 20 is part of the via, which does not require additional process flow and can reduce costs. The via can extend along the thickness direction of the dielectric layer 12. The two ends of the protection structure 20 can be electrically connected to the first routing layer 11 and the second routing layer 13 respectively, so as to ensure that the current flowing through the chip 30 can reach the chip 30 connected to the first routing layer 11 or the second routing layer 13 through the protection structure 20.
[0032] When the protective structure 20 is electrically connected to the first routing layer 11 and the second routing layer 13, one end of the protective structure 20 facing the first routing layer 11 and the other end facing the second routing layer 13 can be connected to the first routing layer 11 and the second routing layer 13 by laser drilling. Alternatively, continue to refer to Figure 1 A first connection terminal 110 is provided on the first routing layer 11, and a second connection terminal 130 is provided on the second routing layer 13. The first connection terminal 110 and the second connection terminal 130 can be located at both ends of a via. The first connection terminal 110 and the second connection terminal 130 are used to connect to both ends of the protection structure 20 so that the current powering the chip 30 can pass through the protection structure 20. The material of the first connection terminal 110 and the second connection terminal 130 can be, but is not limited to, copper, aluminum, or stainless steel.
[0033] In the above embodiments, the protective structure 20 can be made of a metallic element or an alloy. Specifically, the material of the protective structure 20 can be, but is not limited to, one of zinc, cadmium, tin-antimony, tin-lead, lead-antimony, aluminum-magnesium, or aluminum-antimony. The melting point of the protective structure 20 can be between 260°C and 450°C. Specifically, the melting point of the protective structure 20 can be 270°C, 290°C, 350°C, or 420°C. When a short circuit occurs inside the chip 30, the current flowing through the protective structure 20 increases, and the temperature of the protective structure 20 rises rapidly, allowing it to quickly reach its melting point and melt, thereby protecting the circuit board 10 and the components mounted on it.
[0034] In the above embodiments, during the power-on process of chip 30, in order to ensure that chip 30 can operate stably when no short circuit occurs, the resistivity of the protection structure 20 at room temperature can be set to <120 nΩ*m. This ensures that when the current passing through the protection structure 20 is normal, the temperature generated by the protection structure 20 is low, allowing chip 30 to operate normally. It is worth noting that the resistivity of the protection structure 20 at room temperature can be, but is not limited to, 110 nΩ*m, 90 nΩ*m, or 85 nΩ*m; no specific limitation is made here.
[0035] Furthermore, the protective structure 20 can have various shapes, such as cylindrical, rectangular, or triangular. The key is to ensure the protective structure 20 is stably positioned within the via.
[0036] In the above embodiments, when the chip is packaged on the circuit board 10, the chip 30 can be disposed in multiple different locations. For example, the chip 30 can be packaged inside the circuit board 10. For details, please refer to [link / reference]. Figure 1 , Figure 1The direction of the dashed line indicates the direction of current when the chip 30 is powered on. The chip 30 can be located on the side of the first trace layer 11 facing the second trace layer 13. Multiple third connection terminals 111 can also be provided on the side of the first trace layer 11 facing the second trace layer 13. The third connection terminals 111 can be electrically connected to the pins 31 on the chip 30. At this time, the first connection terminals 110 and the second connection terminals 130 can be respectively provided at the positions corresponding to the vias on the dielectric layer 12 on the first trace layer 11 and the second trace layer 13. The two ends of the protection structure 20 are respectively connected to the first connection terminals 110 and the second connection terminals 130. The protection structure 20 can be part of the via so that the protection structure 20 does not occupy additional space on the circuit board 10. When chip 30 is powered on, current flows into chip 30 through the second trace layer 13, the second connection terminal 130, the protection structure 20, the first connection terminal 110, and the first trace layer 11. When chip 30 experiences a short circuit, the current flowing through the second connection terminal 130, the protection structure 20, the first connection terminal 110, and the first trace layer 11 increases. This increased current raises the temperature of the protection structure 20. The temperature of the protection structure 20 first rises to its melting point, causing it to melt and break. This prevents the temperature of the second trace layer 13 and the first trace layer 11 from continuing to rise after a short circuit in chip 30, thus avoiding fire or carbonization of the circuit board 10 and reducing losses. Specifically, when packaging chip 30, it can be packaged near the via in the first trace layer 13. This brings the chip 30 closer to the protection structure 20 located in the via, allowing the protection structure 20 to respond quickly and protect the circuit board 10 in time when a short circuit occurs within chip 30. It is worth mentioning that the chip 30 is packaged in the first wiring layer 11 near the via. This can be understood as the third connection terminal 111 on the first wiring layer 11 being located near the via.
[0037] Reference Figure 2 , Figure 2The direction of the dashed line indicates the direction of current when the chip 30 is powered on. When the chip 30 is packaged inside the circuit board 10, the chip 30 can be located on the side of the first trace layer 11 facing the second trace layer 13. The pins 31 on the chip 30 are directly connected to the side of the first trace layer 11 facing the second trace layer 13. The two ends of the protection structure 20 can be directly connected to the first trace layer 11 and the second trace layer 13. The protection structure 20 is located in a via and can be part of the via so that the protection structure 20 does not occupy additional space on the circuit board 10. When chip 30 is powered on, current flows into chip 30 through the second trace layer 13, protection structure 20, and first trace layer 11. When chip 30 experiences a short circuit, the current flowing through the second trace layer 13, protection structure 20, and first trace layer 11 increases. This increased current raises the temperature of protection structure 20. The temperature of protection structure 20 first rises to its melting point, causing it to melt and break. This prevents the temperature of the second trace layer 13 and first trace layer 11 from rising further, thus avoiding fire or carbonization of circuit board 10 and reducing losses. Specifically, when packaging the chip, it can be packaged near the via in the first trace layer 11 so that protection structure 20 can respond quickly and protect circuit board 10 in a timely manner when a short circuit occurs within chip 30.
[0038] It should be noted that when the chip 30 is specifically packaged in the circuit board 10, the chip 30 can also be electrically connected to the second wiring layer 13. The effect produced is the same as that of the chip 30 being placed on the first wiring layer 11, which will not be elaborated here.
[0039] Reference Figure 3 , Figure 3The direction of the dashed line indicates the direction of current when the chip 30 is powered on. The chip 30 can also be packaged on the outside of the circuit board 10. Specifically, the chip 30 can be connected to the first trace layer 11 and the second trace layer 13. Taking the connection of the chip 30 to the first trace layer 11 as an example: the pin 31 on the chip 30 can be located on the side facing the first trace layer 11, and the first connection terminal 110 and the second connection terminal 130 can be respectively provided at the positions corresponding to the vias on the dielectric layer 12 on the first trace layer 11 and the second trace layer 13. The two ends of the protection structure 20 are respectively connected to the first connection terminal 110 and the second connection terminal 130. The protection structure 20 can be used as part of the via so that the protection structure 20 does not occupy additional space on the circuit board 10. When chip 30 is powered on, current flows into chip 30 through the second trace layer 13, the second connection terminal 130, the protection structure 20, the first connection terminal 110, and the first trace layer 11. When chip 30 is short-circuited, the current passing through the second trace layer 13, the protection structure 20, and the first trace layer 11 will increase. The increased current will cause the temperature of the protection structure to rise. The temperature of the protection structure 20 will first rise to the melting point of the protection structure 20, and then the protection structure 20 will melt. This can prevent the temperature of the second trace layer 13 and the first trace layer 11 from continuing to rise, thus avoiding the circuit board 10 from catching fire or carbonizing, and reducing losses.
[0040] Reference Figure 4 , Figure 4 The direction of the dashed line indicates the direction of current when the chip 30 is powered on. When the chip 30 is also packaged on the outside of the circuit board 10, the pins 31 on the chip 30 can face away from the first trace layer 11. The pins 31 are electrically connected to the first trace layer 11 through leads. The first connection terminal 110 and the second connection terminal 130 can be respectively provided at the positions corresponding to the vias on the dielectric layer 12 on the first trace layer 11 and the second trace layer 13. The two ends of the protection structure 20 are respectively connected to the first connection terminal 110 and the second connection terminal 130. The protection structure 20 can be part of the via so that the protection structure 20 does not occupy additional space on the circuit board. When chip 30 is powered on, current can pass through the second trace layer 13, the protection structure 20, the first trace layer 11, and the lead into chip 30. When chip 30 is short-circuited, the current passing through the second trace layer 13, the protection structure 20, the first trace layer 11, and the lead will increase. The increased current will cause the temperature of the protection structure 20 to rise. The temperature of the protection structure 20 will first rise to the melting point of the protection structure 20, and then the protection structure 20 will melt. This can prevent the temperature of the second trace layer 13 and the first trace layer 11 from continuing to rise, thus avoiding the circuit board 10 from catching fire or carbonizing, and reducing losses.
[0041] When the chip 30 is placed on the outside of the circuit board 10, the two ends of the protection structure 20 can also be electrically connected to the first wiring layer 11 and the second wiring layer 13 without the first connection terminal 110 and the second connection terminal 130. That is, the two ends of the protection structure 20 can be directly electrically connected to the first wiring layer 11 and the second wiring layer 13.
[0042] In the above embodiments, the first routing layer 11 may have multiple first routing lines, and the second routing layer 13 may have multiple second routing lines. The multiple first routing lines and multiple second routing lines can be configured in a one-to-one correspondence. Specifically, when the chip 30 is packaged on the circuit board, the number of chips 30 can be one or multiple. Correspondingly, one or more vias can be provided on the dielectric layer 12, and at least one via can be provided between each corresponding first routing line and second routing line. Each corresponding first routing line and second routing line can correspond to one chip 30.
[0043] Secondly, this application also provides an electronic device, which includes a housing and an encapsulation structure as described in any of the first technical solutions. The encapsulation structure can be disposed within the housing. The electronic device with this encapsulation structure produces the same effect as the encapsulation structure itself, and will not be elaborated further here. The electronic device can be a power chip, or a computer or mobile phone incorporating the power chip, etc.
[0044] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A packaging structure, characterized in that, include: A circuit board, the circuit board comprising a first trace layer, a dielectric layer and a second trace layer stacked together; A protective structure is located within the dielectric layer, and the protective structure is used to electrically connect the first trace layer and the second trace layer. A chip, which is packaged on the circuit board and electrically connected to the first trace layer or the second trace layer, wherein the current flowing through the protective structure flows to the chip through the first trace layer or the second trace layer; The protective structure is made of a hot-melt material, and the melting point of the hot-melt material is lower than the melting point of the first or second trace layer through which the current passes, so that the protective structure melts when the chip is short-circuited. A via is provided on the dielectric layer, the via extends along the thickness direction of the dielectric layer, and the protective structure is disposed on the via; A first connection terminal is provided on the first wiring layer, and a second connection terminal is provided on the second wiring layer. The first connection terminal and the second connection terminal correspond to the via. The first connection terminal and the second connection terminal are electrically connected to both ends of the protective structure, respectively. The chip is packaged within the circuit board.
2. The packaging structure as described in claim 1, characterized in that, The protective structure is a metallic element or alloy, and the melting point of the protective structure is 260℃~450℃.
3. The packaging structure as described in claim 1, characterized in that, The resistivity of the protective structure at room temperature is <120 nΩ. m.
4. The packaging structure according to any one of claims 1 to 3, characterized in that, The chip is packaged on the outside of the circuit board, with the pins on the chip facing the circuit board, and the pins on the chip are electrically connected to the first trace layer or the second trace layer.
5. The packaging structure according to any one of claims 1 to 3, characterized in that, The chip is packaged on the outside of the circuit board, with the pins on the circuit board facing away from the circuit board. The pins on the chip are electrically connected to the first trace layer or the second trace layer via leads.
6. The packaging structure according to any one of claims 1 to 3, characterized in that, The first routing layer has multiple first traces, and the second routing layer has multiple second traces. The multiple first traces and the multiple second traces are arranged in a one-to-one correspondence. At least one of the protection structures can be provided between each pair of first traces and second traces.
7. An electronic device, characterized in that, It includes a housing and an encapsulation structure as described in any one of claims 1 to 6, wherein the encapsulation structure is disposed within the housing.