Array substrate and display panel

Abstract

The present invention provides an array substrate and a display panel. By making the gate layer located between the first active layer and the second active layer at least partially overlap with the first active layer and the second active layer, the area occupied by the first active layer, the second active layer and the gate layer is saved, thereby increasing the design area of ​​the sub-pixels and thus improving the aperture ratio.

Description

Technical Field

[0001] This invention relates to the field of display technology, specifically to an array substrate and a display panel. Background Technology

[0002] The smaller the aperture ratio of a display panel, the smaller the area available for display, which affects the sharpness of the displayed image. Therefore, increasing the aperture ratio of the display panel is key to improving the image quality. Summary of the Invention

[0003] This invention provides an array substrate and a display panel that can improve aperture ratio.

[0004] This invention provides an array substrate comprising a first active layer, a second active layer, a gate layer, a first electrode, and a second electrode. The second active layer is located on the first active layer, the gate layer is located between the first and second active layers, the first electrode is located between the first and gate layers and electrically connected to the first active layer, and the second electrode is located on the side of the second active layer away from the gate layer and electrically connected to the second active layer. The gate layer at least partially overlaps with the first active layer, and the gate layer at least partially overlaps with the second active layer.

[0005] Optionally, in some embodiments of this application, the first active layer and the second active layer overlap, and the second active layer overlaps with the gate layer.

[0006] Optionally, in some embodiments of this application, the mobility of the first active layer is greater than that of the second active layer, and the area of ​​the first electrode is greater than that of the second electrode.

[0007] Optionally, in some embodiments of this application, the ratio of the mobility of the first active layer to the mobility of the second active layer is equal to the ratio of the area of ​​the first electrode to the area of ​​the second electrode.

[0008] Optionally, in some embodiments of this application, the ratio of the area of ​​the first electrode to the area of ​​the second electrode is 2:1 to 10:1.

[0009] Optionally, in some embodiments of this application, the first electrode and the second electrode do not overlap.

[0010] Optionally, in some embodiments of this application, the array substrate further includes a first conductive layer and a second conductive layer. The first conductive layer is located between the first active layer and the first electrode, and includes a first source and a first drain. The first source is electrically connected to one end of the first active layer, the first drain is electrically connected to the other end of the first active layer, and the first drain is electrically connected to the first electrode. The second conductive layer is located between the second active layer and the second electrode, and includes a second source and a second drain. The second source is electrically connected to one end of the second active layer, the second drain is electrically connected to the other end of the second active layer, and the second drain is electrically connected to the second electrode.

[0011] Optionally, in some embodiments of this application, the second source electrode is also electrically connected to the first source electrode, and the array substrate further includes a first insulating layer, a second insulating layer, and a first interlayer dielectric layer. The first insulating layer is located between the first electrode and the gate layer, the second insulating layer is located between the gate layer and the second active layer, and the first interlayer dielectric layer is located between the second active layer and the second conductive layer. The second source electrode is electrically connected to one end of the second active layer through a first via penetrating the first interlayer dielectric layer, and the second source electrode is electrically connected to the first source electrode through a second via penetrating the first interlayer dielectric layer, the second insulating layer, and the first insulating layer; the second drain electrode is electrically connected to the other end of the second active layer through a third via penetrating the first interlayer dielectric layer.

[0012] Optionally, in some embodiments of this application, the first drain is in direct contact with the first electrode, and the second drain is in direct contact with the second electrode.

[0013] Optionally, in some embodiments of this application, the array substrate further includes a second interlayer dielectric layer, which is located between the first active layer and the first conductive layer. The first source is electrically connected to one end of the first active layer through a fourth via penetrating the second interlayer dielectric layer, and the first drain is electrically connected to the other end of the first active layer through a fifth via penetrating the second interlayer dielectric layer.

[0014] The present invention also provides a display panel, the display panel comprising any of the above-described array substrates and a color filter, the color filter comprising a first color filter unit, a second color filter unit, and a black matrix. The first color filter unit overlaps with the first electrode, the second color filter unit overlaps with the second electrode, and the black matrix overlaps with the first active layer and the second active layer.

[0015] Optionally, in some embodiments of this application, the display panel further includes a plurality of sub-pixels, each sub-pixel including a first electrode and a second electrode. The first color filter unit and the second color filter unit corresponding to the first electrode and the second electrode of the same sub-pixel have the same color.

[0016] The present invention provides an array substrate and a display panel. By making the gate layer located between the first active layer and the second active layer at least partially overlap with the first active layer and the second active layer, the area occupied by the first active layer, the second active layer and the gate layer is reduced, which is beneficial to increasing the design area of ​​the sub-pixels, thereby improving the aperture ratio. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figures 1A to 1D This is a schematic diagram of the structure of the array substrate provided in an embodiment of the present invention;

[0019] Figure 2A This is a flowchart illustrating the fabrication process of the array substrate provided in an embodiment of the present invention;

[0020] Figures 2B to 2I This is a schematic diagram of the fabrication process of the array substrate provided in an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of the structure of the display panel provided in an embodiment of the present invention;

[0022] Figures 4A-4B This is a schematic diagram of the structure of the color filter provided in an embodiment of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0024] Specifically, such as Figures 1A to 1D This is a schematic diagram of the structure of an array substrate provided in an embodiment of the present invention. The embodiment of the present invention provides an array substrate, which includes a first active layer AL1, a second active layer AL2, a gate layer GL, a first electrode E1, and a second electrode E2.

[0025] Optionally, the material used to fabricate the first active layer AL1 includes silicon semiconductor materials, oxide semiconductor materials, etc. Optionally, the silicon semiconductor material includes polycrystalline silicon, amorphous silicon, monocrystalline silicon, etc., and the oxide semiconductor material may include indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), or indium gallium zinc tin oxide (IGZTO), etc. Optionally, the first active layer AL1 may be fabricated using a low-temperature polycrystalline silicon process.

[0026] The second active layer AL2 is located on the first active layer AL1. Optionally, the material used to fabricate the second active layer AL2 includes silicon semiconductor materials, oxide semiconductor materials, etc.

[0027] Optionally, the materials used to prepare the first active layer AL1 and the second active layer AL2 can be the same, such as the first active layer AL1 and the second active layer AL2 being both silicon semiconductor materials or both being oxide semiconductor materials.

[0028] Optionally, the materials used to fabricate the first active layer AL1 and the second active layer AL2 can be different. Optionally, the first active layer AL1 is fabricated using a low-temperature polycrystalline silicon process, while the second active layer AL2 is fabricated using amorphous silicon or oxide semiconductor materials. Since amorphous silicon and oxide semiconductor materials have low mobility (typically around 1 cm² / Vs and 10 cm² / Vs, respectively), they help to achieve optimal device performance at low refresh rates and reduce power consumption. Active layers fabricated using a low-temperature polycrystalline silicon process have higher mobility (typically above 100 cm² / Vs), making them suitable for devices with high refresh rates and high resolutions. Therefore, using different semiconductor materials for the first active layer AL1 and the second active layer AL2 can balance the performance of both, which is beneficial for achieving variable refresh rates (i.e., refresh rates varying between high and low refresh rates) and high-resolution designs.

[0029] The gate layer GL is located between the first active layer AL1 and the second active layer AL2.

[0030] The first electrode E1 is located between the first active layer AL1 and the gate layer GL, and is electrically connected to the first active layer AL1. The second electrode E2 is located on the side of the second active layer AL2 away from the gate layer GL, and is electrically connected to the second active layer AL2.

[0031] The gate layer GL at least partially overlaps with the first active layer AL1, and the gate layer GL at least partially overlaps with the second active layer AL2, so as to reduce the area occupied by the first active layer AL1, the second active layer AL2 and the gate layer GL, which is beneficial to increasing the design area of ​​the sub-pixel, thereby improving the aperture ratio.

[0032] Optionally, the first active layer AL1 and the second active layer AL2 overlap, and the second active layer AL2 overlaps with the gate layer GL, so as to further reduce the area occupied by the first active layer AL1, the second active layer AL2 and the gate layer GL.

[0033] Optionally, the mobility of the first active layer is greater than that of the second active layer, and the area of ​​the first electrode E1 is greater than that of the second electrode E2; or the mobility of the first active layer is less than that of the second active layer, and the area of ​​the first electrode E1 is less than that of the second electrode E2, so as to reduce power consumption and improve the display difference problem.

[0034] Optionally, the ratio of the mobility of the first active layer to the mobility of the second active layer is equal to the ratio of the area of ​​the first electrode E1 to the area of ​​the second electrode E2, in order to optimize the display quality.

[0035] Optionally, the ratio of the area of ​​the first electrode E1 to the area of ​​the second electrode E2 is 2:1 to 10:1.

[0036] It should be noted that, Figures 1A-1B The first electrode E1 and the second electrode E2 shown in the array substrate are only used to indicate the relative positional relationship between the film layers containing the first electrode E1 and the second electrode E2. In practical applications, the first electrode E1 and the second electrode E2 can be used as follows: Figures 1C to 1D As shown, the first electrode E1 and the second electrode E2 do not overlap.

[0037] Please continue reading. Figures 1A-1B The array substrate further includes a first conductive layer Ec1 and a second conductive layer Ec2.

[0038] The first conductive layer Ec1 is located between the first active layer AL1 and the first electrode E1. The first conductive layer Ec1 includes a first source S1 and a first drain D1. The first source S1 is electrically connected to one end of the first active layer AL1, the first drain D1 is electrically connected to the other end of the first active layer AL1, and the first drain D1 is electrically connected to the first electrode E1.

[0039] The second conductive layer Ec2 is located between the second active layer AL2 and the second electrode E2. The second conductive layer Ec2 includes a second source S2 and a second drain D2. The second source S2 is electrically connected to one end of the second active layer AL2, the second drain D2 is electrically connected to the other end of the second active layer AL2, and the second drain D2 is electrically connected to the second electrode E2.

[0040] Optionally, the first drain D1 is in direct contact with the first electrode E1, and the second drain D2 is in direct contact with the second electrode E2.

[0041] Optionally, the first source S1 and the first drain D1 can be configured to be on the same layer as the second source S2 and the second drain D2, and the first electrode E1 and the second electrode E2 can also be configured to be on the same layer, so as to reduce the thickness of the array substrate and adjust the loss of data signals transmitted to the first electrode E1 and the second electrode E2, thereby improving the display difference between the corresponding portion of the first electrode E1 and the corresponding portion of the second electrode E2.

[0042] Optionally, the array substrate further includes a third electrode E3 located on the second electrode E2, the third electrode E3 including a common electrode for transmitting a reference voltage.

[0043] Please continue reading. Figures 1A-1B The array substrate further includes a substrate 100, a first insulating layer 101, a second insulating layer 102, a first interlayer dielectric layer 103, and a passivation layer 104.

[0044] Optionally, the substrate 100 includes a rigid substrate and a flexible substrate. The first insulating layer 101 is located between the first electrode E1 and the gate layer GL, the second insulating layer 102 is located between the gate layer GL and the second active layer AL2; the first interlayer dielectric layer 103 is located between the second active layer AL2 and the second conductive layer Ec2, and the passivation layer 104 is located between the second electrode E2 and the third electrode E3.

[0045] The second source S2 is electrically connected to the second active layer AL2 through a first via penetrating the first interlayer dielectric layer 103; the second drain D2 is electrically connected to the other end of the second active layer AL2 through a third via penetrating the first interlayer dielectric layer 103.

[0046] Optionally, the second source S2 is also electrically connected to the first source S1, and the second source S2 is electrically connected to the first source S1 through a second via penetrating the first interlayer dielectric layer 103, the second insulating layer 102 and the first insulating layer 101.

[0047] The materials, thicknesses, and fabrication processes for the substrate 100, the first insulating layer 101, the second insulating layer 102, the first interlayer dielectric layer 103, and the passivation layer 104 can all be based on existing technologies and will not be described in detail here. Optionally, the array substrate further includes a buffer layer 106 located between the first active layer and the substrate 100.

[0048] Optionally, the array substrate further includes a second interlayer dielectric layer 105, which is located between the first active layer AL1 and the first conductive layer Ec1. The first source S1 is electrically connected to one end of the first active layer AL1 through a fourth via penetrating the second interlayer dielectric layer 105, and the first drain D1 is electrically connected to the other end of the first active layer AL1 through a fifth via penetrating the second interlayer dielectric layer 105. Figure 1B As shown.

[0049] Optionally, the array substrate further includes a buffer layer 106 located between the substrate 100 and the first active layer, as well as other parts not shown (such as polarizers, alignment layers, etc.).

[0050] Figure 2A This is a flowchart illustrating the fabrication process of the array substrate provided in an embodiment of the present invention. Figures 2B to 2I This is a schematic diagram of the fabrication process of an array substrate provided in an embodiment of the present invention; the present invention also provides a method for fabricating an array substrate, the method comprising:

[0051] Step S100: Provide a substrate 100, and fabricate a first active layer AL1 on the substrate 100, such as... Figure 2B As shown.

[0052] Step S200: Fabricate a first electrode E1, which is electrically connected to the first active layer AL1, such as... Figure 2D As shown.

[0053] Step S300: Fabricate a gate layer GL, wherein the gate layer GL at least partially overlaps with the first active layer AL1, such as... Figure 2E As shown.

[0054] Step S400: Prepare a second active layer AL2, wherein the second active layer AL2 at least partially overlaps with the gate layer GL, such as... Figure 2F As shown;

[0055] Step S500: Fabricate a second electrode E2, which is electrically connected to the second active layer AL2, such as... Figure 2H As shown.

[0056] Optionally, before step S200, the method further includes: fabricating a first conductive layer Ec1 on the first active layer. The first conductive layer Ec1 includes a first source S1 and a first drain D1, the first source S1 being electrically connected to one end of the first active layer AL1, and the first drain D1 being electrically connected to the other end of the first active layer AL1, as shown below. Figure 2C As shown. The first electrode E1 is electrically connected to the first active layer AL1 through the first drain D1.

[0057] Optionally, after step S200, the method further includes: forming a first insulating layer 101 on the first electrode E1, wherein the gate layer GL is located on the first insulating layer 101, as shown below. Figure 2E As shown.

[0058] Optionally, before fabricating the first conductive layer Ec1, the method further includes: fabricating a second interlayer dielectric layer 105 on the first active layer AL1. The first conductive layer Ec1 is located on the second interlayer dielectric layer 105, the first source S1 is electrically connected to one end of the first active layer AL1 through a fourth via penetrating the second interlayer dielectric layer 105, and the first drain D1 is electrically connected to the other end of the first active layer AL1 through a fifth via penetrating the second interlayer dielectric layer 105.

[0059] Before step S400, the method further includes: fabricating a second insulating layer 102 on the gate layer GL, wherein the second active layer AL2 is located on the second insulating layer 102, as shown below. Figure 2F As shown.

[0060] Optionally, after step S400, the method further includes: fabricating a first interlayer dielectric layer 103 and a second conductive layer Ec2 on the second active layer AL2. The second conductive layer Ec2 includes a second source S2 and a second drain D2. The second source S2 is electrically connected to the second active layer AL2 through a first via penetrating the first interlayer dielectric layer 103; the second drain D2 is electrically connected to the other end of the second active layer AL2 through a third via penetrating the first interlayer dielectric layer 103, as shown below. Figure 2G As shown. The second electrode E2 is electrically connected to the second active layer AL2 through the second drain D2, as... Figure 2H As shown.

[0061] Optionally, after step S500, the method further includes: fabricating a passivation layer 104 and a third electrode E3 on the second electrode E2. The third electrode E3 is located on the passivation layer 104 and includes a common electrode, such as... Figure 2I As shown.

[0062] Optionally, before step S100, a buffer layer 106 is further prepared on the substrate 100.

[0063] The present invention also provides a display panel, the display panel comprising any of the above-described array substrates and an array substrate obtained by any of the above-described array substrate preparation methods.

[0064] like Figure 3This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. The display panel includes any of the above-mentioned array substrate 400 and a color filter. Optionally, the display panel further includes a color filter substrate 500, a liquid crystal 401, a frame adhesive 402, and backlight modules, polarizers, etc. (not shown). The array substrate 400 and the color filter substrate 500 are disposed opposite to each other, and the liquid crystal 401 and the frame adhesive 402 are located between the array substrate 400 and the color filter substrate 500.

[0065] Optionally, the color filter may be disposed in the array substrate. Optionally, when the array substrate is applied in a display panel, the color filter may also be disposed in a color filter substrate disposed opposite to the array substrate.

[0066] Figures 4A-4B This is a schematic diagram of the structure of a color filter provided in an embodiment of the present invention; wherein, Figure 4A It corresponds Figure 1C The color filter of the array substrate shown; Figure 4B It corresponds Figure 1D The array substrate shown has a color filter. The color filter includes a plurality of color filter units (CUs) and a black matrix (BM) located between the plurality of color filter units (CUs). The color filter unit (CU) includes a first color filter unit (CU1) and a second color filter unit (CU2). The first color filter unit (CU1) overlaps with the first electrode (E1), the second color filter unit (CU2) overlaps with the second electrode (E2), and the black matrix (BM) overlaps with the first active layer (AL1) and the second active layer (AL2).

[0067] Taking the display panel comprising multiple sub-pixels as an example, the application of the array substrate 400 will be explained. For details, please refer to [link to relevant documentation]. Figures 1A to 1D and Figures 4A-4B The display panel includes multiple scan lines SL, multiple data lines DL, multiple sub-pixels, and multiple pixel driving circuits.

[0068] Optionally, each scan line SL extends along a first direction x, and multiple scan lines SL are arranged along a second direction y. Optionally, multiple scan lines SL and multiple data lines DL are arranged intersectingly. Optionally, each data line DL extends along the second direction y, and multiple data lines DL are arranged along the first direction x. Optionally, multiple scan lines SL may be on the same layer as the gate layer GL, and multiple data lines DL may be on the same layer as the first conductive layer Ec1 and / or the second conductive layer Ec2.

[0069] Optionally, a plurality of the sub-pixel arrays are arranged. The plurality of sub-pixels include a plurality of pixel electrodes, each of the pixel electrodes including a first electrode E1 and a second electrode E2.

[0070] Optionally, the first electrode E1 and the second electrode E2 of each sub-pixel are located on both sides of a scan line SL, so that the first electrode E1 and the second electrode E2 share a scan signal.

[0071] Optionally, at least one data line DL is provided between two adjacent sub-pixels along the first direction x. A scan line SL may be provided between two adjacent sub-pixels along the second direction y.

[0072] Optionally, when the first electrode E1 and the second electrode E2 of each sub-pixel are located on both sides of a scan line SL, so that the first electrode E1 and the second electrode E2 share a scan signal, the scan line SL may not be provided between two adjacent sub-pixels along the second direction y, thereby reducing the number of scan lines, which is beneficial to increasing the design area of ​​the sub-pixel and improving the aperture ratio.

[0073] Optionally, the first active layer AL1 and the second active layer AL2, in addition to employing Figures 1C to 1D In addition to the form shown, the first active layer AL1 and the second active layer AL2 may be located on opposite sides of the same scan line SL, such that the first active layer AL1 may be located between the first electrode E1 and the scan line SL, and the second active layer AL2 may be located between the second electrode E2 and the scan line SL.

[0074] The plurality of pixel driving circuits are electrically connected to the plurality of sub-pixels, and each pixel driving circuit includes a first transistor T1 and a second transistor T2.

[0075] Optionally, the first transistor T1 includes a first active layer AL1, a gate layer GL, a first source S1, and a first drain D1, and the second transistor T2 includes a second active layer AL2, a gate layer GL, a second source S2, and a second drain D2, thereby making the first electrode E1 electrically connected to the first transistor T1, the second electrode E2 electrically connected to the second transistor T2, and the first transistor T1 and the second transistor T2 share the same gate layer GL. Compared to the design where the first active layer AL1 of the first transistor T1 and the second active layer AL2 of the second transistor T2 each have a corresponding gate layer, this application makes the first transistor T1 and the second transistor T2 share the same gate layer GL, which can reduce the area occupied by the first transistor T1 and the second transistor T2, and the design area available for the sub-pixel will be correspondingly larger, thus increasing the design area of ​​the sub-pixel. The increased design area of ​​the sub-pixel allows for an increased display area for the display image, thereby improving the aperture ratio.

[0076] Understandably, the mobility of the first transistor T1 and the second transistor T2 can be adjusted by changing the materials and fabrication processes of the first active layer AL1 and the second active layer AL2. The gate layer GL included in the first transistor T1 and the second transistor T2 can be used to form the gates of the first transistor T1 and the second transistor T2 respectively.

[0077] When the areas of the first electrode E1 and the second electrode E2 are the same, and the first transistor T1 and the second transistor T2 do not share the same gate layer GL, if the mobilities of the first active layer AL1 and the second active layer AL2 are different, the gate voltage applied to the first transistor T1 and the gate voltage applied to the second transistor T2 will also be different (i.e., one of the gate voltages applied to the first transistor T1 and the second transistor T2 will be larger, and the other smaller. Generally, transistors with active layers containing high mobility have lower gate voltages, and transistors with active layers containing low mobility have higher gate voltages). This increases the complexity of the control circuit and is not conducive to reducing power consumption. If the areas of the first electrode E1 and the second electrode E2 are the same, and the first transistor T1 and the second transistor T2 do not share the same gate layer GL, and the mobility of the first active layer AL1 and the second active layer AL2 is different, then setting the gate voltage applied to the first transistor T1 and the gate voltage applied to the second transistor T2 to be the same will result in a display difference between the portion of the sub-pixel corresponding to the first electrode E1 and the portion of the sub-pixel corresponding to the second electrode E2 when the pixel driving circuit drives the sub-pixel to work, thus affecting the display quality.

[0078] Therefore, to reduce power consumption while improving the display difference between the portion of the sub-pixel corresponding to the first electrode E1 and the portion corresponding to the second electrode E2 caused by the different mobility of the first active layer AL1 and the second active layer AL2, while the first transistor T1 and the second transistor T2 apply the same gate voltage, the areas of the first electrode E1 and the second electrode E2 can be adjusted according to the mobility of the first active layer AL1 and the second active layer AL2. Optionally, the ratio of the area of ​​the first electrode E1 to the area of ​​the second electrode E2 can be adjusted according to the ratio of the mobility of the first active layer AL1 to the mobility of the second active layer AL2.

[0079] Optionally, the area of ​​the first electrode E1 is positively correlated with the mobility of the first active layer AL1; the area of ​​the second electrode E2 is positively correlated with the mobility of the second active layer AL2, so that the areas of the first electrode E1 and the second electrode E2 are adjusted according to the mobility of the first active layer AL1 and the second active layer AL2, thereby reducing power consumption by adjusting the gate voltage applied to the first transistor T1 and the gate voltage applied to the second transistor T2, while improving the problem of display differences between the portion of the sub-pixel corresponding to the first electrode E1 and the portion corresponding to the second electrode E2 caused by the different mobility of the first active layer AL1 and the second active layer AL2, while the same gate voltage is applied to the first transistor T1 and the second transistor T2.

[0080] Optionally, the mobility of the first active layer AL1 is greater than the mobility of the second active layer AL2, and the area of ​​the first electrode E1 is greater than the area of ​​the second electrode E2; or the mobility of the first active layer AL1 is less than the mobility of the second active layer AL2, and the area of ​​the first electrode E1 is less than the area of ​​the second electrode E2.

[0081] By adjusting the areas of the first electrode E1 and the second electrode E2 according to the mobility of the first active layer AL1 and the second active layer AL2, the gate voltage applied to the transistor electrically connected to the one with the smaller area of ​​the first electrode E1 and the second electrode E2 can be reduced (i.e., if the area of ​​the first electrode E1 is smaller than the area of ​​the second electrode; correspondingly, the mobility of the first active layer AL1 is smaller than the mobility of the second active layer AL2, then the gate voltage applied to the first transistor T1 can be reduced, and even the gate voltage level applied to the first transistor T1 can be reduced to the gate voltage level applied to the second transistor T2), thereby reducing power consumption.

[0082] Since the reduction in the gate voltage applied to the first transistor T1 and the gate voltage applied to the second transistor T2 is due to one of the first electrode E1 and the second electrode E2 having a smaller area, it indicates that the proportion of the one with the smaller area in the sub-pixel will be smaller. Therefore, the area ratio of the display difference exhibited by the sub-pixel will be reduced (i.e., if the area of ​​the first electrode E1 is smaller than the area of ​​the second electrode E2, then the proportion of the sub-pixel corresponding to the first electrode E1 in the sub-pixel will be smaller than that of the second electrode E2). The proportion of the corresponding part; therefore, when there is a display difference between the part of the sub-pixel corresponding to the first electrode E1 and the part of the sub-pixel corresponding to the second electrode E2, the display performance of the sub-pixel is also dominated by the part of the sub-pixel corresponding to the second electrode E2. Therefore, compared to the design where the area of ​​the part of the sub-pixel corresponding to the first electrode E1 and the area of ​​the part of the sub-pixel corresponding to the second electrode E2 are 1:1, the area of ​​the part of the sub-pixel corresponding to the first electrode E1 and the area of ​​the part of the sub-pixel corresponding to the second electrode E2 will be 1:x; where x is greater than 1, so the display difference area ratio exhibited by the sub-pixel can be reduced, thus improving display quality while reducing power consumption.

[0083] Optionally, the ratio of the mobility of the first active layer AL1 to the mobility of the second active layer AL2 is equal to the ratio of the area of ​​the first electrode E1 to the area of ​​the second electrode E2. This allows the ratio of the area of ​​the first electrode E1 to the area of ​​the second electrode E2 to be adjusted according to the charging capabilities of the first transistor T1 and the second transistor T2, so that both the portion of the sub-pixel corresponding to the first electrode E1 and the portion corresponding to the second electrode E2 can achieve better display performance, thereby optimizing the display quality.

[0084] Optionally, the mobility of the first active layer AL1 is greater than the mobility of the second active layer AL2, and the ratio of the area of ​​the first electrode E1 to the area of ​​the second electrode E2 is 2:1 to 10:1. Optionally, the ratio of the area of ​​the first electrode E1 to the area of ​​the second electrode E2 is 2:1, 5:2, 3:1, 7:2, 4:1, 9:2, 5:1, 11:2, 6:1, 13:2, 7:1, 15:2, 8:1, 17:2, 9:1, 19:2, or 10:1.

[0085] Optionally, based on existing fabrication process conditions, the ratio of the mobility of the first active layer AL1 to the mobility of the second active layer AL2 is 2:1, and the ratio of the area of ​​the first electrode E1 to the area of ​​the second electrode E2 is 2:1.

[0086] It is understandable that the mobility of the first active layer AL1 may be less than the mobility of the second active layer AL2; correspondingly, the ratio of the area of ​​the first electrode E1 to the area of ​​the second electrode E2 is 1:2 to 1:10.

[0087] The gate voltage applied to the first transistor T1 and the gate voltage applied to the second transistor T2 are applied to the gates of the first transistor T1 and the second transistor T2 through the scan line SL. Optionally, the gate voltage applied to the first transistor T1 is equal to the gate voltage applied to the second transistor T2, so as to reduce power consumption and reduce the complexity of the control circuit.

[0088] Furthermore, setting the first source S1 and the first drain D1 to a different layer than the second source S2 and the second drain D2 allows the first transistor T1 and the second transistor T2 to have a larger overlap area, thereby reducing the area occupied by the first transistor T1 and the second transistor T2. Setting the first electrode E1 to a different layer than the second electrode E2 allows the data signals transmitted from the first transistor T1 and the second transistor T2 to the first electrode E1 and the second electrode E2 to have similar loss levels, thereby improving the display difference between the portion of the sub-pixel corresponding to the first electrode E1 and the portion corresponding to the second electrode E2.

[0089] Please continue reading. Figures 1A-1B and Figure 1C The first electrode E1 and the second electrode E2 within the same pixel electrode are electrically connected to the same data line DL via the first transistor T1 and the second transistor T2, respectively, so as to transmit the same data signal to the first electrode E1 and the second electrode E2 via the same data line DL.

[0090] Optionally, the second source S2 and the first source S1 are electrically connected to the same data line DL. Optionally, when the second source S2 and the first source S1 are electrically connected to the same data line DL, the second source S2 is electrically connected to the first source S1 through a second via penetrating the first interlayer dielectric layer 103, the second insulating layer 102, and the first insulating layer 101. Optionally, when the second source S2 and the first source S1 are electrically connected to the same data line DL, the second source S2 can also be electrically connected to the first source S1 through an intermediate electrode on the same layer as the gate layer GL.

[0091] Optionally, the first electrode E1 and the second electrode E2 can receive different data signals, such as... Figure 1D As shown, the first electrode E1 and the second electrode E2 within the same pixel electrode are electrically connected to different data lines DL via the first transistor T1 and the second transistor T2, respectively. This effectively controls the switching frequency of the first transistor T1 and the second transistor T2, as well as the voltage ratio of the first electrode E1 and the second electrode E2, based on the luminous efficiency of each sub-pixel, thereby greatly improving the uniformity of the image display transmittance. Simultaneously, since the data signals received by the different first electrodes E1 and the second electrodes E2 are different, if one of the first electrodes E1 and the second electrode E2 needs to receive a valid data signal, the data line DL electrically connected to the other of the first electrodes E1 and the second electrode E2 may not transmit that data signal, thus reducing power consumption.

[0092] Optionally, the data line DL includes a first data line (such as the first data line including...). Figure 1D The DL(n), DL(n+2), DL(n+4) in the first data line and the second data line (such as the first data line including the second data line) Figure 1D In the DL(n-1), DL(n+1), and DL(n+3), the first source S1 of the first transistor T1 is electrically connected to the first data line, and the second source S2 is electrically connected to the second data line.

[0093] Optionally, the colors displayed by the sub-pixels corresponding to the first electrode E1 and the sub-pixels corresponding to the second electrode E2 can be the same or different. Optionally, the colors displayed by the sub-pixels corresponding to the first electrode E1 include red, green, blue, yellow, white, etc.; the colors displayed by the sub-pixels corresponding to the second electrode E2 include red, green, blue, yellow, white, etc. It is understood that in order to achieve color display of the sub-pixels corresponding to the first electrode E1 and the sub-pixels corresponding to the second electrode E2, the color filter also needs to be set.

[0094] Optionally, the colors of the first color filter units CU1 and the second color filter units CU2 corresponding to the first electrode E1 and the second electrode E2 of the same sub-pixel are the same, so that the portion of the sub-pixel corresponding to the first electrode E1 and the portion corresponding to the second electrode E2 display the same color; or the colors of the first color filter units CU1 and the second color filter units CU2 corresponding to the first electrode E1 and the second electrode E2 of the same sub-pixel are different, so that the portion of the sub-pixel corresponding to the first electrode E1 and the portion corresponding to the second electrode E2 display different colors. The colors of the first color filter units CU1 corresponding to the first electrode E1 of different sub-pixels can be the same or different, and the colors of the second color filter units CU2 corresponding to the second electrode E2 of different sub-pixels can be the same or different. For example, in... Figures 1C to 1D In the image, the color of the first color filter unit CU1 corresponding to the first electrode E1 of sub-pixel P1 is red, and the color of the second color filter unit CU2 corresponding to the second electrode E2 of sub-pixel P1 is red; the color of the first color filter unit CU1 corresponding to the first electrode E1 of sub-pixel P2 is green, and the color of the second color filter unit CU2 corresponding to the second electrode E2 of sub-pixel P2 is green; the color of the first color filter unit CU1 corresponding to the first electrode E1 of sub-pixel P3 is blue, and the color of the second color filter unit CU2 corresponding to the second electrode E2 of sub-pixel P3 is blue.

[0095] Optionally, in adopting Figure 1D When designing the array substrate shown, the switching frequency and voltage distribution ratio of the transistors corresponding to the first electrode E1 and the second electrode E2 of the sub-pixels can be controlled according to the light transmittance of the color filter unit CU (e.g., the light transmittance of the color filter unit CU corresponding to the sub-pixel emitting red light is less than that of the color filter unit CU corresponding to the sub-pixel emitting green light, but greater than that of the color filter unit CU corresponding to the sub-pixel emitting blue light). This greatly improves the uniformity of the screen display transmittance. Furthermore, different voltage signals can be independently given to the parts of the sub-pixels corresponding to the first electrode E1 and the parts corresponding to the second electrode E2 to reduce power consumption.

[0096] Optionally, the first electrode E1 and the second electrode E2 may belong to different sub-pixels. Optionally, the black matrix BM also overlaps with the gate layer GL and the data line DL.

[0097] This application also provides a display device, including the aforementioned display panel. The display device includes portable display devices (such as laptops, mobile phones, etc.), fixed terminals (such as desktop computers, televisions, etc.), measuring devices (such as fitness trackers, thermometers, etc.), etc.

[0098] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An array substrate, characterized in that, include: First active layer; The second active layer is located on top of the first active layer; A gate layer is located between the first active layer and the second active layer; The first electrode is located between the first active layer and the gate layer, and is electrically connected to the first active layer; as well as The second electrode is located on the side of the second active layer away from the gate layer and is electrically connected to the second active layer. Wherein, the gate layer at least partially overlaps with the first active layer, and the gate layer at least partially overlaps with the second active layer; The mobility of the first active layer is greater than that of the second active layer, and the area of ​​the first electrode is greater than that of the second electrode.

2. The array substrate according to claim 1, characterized in that, The first active layer and the second active layer overlap, and the second active layer overlaps with the gate layer.

3. The array substrate according to claim 1, characterized in that, The ratio of the mobility of the first active layer to the mobility of the second active layer is equal to the ratio of the area of ​​the first electrode to the area of ​​the second electrode.

4. The array substrate according to claim 1, characterized in that, The ratio of the area of ​​the first electrode to the area of ​​the second electrode is 2:1 to 10:

1.

5. The array substrate according to claim 1, characterized in that, The first electrode and the second electrode do not overlap.

6. The array substrate according to claim 5, characterized in that, Also includes: A first conductive layer is located between the first active layer and the first electrode, including a first source and a first drain. The first source is electrically connected to one end of the first active layer, the first drain is electrically connected to the other end of the first active layer, and the first drain is electrically connected to the first electrode. The second conductive layer is located between the second active layer and the second electrode, and includes a second source and a second drain. The second source is electrically connected to one end of the second active layer, the second drain is electrically connected to the other end of the second active layer, and the second drain is electrically connected to the second electrode.

7. The array substrate according to claim 6, characterized in that, The second source electrode is also electrically connected to the first source electrode, and the array substrate further includes: A first insulating layer is located between the first electrode and the gate layer; A second insulating layer is located between the gate layer and the second active layer; and The first interlayer dielectric layer is located between the second active layer and the second conductive layer; The second source is electrically connected to one end of the second active layer through a first via penetrating the first interlayer dielectric layer, and the second source is electrically connected to the first source through a second via penetrating the first interlayer dielectric layer, the second insulating layer, and the first insulating layer; the second drain is electrically connected to the other end of the second active layer through a third via penetrating the first interlayer dielectric layer.

8. The array substrate according to claim 6, characterized in that, The first drain electrode is in direct contact with the first electrode, and the second drain electrode is in direct contact with the second electrode.

9. The array substrate according to claim 6, characterized in that, Also includes: The second interlayer dielectric layer is located between the first active layer and the first conductive layer. The first source electrode is electrically connected to one end of the first active layer through a fourth via penetrating the second interlayer dielectric layer, and the first drain electrode is electrically connected to the other end of the first active layer through a fifth via penetrating the second interlayer dielectric layer.

10. A display panel, characterized in that... Includes the array substrate and color filter according to any one of claims 1 to 9, wherein the color filter includes a first color filter unit, a second color filter unit, and a black matrix; Wherein, the first color filter unit overlaps with the first electrode, the second color filter unit overlaps with the second electrode, and the black matrix overlaps with the first active layer and the second active layer.

11. The display panel according to claim 10, characterized in that, Also includes: Multiple sub-pixels, each of which includes the first electrode and the second electrode; Wherein, the first color filter unit and the second color filter unit corresponding to the first electrode and the second electrode of the same sub-pixel have the same color.

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