Integrated power device with energy-harvesting gate driver

Abstract

The present disclosure relates to integrated power devices with energy harvesting gate drivers. An electronic circuit is disclosed. The electronic circuit comprises a transistor having a gate terminal, a source terminal, and a drain terminal; and a gate driver circuit comprising a pull-down transistor coupled to the gate terminal; and an input terminal arranged to receive an input signal and to produce a corresponding output signal at an output terminal coupled to the gate terminal; wherein the gate driver circuit is arranged to store energy harvested from the input signal and to use the stored energy to change a conductive state of the pull-down transistor. In one aspect, the transistor comprises gallium nitride (GaN). In another aspect, the pull-down transistor comprises GaN.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 202,973, filed July 1, 2021, entitled “Integrated Power Device with Energy Harvesting Gate Driver,” which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] The described implementation generally relates to power conversion devices, and more specifically, this implementation relates to integrated power conversion devices utilizing gallium nitride (GaN) circuitry. Background Technology

[0004] Electronic devices such as computers, servers, and televisions use one or more power conversion circuits to convert one form of electrical energy into another. Some power conversion circuits use a circuit topology called a half-bridge converter to convert high DC voltage to lower DC voltage. Because many electronic devices are sensitive to the size and efficiency of power conversion circuits, new power converters can provide relatively higher efficiency and smaller size for new electronic devices. Summary of the Invention

[0005] In some embodiments, an electronic circuit is disclosed. The electronic circuit includes: a transistor having a gate terminal, a source terminal, and a drain terminal; and a gate driver circuit including: a pull-down transistor coupled to the gate terminal; and an input terminal arranged to receive an input signal and generate a corresponding output signal at an output terminal coupled to the gate terminal; wherein the gate driver circuit is arranged to store energy collected from the input signal and to use the stored energy to change the conductivity state of the pull-down transistor.

[0006] In some implementations, the transistor comprises gallium nitride (GaN).

[0007] In some implementations, the pull-down transistor comprises GaN.

[0008] In some implementations, the gate driver circuitry comprises silicon.

[0009] In some implementations, the gate driver circuit uses the stored energy to switch the pull-down transistor from an on state to an off state.

[0010] In some implementations, the gate driver circuit and the transistor are housed within an integrated electronic package.

[0011] In some implementations, the integrated electronic package includes power input contacts, power output contacts, and input signal contacts.

[0012] In some implementations, the input signal is a pulse width modulation (PWM) signal that includes a series of on and off commands.

[0013] In some implementations, the gate driver circuit is arranged to change the conduction state of the pull-down transistor from the off state to the on state during the off command of the PWM signal.

[0014] In some embodiments, the electronic circuit includes an integrated electronic package having a first external contact, a second external contact, and a third external contact.

[0015] In some implementations, the transistor and the gate driver circuit are housed within a TO-247 package.

[0016] In some implementations, the integrated electronic package is a TO leadless (TOLL) package.

[0017] In some embodiments, the gate driver circuit includes an energy harvesting circuit coupled to the gate terminal, wherein the energy harvesting circuit is arranged to store energy harvested from the input signal and to operate the gate driver circuit using the stored energy when the PWM signal is in a shutdown command.

[0018] In some embodiments, a circuit is disclosed. The circuit includes a first transistor having a first gate terminal, a first source terminal, and a first drain terminal, and a current flow control circuit arranged to receive an input signal and, in response, transmit a corresponding output signal to the first gate terminal; wherein the current flow control circuit includes a first path and a second path, the first path having a first impedance element coupled in series with a first unidirectional current conductor oriented to allow current to flow to the first gate terminal, and the second path having a second impedance element coupled in series with a second unidirectional current conductor oriented to allow current to flow out of the first gate terminal.

[0019] In some embodiments, the circuit further includes a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, wherein the second drain terminal is coupled to the first gate terminal, and wherein the second transistor is arranged to clamp the voltage at the first gate terminal to a preset voltage value.

[0020] In some embodiments, the circuit further includes a third transistor having a third gate terminal, a third source terminal, and a third drain terminal, wherein the third source terminal is coupled to the first gate terminal, and the third drain terminal is coupled to the current flow control circuit.

[0021] In some embodiments, a circuit is disclosed. The circuit includes: a first transistor having a first gate terminal, a first source terminal, and a first drain terminal; a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, the second drain terminal being coupled to the first gate terminal; and a first control circuit coupled to the second gate terminal and arranged to change the conduction state of the second transistor from an off state to an on state in response to a voltage at the first gate terminal being lower than a first threshold voltage.

[0022] A third transistor having a third gate terminal, a third source terminal, and a third drain terminal; and a second control circuit coupled to the third gate terminal and arranged to change the conduction state of the third transistor from an off state to an on state in response to the voltage at the first gate terminal being higher than a second threshold.

[0023] In some embodiments, the second transistor is arranged to clamp the voltage at the first gate terminal to a first preset value.

[0024] In some implementations, the third transistor is arranged to clamp the voltage at the first gate terminal to a second preset value.

[0025] In some embodiments, the circuit further includes a current flow control circuit arranged to receive an input signal and, in response, transmit a corresponding output signal to the first gate terminal. The current flow control circuit includes a first path and a second path. The first path has a first impedance element coupled in series with a first unidirectional current conductor oriented to allow current to flow to the first gate terminal, and the second path has a second impedance element coupled in series with a second unidirectional current conductor oriented to allow current to flow out of the first gate terminal. Attached Figure Description

[0026] Figure 1 This illustrates the integration of GaN power devices and silicon devices in the same package according to embodiments of this disclosure;

[0027] Figure 2A schematic diagram illustrates a gate driver circuit with energy harvesting, integrated pull-up and pull-down transistors, and voltage clamping features according to an embodiment of the present disclosure;

[0028] Figure 3 It shows Figure 2 The graph shows the quiescent current at the input terminals of the gate driver circuit. Figure 2 A graph showing the gate voltage of a GaN power transistor;

[0029] Figure 4A A schematic diagram of a circuit with saturation current protection features according to an embodiment of the present disclosure is shown;

[0030] Figure 4B The illustration shows Figure 4A A graph showing how the voltage at each node in the circuit changes over time.

[0031] Figure 5 A schematic diagram of a circuit with saturation current protection features according to an embodiment of the present disclosure is shown;

[0032] Figure 6 A schematic diagram of a circuit with saturation current protection features according to an embodiment of the present disclosure is shown;

[0033] Figure 7A A schematic diagram illustrating a circuit with conduction dv / dt control characteristics according to an embodiment of the present disclosure is provided.

[0034] Figure 7B A graph illustrating the rate of change of drain-source voltage over time during the conduction period of a GaN power transistor is provided.

[0035] Figure 7C The drain-source voltage variation over time is shown. Figure 7A The rate of change of the resistance value of the external resistor in the circuit;

[0036] Figure 8 A schematic diagram illustrating a gate driver with dV / dt control circuitry and gate clamping features according to an embodiment of the present disclosure is provided.

[0037] Figure 9 A schematic diagram of a circuit with turn-off dI / dt control characteristics according to an embodiment of the present disclosure is shown;

[0038] Figure 10 A schematic diagram of a gate driver circuit with hysteresis according to an embodiment of the present disclosure is shown;

[0039] Figure 11 Explanation Figure 10 The voltage at each node within the gate circuit;

[0040] Figure 12 A schematic diagram illustrating a voltage regulator according to an embodiment of this disclosure is provided;

[0041] Figure 13 This describes an integrated GaN power device in a TO-247 package according to an embodiment of this disclosure; and

[0042] Figure 14A An integrated GaN power device according to an embodiment of this disclosure is described. Figure 14B An integrated GaN power device in a four-terminal TO-247 package according to an embodiment of the present disclosure is described. Figure 14C This invention describes an integrated GaN power device in a TO leadless (TOLL) package according to an embodiment of the present disclosure. Detailed Implementation

[0043] The circuits and related technologies disclosed herein generally relate to gallium nitride (GaN) power conversion devices. More specifically, the devices, circuits, and related technologies disclosed herein relate to GaN integrated circuits, wherein a gate driver integrated circuit (IC) can be used to harvest energy from an input pulse-width modulation (PWM) signal to power the gate driver IC, thereby eliminating the need for a power supply for the gate driver IC. In some embodiments, the gate driver IC can be integrated together with a GaN power transistor in a package to form an integrated GaN power device, wherein the integrated GaN power device can be a pin-to-pin compatible alternative to a discrete silicon power MOSFET and its drive circuitry. In various embodiments, the gate driver IC can store the energy harvested from the PWM signal and can continue to operate and drive the GaN power transistor even when the PWM signal is low, such as... Figure 1 This is further explained in the text.

[0044] In some embodiments, the gate driver IC may include various protection circuitry to keep the GaN power transistor within its safe operating region, as outlined herein and described in more detail below. More specifically, in some embodiments, the IC may include a pull-down transistor for pulling down the gate voltage of the GaN power transistor. The pull-down transistor may be integrated into the IC or integrated into the same die as the GaN transistor. The IC may drive the gate of the pull-down transistor, such as... Figure 2 This is further explained in the text.

[0045] In various embodiments, the IC may include a pull-up transistor. The pull-up transistor can enable a PWM signal to drive the gate of the GaN power transistor to a high state. In some embodiments, the IC may include a clamping circuit that can protect the GaN power transistor and the IC's internal circuitry. The clamping circuit can implement a relatively high operating voltage for PWM, such as 10V to 30V, while allowing the gate of the GaN transistor to remain within its safe operating region, such as below 6.0V. Those skilled in the art who benefit from this disclosure will understand that the operating voltage can be set to any suitable value. Figure 2 The operation of the pull-up transistor and clamping circuit is described in more detail.

[0046] In some implementations, the IC may include a saturation current protection circuit. This circuit senses the voltage at the drain of the GaN power transistor and triggers a protection circuit to prevent the GaN transistor from entering or remaining in its saturation region. As those skilled in the art will understand, GaN transistors can operate normally in their linear operating region; however, if a GaN transistor enters its saturation operating region, the drain current increases with the corresponding drain voltage, which is undesirable in power conversion applications. In some implementations, the saturation protection circuit may use a depletion-mode (D-mode) GaN transistor to sense the drain voltage of the GaN transistor and turn off the GaN transistor when saturation is sensed. The saturation protection circuit is shown in Figures 4 to 5. Figure 6 This will be discussed in detail later.

[0047] In various implementations, the IC may include a dv / dt control circuit by utilizing an external resistor connected in series with the PWM signal. The DV / dt control circuit... Figures 7A to 7C and Figure 8 This will be discussed in detail below. In various implementations, the IC may include a turn-off dI / dt control circuit by utilizing package junction line inductance. By using the turn-off dI / dt control circuit, the gate of the GaN transistor can be kept in its safe operating region, where the stress voltage on the gate of the GaN transistor can be kept at a relatively minimum. Figure 9 The dI / dt control circuit for shutdown is described in more detail.

[0048] In some implementations, the IC may include a gate drive voltage generation circuit with hysteresis to control the gate voltage of the GaN transistor, thereby reducing power consumption and increasing operating speed. The gate drive voltage generation circuit with hysteresis... Figures 10 to 11 A more detailed description is provided below.

[0049] Those skilled in the art who will benefit from this disclosure will understand that any portion and / or any combination of the features described herein can be integrated within an IC, within a GaN transistor, or the features can be partially integrated within both the IC and a GaN transistor. In various embodiments, the integrated GaN power device can operate at relatively higher frequencies than the silicon power MOSFET it replaces. Furthermore, the IC can be formed from silicon, silicon carbide, GaN, or any other suitable semiconductor material. In various embodiments, the integrated power device can be used in high-current and / or high-voltage power conversion applications, such as (but not limited to) AC-to-DC converters, and applications such as solar power conversion, automotive, and battery charging applications.

[0050] Several illustrative embodiments will now be described with reference to the accompanying drawings, which form part of the embodiments. The following description provides embodiments only and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the following description of the embodiments will provide those skilled in the art with a description of implementing one or more embodiments. It should be understood that various changes can be made to the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for illustrative purposes in order to provide a thorough understanding of certain inventive embodiments. However, it will be apparent, however, that various embodiments can be implemented without these specific details. The drawings and descriptions are not intended to be restrictive. The terms “example” or “exemplary” are used herein to mean “serves as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as superior to or better than other embodiments or designs.

[0051] Integrated GaN power package

[0052] Figure 1 An integrated GaN power device 100 according to an embodiment of this disclosure is described. For example... Figure 1 As shown, the integrated GaN power device 100 may include a GaN power transistor 114 and a gate driver integrated circuit (IC) 112 in a semiconductor package 110. By integrating the GaN power transistor 114 and the gate driver IC into a single semiconductor package 110, most package parasitic elements can be eliminated, thereby allowing the integrated GaN power device 100 to be used in high-current and high-power applications. The integrated GaN power device 100 may include a top plate 118. The drain of the GaN power transistor 114 may be coupled to the top plate 118 via a plurality of bonding lines 120, wherein the top plate 118 is coupled to a plurality of pins 102 to form the drain of the integrated GaN power device 100. The integrated GaN power device 100 may also include a die pad 116.

[0053] The source of power transistor 114 can be coupled to die pad 116 via multiple bonding wires 122. Die pad 116 can be coupled to multiple pins 104 to form the source of integrated GaN power device 100. The ground terminal of IC 112 can be coupled to pin 106 via bonding wire 126 to form a low parasitic (Kelvin) source connection of IC. The input terminal of IC can be connected to input pin 108 via bonding wire 124 to form a drive signal to the input in integrated GaN power device 100. In some embodiments, input pin 108 can be coupled to a pulse width modulation (PWM) signal to drive IC 112. IC can be coupled to GaN power transistor 114 via bonding wire 128. In many embodiments, IC can be coupled to GaN power transistor 114 via clips (e.g., copper clips). In some embodiments, IC can be coupled to GaN power transistor 114 via bumps. In various embodiments, IC 112 can drive GaN power transistor 114 and may include various features for driving the GaN power transistor and keeping it within its safe operating region. In the illustrated embodiments, the integrated GaN power device 100 can be used to replace silicon power MOSFETs in various applications. Those skilled in the art will understand that the gate driver IC 112 can be used to drive GaN high electron mobility transistors (HEMTs) and other power transistors, such as (but not limited to) isolated gate bipolar transistors (IGBTs) and silicon MOSFETs.

[0054] In various implementations, the gate driver IC 112 can operate without a power supply (V). dd This feature eliminates the need for V in package 110. dd This eliminates the need for additional pins and allows for pin-to-pin compatibility of the integrated GaN power device 100, making it interchangeable with discrete silicon power MOSFETs or other packaged semiconductor devices. In some implementations, when the PWM signal is high, energy for the operation of IC 112 can be drawn from the input PWM signal, and the IC can store this energy in its internal components. When the PWM signal is low, the IC can continue to operate by utilizing the stored energy. Furthermore, even when the energy stored in the IC has dissipated, the IC can continue to actively pull down the gate of the GaN power transistor 114 to prevent unintentional turn-on due to dv / dt events.

[0055] In the illustrated embodiment, the input pin 108 of package 110 can draw a relatively low current, similar to the gate of its alternative discrete silicon power MOSFET. Similar to the gate of a silicon power MOSFET, the PWM signal can have both low and high logic states. For example, in the low state, the PWM signal can be zero volts, while its high state value can be 10V to 30V. IC 112 can drive the gate of GaN power transistor 114 at an appropriate voltage value (e.g., between 0V and 6V), even when the PWM signal varies between 0V and 10V to 30V. Thus, even when the PWM signal exceeds the safe operating voltage of the GaN transistor, IC 112 can keep the gate of GaN power transistor 114 within its safe operating region and prevent damage to the gate of the GaN transistor. As will be understood by those skilled in the art who benefit from this disclosure, the value of the operating voltage can be set to any suitable value appropriate for a particular application.

[0056] In some implementations, during power-on, IC 112 can turn on and perform a power-on function to keep the GaN power transistor 114 in its safe operating region during power-on. IC 112 can drive the gate of the GaN power transistor 114 while monitoring the state of the GaN power transistor 114 by sensing various characteristics of the GaN transistor, such as, but not limited to, overcurrent, overvoltage characteristics, and overtemperature. This is to eliminate the dependence on factors such as V... dd As required by the power pin, IC 112 can draw power from the input PWM signal and store the energy in its internal capacitor 228. Even when the PWM signal is low and the GaN transistor 114 is off, IC 112 can still operate using the stored energy. During the PWM low state, IC 112 can continue to operate and can actively keep the gate of the GaN power transistor 114 low to prevent the gate from turning on due to dv / dt events, which could potentially damage the GaN transistor.

[0057] In some implementations, during standby, there is little or no leakage current in the input terminals of the integrated GaN power device 100. In various implementations, semiconductor packages such as, but not limited to, dual flat leadless (DFN) or TO-247 can be used to integrate IC 112 and GaN power transistor 114 to form pin-to-pin alternatives to discrete silicon power MOSFETs, silicon carbide (SiC) FETs, or other power devices without modifying the printed circuit board (PCB) layout. As those skilled in the art will understand, in some applications, it may be difficult to use GaN power transistors in transistor outline (TO-type) power packages (such as three-terminal or four-terminal TO-247 or TOLL packages) because the relatively high parasitic inductance of the package can cause excessive ringing and oscillation in high-current applications. In the illustrated embodiment, by integrating the gate driver IC 112 together with the GaN power transistor 114 into a TO package, the GaN power transistor 114 can be used in TO-type packages such as, but not limited to, three-terminal TO-247, four-terminal TO-247, and TOLL packages, wherein various features of the gate driver IC, such as, but not limited to, dv / dt control and dI / dt control, allow the use of the GaN power transistor in the TO package. Furthermore, the integrated GaN power device 100 can be used as a pin-to-pin replacement for discrete power MOSFETs, silicon carbide (SiC) FETs, or other power devices without requiring modification to the printed circuit board (PCB) layout. As will be understood by those skilled in the art who benefit from this disclosure, other suitable semiconductor packages can be used for the integration of the GaN power transistor 114 and the gate driver IC 112, as suitable for a particular application.

[0058] Energy harvesting circuit, integrated pull-up and pull-down transistor circuit, and voltage clamping circuit

[0059] Figure 2 A schematic diagram of a circuit 200 with energy harvesting, integrated pull-up and pull-down transistors, and voltage clamping features according to an embodiment of this disclosure is shown. In some embodiments, circuit 200 may be used in an integrated GaN power device 100. For example... Figure 2As shown, circuit 200 may include a GaN power transistor 202 having a gate 208, a drain 204, and a source 206. In some embodiments, GaN power transistor 202 is similar to GaN power transistor 114. Drain 204 may be coupled to pin 277, and source 206 may be coupled to pin 279. In some embodiments, drain 204 and source 206 may not be coupled to pins, but may be coupled to other circuit nodes monolithically integrated with GaN power transistor 202. Circuit 200 may also include an input terminal pin 257 configured to receive a signal 278. In some embodiments, signal 278 may be a pulse width modulation (PWM) signal. Input terminal pin 257 may be connected to a pull-up transistor 210 having a collector 254, a base 216, and a source 214. In various embodiments, pull-up transistor 210 may be a bipolar NPN transistor, while in other embodiments, it may be a P-MOSFET. In some embodiments, pull-up transistor 210 may be an N-MOSFET. In various embodiments, the pull-up transistor 210 may be formed in a compound semiconductor substrate or any other suitable substrate. In some embodiments, the pull-up transistor 210 may be integrated within the gate driver IC 112. In various embodiments, the pull-up transistor may be a GaN-based transistor and integrated in the same die as the GaN power transistor 202.

[0060] Source 214 can be connected to the gate 208 of GaN power transistor 202. In some embodiments, GaN power transistor 202, together with circuitry 200, can be arranged for use in a low-side configuration. In various embodiments, GaN power transistor 202, together with circuitry 200, can be arranged for use in a half-bridge configuration. In some embodiments, GaN power transistor 202, together with circuitry 200, can be arranged for use in a high-side configuration. When signal 278 is high, pull-up transistor 210 can be turned on, allowing current to flow into gate 208, thereby charging the capacitance of gate 208. This allows GaN power transistor 202 to turn on. In various embodiments, pull-up transistor 210 can be a bipolar NPN transistor, while in other embodiments, pull-up transistor 210 can be a P-MOSFET. In some embodiments, transistor 210 can be an N-MOSFET. In various embodiments, transistor 210 can be formed in a compound semiconductor substrate or any other suitable substrate. The pull-up transistor 210 can be integrated within the gate driver IC 112, or it can be a GaN-based transistor integrated into the same die as the GaN power transistor 202.

[0061] Signal 278 can power the base 216 of transistor 210 via resistor 252. When signal 278 goes high, pull-up transistor 210 can pull up the gate 208 of GaN power transistor 202 by providing current to charge the gate 208. Circuit 200 may include a substrate terminal 248 that can be connected to the substrate 280 of IC 112 die. In various embodiments, substrate 280 may be connected to ground. Circuit 200 may include a pull-down transistor 230 having a gate terminal 236, a source terminal 234, and a drain terminal 232. The drain terminal 232 of pull-down transistor 230 can be connected to the gate 208 of GaN power transistor 202, and the source terminal 234 of pull-down transistor 230 can be connected to the source 206 of GaN power transistor 202 and substrate 248. The pull-down transistor is arranged to pull down the gate 208 of GaN power transistor 202 when the PWM signal is low. The gate terminal 236 of the pull-down transistor 230 can be connected to the logic circuit 289, and the signal V generated by the logic circuit 289... ptg2 Drive. When the PWM signal goes low, signal V ptg2 The drain terminal 232 can be raised, which can turn on the pull-down transistor 230, causing the drain terminal 232 to go low and pull down the gate 208 of the GaN power transistor 202. The pull-down transistor 230 can be formed in the same die as the gate driver circuit, or it can be GaN-based and formed in the same die as the GaN power transistor 202, and integrated in the same die as the GaN power transistor 202. The pull-down transistor 230 can be a relatively large transistor to provide a stable pull-down of the gate 208 of the GaN power transistor 202.

[0062] In some embodiments, circuit 200 may include clamping circuit 295. Clamping circuit 295 may clamp the gate 208 of GaN power transistor 202 such that the gate remains within its safe operating region. Clamping circuit 295 may allow the PWM signal to have a wide range of operating voltages, such as 10V to 30V, while keeping the gate 208 of GaN power transistor 202 within its safe operating region, such as below 6.0V. Those skilled in the art who benefit from this disclosure will understand that the operating voltage can be set to any suitable value. Clamping circuit 295 may include Zener diode 250 and two diode-connected NPN transistors 262 and 272.

[0063] The source 266 of transistor 262 can be connected to Zener diode 250. The collector 268 can be connected to the base of transistor 262 and the source 264 of transistor 272. Transistor 272 can have a collector 274 connected to its base 276, wherein the collector 274 is also connected to the base 216 of pull-up transistor 210. Zener diode 250 can generate a voltage (V) at its cathode 233. z V z The value could be, for example, 5.2V. Diode-connected transistors 262 and 272 can each generate, for example, a voltage drop of 0.7V across their collector-to-source terminals. Therefore, the voltage at the base 216 of transistor 210 could be V. z +2V be Those skilled in the art will understand that the connection order of these three devices can be different, and the resulting voltage is V. z +2V be The voltage at the gate 208 of the GaN power transistor 202 can be one V lower than the voltage at the base 216. be Therefore, the voltage at the gate 208 of the GaN power transistor 202 can be V. z +V be This voltage can have a value of, for example, 5.9V, thereby clamping the gate 208 to a voltage below 6.0V to prevent the gate 208 from exceeding its safe operating voltage.

[0064] Circuit 200 may include clamping circuit 295. Clamping circuit 295 may clamp the gate 208 of GaN power transistor 202 such that the gate 208 remains within its safe operating region. Clamping circuit 295 may allow the PWM signal to have a wide range of operating voltages, such as 10V to 30V, while keeping the gate 208 of GaN power transistor 202 within its safe operating region, such as below 6.0V. Those skilled in the art who benefit from this disclosure will understand that the operating voltage can be set to any suitable value. Clamping circuit 295 may include Zener diode 250 and two diode-connected NPN transistors 262 and 272. Transistor 262 has a source 266 that can be connected to Zener diode 250 and a collector 268 that can be connected to the base of transistor 262 and the source 264 of transistor 272.

[0065] Transistor 272 may have a collector 274, which may be connected to the base 216 of pull-up transistor 210. A Zener diode may generate a voltage Vz at its cathode 233, which may be, for example, 5.2V. Diode-connected transistors 262 and 272 may each generate a voltage drop across their collector-to-source terminals, for example, 0.7V. Therefore, the voltage at base 216 may be V... z +2Vbe The voltage at the gate 208 of the GaN power transistor 202 can be one V lower than the voltage at the base 216 of the transistor 210. be Therefore, the voltage at the gate 208 of the GaN power transistor 202 can be V. z +V be This voltage can have a value of, for example, 5.9V. Therefore, the clamping circuit 295 can clamp the gate 208 to a voltage below 5.9V and prevent the gate 208 from exceeding its safe operating voltage. Those skilled in the art who benefit from this disclosure will understand that the output voltage of the clamping circuit can be set to any suitable value. In some embodiments, the transistor 262 can be a diode-connected NPN bipolar transistor. The diode-connected transistor 262 can mitigate V... z Temperature variations. In various embodiments, transistor 272 can mitigate manufacturing process variations and temperature variations in the characteristics of transistor 210. Those skilled in the art will understand that the connection order of transistors 262 and 272 can be different while mitigating temperature and manufacturing process variations.

[0066] Circuit 200 may include energy harvesting and storage circuitry 299. Storage circuitry 299 may include a transistor 218 connected in series with an energy storage capacitor 228. In some embodiments, transistor 218 may be configured as a diode-connected transistor. In various embodiments, a diode may be used instead of transistor 218. Transistor 218 may have a collector terminal 220, a source terminal 222, and a base terminal 226. Collector terminal 220 may be connected to base terminal 226. Source terminal 222 may be connected to capacitor 228. When the PWM signal goes high, transistor 210 may turn on, causing transistor 218 to also turn on. Capacitor 228 may charge and store energy from the PWM signal. Therefore, an energy equal to V can be generated at the source terminal 222 of transistor 218. z The voltage, because when the voltage at the source 214 of transistor 210 is V z +V be At this time, the voltage at the source terminal 222 of transistor 218 can be one V lower than the voltage at the source terminal 214 of transistor 210. be The voltage at the source terminal 222 of transistor 218 can be, for example, 5.2V. This voltage can be used to power the circuitry within IC 112 even when the PWM signal goes low. In some embodiments, this disclosure includes methods for generating a voltage at the gate of GaN power transistor 202 and storing the regulated voltage in a storage element such as capacitor 228.

[0067] Circuit 200 may include transistor 240, which can be used to turn off the charging of the gate 208 of GaN power transistor 202 when the PWM goes low. The drain 242 of transistor 240 may be connected to the base 216 of pull-up transistor 210, and the source 244 of transistor 240 may be connected to substrate 248. The gate 246 of transistor 240 may be configured to receive signal V. ptg2 When signal 278 goes low, signal V ptg2 246 can go high and turn on transistors 230 and 240. Pull-down transistor 230 can pull down the gate of GaN power transistor 202, and transistor 240 can pull down the base 216 of transistor 210, thereby turning it off. By turning off pull-up transistor 210, charging of the gate 208 of GaN power transistor 202 can be stopped.

[0068] Figure 3 It shows Figure 2 The diagram 300 shows the quiescent current at input terminal pin 257 of circuit 200, and... Figure 2 Figure 310 shows the gate voltage of the GaN power transistor 202 in circuit 200. Figure 308 shows the quiescent current, and Figure 310 shows the gate voltage plotted as a function of PWM voltage 306. Figure 3 As shown, as the PWM voltage 306 increases, the gate voltage of the GaN power transistor increases linearly with gate charging. The gate voltage increases to approximately 6.0V and is clamped at that voltage because the clamping circuit 295 clamps the gate 208 of the GaN power transistor 202. Furthermore, Figure 308 shows that no quiescent current flows into the PWM terminal before the gate is clamped. There is no current before the clamping circuit 295 is activated. When the gate 208 is clamped, the quiescent current increases linearly. In some embodiments, this feature can make the integrated GaN power device 100 compatible with discrete power applications because the standby gate current of the integrated GaN power device is zero.

[0069] Saturation current protection circuit

[0070] Figure 4A A schematic diagram of a circuit 400A with saturation current protection features according to an embodiment of this disclosure is shown. For example... Figure 4A As shown, circuit 400A may include a GaN power transistor 440 having a gate 412, a drain 422, and a source 428. The drain 422 may be connected to a load. Circuit 400A can be used to detect when the GaN power transistor 440 enters its saturation operating region. Operation in the saturation region may occur when the drain current of the transistor increases while its drain-source voltage remains relatively constant.

[0071] like Figure 4AAs shown, the source 428 of the GaN power transistor 440 can be connected to ground node 430. Circuit 400A can monitor the drain voltage of the GaN power transistor using GaN transistor 442. In some embodiments, transistor 442 can be a depletion-mode GaN transistor. While GaN power transistor 440 can be a high-voltage transistor with, for example, an operating voltage of 400V, circuit 400A can be a low-voltage circuit for monitoring GaN power transistor 440 and preventing it from operating in the saturation region. In the illustrated embodiment, the voltage at the drain 422 of GaN power transistor 440 can be monitored, and when said voltage exceeds a threshold (e.g., 8V), circuit 400A can turn off GaN power transistor 440 to protect it from damage, thereby preventing damage to the power converter. More specifically, in some embodiments, circuit 400A can use depletion-mode (D-mode) GaN transistor 442, wherein the drain 422 of GaN power transistor 440 is connected to the drain 421 of transistor 442. The gate 426 of transistor 442 can be connected to ground node 430. The source 424 of transistor 442 can be connected to resistor divider 419.

[0072] Circuit 400A may include comparator 406 and logic circuit 408. In some embodiments, resistor divider 419, comparator 406, and logic circuit 408 may be formed using low-voltage silicon technology. In various embodiments, resistor divider 419, comparator 406, and logic circuit 408 may be formed using GaN technology and integrated within the same die as GaN power transistor 440. In some embodiments, resistor divider 419 may include two resistors 402 and 404 connected in series. The output 416 of the resistor divider may be connected to the first input 499 of comparator 406, while the second input 414 of comparator 406 may be connected to a reference voltage (V). ref 415. The reference voltage 415 can have a value of, for example, 2.5V. The output 418 of the comparator can be connected to the logic circuit 408. The voltage at the drain 422 of the GaN power transistor 440 can vary from, for example, 0V to 400V. The source 424 of the D-mode GaN transistor 442 can be clamped at its pinch-off voltage (e.g., 15V).

[0073] The source 424 of the D-mode GaN transistor 442 follows the drain voltage of the GaN power transistor 440 until its pinch-off voltage is reached. Thereafter, the source 424 of the D-mode GaN transistor 442 is clamped at the pinch-off voltage (e.g., 15V). In some embodiments, the source voltage of the D-mode GaN transistor 442 follows its drain voltage until the source voltage reaches the transistor's pinch-off voltage. At this point, the source voltage is clamped to the pinch-off voltage and remains constant at said voltage. In this way, the D-mode GaN transistor 442 allows its source 424 to be connected to a resistor divider 419, while the drain 421 of the D-mode GaN transistor 442 can operate at high voltages, for example, up to 400V. When the voltage at the source 424 of the D-mode GaN transistor 442 exceeds a preset value (e.g., 8V), it can turn off the GaN power transistor 440.

[0074] Resistor divider 419 provides output 416, which tracks its input at node 423 but at a lower voltage level. The output voltage of resistor divider 419 can be compared to a reference voltage 415 (e.g., 2.5V), which is the threshold voltage of comparator 406. When the voltage at input 499 of the comparator exceeds V... ref When the comparator 406 is high, its output 418 voltage can switch from a low state to a high state. The output 418 of the comparator 406 can be connected to logic circuit 408. When the comparator output 418 goes high, the output 420 of logic circuit 408 turns off the gate of GaN power transistor 440, thus turning off GaN power transistor 440. Those skilled in the art will understand that transistor 442 can be a D-mode GaN transistor, which can be integrated within the same die as GaN power transistor 440. In some embodiments, transistor 442 can be an enhancement-mode GaN transistor. In various embodiments, transistor 442 can be a silicon transistor.

[0075] Figure 4B Graph 400B illustrates the voltage change over time at nodes within circuit 400A. Graph 422a shows the drain voltage of GaN power transistor 440, which can range from 0 volts to 400 V. Graph 424a shows the source voltage of D-mode GaN transistor 442 following the drain voltage of GaN power transistor 440 (Graph 422a). As shown in Graph 424a, the source voltage changes from 0 V to 15 V, where the source of D-mode GaN transistor 442 is clamped at 15 V. Graph 416a shows the output voltage 416 of resistor divider 419. Graph 415a shows V at 2.5 V. refValue. Finally, Figure 418a shows the output voltage of comparator 406, where 416a (the output of the resistor divider) crosses 415a (V). ref When the voltage is high, the comparator switches from a low state to a high state. As those skilled in the art will understand, the voltages shown in Figure 400B are merely examples, and other implementations may have different operating characteristics.

[0076] Figure 5 A schematic diagram of a circuit 500 including saturation current protection features according to an embodiment of the present disclosure is illustrated. Circuit 500 is similar to circuit 400A, except that the gate 526 of transistor 542 is connected to the gate 512 of GaN power transistor 540. This allows the use of a low-pinch-out (e.g., 5V) D-mode GaN transistor to sense the drain voltage at the drain 522 of GaN power transistor 540. To monitor the drain voltage of GaN power transistor 540 using a D-mode GaN transistor 542 with a low-pinch-out voltage, a dynamic bias of the gate 526 can be used to allow proper operation of the D-mode GaN transistor. The dynamic bias increases the gate voltage of the D-mode GaN transistor 542 and causes the gate-source voltage of the D-mode GaN transistor to vary, rather than remain constant.

[0077] Circuit 500 can be used to detect when GaN power transistor 440 enters its saturation operating region. The source 528 of GaN power transistor 540 can be connected to ground node 530. Circuit 500 can monitor the drain voltage of GaN power transistor using transistor 542. While GaN power transistor 540 can be a high-voltage transistor with, for example, an operating voltage of 400V, circuit 500 can utilize low-voltage circuitry to monitor the GaN power transistor and prevent it from operating in the saturation region. In some embodiments, this can be accomplished by monitoring the voltage at the drain 522 of GaN power transistor 540, and when the voltage exceeds a threshold (e.g., 8V), circuit 500 can turn off the GaN power transistor to protect it from damage. More specifically, circuit 500 can use a D-mode GaN transistor 542, where the drain 522 of GaN power transistor 540 is connected to the drain 521 of transistor 542. Circuit 500 may include comparator 506 and logic circuitry 508.

[0078] In some implementations, the resistor divider 519, comparator 506, and logic circuit 508 can be formed using low-voltage silicon technology. In various implementations, the resistor divider 519, comparator 506, and logic circuit 508 can be formed using GaN technology and integrated within the same die as the GaN power transistor 540. The resistor divider 519 may include two resistors 502 and 504 connected in series. The output 516 of the resistor divider can be connected to the first input of the comparator 506, while the second input 514 of the comparator 506 can be connected to a reference voltage (V). ref 515. The reference voltage 515 can have a value of, for example, 2.5V. The output 518 of the comparator can be connected to logic circuit 508. The voltage at the drain 522 of the GaN power transistor 540 can vary, for example, from 0V to 400V. The source 524 of transistor 542 is clamped at its pinch-off voltage (e.g., 15V). The source 524 of transistor 542 follows the drain voltage of GaN power transistor 540 until its pinch-off voltage is reached. Thereafter, the source 524 of transistor 542 is clamped at the pinch-off voltage (e.g., 15V). Transistor 542 has the characteristic that its source voltage follows its drain voltage until the source voltage reaches the transistor's pinch-off voltage. At this point, the source voltage is clamped to the pinch-off voltage and remains constant at said voltage. In this way, the D-mode GaN transistor 542 can connect its source 524 to a low-voltage resistor divider 519, while the drain 521 of the D-mode GaN transistor 542 can operate at high voltages, for example, up to 400V. When the voltage at the source 524 of the transistor 542 exceeds a preset value (e.g., 8V), it can turn off the GaN power transistor 540.

[0079] Resistor divider 519 provides an output at 516 that tracks its input at node 523 but at a lower voltage level. The output voltage of resistor divider 519 can be compared to a reference voltage 515 (e.g., 2.5V), which is the threshold voltage of comparator 506. When the voltage at input 599 of the comparator exceeds V... ref When comparator 506 goes high, its output voltage at 518 can switch from a low state to a high state. The output 518 of comparator 506 can be connected to logic circuit 508. When output 518 goes high, the output 520 of logic circuit 508 turns off the gate of GaN power transistor 540, thus turning off GaN power transistor 540. Those skilled in the art will understand that transistor 542 can be a D-mode GaN transistor, which can be integrated within the same die as GaN power transistor 540. In some embodiments, transistor 542 can be an enhancement-mode GaN transistor. In various embodiments, transistor 542 can be a silicon transistor.

[0080] Figure 6 A schematic diagram of a circuit 600 with saturation current protection features according to an embodiment of this disclosure is illustrated. Circuit 600 is similar to circuit 400A, except that the gate 626 of transistor 642 is connected to and independently controlled by the output of logic circuit 608. This allows the use of a low-pinch-out (e.g., 5V) D-mode GaN transistor to sense the drain voltage at the drain 622 of GaN power transistor 640. To monitor the drain voltage of GaN power transistor 640 using a D-mode GaN transistor 642 with low pinch-out voltage, independent biasing of the gate 626 can be used to allow proper operation of the D-mode GaN transistor. Dynamic biasing can increase the gate voltage of D-mode GaN transistor 642 and cause the gate-source voltage of the D-mode GaN transistor to vary, rather than remain constant.

[0081] Circuit 600 can be used to detect when the GaN power transistor 640 enters its saturation operating region. The source 628 of the GaN power transistor 640 can be connected to ground node 630. Circuit 600 can monitor the drain voltage of the GaN power transistor using transistor 642. Although the GaN power transistor 640 can be a high-voltage transistor with, for example, an operating voltage of 400V, circuit 600 can utilize a low-voltage circuit to monitor the GaN power transistor and prevent it from operating in the saturation region. This can be done by monitoring the voltage at the drain 622 of the GaN power transistor 640, and when the voltage exceeds a threshold (e.g., 8V), circuit 600 can turn off the GaN power transistor to protect it from damage. More specifically, circuit 600 can use a D-mode GaN transistor 642, where the drain 622 of the GaN power transistor 640 is connected to the drain 621 of transistor 642.

[0082] Circuit 600 may include comparator 606 and logic circuit 608. In some embodiments, resistor divider 619, comparator 606, and logic circuit 608 may be formed using low-voltage silicon technology. In various embodiments, resistor divider 619, comparator 606, and logic circuit 608 may be formed using GaN technology and integrated within the same die as GaN power transistor 640. Resistor divider 619 may include two resistors 602 and 604 connected in series. The output 616 of resistor divider may be connected to the first input of comparator 606, while the second input 614 of comparator 606 may be connected to a reference voltage (V). ref 615. The reference voltage 615 can have a value of, for example, 2.5V. The comparator output 618 can be connected to logic circuit 608.

[0083] The voltage at the drain 622 of the power transistor 640 can vary, for example, from 0V to 400V. The source 624 of the transistor 642 is clamped at its pinch-off voltage (e.g., 15V). The source 624 of the transistor 642 follows the drain voltage of the GaN power transistor 640 until its pinch-off voltage is reached. Thereafter, the source 624 of the transistor 642 is clamped at the pinch-off voltage (e.g., 15V). The transistor 642 has the characteristic that its source voltage follows its drain voltage until the source voltage reaches the transistor's pinch-off voltage. At this point, the source voltage is clamped to the pinch-off voltage and remains constant at said voltage. In this way, the D-mode GaN transistor 642 can connect its source 624 to a resistor divider 619, while the drain 621 of the D-mode GaN transistor 642 can operate at high voltages, for example, up to 400V. When the voltage at the source 624 of transistor 642 exceeds a preset value (e.g., 8V), it can turn off GaN power transistor 640.

[0084] A resistor divider 619 provides an output at 616 that tracks its input at node 623 but at a lower voltage level. The output voltage of resistor divider 619 can be compared to a reference voltage 615 (e.g., 2.5V), which is the threshold voltage of comparator 606. When the voltage at the comparator's input 699 exceeds V... ref When the output voltage 618 is high, comparator 606 can switch the output voltage 618 from a low state to a high state. The output 618 of comparator 606 can be connected to logic circuit 608. When the output 618 goes high, the output 620 of logic circuit 608 turns off the gate 612 of GaN power transistor 640, thus turning off GaN power transistor 640. Those skilled in the art will understand that transistor 642 can be a D-mode GaN transistor, which can be integrated within the same die as GaN power transistor 640. In some embodiments, transistor 642 can be an enhancement-mode GaN transistor. In various embodiments, transistor 642 can be a silicon transistor.

[0085] dv / dt control

[0086] Figure 7AA schematic diagram of a circuit 700A with turn-on dv / dt control features according to an embodiment of the present disclosure is illustrated. Circuit 700A can be used to mitigate the relatively high parasitic inductance of an electronic package, such as, but not limited to, a TO-247 or TOLL package. Circuit 700A illustrates a variation of circuit 200. Circuit 700A illustrates a GaN power transistor 202 together with a driver IC 710 and turn-on dV / dt control circuitry. Circuit 700A may include an impedance element 704. In some embodiments, circuit 200 may be coupled to impedance element 704. The impedance element may be external to the integrated GaN power device 100. In various embodiments, impedance element 704 may include one or more passive components. In some embodiments, impedance element 704 may be a resistive element, while in other embodiments, impedance element 704 may include a resistive element and a capacitive element, wherein the capacitive element is coupled in parallel to the resistive element. In various embodiments, impedance element 704 may include a network of resistive and capacitive elements. Impedance element 704 may be coupled to input terminal pin 257. Impedance element 704 can be configured to receive signal 278. Impedance element 704 can be used to control the rate of change (dV / dt) of the voltage of GaN power transistor 202 over time. As described above... Figure 1 As discussed herein, the integrated GaN power device 100 can be used as a pin-to-pin replacement for discrete silicon power MOSFETs, thus the ability to control dV / dt at the drain 204 of the GaN power transistor 202 can be beneficial. Without dV / dt control circuitry, parasitic dV / dt can cause ringing and oscillation at the drain 204, which can couple to the gate 208 and cause erroneous turn-on of the GaN power transistor 202.

[0087] The conduction dV / dt control of power transistor 202 can be achieved using impedance element 704. Impedance element 704 can be used to mitigate the relatively rapid rate of change of voltage at input terminal pin 257 over time. Gate drive node 730 can be connected to the gate 208 of GaN power transistor 202. Capacitors 712 and 718 and inductor 716 are package parasitic elements. The substrate can be grounded at node 706 and connected to the source 206 of GaN power transistor 202. In some embodiments, impedance element 704 can be integrated into the gate driver IC. In various embodiments, the current flowing through input terminal pin 257 to the gate of GaN power transistor 202 can be limited by limiting the current of pull-up transistor 210 in order to control conduction dV / dt. This can be achieved by reducing the gate drive of pull-up transistor 210.

[0088] Figure 7BFigure 700B illustrates the variation of the PWM voltage 740 over time 748 and the drain-source voltage (V) at the turn-on point of the GaN power transistor 202. ds The rate of change of 742 over time. Figure 7B As can be seen, as the resistance of impedance element 704 increases, the slope of the drain conduction falling edge decreases, indicating a decrease in dv / dt. Circuit 200 achieves this feature because when signal 278 goes high, the current charging the gate 208 of GaN power transistor 202 flows through impedance element 704, which is connected in series with pull-up transistor 210. In this way, dv / dt at drain 204 can be controlled, and electromagnetic interference (EMI) of the power converter can be reduced. Figure 7C A graph illustrating the variation of dv / dt 770 with the resistance 778 of the impedance element 704 in circuit 700A is provided. Graphs 772, 774, and 776 show the variation of dv / dt with the high values ​​of the resistance 778 for PWM at 8V, 10V, and 12V, respectively. As the resistance value increases from, for example, a few ohms to several thousand ohms, the dv / dt value can decrease from, for example, 100V / ns to 10V / ns.

[0089] Figure 8 A schematic diagram of circuit 800, including dv / dt control circuitry and gate clamping features, according to an embodiment of this disclosure is illustrated. Circuit 800 shows a gate driver and control circuitry 883 coupled to a GaN-based circuit 889. Circuit 800 can be used to mitigate ringing and oscillation caused by the relatively high parasitic inductance of an electronic package, such as, but not limited to, [missing information - likely related to...]. Figure 1The described TO-247 or TOLL package. The GaN-based circuit 889 may include a GaN power transistor 202 having a gate 208, a drain 204, and a source 206. The GaN-based circuit 889 may further include a pull-down transistor 822 having a drain 824, a gate 828, and a source 826. The drain 824 may be connected to the gate 208, while the source 826 may be connected to ground node 840. In some embodiments, the GaN-based circuit 889 may be used in a high-side arrangement, where the source 826 may be connected to the switching node (Vsw) of a half-bridge. The gate driver and control circuit 883 may include a pull-up transistor 814 having a gate 816, a drain 818, and a source 820. The gate 208 may be coupled to the source 820. The pull-up transistor 814 may include a body diode 819. The drain 818 may be coupled to an input terminal pin 855. In some embodiments, the gate driver and control circuitry 883 may be formed on a silicon-based die, while the GaN-based circuitry 889 may be formed on a GaN-based die. In various embodiments, the gate driver and control circuitry 883 may be monolithically formed on the same die as the GaN-based circuitry 889. In some embodiments, although the gate driver and control circuitry 883 are formed on a separate die from the GaN-based circuitry 883, the pull-up transistor may be formed on the same die as the GaN-based circuitry 889. In various embodiments, the input terminal pin 855 may be connected to an external component.

[0090] Circuit 800 may further include current flow control circuitry. The current flow control circuitry may include impedance element 804, unidirectional current conductor 806, impedance element 808, and unidirectional current conductor 810. Impedance element 804 may include one or more passive components. In some embodiments, the impedance element may be a resistive element, while in other embodiments, the impedance element may include a resistive element and a capacitive element, wherein the capacitive element is coupled in parallel to the resistive element. In various embodiments, the impedance element may include a network of resistive and capacitive elements. The unidirectional current conductor may include, but is not limited to, a diode. Impedance element 804 may be coupled to node 802. Node 802 may be configured to receive signal 278. In some embodiments, impedance element 804, unidirectional current conductor 806, impedance element 808, and unidirectional current conductor 810 may be... Figure 1The integrated GaN power device 100 is external to the device. In various embodiments, the impedance element 804, unidirectional current conductor 806, impedance element 808, and unidirectional current conductor 810 may be external to or internal to the integrated GaN power device 100. The source 820 may be connected to the gate 208. The pull-up transistor 814 may be a bipolar transistor or a MOSFET. In some embodiments, the pull-up transistor 814 may be an N-MOSFET, while in other embodiments, the pull-up transistor 814 may be a P-MOSFET.

[0091] Gate driver and control circuitry 883 may include logic circuitry and control circuitry 812 coupled to gate 828. Control and logic circuitry 812 may be configured to control the conductivity of pull-down transistor 822. In some embodiments, pull-down transistor 822 may be GaN-based and formed on the same die as GaN power transistor 202. In various embodiments, pull-down transistor 822 may be formed on a separate die. In some embodiments, pull-down transistor 822 may be formed in silicon or other suitable semiconductor substrate. Circuitry 800 may further include clamping circuitry 853. In some embodiments, circuitry 800 may not include clamping circuitry 853. Circuitry 800 may also include control circuitry 869 arranged to control the conductivity state of gate 816. In some embodiments, circuitry 800 may not include control circuitry gate 816, instead, gate 816 may be connected to input terminal pin 855 via an impedance element.

[0092] When signal 278 goes high, pull-up transistor 814 can be turned on. Therefore, current can flow through impedance element 804, unidirectional current conductor 806, and transistor pull-up resistor 814 to gate 208. In this way, the capacitance of gate 208 can be charged, causing GaN power transistor 202 to enter a conducting state. By setting the value of impedance element 804, the user can control the conduction dV / dt of GaN power transistor 202. In this way, ringing and oscillation can be prevented, thus keeping GaN power transistor 202 in its safe operating area (SOA). Pull-up transistor 814 can act as a clamp to hold GaN power transistor 202 in its SOA. Clamping circuit 853 can set the voltage at gate 816 so that most of the input signal voltage can drop across drain 818 to source 820. For example, GaN power transistor may have a 7V rating. When the input signal 278 may be at, for example, 10V to 20V, the disclosed turn-on dV / dt control can keep the GaN power transistor in its SOA. As will be understood by those skilled in the art who benefit from this disclosure, the disclosed turn-on dV / dt control circuitry can control dV / dt for other voltage values ​​at the input signal (e.g., 1V to 50V). Furthermore, as will be understood by those skilled in the art, the disclosed turn-on dV / dt control circuitry can utilize an external impedance element to control dV / dt. In various embodiments, the impedance element may include one or more passive components. In some embodiments, the impedance element may be a resistive element, while in other embodiments, the impedance element may include a resistive element and a capacitive element, wherein the capacitive element is coupled in parallel to the resistive element. In various embodiments, the impedance element may include a network of resistive and capacitive elements. In some embodiments, the gate 816 may be controlled by other logic circuitry instead of clamping circuitry 853. In various embodiments, clamping circuitry 853 may be similar to clamping circuitry 295.

[0093] When signal 278 goes low, the charge on gate 208 can be discharged through body diode 819, impedance element 808, and unidirectional current conductor 810. In this way, the charge on gate 208 can be discharged, thus lowering the voltage at gate 208 and causing GaN power transistor 202 to enter a non-conductive state. By setting the value of impedance element 808, the user can control the turn-off dV / dt of GaN power transistor 202. This prevents ringing and oscillation, thereby keeping the GaN power transistor in a non-conductive state. Furthermore, logic and control circuitry 812 can sense the voltage at gate 208. When the voltage drops below a threshold value, logic and control circuitry 812 can turn on pull-down transistor 822 after a relatively short period of time. In this way, gate 208 remains low and prevents GaN power transistor 202 from turning on due to erroneous conduction. In some embodiments, circuitry 800 can be used in a high-side configuration. In various embodiments, circuitry 800 can be used in a half-bridge configuration. In some embodiments, circuitry 800 can be used in a low-side configuration.

[0094] Turn off dI / dt control

[0095] Figure 9 A schematic diagram of a circuit 900 with turn-off dI / dt control features according to an embodiment of the present disclosure is illustrated. Circuit 900 can be used to mitigate the relatively high parasitic inductance of a TO-247 or TOLL package. Circuit 900 may include a GaN power transistor 926 having a source 928, a gate 924, and a drain 922. In some embodiments, the GaN power transistor can be connected within the package of the GaN power transistor by connecting a bonding wire between the GaN transistor die and its package. The bonding wire may have an associated inductance. Circuit 900 shows an inductance 920 of the bonding wire having an inductance value L. For example, the bonding wire inductance may be generated by a lower bonding between the source 928 of the GaN power transistor 926 and the package pad. Element 918 represents an inductance packaged to a printed circuit board. The bonding wire inductance L of 920 can be used to sense the rate of change (dI / dt) of the current in the source of the GaN power transistor 926 over time. When the GaN power transistor is turned off, the current through the source of the GaN power device decreases. This causes a rapid change in the voltage across inductor 920 (given by LxdI / dt). The voltage across inductor 920 is detected by resistors 914 and 916. Resistor 914 is connected to the cathode 919 of diode 912, and resistor 916 is connected to the anode 917 of diode 912.

[0096] The induced voltage is fed back to the source 910 of the pull-down transistor 904. The drain 902 of the transistor 904 can be connected to the gate 924 of the GaN power transistor 926. In some embodiments, the pull-down transistor 904 can be a silicon transistor, while in other embodiments, the pull-down transistor can be a GaN transistor, which can be integrated within the same die as the GaN power transistor 926. When the voltage across the inductor 920 increases, the voltage at the source 910 of the pull-down transistor 904 increases because the voltage across the inductor 920 is fed back to the source 910 with positive polarity. When the voltage at the source 910 of the pull-down transistor 904 increases, the gate-source voltage (V... gs The voltage across inductor 920 will decrease, resulting in less drive for pull-down transistor 904. This, in turn, reduces the turn-off speed of GaN power transistor 926. The more voltage generated across inductor 920, the less drive pull-down transistor 904 can have, which in turn slows down the turn-off of GaN power transistor 926. Those skilled in the art will understand that transistor 904, resistors 914 and 916, and diode 912 can be GaN formed and integrated in the same die as GaN power transistor 926, or they can be silicon formed, or some components can be GaN formed while others are silicon formed.

[0097] In some implementations, voltage feedback across inductor 920 can be used to modulate the voltage at the gate 906 of pull-down transistor 904 to reduce pull-down drive and slow the turn-off of GaN power transistor 926. The source 910 of transistor 904 can be connected to the source 928 of GaN power transistor 926, simultaneously modulating the voltage at the gate 906 of pull-down transistor 904 to adjust the drive capability of pull-down transistor 904. In various implementations, the inductance L of inductor 920 can be varied due to manufacturing variations. Circuit 900 can compensate for variations in the value of inductance L. For example, if the value of inductance L decreases, the signal generated across inductor 920 also decreases; however, this signal will be sufficient to provide feedback to pull-down transistor 904 because the value of LxdI / dt of GaN power transistor also decreases.

[0098] In some implementations, the shutdown dI / dt control can control voltage spikes across the driver and the drain-source of the power transistor 926. The shutdown dI / dt control can mitigate these spikes regardless of the value of inductor L. For example, if the value of inductor L decreases, the shutdown dI / dt control system can mitigate higher dI / dt. The shutdown dI / dt control can mitigate voltage spikes as long as LxdI / dt is conducting, including a feedback loop comprising resistor 916, diode 912, and resistor 914. In various implementations, diode 912 can provide feedback of a positive voltage across the junction line inductor 920 (i.e., node 930 is positive relative to node 932). In this way, the shutdown dI / dt control system can prevent voltage ringing from being fed back into the system, which would cause high-frequency oscillations. Those skilled in the art will understand that, when the junction line inductor 920 is available, the described shutdown dI / dt control system and circuitry can be used in any power conversion circuit including power transistors, including but not limited to t, GaN, and / or silicon power transistors.

[0099] Gate driver circuit with hysteresis

[0100] Figure 10A schematic diagram of a gate driver circuit 1000 with hysteresis according to an embodiment of the present disclosure is illustrated. Circuit 1000 can be used within circuit 200 to provide gate drive using hysteresis technology, which can be used to drive GaN power transistor 202. Circuit 1000 may include a GaN power transistor 1024 having a source 1030, a gate 1026, and a drain 1028. Circuit 1000 may include a rail 1020 configured to receive a PWM signal 1011. When the PWM signal 1011 is high, it can turn on transistor 1010, which can begin charging the gate 1026 of the GaN power transistor 1024. The source 1012 of transistor 1010 may be connected to rail 1020, which is connected to the input PWM signal 1011. A Zener diode 1018 may be connected to the gate 1014 of transistor 1010 to clamp the voltage at the gate 1014 of transistor 1010. The gate of the GaN power transistor 1024 can be connected to a feedback and hysteresis circuit 1050. The feedback and hysteresis circuit may include a resistor divider formed by resistors 1052, 1054, and 1056 and transistor 1070. Comparator 1094 may connect its first input 1096 to the output 1049 of the resistor divider formed by resistors 1052, 1054, and 1056. Comparator 1094 can monitor the gate voltage of the GaN power transistor 1024 via the resistor divider. When the gate of the GaN power transistor 1024 is low, the drain 1016 of transistor 1010 is low, so transistor 1010 can turn on and charge the gate of the GaN power transistor 1024. When charged, the voltage at the gate 1026 of the GaN power transistor becomes high.

[0101] Comparator 1094 can compare the voltage at its first input terminal 1096 with the reference voltage V at node 1077. refThe high state of the gate of GaN power transistor 1024 is detected. When the voltage at the first input 1096 goes high, comparator 1094 switches, and its output 1098 can go high. Output 1098 can then turn on transistor 1005 through buffer 1015. Transistor 1005 can be connected to the gate 1006 of PMOS transistor 1004 through resistor 1092. When transistor 1005 is turned on, the voltage at the gate 1006 of PMOS transistor 1004 goes low, thus turning on PMOS transistor 1004. The source 1002 of PMOS transistor 1004 can be connected to rail 1020, and the drain 1008 can be connected to the gate 1014 of transistor 1010. Zener diode 1022 can be connected to the gate 1006 of PMOS transistor 1004 to clamp its gate voltage and prevent damage to its gate. When PMOS transistor 1004 is turned on, it can turn off transistor 1010. Therefore, the gate of the GaN power transistor can be kept in a high state. If the voltage at the gate of the GaN power transistor drops due to leakage through parasitic elements, the comparator 1094 can be turned on again due to hysteresis, and the transistor 1010 is turned on again to charge the gate of the GaN power transistor.

[0102] By utilizing pull-up transistor 1010, circuit 1000 can implement PWM signals with a wide voltage variation range (e.g., from 5V to 30V). When pull-up transistor 1010 is introduced into circuit 1000, the gate 1014 of the pull-up transistor can be controlled using feedback and hysteresis circuit 1050. Circuit 1000 may include buffer 1019, which can control the gate 1080 of transistor 1086 and the gate 1076 of transistor 1070. When the gate of GaN power transistor 1024 is high, the inverted output 1017 of comparator 1094 is high. The inverted output 1017 drives the gate 1080 of transistor 1086 through buffer 1019 and turns off transistor 1086, which allows the voltage at the drain 1082 connected to resistor 1090 to rise towards rail 1020, enabling transistor 1010 to turn off. Simultaneously, transistor 1005 can be turned on, causing transistor 1004 to turn off. Transistors 1032, 1060, and 1042, combined with Zener diode 1040, form a clamping circuit for the gate 1026 of GaN power transistor 1024 to prevent the gate voltage from exceeding its safe operating region. Circuit 1000 can drive the gate of GaN power transistor 1024 with both relatively low and relatively high PWM voltages.

[0103] Figure 11Graph 1100 illustrates the voltages at various nodes within circuit 1000. Graph 1102 shows the PWM signal going high. Graph 1104 shows the comparator input voltage at the first input 1096 going high. Graph 1106 shows the comparator output voltage at 1098 going high. Graph 1108 shows the voltage at the gate of the GaN power transistor 1024 going high.

[0104] In various embodiments, hysteresis can be implemented, for example, within the comparator 1094 itself. The comparator may have hysteresis, or it may use two different levels of reference voltage. In some embodiments, the gate driver circuit with hysteresis can control the pull-up transistor 1010 in various ways. In some embodiments, the gate driver with hysteresis can operate without the gate clamping circuitry including transistors 1032, 1060, and 1042. The gate driver circuit with hysteresis can operate with or without clamping circuitry. In various embodiments, the gate driver with hysteresis can be used in many gate driver applications. Furthermore, the gate driver with hysteresis circuitry can be used as a voltage regulator, such as... Figure 12 As shown.

[0105] Figure 12 A schematic diagram of a voltage regulator 1200 according to an embodiment of the present disclosure is shown. The voltage regulator 1200 can regulate the gate voltage of transistor 1010 of circuit 1000. Drain 1016 can be connected to capacitor 1220 and load 1218. Resistors 1208 and 1210 can form a resistor divider arranged to provide a feedback signal. The feedback signal can be generated at node 1206 and fed into the input of comparator 1204. Comparator 1204 can have hysteresis. Comparator 1204 can compare the voltage at node 1206 with a reference voltage Vref and provide the voltage at node 1227 to controller circuit 1202. Controller circuit 1202 can regulate the gate voltage of transistor 1010.

[0106] Figure 13 An integrated GaN power device 1300 according to an embodiment of this disclosure is described. For example... Figure 13 As shown, the integrated GaN power device 1300 can be packaged in a TO-247 package to integrate the gate driver IC 112 and the integrated GaN power transistor 114. The integrated GaN power device 1300 may include a source terminal 1302, a drain terminal 1304, and a PWM terminal 1306. The integrated GaN power device 1300 can be a compatible alternative to the power MOSFET and its drive circuitry in a TO-247 package.

[0107] Figure 14AAn integrated GaN power device 1400A according to an embodiment of this disclosure is described. For example... Figure 14A As shown, the integrated GaN power device 1400A can be packaged in a TO-247 or TO leadless (TOLL) package to integrate the gate driver IC 112 and the GaN power transistor 114. In the illustrated embodiment, the integrated GaN power device 1400A may include a source terminal 1404, a drain terminal 1402, a PWM terminal 1408, and a Kelvin source 1406. In some embodiments, the integrated GaN power device 1400A may not include a Kelvin source and may be packaged in a three-terminal TO-247 or a three-terminal TOLL package. In various embodiments, the integrated GaN power device 1400A may be a compatible alternative to the power MOSFET and its drive circuitry in a three-terminal or four-terminal TO-247 package. In many embodiments, the integrated GaN power device 1400A may be a compatible alternative to the power MOSFET in a three-terminal or four-terminal TOLL package and its drive circuitry. Figure 14B This describes an integrated GaN power device 1400B in a four-terminal TO-247 package according to an embodiment of this disclosure. Figure 14C This describes an integrated GaN power device 1400C in a TOLL package according to an embodiment of this disclosure.

[0108] Although this document describes and illustrates an integrated power device with an energy harvesting gate driver in a specific configuration of GaN integrated power devices, embodiments of the invention are applicable to other configurations of GaN and non-GaN devices. For example, any semiconductor device can be used with embodiments of this disclosure. In some cases, embodiments of this disclosure are particularly suitable for silicon and other compound semiconductor devices.

[0109] For simplicity, the integrated GaN power device 100 is not shown in the figure (see figure). Figure 1 Details of the various internal components, such as the substrate, various lead frames and other components.

[0110] In the foregoing specification, embodiments of the invention have been described with reference to numerous specific details, which may vary depending on the implementation. Therefore, the specification and drawings are to be considered illustrative rather than restrictive. The sole and exclusive indication of the scope of this disclosure, and the content intended by the applicant as the scope of this disclosure, is the literal and equivalent scope of the set of claims published in this application, in the specific form of such claims, including any subsequent corrections. Specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of the embodiments of this disclosure.

[0111] Furthermore, spatial relative terms, such as “bottom” or “top,” can be used to describe the relationship between an element and / or feature and another element and / or feature, as illustrated in the figures. It should be understood that, in addition to the orientation depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use and / or operation. For example, if the device in the figure is flipped, then the element described as the “bottom” surface can be oriented “above” other elements or features. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein should be interpreted accordingly.

[0112] The terms “and,” “or,” and “one / or” as used herein may have a variety of meanings, which are expected to depend at least in part on the context in which such terms are used. Generally, “or,” when used to relate a list such as, for example, A, B, or C, implies A, B, and C, used here in an inclusive sense, and A, B, or C, used here in an exclusive sense. Furthermore, the term “one or more” as used herein can be used to describe any feature, structure, or property in the singular form, or can be used to describe some combination of features, structures, or properties. However, it should be noted that this is merely an illustrative example, and the claimed subject matter is not limited to this example. Additionally, if the term “at least one of” is used to relate a list (e.g., A, B, or C), it can be interpreted as referring to any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0113] Throughout this specification, the terms "an example," "an example," "some examples," or "exemplary implementation" refer to a particular feature, structure, or characteristic described in conjunction with a feature and / or example that may be included in at least one feature and / or example of the claimed subject matter. Therefore, the appearance of the phrases "in an example," "an example," "some examples," or "in some implementations," or other similar phrases throughout this specification does not necessarily refer to the same feature, example, and / or limitation. Furthermore, a particular feature, structure, or characteristic may be combined in one or more examples and / or features.

[0114] In the foregoing detailed description, numerous specific details have been set forth to provide a comprehensive understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other instances, methods and apparatus known to those of ordinary skill in the art have not been described in detail so as not to obscure the claimed subject matter. Therefore, it is intended that the claimed subject matter be limited to the specific examples disclosed, but rather that such claimed subject matter may also encompass all aspects falling within the scope of the appended claims and their equivalents.

Claims

1. An electronic circuit, said electronic circuit comprising: A transistor, the transistor comprising a gate terminal, a source terminal, and a drain terminal; and Gate driver circuit, the gate driver circuit comprising: A pull-down transistor, the pull-down transistor being coupled to the gate terminal; and An input terminal is arranged to receive an input signal and generate a corresponding output signal at an output terminal coupled to the gate terminal; The gate driver circuit is arranged to store energy collected from the input signal and to use the stored energy to change the conduction state of the pull-down transistor from the on state to the off state.

2. The electronic circuit of claim 1, wherein the transistor comprises gallium nitride (GaN).

3. The electronic circuit of claim 2, wherein the pull-down transistor comprises GaN.

4. The electronic circuit of claim 1, wherein the gate drive circuit comprises silicon.

5. The electronic circuit according to claim 1, wherein the gate driver circuit and the transistor are disposed within an integrated electronic package.

6. The electronic circuit according to claim 5, wherein the integrated electronic package includes a power input contact, a power output contact, and an input signal contact.

7. The electronic circuit of claim 1, wherein the input signal is a pulse width modulation (PWM) signal comprising a series of on and off commands.

8. The electronic circuit of claim 7, wherein the gate driver circuit is arranged to change the conduction state of the pull-down transistor from the off state to the on state during the off command of the PWM signal.

9. The electronic circuit of claim 5, wherein the electronic circuit comprises an integrated electronic package having a first external contact, a second external contact, and a third external contact.

10. The electronic circuit of claim 1, wherein the transistor and the gate driver circuit are disposed within a TO-247 package.

11. The electronic circuit according to claim 5, wherein the integrated electronic package is a TO leadless (TOLL) package.

12. The electronic circuit of claim 7, wherein the gate driver circuit includes an energy harvesting circuit coupled to the gate terminal, and wherein the energy harvesting circuit is arranged to store energy harvested from the input signal, and to operate the gate driver circuit using the stored energy when the PWM signal is in an off command.

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