Comparator and data converter

Abstract

The application provides a comparator, comprising several stages of preamplifier circuits, a dynamic latch comparison circuit and an error elimination circuit, a first input end and a second input end of a first stage of preamplifier circuits are used for receiving data to be compared, a first input end of a later stage of preamplifier circuits is connected with a first output end of a former stage of preamplifier circuits, a second input end of the later stage of preamplifier circuits is connected with a second output end of the former stage of preamplifier circuits, a first input end of the dynamic latch comparison circuit is connected with a first output end of a last stage of preamplifier circuits, a second input end of the dynamic latch comparison circuit is connected with a second output end of the last stage of preamplifier circuits, and the error elimination circuit is connected with part of the preamplifier circuits and the dynamic latch comparison circuit, so as to eliminate input errors of the preamplifier circuits and input errors of the dynamic latch comparison circuit, and further reduce errors of the comparator.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a comparator and data converter. Background Technology

[0002] A Successive Approximation Analog-Digital Converter (SAR ADC) is a type of data converter that performs successive comparisons during each data conversion process. The circuit internally uses a binary divider method to compare the input analog signal, ultimately converting the input analog signal into a several-bit output digital signal. A high-precision voltage comparator is used during the successive comparison process.

[0003] In the prior art, input errors in voltage comparators are eliminated by error elimination circuits. However, the error elimination circuits use transmission gates as switches, and the leakage current from the source and drain of the transmission gates to the substrate is inconsistent, which can also cause additional errors.

[0004] Therefore, it is necessary to provide a new type of comparator and data converter to solve the above-mentioned problems existing in the prior art. Summary of the Invention

[0005] The purpose of this invention is to provide a comparator and data converter to reduce input errors.

[0006] To achieve the above objectives, the comparator of the present invention includes several stages of preamplifier circuits, a dynamic latch comparator circuit, and an error elimination circuit. The first and second input terminals of the first stage preamplifier circuit are respectively used to receive the data to be compared. The first input terminal of the subsequent stage preamplifier circuit is connected to the first output terminal of the previous stage preamplifier circuit, and the second input terminal of the subsequent stage preamplifier circuit is connected to the second output terminal of the previous stage preamplifier circuit. The first input terminal of the dynamic latch comparator circuit is connected to the first output terminal of the last stage preamplifier circuit, and the second input terminal of the dynamic latch comparator circuit is connected to the second output terminal of the last stage preamplifier circuit. The error elimination circuit is connected to a portion of the preamplifier circuit and the dynamic latch comparator circuit to eliminate the input error of the preamplifier circuit and the input error of the dynamic latch comparator circuit.

[0007] The beneficial effect of the comparator is that the error elimination circuit is connected to part of the preamplifier circuit and the dynamic latch comparator circuit to eliminate the input error of the preamplifier circuit and the input error of the dynamic latch comparator circuit, thereby reducing the error of the comparator.

[0008] Optionally, the preamplifier circuit includes a first-stage preamplifier circuit, a second-stage preamplifier circuit, a third-stage preamplifier circuit, and a fourth-stage preamplifier circuit. The first input terminal and the second input terminal of the first-stage preamplifier circuit are respectively used to receive the data to be compared. The first input terminal of the second-stage preamplifier circuit is connected to the first output terminal of the first-stage preamplifier circuit, and the second input terminal of the second-stage preamplifier circuit is connected to the second output terminal of the first-stage preamplifier circuit. The first input terminal of the third-stage preamplifier circuit is connected to the first output terminal of the second-stage preamplifier circuit, and the second input terminal of the third-stage preamplifier circuit is connected to the second output terminal of the second-stage preamplifier circuit. The first input terminal of the fourth-stage preamplifier circuit is connected to the first output terminal of the third-stage preamplifier circuit, and the second input terminal of the fourth-stage preamplifier circuit is connected to the second output terminal of the third-stage preamplifier circuit.

[0009] Optionally, the error elimination circuit is connected to the third-stage preamplifier circuit, the fourth-stage preamplifier circuit, and the dynamic latch comparator circuit.

[0010] Optionally, the first-stage preamplifier circuit, the second-stage preamplifier circuit, the third-stage preamplifier circuit, and the fourth-stage preamplifier circuit each include a first resistor, a second resistor, a first NMOS transistor, a second NMOS transistor, and a first current source. One end of the first resistor and one end of the second resistor are both connected to the power supply voltage. The other end of the first resistor is connected to the drain of the first NMOS transistor, and the other end of the second resistor is connected to the drain of the second NMOS transistor. The sources of the first NMOS transistor and the second NMOS transistor are connected to the positive terminal of the first current source. The negative terminal of the first current source is grounded. The gate of the first NMOS transistor is the first input terminal, and the gate of the second NMOS transistor is the second input terminal.

[0011] Optionally, the dimensions of the first NMOS transistor and the second NMOS transistor in the first-stage preamplifier circuit and the second-stage preamplifier circuit are greater than the dimensions of the first NMOS transistor and the second NMOS transistor in the third-stage preamplifier circuit and the fourth-stage preamplifier circuit.

[0012] Optionally, the error elimination circuit includes several error elimination sub-circuits, each including a capacitor and a switch. One end of the capacitor is connected to one end of the switch, and the other end of the switch is connected to a threshold voltage.

[0013] Optionally, the dynamic latch comparator circuit includes a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a second current source. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the power supply voltage. The drain of the first PMOS transistor is connected to the drain of the third NMOS transistor, the gate of the second PMOS transistor, and the gate of the fourth NMOS transistor. The drain of the second PMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the first PMOS transistor, and the gate of the third NMOS transistor. The source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor, serving as the first output terminal of the dynamic latch comparator circuit. The source of the fourth NMOS transistor is connected to the drain of the sixth NMOS transistor, serving as the second output terminal of the dynamic latch comparator circuit. The sources of both the fifth and sixth NMOS transistors are connected to the positive terminal of the second current source, and the negative terminal of the second current source is grounded. The gate of the fifth NMOS transistor is the first input terminal of the dynamic latch comparator circuit, and the gate of the sixth NMOS transistor is the second input terminal of the dynamic latch comparator circuit.

[0014] The present invention also provides a data converter including the comparator. Attached Figure Description

[0015] Figure 1 This is a circuit diagram of a conventional comparator in the prior art;

[0016] Figure 2 This is a schematic diagram of a switch in the prior art;

[0017] Figure 3 This is a circuit diagram of a comparator in some embodiments of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.

[0019] Figure 1This is a circuit diagram of a conventional comparator in the prior art. (Refer to...) Figure 1 A conventional comparator includes a first-stage preamplifier circuit 101, a second-stage preamplifier circuit 102, a third-stage preamplifier circuit 103, a fourth-stage preamplifier circuit 104, a dynamic latch comparator circuit 105, and an error cancellation circuit.

[0020] Reference Figure 1 The first-stage preamplifier circuit 101, the second-stage preamplifier circuit 102, the third-stage preamplifier circuit 103, and the fourth-stage preamplifier circuit 104 each include a first resistor 1011, a second resistor 1012, a first NMOS transistor 1013, a second NMOS transistor 1014, and a first current source 1015. One end of the first resistor 1011 and one end of the second resistor 1012 are connected to the power supply voltage. The other end of the first resistor 1011 is connected to the drain of the first NMOS transistor 1013 as a second output terminal. The other end of the second resistor 1012 is connected to the drain of the second NMOS transistor 1014 as a first output terminal. The sources of the first NMOS transistor 1013 and the second NMOS transistor 1014 are connected to the positive terminal of the first current source 1015. The negative terminal of the first current source 1015 is grounded. The gate of the first NMOS transistor 1013 is the first input terminal, and the gate of the second NMOS transistor 1014 is the second input terminal.

[0021] Reference Figure 1The dynamic latch comparator circuit 105 includes a first PMOS transistor 1051, a second PMOS transistor 1052, a third NMOS transistor 1053, a fourth NMOS transistor 1054, a fifth NMOS transistor 1055, a sixth NMOS transistor 1056, and a second current source 1057. The sources of the first PMOS transistor 1051 and the second PMOS transistor 1052 are both connected to the power supply voltage. The drain of the first PMOS transistor 1051 is connected to the drain of the third NMOS transistor 1053, the gate of the second PMOS transistor 1052, and the gate of the fourth NMOS transistor 1054. The drain of the second PMOS transistor 1052 is connected to the drain of the fourth NMOS transistor 1054, the gate of the first PMOS transistor 1051, and the gate of the third NMOS transistor 1056. The gate of the third NMOS transistor 1053 is connected, the source of the third NMOS transistor 1053 is connected to the drain of the fifth NMOS transistor 1055, serving as the first output terminal of the dynamic latch comparator circuit 105. The source of the fourth NMOS transistor 1054 is connected to the drain of the sixth NMOS transistor 1056, serving as the second output terminal of the dynamic latch comparator circuit 105. The sources of the fifth NMOS transistor 1055 and the sixth NMOS transistor 1056 are both connected to the positive terminal of the second current source 1057. The negative terminal of the second current source 1057 is grounded. The gate of the fifth NMOS transistor 1055 is the first input terminal of the dynamic latch comparator circuit 105, and the gate of the sixth NMOS transistor 1056 is the second input terminal of the dynamic latch comparator circuit 105.

[0022] Reference Figure 1The error elimination circuit includes eight error elimination sub-circuits, namely, a first error elimination sub-circuit 1061, a second error elimination sub-circuit 1062, a third error elimination sub-circuit 1063, a fourth error elimination sub-circuit 1064, a fifth error elimination sub-circuit 1065, a sixth error elimination sub-circuit 1066, a seventh error elimination sub-circuit 1067, and an eighth error elimination sub-circuit 1068. The first error elimination sub-circuit 1061 includes a first capacitor 10611 and a first switch 10612, and the second error elimination sub-circuit 1062 includes a second capacitor 10621 and a second switch 10622. The third error elimination subcircuit 1063 includes a third capacitor 10631 and a third switch 10632; the fourth error elimination subcircuit 1064 includes a fourth capacitor 10641 and a fourth switch 10642; the fifth error elimination subcircuit 1065 includes a fifth capacitor 10651 and a fifth switch 10652; the sixth error elimination subcircuit 1066 includes a sixth capacitor 10661 and a sixth switch 10662; the seventh error elimination subcircuit 1067 includes a seventh capacitor 10671 and a seventh switch 10672; and the eighth error elimination subcircuit 1068 includes an eighth capacitor 10681 and an eighth switch 10682.

[0023] Reference Figure 1 One end of the first capacitor 10611 is connected to one end of the first switch 10612 and the gate of the first NMOS transistor 1013 of the second-stage preamplifier circuit 102. The other end of the first capacitor 10611 is connected to the drain of the second NMOS transistor 1014 of the first-stage preamplifier circuit 101. The other end of the first switch 10612 is connected to the threshold voltage Vcom. One end of the second capacitor 10621 is connected to one end of the second switch 10622 and the gate of the second NMOS transistor 1014 of the second-stage preamplifier circuit 102. The other end of the second capacitor 10621 is connected to the drain of the first NMOS transistor 1013 of the first-stage preamplifier circuit 101. The other end of the second switch 10622 is connected to the threshold voltage Vcom.

[0024] Reference Figure 1One end of the third capacitor 10631 is connected to one end of the third switch 10632 and the gate of the first NMOS transistor 1013 of the third-stage preamplifier circuit 103. The other end of the third capacitor 10631 is connected to the drain of the second NMOS transistor 1014 of the second-stage preamplifier circuit 102. The other end of the third switch 10632 is connected to the threshold voltage Vcom. One end of the fourth capacitor 10641 is connected to one end of the fourth switch 10642 and the gate of the second NMOS transistor 1014 of the third-stage preamplifier circuit 103. The other end of the fourth capacitor 10641 is connected to the drain of the first NMOS transistor 1013 of the second-stage preamplifier circuit 102. The other end of the fourth switch 10642 is connected to the threshold voltage Vcom.

[0025] Reference Figure 1 One end of the fifth capacitor 10651 is connected to one end of the fifth switch 10652 and the gate of the first NMOS transistor 1013 of the fourth-stage preamplifier circuit 104. The other end of the fifth capacitor 10651 is connected to the drain of the second NMOS transistor 1014 of the third-stage preamplifier circuit 103. The other end of the fifth switch 10652 is connected to the threshold voltage Vcom. One end of the sixth capacitor 10661 is connected to one end of the sixth switch 10662 and the gate of the second NMOS transistor 1014 of the fourth-stage preamplifier circuit 104. The other end of the sixth capacitor 10661 is connected to the drain of the first NMOS transistor 1013 of the third-stage preamplifier circuit 103. The other end of the sixth switch 10662 is connected to the threshold voltage Vcom.

[0026] Reference Figure 1 One end of the seventh capacitor 10671 is connected to one end of the seventh switch 10672 and the gate of the fifth NMOS transistor 1055. The other end of the seventh capacitor 10671 is connected to the drain of the second NMOS transistor 1014 of the fourth preamplifier circuit. The other end of the seventh switch 10672 is connected to the threshold voltage Vcom. One end of the eighth capacitor 10681 is connected to one end of the eighth switch 10682 and the gate of the sixth NMOS transistor 1056. The other end of the eighth capacitor 10681 is connected to the drain of the first NMOS transistor 1013 of the fourth preamplifier circuit 104. The other end of the eighth switch 10682 is connected to the threshold voltage Vcom.

[0027] Reference Figure 1The first input terminal of the first-stage preamplifier circuit 101 is used to receive the first comparison data Vinp, and the second input terminal of the first-stage preamplifier circuit 101 is used to receive the second comparison data Vinn. The input error of the first input terminal of the first-stage preamplifier circuit 101 is Vos1, and the gain of the first-stage preamplifier circuit 101 is A1. The input error of the first input terminal of the second-stage preamplifier circuit 102 is Vos2, and the gain of the first-stage preamplifier circuit 101 is A2. The input error of the first input terminal of the third-stage preamplifier circuit 103 is Vos3, and the gain of the first-stage preamplifier circuit 101 is A3. The input error of the first input terminal of the fourth-stage preamplifier circuit 104 is Vos4, and the gain of the first-stage preamplifier circuit 101 is A4. Therefore, the total error Vos = Vos1 + Vos2 / A1 + Vos3 / A2 / A1 + Vos4 / A3 / A2 / A1.

[0028] Figure 2 This is a schematic diagram of a switch in the prior art. (Refer to...) Figure 1 and Figure 2 The circuits of the first switch 10612, the second switch 10622, the third switch 10632, the fourth switch 10642, the fifth switch 10652, the sixth switch 10662, the seventh switch 10672, and the eighth switch 10682 are all... Figure 2 The switch shown is identical to the one described above, and is a transmission gate composed of a PMOS transistor and an NMOS transistor. When the switch is off, the gate of the PMOS transistor is connected to the power supply voltage Vdd, and the gate of the NMOS transistor is grounded to Vss; when the switch is on, the gate of the PMOS transistor is grounded to Vss, and the gate of the NMOS transistor is connected to the power supply voltage Vdd.

[0029] Reference Figure 1 Leakage current exists in the first-stage preamplifier circuit 101, the second-stage preamplifier circuit 102, the third-stage preamplifier circuit 103, and the fourth-stage preamplifier circuit 104, with the leakage current effect of the previous stage being more pronounced than that of the next stage. Taking the first-stage preamplifier circuit 101 as an example, during the comparison phase, point A is the gate of the first NMOS transistor 1013 in the second-stage preamplifier circuit 102, and point B is the gate of the second NMOS transistor 1014 in the second-stage preamplifier circuit 102. The voltages at points A and B are different, which results in a different leakage current from point A to the substrate of the first switch 10612 and a different leakage current from point B to the substrate of the second switch 10622, leading to a different current I flowing through the first switch 10612. leakAWith the current I flowing through the second switch 10622 leakB The difference in charge loss rate between the electrode plates of the first capacitor 10611 and the second capacitor 10621 results in a different rate of charge loss at one end, causing the voltage change rate ΔVa at point A to differ from the voltage change rate ΔVb at point B. This phenomenon is equivalent to creating an error voltage V between points A and B. offset Furthermore, the higher the temperature, the greater the error voltage V. offset The larger it is.

[0030] Reference Figure 1 Taking Vinp = 1.2V, Vinn = 1.199V, A1 = A2 = 10 as an example, Vinp - Vinn = 1mV, the voltage at point A Va = 1.2V, the voltage at point B Vb = 1.19V, Va - Vb = 10mV. The first-stage preamplifier circuit 101 amplifies 1mV to 10mV. At this point, the correct relationship is Va > Vb. However, due to the leakage effect, ΔVa = 0.05V, ΔVb = 0.02V, so the actual Va = 1.2 - 0.05 = 1.15V, and the actual Vb = 1.19 - 0.02 = 1.17V. Therefore, it will be incorrectly judged that Va > Vb. <Vb。

[0031] To address the problems existing in the prior art, embodiments of the present invention provide a comparator, including several stages of preamplifier circuits, a dynamic latch comparator circuit, and an error elimination circuit. The first and second input terminals of the first-stage preamplifier circuit are respectively used to receive data to be compared. The first input terminal of the subsequent-stage preamplifier circuit is connected to the first output terminal of the preceding-stage preamplifier circuit, and the second input terminal of the subsequent-stage preamplifier circuit is connected to the second output terminal of the preceding-stage preamplifier circuit. The first input terminal of the dynamic latch comparator circuit is connected to the first output terminal of the last-stage preamplifier circuit, and the second input terminal of the dynamic latch comparator circuit is connected to the second output terminal of the last-stage preamplifier circuit. The error elimination circuit is connected to a portion of the preamplifier circuits and the dynamic latch comparator circuit to eliminate the input errors of the preamplifier circuits and the dynamic latch comparator circuit.

[0032] In some embodiments, the preamplifier circuit includes a first-stage preamplifier circuit, a second-stage preamplifier circuit, a third-stage preamplifier circuit, and a fourth-stage preamplifier circuit. The first input terminal and the second input terminal of the first-stage preamplifier circuit are respectively used to receive data to be compared. The first input terminal of the second-stage preamplifier circuit is connected to the first output terminal of the first-stage preamplifier circuit, and the second input terminal of the second-stage preamplifier circuit is connected to the second output terminal of the first-stage preamplifier circuit. The first input terminal of the third-stage preamplifier circuit is connected to the first output terminal of the second-stage preamplifier circuit, and the second input terminal of the third-stage preamplifier circuit is connected to the second output terminal of the second-stage preamplifier circuit. The first input terminal of the fourth-stage preamplifier circuit is connected to the first output terminal of the third-stage preamplifier circuit, and the second input terminal of the fourth-stage preamplifier circuit is connected to the second output terminal of the third-stage preamplifier circuit.

[0033] In some embodiments, the error elimination circuit is connected to the third-stage preamplifier circuit, the fourth-stage preamplifier circuit, and the dynamic latch comparator circuit.

[0034] In some embodiments, the error elimination circuit includes several error elimination sub-circuits, each including a capacitor and a switch. One end of the capacitor is connected to one end of the switch, and the other end of the switch is connected to a threshold voltage.

[0035] Figure 3 This is a circuit diagram of a comparator in some embodiments of the present invention. (Refer to...) Figure 3 The comparator includes a first-stage preamplifier circuit 101, a second-stage preamplifier circuit 102, a third-stage preamplifier circuit 103, a fourth-stage preamplifier circuit 104, a dynamic latch comparator circuit 105, and an error elimination circuit.

[0036] Reference Figure 3The first-stage preamplifier circuit 101, the second-stage preamplifier circuit 102, the third-stage preamplifier circuit 103, and the fourth-stage preamplifier circuit 104 each include a first resistor 1011, a second resistor 1012, a first NMOS transistor 1013, a second NMOS transistor 1014, and a first current source 1015. One end of the first resistor 1011 and one end of the second resistor 1012 are connected to the power supply voltage. The other end of the first resistor 1011 is connected to the drain of the first NMOS transistor 1013, and the other end of the second resistor 1012 is connected to the drain of the second NMOS transistor 1014. The sources of the first NMOS transistor 1013 and the second NMOS transistor 1014 are connected to the positive terminal of the first current source 1015. The negative terminal of the first current source 1015 is grounded. The gate of the first NMOS transistor 1013 is the first input terminal, and the gate of the second NMOS transistor 1014 is the second input terminal. The data to be compared includes a first data to be compared and a second data to be compared. The gate of the first NMOS transistor 1013 of the first-stage preamplifier circuit 101 is connected to the first data to be compared, and the gate of the second NMOS transistor 1014 of the first-stage preamplifier circuit 101 is connected to the second data to be compared.

[0037] Reference Figure 3 The dimensions of the first NMOS transistor 1013 and the second NMOS transistor 1014 in the first-stage preamplifier circuit 101 and the second-stage preamplifier circuit 102 are greater than the dimensions of the first NMOS transistor 1013 and the second NMOS transistor 1014 in the third-stage preamplifier circuit 103 and the fourth-stage preamplifier circuit 104.

[0038] Reference Figure 3The dynamic latch comparator circuit 105 includes a first PMOS transistor 1051, a second PMOS transistor 1052, a third NMOS transistor 1053, a fourth NMOS transistor 1054, a fifth NMOS transistor 1055, a sixth NMOS transistor 1056, and a second current source 1057. The sources of the first PMOS transistor 1051 and the second PMOS transistor 1052 are both connected to the power supply voltage. The drain of the first PMOS transistor 1051 is connected to the drain of the third NMOS transistor 1053, the gate of the second PMOS transistor 1052, and the gate of the fourth NMOS transistor 1054. The drain of the second PMOS transistor 1052 is connected to the drain of the fourth NMOS transistor 1054, the gate of the first PMOS transistor 1051, and the gate of the third NMOS transistor 1056. The gate of the third NMOS transistor 1053 is connected, the source of the third NMOS transistor 1053 is connected to the drain of the fifth NMOS transistor 1055, serving as the first output terminal of the dynamic latch comparator circuit 105. The source of the fourth NMOS transistor 1054 is connected to the drain of the sixth NMOS transistor 1056, serving as the second output terminal of the dynamic latch comparator circuit 105. The sources of the fifth NMOS transistor 1055 and the sixth NMOS transistor 1056 are both connected to the positive terminal of the second current source 1057. The negative terminal of the second current source 1057 is grounded. The gate of the fifth NMOS transistor 1055 is the first input terminal of the dynamic latch comparator circuit 105, and the gate of the sixth NMOS transistor 1056 is the second input terminal of the dynamic latch comparator circuit 105.

[0039] Reference Figure 3 The error elimination circuit includes six error elimination sub-circuits, namely, a third error elimination sub-circuit 1063, a fourth error elimination sub-circuit 1064, a fifth error elimination sub-circuit 1065, a sixth error elimination sub-circuit 1066, a seventh error elimination sub-circuit 1067, and an eighth error elimination sub-circuit 1068. The third error elimination sub-circuit 1063 includes a third capacitor 10631 and a third switch 10632; the fourth error elimination sub-circuit 1064 includes a fourth capacitor 10641 and a fourth switch 10642; the fifth error elimination sub-circuit 1065 includes a fifth capacitor 10651 and a fifth switch 10652; the sixth error elimination sub-circuit 1066 includes a sixth capacitor 10661 and a sixth switch 10662; the seventh error elimination sub-circuit 1067 includes a seventh capacitor 10671 and a seventh switch 10672; and the eighth error elimination sub-circuit 1068 includes an eighth capacitor 10681 and an eighth switch 10682.

[0040] Reference Figure 3One end of the third capacitor 10631 is connected to one end of the third switch 10632 and the gate of the first NMOS transistor 1013 of the third-stage preamplifier circuit 103. The other end of the third capacitor 10631 is connected to the drain of the second NMOS transistor 1014 of the second-stage preamplifier circuit 102. The other end of the third switch 10632 is connected to the threshold voltage Vcom. One end of the fourth capacitor 10641 is connected to one end of the fourth switch 10642 and the gate of the second NMOS transistor 1014 of the third-stage preamplifier circuit 103. The other end of the fourth capacitor 10641 is connected to the drain of the first NMOS transistor 1013 of the second-stage preamplifier circuit 102. The other end of the fourth switch 10642 is connected to the threshold voltage Vcom.

[0041] Reference Figure 3 One end of the fifth capacitor 10651 is connected to one end of the fifth switch 10652 and the gate of the first NMOS transistor 1013 of the fourth-stage preamplifier circuit 104. The other end of the fifth capacitor 10651 is connected to the drain of the second NMOS transistor 1014 of the third-stage preamplifier circuit 103. The other end of the fifth switch 10652 is connected to the threshold voltage Vcom. One end of the sixth capacitor 10661 is connected to one end of the sixth switch 10662 and the gate of the second NMOS transistor 1014 of the fourth-stage preamplifier circuit 104. The other end of the sixth capacitor 10661 is connected to the drain of the first NMOS transistor 1013 of the third-stage preamplifier circuit 103. The other end of the sixth switch 10662 is connected to the threshold voltage Vcom.

[0042] Reference Figure 3 One end of the seventh capacitor 10671 is connected to one end of the seventh switch 10672 and the gate of the fifth NMOS transistor 1055. The other end of the seventh capacitor 10671 is connected to the drain of the second NMOS transistor 1014 of the fourth preamplifier circuit. The other end of the seventh switch 10672 is connected to the threshold voltage Vcom. One end of the eighth capacitor 10681 is connected to one end of the eighth switch 10682 and the gate of the sixth NMOS transistor 1056. The other end of the eighth capacitor 10681 is connected to the drain of the first NMOS transistor 1013 of the fourth preamplifier circuit 104. The other end of the eighth switch 10682 is connected to the threshold voltage Vcom.

[0043] Reference Figure 3Point A is the gate of the first NMOS transistor 1013 in the second-stage preamplifier circuit 102, point B is the gate of the second NMOS transistor 1014 in the second-stage preamplifier circuit 102, point C is the gate of the first NMOS transistor 1013 in the third-stage preamplifier circuit 103, and point D is the gate of the second NMOS transistor 1014 in the third-stage preamplifier circuit 103.

[0044] Reference Figure 3 Taking Vinp = 1.2V, Vinn = 1.199V, A1 = A2 = 10 as an example, Vinp - Vinn = 1mV, voltage at point A Va = 1.2V, voltage at point B Vb = 1.19V, Va - Vb = 10mV, voltage at point C Vc = 1.2V, voltage at point D Vd = 1.1V, Vc - Vd = 100mV, the voltage change rate at point C ΔVc = 0.05V, and the voltage change rate at point D ΔVd = 0.02V. Therefore, the actual Vc = 1.2 - 0.05 = 1.15V, and the actual Vd = 1.1 - 0.02 = 1.08V. Thus, the final judgment is Vc > Vd, and the judgment is correct. Furthermore, the subsequent leakage effect has a smaller impact, so the judgment result must also be correct. Therefore, the error has been successfully eliminated.

[0045] The present invention also provides a data converter, including a comparator. Specifically, the data converter is a successive approximation analog-to-digital converter.

[0046] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A comparator, characterized in that, The system includes several stages of preamplifier circuits, dynamic latch comparator circuits, and error elimination circuits. The first and second input terminals of the first-stage preamplifier circuit are used to receive the data to be compared. The first input terminal of the next-stage preamplifier circuit is connected to the first output terminal of the previous-stage preamplifier circuit, and the second input terminal of the next-stage preamplifier circuit is connected to the second output terminal of the previous-stage preamplifier circuit. The first input terminal of the dynamic latch comparator circuit is connected to the first output terminal of the last-stage preamplifier circuit, and the second input terminal of the dynamic latch comparator circuit is connected to the second output terminal of the last-stage preamplifier circuit. The error elimination circuit is connected to a portion of the preamplifier circuits and the dynamic latch comparator circuits to eliminate the input errors of the preamplifier circuits and the dynamic latch comparator circuits. The preamplifier circuit includes a first-stage preamplifier circuit, a second-stage preamplifier circuit, a third-stage preamplifier circuit, and a fourth-stage preamplifier circuit. The first input terminal and the second input terminal of the first-stage preamplifier circuit are respectively used to receive data to be compared. The first input terminal of the second-stage preamplifier circuit is connected to the first output terminal of the first-stage preamplifier circuit, and the second input terminal of the second-stage preamplifier circuit is connected to the second output terminal of the first-stage preamplifier circuit. The first input terminal of the third-stage preamplifier circuit is connected to the first output terminal of the second-stage preamplifier circuit, and the second input terminal of the fourth-stage preamplifier circuit is connected to the second output terminal of the third-stage preamplifier circuit. The error elimination circuit is connected to the third-stage preamplifier circuit, the fourth-stage preamplifier circuit, and the dynamic latch comparator circuit.

2. The comparator according to claim 1, characterized in that, The first-stage preamplifier circuit, the second-stage preamplifier circuit, the third-stage preamplifier circuit, and the fourth-stage preamplifier circuit all include a first resistor, a second resistor, a first NMOS transistor, a second NMOS transistor, and a first current source. One end of the first resistor and one end of the second resistor are both connected to the power supply voltage. The other end of the first resistor is connected to the drain of the first NMOS transistor, and the other end of the second resistor is connected to the drain of the second NMOS transistor. The sources of the first NMOS transistor and the second NMOS transistor are connected to the positive terminal of the first current source. The negative terminal of the first current source is grounded. The gate of the first NMOS transistor is the first input terminal, and the gate of the second NMOS transistor is the second input terminal.

3. The comparator according to claim 2, characterized in that, The dimensions of the first NMOS transistor and the second NMOS transistor in the first-stage preamplifier circuit and the second-stage preamplifier circuit are greater than the dimensions of the first NMOS transistor and the second NMOS transistor in the third-stage preamplifier circuit and the fourth-stage preamplifier circuit.

4. The comparator according to claim 1, characterized in that, The error elimination circuit includes several error elimination sub-circuits, each including a capacitor and a switch. One end of the capacitor is connected to one end of the switch, and the other end of the switch is connected to a threshold voltage.

5. The comparator according to claim 1, characterized in that, The dynamic latch comparator circuit includes a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a second current source. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the power supply voltage. The drain of the first PMOS transistor is connected to the drain of the third NMOS transistor, the gate of the second PMOS transistor, and the gate of the fourth NMOS transistor. The drain of the second PMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the first PMOS transistor, and the gate of the third NMOS transistor. The source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor, serving as the first output terminal of the dynamic latch comparator circuit. The source of the fourth NMOS transistor is connected to the drain of the sixth NMOS transistor, serving as the second output terminal of the dynamic latch comparator circuit. The sources of both the fifth and sixth NMOS transistors are connected to the positive terminal of the second current source, and the negative terminal of the second current source is grounded. The gate of the fifth NMOS transistor is the first input terminal of the dynamic latch comparator circuit, and the gate of the sixth NMOS transistor is the second input terminal of the dynamic latch comparator circuit.

6. A data converter comprising a comparator as described in any one of claims 1 to 5.

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