Display device and method of manufacturing the same

Abstract

A display device and a manufacturing method thereof are provided, the display device including a first base layer including a first opening, a first barrier layer on a surface of the first base layer and including a second opening, and a pad electrode on the first barrier layer and overlapping the second opening in a plan view. At least one first recess is formed at a surface of the first barrier layer, a second recess is formed at a surface of the pad electrode, and the first opening exposes the at least one first recess and the second recess.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2021-0086006, filed on June 30, 2021, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosure generally relates to a display device and a method for manufacturing the same. Background Technology

[0003] With increasing interest in information displays and demand for portable information media, research and commercialization have focused on display devices. Summary of the Invention

[0004] An embodiment provides a display device and a method for manufacturing the same, wherein short circuits in the display device can be prevented.

[0005] According to one aspect of the disclosure, a display device is provided, the display device comprising: a first substrate layer including a first opening; a first barrier layer located on a surface of the first substrate layer and including a second opening; and a pad electrode located on the first barrier layer and superimposed on the second opening in a plan view. At least one first groove is formed at the surface of the first barrier layer, a second groove is formed at the surface of the pad electrode, and the first opening exposes at least one first groove and the second groove.

[0006] The pad electrode and the chip on the film can be electrically connected to each other through the first opening.

[0007] The pad electrode and the chip on the film can be electrically connected to each other via a connecting ball.

[0008] The connecting ball can be located in the second groove formed in the pad electrode.

[0009] The pad electrode may include a first layer and a second layer. The first layer may include titanium, and the second layer may include copper.

[0010] The second groove can be formed on the lower surface of the second layer.

[0011] The display device may further include: a second barrier layer, stacked in a plan view with the upper surface of the first barrier layer and the upper surface of the pad electrode; a second substrate layer, located on the second barrier layer; and a pixel circuit layer, located on the second substrate layer. The pixel circuit layer may include data lines.

[0012] The second substrate layer may include openings filled with a conductive material. Data lines can be electrically connected to the pad electrodes through the conductive material.

[0013] According to another aspect of the disclosure, a method for manufacturing a display device is provided, the method comprising the steps of: forming at least one metal portion on the surface of a substrate layer; forming a first barrier layer on the substrate layer and the at least one metal portion; forming a pad electrode on the first barrier layer; forming a second barrier layer on the first barrier layer and the pad electrode; forming a first opening in the substrate layer; forming a first groove at the lower surface of the first barrier layer by removing at least one metal portion; and forming a second groove at the lower surface of the pad electrode by partially removing the pad electrode.

[0014] The steps of forming the first groove and forming the second groove may include using an atmospheric pressure plasma process to form the first groove and the second groove.

[0015] The step of forming the first barrier layer may include: depositing the first barrier layer on a substrate layer and at least one metal portion; and forming a second opening in the first barrier layer.

[0016] The step of forming a pad electrode may include: depositing a pad electrode material on a first barrier layer; and forming a pad electrode such that a portion of the pad electrode overlaps with a second opening in a plan view.

[0017] A second groove can be formed on the lower surface of the pad electrode in the second opening.

[0018] The connecting ball that electrically connects the chip on the film and the pad electrode can be set to correspond to the second groove.

[0019] According to another aspect of the disclosure, a display device is provided, the display device comprising: at least one display panel including a first substrate layer having a first opening; a first barrier layer located on a surface of the first substrate layer, the first barrier layer including a second opening; and a pad electrode located on the first barrier layer and superimposed on the second opening in a plan view. At least one first groove is formed at the surface of the first barrier layer, and a second groove is formed at the surface of the pad electrode, and the first opening exposes at least one first groove and the second groove.

[0020] In the first opening, the pad electrode and the chip on the membrane can be electrically connected to each other via a connecting ball.

[0021] The pad electrode may include a first layer and a second layer. The first layer may include titanium, and the second layer may include copper.

[0022] The second groove can be formed on the lower surface of the second layer.

[0023] The display device may further include: a second barrier layer, stacked in a plan view with the upper surface of the first barrier layer and the upper surface of the pad electrode; a second substrate layer, located on the second barrier layer; and a pixel circuit layer, located on the second substrate layer. The pixel circuit layer may include data lines.

[0024] The second substrate layer may include openings filled with a conductive material. Data lines can be electrically connected to the pad electrodes through the conductive material. Attached Figure Description

[0025] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the exemplary embodiments to those skilled in the art.

[0026] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as "between" two elements, it can be the only element between the two elements, or there may be one or more intervening elements. The same reference numerals always denote the same element.

[0027] Figure 1 This is a schematic plan view illustrating a display device according to an embodiment.

[0028] Figure 2 This is a schematic plan view illustrating a display device according to an embodiment.

[0029] Figure 3 This is a schematic diagram illustrating the equivalent circuit of a pixel of a display device according to an embodiment.

[0030] Figure 4 This is a schematic cross-sectional view that mainly shows the pixel circuit layer and display element layer of the pixels of the display device according to an embodiment.

[0031] Figure 5 This is a schematic cross-sectional view mainly showing the pixel circuit layer, display element layer, light conversion layer, etc. of the display device according to the embodiment.

[0032] Figure 6 This is a schematic cross-sectional view mainly showing the pixel circuit layer, display element layer, light conversion layer, etc. of the display device according to the embodiment.

[0033] Figure 7 This is a schematic cross-sectional view showing a display device according to an embodiment.

[0034] Figures 8 to 10 It is shown in sequence. Figure 7 A schematic cross-sectional view of the manufacturing method of the display device shown.

[0035] Figure 11 This is a schematic cross-sectional view showing the state in which the chip on the film is attached to the display device according to an embodiment.

[0036] Figure 12 This is a schematic rear view showing a state in which a first opening is formed in the substrate layer of the display device according to an embodiment.

[0037] Figure 13 This is a schematic rear view showing the state in which the chip on the film is attached to the display device according to an embodiment. Detailed Implementation

[0038] The disclosure can be applied to various changes and different shapes, therefore detailed descriptions are given only by specific examples. However, the examples are not limited to certain shapes, but are applicable to all changes and equivalent materials and substitutions. The included figures are shown in a manner that expands upon the figures for better understanding.

[0039] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, the “first” element discussed below may also be referred to as the “second” element without departing from the teaching. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise.

[0040] It will also be understood that, when used in this specification, the term "comprising" and / or variations thereof indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence and / or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Furthermore, the expression that an element, such as a layer, region, substrate, or plate, is placed "on" or "above" another element indicates not only that the element is placed "directly" on or "straight above" another element, but also that another element is placed between the two elements. Conversely, the expression that an element, such as a layer, region, substrate, or plate, is placed "below" or "under" another element indicates not only that the element is placed "directly" below or "straight below" another element, but also that another element is placed between the two elements.

[0041] As used herein, the terms “about” or “approximately” include the stated value and mean within an acceptable range of deviation from the stated value, as determined by a person of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0042] It will be understood that the terms “contact,” “connected to,” and “bonded to” can include physical and / or electrical contact, connection, or bonding, and vice versa.

[0043] For the purposes of its meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one of the groups of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0044] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure.

[0045] The embodiments will be described in detail below with reference to the accompanying drawings.

[0046] Figure 1 This is a schematic plan view illustrating a display device according to an embodiment. Figure 2 This is a schematic plan view illustrating a display device according to an embodiment.

[0047] Reference Figure 1 The display device can be a multi-screen display device (TDD) that includes a display panel.

[0048] A multi-screen display device (TDD, also known as a video wall display) may include display devices DD1, DD2, DD3 and DD4 arranged in a matrix on the first direction DR1 and the second direction DR2.

[0049] Display devices DD1, DD2, DD3, and DD4 can each display a single image, or display images separately. Display devices DD1, DD2, DD3, and DD4 may include display panels of the same kind, structure, size, or type, but the disclosure is not limited thereto.

[0050] Display devices DD1, DD2, DD3 and DD4 can be physically combined with each other through a housing (not shown) that can be located on the bottom of display devices DD1, DD2, DD3 and DD4 to form a multi-screen display device TDD.

[0051] Display devices DD1, DD2, DD3, and DD4 can be implemented in various shapes. Although Figure 1 The display devices DD1, DD2, DD3 and DD4 are shown to have rectangular plate shapes, but the disclosure is not limited thereto, and each of the display devices DD1, DD2, DD3 and DD4 may have a shape such as a circular shape or an elliptical shape.

[0052] Reference Figure 2 Describe display device DD1 among display devices DD1, DD2, DD3 and DD4.

[0053] The display device DD1 includes a display area DA and a non-display area NA implemented or disposed on a display panel DP. The display area DA is the area including pixels PXL, thereby displaying an image, and the non-display area NA is the area other than the display area DA, thereby not displaying an image. The non-display area NA may be a border area surrounding the display area DA.

[0054] The display area DA can be located on the surface of the display device DD1. In the example, the display area DA can be located on the front surface of the display device DD1. The display area DA can also be located on the side and rear surfaces of the display device DD1.

[0055] The non-display area NA may be located around the display area DA and may optionally include lines, pads (also called "solder pads" or "solder pads"), drive circuitry, etc., that are electrically connected to the pixels PXL of the display area DA.

[0056] The display device DD1 may include scan lines S1, ..., Si, ... and Sn, control lines CL1, ..., CLI, ... and CLn, data lines D1, ..., Dj, ... and Dm, sensing lines SEN1, ..., SENj, ... and SENm, and a pixel PXL. The pixel PXL may be electrically connected to the scan lines Si, control lines CLI, data lines Dj, and sensing lines SENj.

[0057] Despite Figure 2 Although not shown, the scan lines S1, ..., Si, ... and Sn, and the control lines CL1, ..., Cl1, ... and CLn can be electrically connected to the gate pad unit (or gate pad portion) disposed on one side of the display device DD1. Furthermore, the data lines D1, ..., Dj, ... and Dm, and the sensing lines SEN1, ..., SENj, ... and SENm can be electrically connected to the data pad portion disposed on one side of the display device DD1.

[0058] In display devices DD1, DD2, DD3, and DD4, the image displayed on the screen of the multi-screen display device TDD may be interrupted due to the non-display area NA located in the boundary region between display devices DD1, DD2, DD3, and DD4. If the non-display area NA has a relatively large width (or area), the image interruption may be amplified in the boundary region between display devices DD1, DD2, DD3, and DD4. The non-display area NA located in the boundary region between display devices DD1, DD2, DD3, and DD4 may be referred to as a seam region, assembly joint region, or invalid space region.

[0059] When the boundary area between display devices DD1, DD2, DD3, and DD4 is visually identifiable, the brightness of the image displayed on the screen of a multi-screen display device (TDD) may degrade. A back-surface bonding structure may be required, which can improve the color and brightness deviation of each display device and reduce the seam area, making the boundary area between display devices DD1, DD2, DD3, and DD4 visually indistinguishable. A back-surface bonding structure refers to a structure in which, in each of display devices DD1, DD2, DD3, and DD4, the chip-on-film (COF), flexible printed circuit board, etc., is electrically connected to the lower surface of display device DD1, DD2, DD3, or DD4. The back-surface bonding structure for reducing the seam area will be described in detail below.

[0060] Pixels PXL can be disposed within the display area DA. Each of the pixels PXL can be the smallest unit for displaying an image. Each of the pixels PXL can include a light-emitting element that emits white light and / or colored light. Each of the pixels PXL can emit light of any color among red, green, and blue. However, the disclosure is not limited thereto; each of the pixels PXL can emit light of colors such as cyan, magenta, or yellow.

[0061] Although a rectangular shape for pixel PXL has been shown in the figure, the disclosure is not limited thereto, and the shape of pixel PXL can be modified in various ways. Each of pixel PXL may include a pixel circuit layer PCL located on the substrate layer BSL, which will be described below, a display element layer DPL located on the pixel circuit layer PCL, etc.

[0062] In the following text, reference will be made to Figure 3 Describes the connection relationship of pixels in a display device according to an embodiment.

[0063] Figure 3 This is a schematic diagram illustrating the equivalent circuit of a pixel of a display device according to an embodiment.

[0064] Reference Figure 3The pixel PXL may include at least one light-emitting unit (light-emitting part) EMU for generating light with a brightness corresponding to the data signal. The pixel PXL may also optionally include a pixel circuit PXC for driving the light-emitting part EMU.

[0065] The light-emitting unit (EMU) may include a light-emitting element (LD) connected in parallel between a first power line PL1, which is subjected to a voltage of a first driving power supply VDD, and a second power line PL2, which is subjected to a voltage of a second driving power supply VSS.

[0066] The light-emitting unit (EMU) may include a first electrode EL1 electrically connected to a first driving power supply VDD via a pixel circuit PXC and a first power line PL1, a second electrode EL2 electrically connected to a second driving power supply VSS via a second power line PL2, and a light-emitting element LD connected in parallel in the same direction between the first electrode EL1 and the second electrode EL2. In an embodiment, the first electrode EL1 may be an anode, and the second electrode EL2 may be a cathode.

[0067] Each of the light-emitting elements (LDs) included in the light-emitting unit (EMU) may include one end (or the first end) electrically connected to the first driving power supply (VDD) via the first electrode (EL1) and the other end (or the second end) electrically connected to the second driving power supply (VSS) via the second electrode (EL2).

[0068] The first driving power supply VDD and the second driving power supply VSS can have different potentials. In the example, the first driving power supply VDD can be set to a high potential, and the second driving power supply VSS can be set to a low potential. During the emission period of pixel PXL, the potential difference between the first driving power supply VDD and the second driving power supply VSS can be set to be equal to or higher than the threshold voltage of the light-emitting element LD.

[0069] As described above, light-emitting elements LD, which are electrically connected in parallel in the same direction (e.g., the forward direction) between a first electrode EL1 and a second electrode EL2 supplied with voltages of different potentials, can each form an effective light source. The effective light source can constitute the light-emitting unit EMU of pixel PXL.

[0070] In some embodiments, in addition to the light-emitting element LD that forms the corresponding effective light source, the light-emitting unit (EMU) may also include at least one ineffective light source, such as a reverse light-emitting element LDr. The reverse light-emitting element LDr is connected in parallel with the light-emitting element LD that forms the effective light source between the first electrode EL1 and the second electrode EL2, and may be connected between the first electrode EL1 and the second electrode EL2 in a direction opposite to the direction along which the light-emitting element LD is electrically connected. Although a predetermined driving voltage (e.g., a forward driving voltage) is applied between the first electrode EL1 and the second electrode EL2, the reverse light-emitting element LDr remains in a deactivated state; therefore, essentially no current flows through the reverse light-emitting element LDr.

[0071] The light-emitting elements (LDs) of the light-emitting unit (EMU) can emit light with a brightness corresponding to the driving current supplied through the pixel circuit (PXC). For example, during each frame period, the pixel circuit (PXC) can supply a driving current corresponding to the grayscale value of a frame of data (or data) to the light-emitting unit (EMU). The driving current supplied to the light-emitting unit (EMU) can be shunt and flow through the light-emitting elements (LDs). Therefore, the light-emitting unit (EMU) can emit light with a brightness corresponding to the driving current, and each light-emitting element (LD) emits light with a brightness corresponding to the driving current flowing through it.

[0072] although Figure 3 An embodiment in which all light-emitting elements (LDs) constituting the light-emitting unit (EMU) are electrically connected in parallel is shown, but the disclosure is not limited thereto. In some embodiments, the light-emitting unit (EMU) may include two series stages. In some embodiments, the light-emitting elements (LDs) may be electrically connected to each other in n series stages. For example, the light-emitting unit (EMU) may be constructed in a hybrid series-parallel structure.

[0073] The pixel circuit PXC can be electrically connected to the scan line Si and data line Dj of the pixel PXL. In the example, the pixel PXL is set in the display area DA (see...). Figure 2 In the case where the pixel is in the i-th row (i is a positive integer) and j-th column (j is a positive integer), the pixel circuit PXC of pixel PXL can be electrically connected to the i-th scan line Si and the j-th data line Dj of display area DA. The pixel circuit PXC can also be electrically connected to the i-th control line CLI and the j-th sensing line SENj of display area DA.

[0074] The pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0075] The first terminal of the first transistor T1 (or driving transistor) can be electrically connected to the first driving power supply VDD, and the second terminal of the first transistor T1 can be electrically connected to the first electrode EL1 of the light-emitting element EMU. The gate electrode of the first transistor T1 can be electrically connected to the first node N1. Therefore, the first transistor T1 can control the amount of driving current supplied to the light-emitting element LD according to the voltage of the first node N1.

[0076] In an embodiment, the first transistor T1 may optionally include a bottom metal layer BML. For example, in a plan view, the gate electrode of the first transistor T1 and the bottom metal layer BML may be stacked on top of each other, and an insulating layer is disposed between the gate electrode of the first transistor T1 and the bottom metal layer BML.

[0077] The first terminal of the second transistor T2 (or switching transistor) can be electrically connected to the data line Dj, and the second terminal of the second transistor T2 can be electrically connected to the first node N1. The gate electrode of the second transistor T2 can be electrically connected to the scan line Si. When a scan signal (high level) with a conduction voltage is supplied from the scan line Si, the second transistor T2 can be turned on to electrically connect the data line Dj and the first node N1 to each other. When a frame data signal is supplied to the data line Dj, the data signal is transmitted to the first node N1. The storage capacitor Cst can be changed according to the data signal transmitted to the first node N1.

[0078] A third transistor T3 can be electrically connected between the first transistor T1 and the sensing line SENj. A first terminal of the third transistor T3 can be electrically connected to a second terminal of the first transistor T1, and a second terminal of the third transistor T3 can be electrically connected to the sensing line SENj. The gate electrode of the third transistor T3 can be electrically connected to the control line CLI. The third transistor T3 can be turned on by a control signal (high level) having a gate on-state voltage (which is supplied to the control line CLI during the sensing period) to electrically connect the sensing line SENj and the first transistor T1 to each other. The sensing period can be the period in which characteristic information (e.g., the threshold voltage of the first transistor T1, etc.) of each of the pixels PXL set in the display area DA is extracted.

[0079] One electrode of the storage capacitor Cst can be electrically connected to the first node N1, and the other electrode of the storage capacitor Cst can be electrically connected to the second terminal of the first transistor T1. The storage capacitor Cst can be charged to a voltage corresponding to the difference between the voltage of the data signal supplied to the first node N1 and the voltage of the second terminal of the first transistor T1, and the charged voltage is maintained until the data signal of the next frame is supplied.

[0080] although Figure 3An embodiment in which the first transistor T1 to the third transistor T3 are N-type transistors is shown, but the disclosure is not limited thereto. In some embodiments, at least one of the first transistor T1 to the third transistor T3 may be changed to a P-type transistor.

[0081] although Figure 3 An embodiment is shown in which the light-emitting unit EMU is electrically connected between the pixel circuit PXC and the second driving power supply VSS, but the light-emitting unit EMU can also be electrically connected between the first driving power supply VDD and the pixel circuit PXC.

[0082] In the following text, reference will be made to Figures 4 to 6 The structure of the pixels of the display device according to the embodiment is described in detail.

[0083] Figure 4 This is a schematic cross-sectional view that mainly shows the pixel circuit layer and display element layer of the pixels of the display device according to an embodiment. Figure 5 This is a schematic cross-sectional view that mainly shows the pixel circuit layer, display element layer, light conversion layer, etc. of the pixels of the display device according to the embodiment. Figure 6 This is a schematic cross-sectional view mainly showing the pixel circuit layer, display element layer, light conversion layer, etc. of the display device according to the embodiment.

[0084] First, refer to Figure 4 and Figure 5 According to the embodiment, the pixel PXL may include a first substrate layer BSL1, a pixel circuit layer PCL, a display element layer DPL, a light conversion layer LCL, and a thin film encapsulation layer TFE.

[0085] The first substrate layer BSL1 can be a rigid substrate or a flexible substrate. For example, when the first substrate layer BSL1 is a rigid substrate, it can be formed as a glass substrate, a quartz substrate, a glass-ceramic substrate, a crystalline glass substrate, etc. When the first substrate layer BSL1 is a flexible substrate, it can be formed as a polymer organic substrate, such as polyimide or polyamide, or a plastic substrate.

[0086] The pixel circuit layer PCL is located on the first substrate layer BSL1.

[0087] The pixel circuit layer PCL may include at least one transistor, a storage capacitor, and wires electrically connected thereto. The pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, and / or a passivation layer PSV, sequentially stacked on the surface of the first substrate layer BSL1.

[0088] A bottom metal layer BML is located on the first substrate layer BSL1. The bottom metal layer BML is positioned such that at least a portion of the bottom metal layer BML is stacked with the semiconductor pattern SCP and gate electrode GAT of the first transistor T1, which will be described below. The bottom metal layer BML can be electrically connected to the second electrode TE2 of the first transistor T1 through contact holes of the buffer layer BFL, the gate insulating layer GI, and the first interlayer insulating layer ILD1. The second electrode TE2 of the first transistor T1 can be connected to... Figure 3 The second terminal of the first transistor T1 shown is substantially the same or similar.

[0089] The buffer layer BFL is located on the first substrate layer BSL1 and the bottom metal layer BML. The buffer layer BFL may cover the first substrate layer BSL1 and the bottom metal layer BML (or be stacked with the first substrate layer BSL1 and the bottom metal layer BML). The buffer layer BFL prevents impurities from diffusing from the outside into the pixel circuit layer PCL. The buffer layer BFL may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) and such as aluminum oxide (AlO) x At least one of the metal oxides of (). For example, the buffer layer BFL may have approximately The thickness. In some embodiments, the buffer layer BFL may be omitted.

[0090] The semiconductor pattern SCP of the first transistor T1 is located on the buffer layer BFL. The semiconductor pattern SCP may include a channel region and source and drain regions located on both sides of the channel region. The source region of the semiconductor pattern SCP may be electrically connected to the second electrode TE2, and the drain region of the semiconductor pattern SCP may be electrically connected to the first electrode TE1. For example, the source and drain regions may extend to be electrically connected to electrodes of another layer through contact holes, respectively.

[0091] The semiconductor pattern SCP may include at least one of polycrystalline silicon, amorphous silicon, and oxide semiconductor.

[0092] The gate insulating layer GI is located on the semiconductor pattern SCP and the buffer layer BFL. The gate insulating layer GI covers (or is stacked with) the semiconductor pattern SCP and the buffer layer BFL. The gate insulating layer GI may comprise an inorganic material. In this example, the gate insulating layer GI may comprise silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) and aluminum oxide (AlO x At least one of the following. In some embodiments, the gate insulating layer GI may include an organic material.

[0093] The gate electrode GAT of the first transistor T1 is located on the gate insulating layer GI. The gate electrode GAT can be positioned to overlap with the channel region of the semiconductor pattern SCP.

[0094] The first interlayer insulating layer ILD1 is located on the gate electrode GAT and the gate insulating layer GI. The first interlayer insulating layer ILD1 covers the gate electrode GAT and the gate insulating layer GI.

[0095] The first interlayer insulating layer ILD1 and the gate insulating layer GI may comprise the same material. In this example, the first interlayer insulating layer ILD1 may comprise silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) and aluminum oxide (AlO x At least one of the following.

[0096] The first electrode TE1 and the second electrode TE2 of the first transistor T1 are located on the first interlayer insulating layer ILD1. The first electrode TE1 can be a drain electrode electrically connected to the drain region of the semiconductor pattern SCP, and the second electrode TE2 can be a source electrode electrically connected to the source region of the semiconductor pattern SCP. The first electrode TE1 can be connected to... Figure 3 The first terminals of the first transistor T1 shown are substantially the same or similar. Therefore, the first electrode TE1 can be connected via the first electric field line PL1 (see...). Figure 3 A first drive power supply VDD (see) is applied. Figure 3 The voltage of the first drive power supply VDD is transmitted to the first electrode EL1, which will be described below, via the first contact hole CH1. The second electrode TE2 can be physically connected and / or electrically connected to the first electrode EL1 of the display element layer DPL through the first contact hole CH1. Therefore, the first transistor T1 can transmit the voltage of the first drive power supply VDD to the first electrode EL1. In some embodiments, the first electrode TE1 can be the source electrode, and the second electrode TE2 can be the drain electrode.

[0097] The driving voltage line DVL is located on the first interlayer insulation layer ILD1. The driving voltage line DVL and... Figure 3 A portion of the second power line PL2 shown can have the same construction. The drive voltage line DVL can be physically connected and / or electrically connected to the second electrode EL2 of the display element layer DPL, which will be described below, via the second contact hole CH2. Therefore, the drive voltage line DVL can transmit the second drive power supply VSS (see...) Figure 3 The voltage of ) is transmitted to the second electrode EL2.

[0098] The second interlayer insulating layer ILD2 is located on the first interlayer insulating layer ILD1, the first electrode TE1 of the first transistor T1, the second electrode TE2 of the first transistor T1, and the driving voltage line DVL. The second interlayer insulating layer ILD2 covers the first interlayer insulating layer ILD1, the first electrode TE1 of the first transistor T1, the second electrode TE2 of the first transistor T1, and the driving voltage line DVL (or is superimposed on the first interlayer insulating layer ILD1, the first electrode TE1 of the first transistor T1, the second electrode TE2 of the first transistor T1, and the driving voltage line DVL).

[0099] The second interlayer insulating layer ILD2 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N y At least one of the following. In some embodiments, the second interlayer insulation layer ILD2 may be an organic insulation layer comprising organic materials.

[0100] The passivation layer PSV is located on the second interlayer insulating layer ILD2. The passivation layer PSV may include at least one organic insulating layer and substantially planarizes the surface of the pixel circuit layer PCL. The passivation layer PSV may be constructed as a single layer or multiple layers and may include inorganic and organic insulating materials. For example, the passivation layer PSV may include at least one of polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0101] The display element layer (DPL) is located on the pixel circuit layer (PCL), which includes the passivation layer (PSV). The first contact hole (CH1) of the passivation layer (PSV) allows the second electrode (TE2) of the first transistor (T1) to be electrically connected to the first electrode (EL1) of the display element layer (DPL). The drive voltage line (DVL) and the second electrode (EL2) of the display element layer (DPL) can be electrically connected to each other through the second contact hole (CH2) of the passivation layer (PSV).

[0102] The display element layer (DPL) may include a light-emitting element (LD) for each pixel (PXL) and electrodes electrically connected to the LD. The LD may be a micro-inorganic light-emitting diode as small as nanometers or micrometers, fabricated by growing a nitride-based semiconductor. In embodiments, each LD may be a micro-inorganic light-emitting diode with a columnar or cylindrical shape having an aspect ratio greater than 1, but the disclosure is not limited thereto.

[0103] The display element layer (DPL) may include a first dam (BNK1), a second dam (BNK2), a first electrode (EL1) and a second electrode (EL2), a first insulating layer (INS1), a light-emitting element (LD), a second insulating layer (INS2), a first contact electrode (CNE1), a second contact electrode (CNE2), and a third insulating layer (INS3).

[0104] The first dam BNK1 is located on the passivation layer PSV. The first dam BNK1 may be disposed on the bottom of the portions of the first electrode EL1 and the second electrode EL2 to guide the light emitted from the light-emitting element LD in the image display direction of the display device (e.g., the upward direction of each pixel PXL, for example, the third direction DR3), such that the portions of the first electrode EL1 and the second electrode EL2 may protrude in the upward direction (e.g., the third direction DR3).

[0105] The first dike BNK1 may include an inorganic insulating layer made of inorganic materials or an organic insulating layer made of organic materials. In some embodiments, the first dike BNK1 may include a single organic insulating layer or a single inorganic insulating layer, but the disclosure is not limited thereto.

[0106] The second dam BNK2 is located on the passivation layer PSV. The second dam BNK2 is a structure for defining the emission region of each of the pixels PXL, and may be located in the non-emission region of each pixel PXL to surround the emission region of each pixel PXL. For example, the second dam BNK2 may be a pixel defining layer or a dam structure. The second dam BNK2 may include at least one light-blocking material and at least one reflective material. In some embodiments, the second dam BNK2 may be implemented as a dam structure superimposed on the first light-blocking portion LBP1, which will be described below, to define the area in which the light-emitting element LD is supplied (or input) in each pixel PXL.

[0107] Each of the first electrode EL1 and the second electrode EL2 is located on the first dam BNK1 and has a surface corresponding to the shape of the first dam BNK1. The first electrode EL1 and the second electrode EL2 may comprise a material with uniform reflectivity. Therefore, the first electrode EL1 and the second electrode EL2 enable light emitted from the light-emitting element LD to travel in the image display direction of the display device (e.g., third direction DR3). In an embodiment, the first electrode EL1 may be an anode and the second electrode EL2 may be a cathode.

[0108] The first insulating layer INS1 is located between the passivation layer PSV and each of the first contact electrode CNE1 and the second contact electrode CNE2. The first insulating layer INS1 can fill the space between the light-emitting element LD and the passivation layer PSV to stably support the light-emitting element LD. The first insulating layer INS1 may include at least one material selected from inorganic insulating materials and organic insulating materials, and is constructed as a single layer or multiple layers.

[0109] The light-emitting element LD is located on the first insulating layer INS1. At least one light-emitting element LD may be disposed between the first electrode EL1 and the second electrode EL2. In some embodiments, the light-emitting elements LD may be disposed between the first electrode EL1 and the second electrode EL2 and connected in parallel with each other.

[0110] Each of the light-emitting elements (LDs) can emit light of any color, white, and blue. In an embodiment, the LDs can be configured to be sprayed in a solution to be input to each pixel PXL.

[0111] The light-emitting element LD may include a first semiconductor layer SCL1, an active layer ACT, and a second semiconductor layer SCL2 sequentially disposed in a first direction DR1. The light-emitting element LD may also include an insulating film (not shown) surrounding the outer peripheral surfaces of the first semiconductor layer SCL1, the active layer ACT, and the second semiconductor layer SCL2.

[0112] The first semiconductor layer SCL1 may include a semiconductor of a first conductivity type. For example, the first semiconductor layer SCL1 may include at least one P-type semiconductor layer. In the example, the first semiconductor layer SCL1 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and includes a P-type semiconductor layer doped with a first conductivity type dopant (or P-type dopant) such as Mg.

[0113] The active layer ACT can be formed in a single quantum well structure or a multi-quantum well structure. In some embodiments, materials such as AlGaN or AlInGaN can be used to form the active layer ACT. The active layer ACT can be formed from various materials. The position of the active layer ACT can be varied depending on the type of light-emitting element LD. The active layer ACT can emit light with a wavelength of about 400 nm to about 900 nm and uses a dual heterostructure.

[0114] The second semiconductor layer SCL2 may include a semiconductor layer of a different type than the first semiconductor layer SCL1. For example, the second semiconductor layer SCL2 may include at least one N-type semiconductor layer. In the example, the second semiconductor layer SCL2 may include any one of the semiconductor materials InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be an N-type semiconductor layer doped with a second conductivity type dopant (or an N-type dopant) such as Si, Ge, or Sn.

[0115] The end of the first semiconductor layer SCL1 in one direction can be referred to as the first end EP1 of the light-emitting element LD, and the other end of the second semiconductor layer SCL2 in one direction can be referred to as the second end EP2 of the light-emitting element LD.

[0116] The second insulating layer INS2 is located on a portion of the light-emitting element LD. The second insulating layer INS2 covers a portion of the top surface of each light-emitting element LD and exposes the first end EP1 and the second end EP2 of the light-emitting element LD. The second insulating layer INS2 can stably fix the light-emitting element LD. In the case where there is a void between the first insulating layer INS1 and the light-emitting element LD before the formation of the second insulating layer INS2, the void can be at least partially filled with the second insulating layer INS2.

[0117] The first contact electrode CNE1 is located on the first electrode EL1, and the first contact electrode CNE1 physically connects and / or electrically connects the first electrode EL1 to an end of the light-emitting element LD (e.g., the first end EP1). The first contact electrode CNE1 may be positioned to overlap with portions of the first insulating layer INS1, the second insulating layer INS2, the first electrode EL1, and the light-emitting element LD. The first insulating layer INS1 may be removed from the portion where the first electrode EL1 and the first contact electrode CNE1 are electrically connected to each other (e.g., the portion where the first electrode EL1 and the first contact electrode CNE1 are in direct contact with each other).

[0118] The second contact electrode CNE2 is located on the second electrode EL2, and the second contact electrode CNE2 physically connects and / or electrically connects the second electrode EL2 to an end of the light-emitting element LD (e.g., the second end EP2). The second contact electrode CNE2 may be positioned to overlap with portions of the first insulating layer INS1, the second insulating layer INS2, the second electrode EL2, and the light-emitting element LD. The first insulating layer INS1 may be removed from the portion where the second electrode EL2 and the second contact electrode CNE2 are electrically connected to each other (e.g., the portion where the second electrode EL2 and the second contact electrode CNE2 are in direct contact with each other).

[0119] The first contact electrode CNE1 and the second contact electrode CNE2 can be made of a transparent conductive material. For example, the first contact electrode CNE1 and the second contact electrode CNE2 can include materials such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). Therefore, the first contact electrode CNE1 and the second contact electrode CNE2 enable light emitted from the light-emitting element LD and then reflected by the first electrode EL1 and the second electrode EL2 to travel in the image display direction of the display device (e.g., the third direction DR3).

[0120] The third insulating layer INS3 is located above the first contact electrode CNE1, the second contact electrode CNE2, and the second embankment BNK2. The third insulating layer INS3 may include at least one organic layer and at least one inorganic layer, and is located entirely on the surface of the display element layer DPL.

[0121] Reference Figure 5 The light conversion layer LCL is located on the display element layer DPL.

[0122] The light conversion layer LCL may include at least one of a color conversion layer CCL containing quantum dots (e.g., red quantum dots QDr or green quantum dots QDg) and a color filter CF located on the display element layer DPL or the color conversion layer CCL. The light conversion layer LCL may also include, sequentially disposed on the display element layer DPL, a color conversion layer CCL, a cover layer CVL, a first light-blocking portion LBP1, a first planarization layer PLL1, a color filter CF, and a second light-blocking portion LBP2.

[0123] The color conversion layer (CCL) is disposed above the light-emitting element (LD) and may include color conversion particles (e.g., quantum dots (QDs) of a certain color) for converting light of a first color emitted from the LD into light of a second color.

[0124] For example, when at least one pixel PXL is set as a red (or green) pixel PXL and a blue light-emitting element LD is set as the light source of pixel PXL, a color conversion layer CCL including a red (or green) quantum dot QD for converting blue light into red (or green) light can be disposed above pixel PXL. A red (or green) color filter CF can be disposed above the color conversion layer CCL.

[0125] The cover layer CVL used to protect the color conversion layer CCL can be located on top of the color conversion layer CCL. The first light blocking part LBP1 can be set in an area corresponding to the outside of the color conversion layer CCL.

[0126] The first planarization layer PLL1 may be located on the cover layer CVL and the first light-blocking portion LBP1. The first planarization layer PLL1 can planarize the top surfaces of the color conversion layer CCL and the first light-blocking portion LBP1, and includes organic or inorganic materials.

[0127] A color filter CF can be disposed in the light-emitting region of each pixel PXL. The color filter CF may include a color filter material that allows light of the color corresponding to the color of each pixel PXL to selectively pass through it. A second light-blocking part LBP2 may be disposed outside the color filter CF.

[0128] The thin-film encapsulation layer TFE is located on the light conversion layer LCL.

[0129] The thin-film encapsulation layer (TFE) can be constructed as a single layer or multiple layers. The TFE may include an insulating layer covering the display element layer (DPL). In an example, the TFE may include at least one inorganic layer and at least one organic layer. For instance, the TFE may have a structure in which inorganic and organic layers are alternately stacked.

[0130] The thin-film encapsulation layer TFE may include a first encapsulation layer ENC1, a second encapsulation layer ENC2, and a third encapsulation layer ENC3. For example, the first encapsulation layer ENC1 and the third encapsulation layer ENC3 may be constructed as inorganic layers comprising inorganic materials, and the second encapsulation layer ENC2 may be constructed as an organic layer comprising organic materials.

[0131] Reference Figure 6 The display device according to the embodiment may include a first substrate layer BSL1, a pixel circuit layer PCL, a display element layer DPL, a light conversion layer LCL, a film layer FIL, a second substrate layer BSL2, a first blocking layer BRL1, a second blocking layer BRL2, and a pad electrode PAD. Figure 6 The first substrate layer BSL1, pixel circuit layer PCL, and display element layer DPL shown in the figure are in contrast to the reference layer. Figure 4 and Figure 5 The first substrate layer BSL1, pixel circuit layer PCL, and display element layer DPL are described as being basically similar; therefore, the differences between them will be mainly described below.

[0132] The first substrate layer BSL1 may further include openings, and a conductive material CM may fill the openings in the first substrate layer BSL1. The conductive material CM can electrically connect the data line DL, which will be described below, to the pad electrode PAD.

[0133] The pixel circuit layer PCL may also include a data line DL located between the first substrate layer BSL1 and the buffer layer BFL. The data line DL can be connected to... Figure 2 and Figure 3 The data line (multiple data lines) shown corresponds to a portion of DL.

[0134] The data line DL can be electrically connected to the pad electrode PAD through the conductive material CM filled in the opening of the first substrate layer BSL1.

[0135] The pixel circuit layer PCL may include a first transistor T1, and the first transistor T1 may include a bottom metal layer BML, a semiconductor pattern SCP, a gate electrode GAT, a first electrode TE1, and a second electrode TE2. The second electrode TE2 may be electrically connected to the source region of the semiconductor pattern SCP, and the first electrode TE1 may be electrically connected to the drain region of the semiconductor pattern SCP. The first transistor T1 may be a P-type transistor. Therefore, the first electrode TE1 of the first transistor T1 may be physically connected and / or electrically connected to the first electrode EL1 of the display element layer DPL.

[0136] Pixel PXL can include a first sub-pixel PXL1, a second sub-pixel PXL2, and a third sub-pixel PXL3.

[0137] The light conversion layer LCL may include first color filters to third color filters CF1, CF2 and CF3 corresponding to the colors of the first to third sub-pixels PXL1, PXL2 and PXL3.

[0138] The first color filter CF1 can be located above the first sub-pixel PXL1 to allow light generated from the first sub-pixel PXL1 to selectively pass through it. For example, the first color filter CF1 can be a blue color filter.

[0139] The second color filter CF2 can be positioned above the second sub-pixel PXL2 to allow light generated from the second sub-pixel PXL2 to selectively pass through it. For example, the second color filter CF2 can be a green color filter.

[0140] The third color filter CF3 can be positioned above the third sub-pixel PXL3 to allow light generated from the third sub-pixel PXL3 to selectively pass through it. For example, the third color filter CF3 can be a red color filter.

[0141] The first light-blocking portion LBP1 is a portion used to block light and is located above the second dam BNK2. The first light-blocking portion LBP1 can be located between the light-scattering layer LSL of the scatterer SCT and the first color conversion layer CCL1, between the first color conversion layer CCL1 and the second color conversion layer CCL2, etc. The first light-blocking portion LBP1 and the second dam BNK2 can be made of the same material, but the disclosure is not limited thereto. The first light-blocking portion LBP1 and the second dam BNK2 together can have a dam structure that defines the area in which the light-emitting element LD is supplied in the first sub-pixel to the third sub-pixel PXL1, PXL2, and PXL3.

[0142] The second light-blocking portion LBP2 is a portion used to block light and is located on the first planarization layer PLL1. The second light-blocking portion LBP2 may be located between the first color filter CF1 and the second color filter CF2, and between the second color filter CF2 and the third color filter CF3.

[0143] In some embodiments, the second light-blocking portion LBP2 can be configured such that portions of at least two of the first color filter CF1, the second color filter CF2, and the third color filter CF3 are stacked on top of each other. For example, the second light-blocking portion LBP2 located between the first color filter CF1 and the second color filter CF2 may include a portion of the first color filter CF1, a portion of the third color filter CF3, and a portion of the second color filter CF2, and the portions of the first to third color filters CF1, CF2, and CF3 may be stacked to block light. The second light-blocking portion LBP2 located between the second color filter CF2 and the third color filter CF3 may include a portion of the first color filter CF1 and a portion of the third color filter CF3, and the portions of the first and third color filters CF1 and CF3 may be stacked to block light.

[0144] The second planarization layer PLL2 may be located on the first to third color filters CF1, CF2 and CF3 and the second light blocking portion LBP2. The second planarization layer PLL2 can planarize the top surface of the first to third color filters CF1, CF2 and CF3 and the second light blocking portion LBP2, and includes organic or inorganic materials.

[0145] The film layer FIL is located on the second planarization layer PLL2 and can be a film layer that prevents the reflection of light incident from the outside. For example, the film layer FIL may include a protective film, triacetyl cellulose (TAC), and pressure-sensitive adhesive (PSA).

[0146] In some embodiments, the thin film encapsulation layer may be located between the second planarization layer PLL2 and the film layer FIL, and the film layer FIL may be omitted.

[0147] The second substrate layer BSL2 is located below the first substrate layer BSL1 and may include a first opening OPN1. The chip on the film can be electrically connected to the display device through the first opening OPN1.

[0148] The first barrier layer BRL1 and the second barrier layer BRL2 can be located between the first substrate layer BSL1 and the second substrate layer BSL2.

[0149] The pad electrode PAD can be located between the first substrate layer BSL1 and the second substrate layer BSL2.

[0150] The pad electrode (PAD) can be electrically connected to the data line (DL) via the conductive material (CM).

[0151] In some embodiments, the lower film and the heat dissipation film may be located below the second substrate layer BSL2. Additionally, the on-film chip may be located between the second substrate layer BSL2 and the lower film, and on the bottom of the heat dissipation film. In some embodiments, the positions of the lower film, the heat dissipation film, and the on-film chip of the display device can be varied.

[0152] In the following text, reference will be made to Figures 7 to 10 A display device and a method of manufacturing the same according to an embodiment are described.

[0153] Figure 7 This is a schematic cross-sectional view showing a display device according to an embodiment. Figures 8 to 10 It is shown in sequence. Figure 7 A schematic diagram of the manufacturing method of the display device shown.

[0154] Reference Figure 7 The display device may include a second substrate layer BSL2, a first barrier layer BRL1, a pad electrode PAD, a second barrier layer BRL2, a first substrate layer BSL1, a buffer layer BFL, a pixel circuit layer PCL, a display element layer DPL, a light conversion layer LCL, and a film layer FIL. The first substrate layer BSL1, buffer layer BFL, pixel circuit layer PCL, display element layer DPL, light conversion layer LCL, and film layer FIL are compared with a reference... Figure 6 The first substrate layer BSL1, buffer layer BFL, pixel circuit layer PCL, display element layer DPL, light conversion layer LCL, and film layer FIL are substantially the same or similar, therefore, their repeated descriptions will be omitted.

[0155] The second substrate layer BSL2 (or substrate BSL) can be a rigid substrate or a flexible substrate. For example, when the second substrate layer BSL2 is a rigid substrate, it can be a glass substrate, a quartz substrate, a glass-ceramic substrate, a crystalline glass substrate, etc. When the second substrate layer BSL2 is a flexible substrate, it can be a polymer organic substrate including polyimide, polyamide, etc., a plastic substrate, etc.

[0156] The second substrate layer BSL2 may include a first opening OPN1. The first opening OPN1 of the second substrate layer BSL2 may expose at least one surface (e.g., the lower surface) of the first barrier layer BRL1, which will be described below, and at least one surface (e.g., the lower surface) of the pad electrode PAD, which will be described below. The first opening OPN1 of the second substrate layer BSL2 may expose a first groove GRO1 formed on the lower surface of the first barrier layer BRL1 and a second groove GRO2 formed on the lower surface of the pad electrode PAD.

[0157] The pad electrode PAD and the chip on the film can be electrically connected to each other through the first opening OPN1 of the second substrate layer BSL2.

[0158] The first barrier layer BRL1 is located on the surface of the second substrate layer BSL2. For example, the first barrier layer BRL1 can be located on the top surface of the second substrate layer BSL2. The first barrier layer BRL1 may include amorphous silicon, silicon oxide (SiO2), etc. x ) and such as aluminum oxide (AlO) x At least one of the metal oxides of ). For example, the first barrier layer BRL1 may have approximately The thickness. However, disclosure is not limited to this.

[0159] The first barrier layer BRL1 may include a second opening OPN2. At least a portion of the pad electrode PAD, as described below, may be located in the second opening OPN2 of the first barrier layer BRL1.

[0160] The first barrier layer BRL1 may include at least one first groove GRO1 formed on its surface. The first groove GRO1 may be formed on the lower surface of the first barrier layer BRL1, and the lower surface of the first barrier layer BRL1 with the first groove GRO1 may be disposed in the first opening OPN1 of the second substrate layer BSL2. For example, at least one first groove GRO1 formed on the first barrier layer BRL1 may be exposed to the outside. In some embodiments, a desiccant, an anti-vibration agent, etc., may be located in the first groove GRO1.

[0161] The pad electrode PAD is located on the first barrier layer BRL1 and is positioned to cover the second opening OPN2 of the first barrier layer BRL1 (or to be stacked with the second opening OPN2 of the first barrier layer BRL1). For example, the pad electrode PAD can be stacked with at least a portion of the top surface of the first barrier layer BRL1 and at least a portion of the side surface of the first barrier layer BRL1 through the second opening OPN2.

[0162] The pad electrode PAD may include a first layer PADa and a second layer PADb. For example, the first layer PADa may include titanium (Ti) or be made of titanium (Ti), and the second layer PADb may include copper (Cu) or be made of copper (Cu). The first layer PADa may have approximately The thickness of the second layer of PADb can be approximately [missing information]. The thickness of the pad electrode PAD. However, the disclosure is not limited to this, and in some embodiments the material forming the pad electrode PAD can be varied. The thickness of the pad electrode PAD can be varied.

[0163] The pad electrode PAD may include a second groove GRO2 formed on its surface. The second groove GRO2 may be formed on the lower surface of the second layer PADb of the pad electrode PAD disposed in the second opening OPN2 of the first barrier layer BRL1. In an embodiment, the second groove GRO2 may be formed on the lower surface of the pad electrode PAD disposed in the second opening OPN2 of the first barrier layer BRL1 when the first layer PADa of the pad electrode PAD disposed in the second opening OPN2 of the first barrier layer BRL1 is removed by an atmospheric pressure plasma process.

[0164] Connecting balls (or solder balls) can be located in the second groove GRO2 of the pad electrode PAD to electrically connect the chip on film and the pad electrode PAD to each other. For example, in an embodiment, since the second groove GRO2 is formed on the lower surface of the pad electrode PAD, the point (or dot) where the connecting balls are positioned during the soldering process can be easily detected, and the connecting balls can be prevented from being arbitrarily distributed on the lower surface of the display device. Therefore, the connecting balls that electrically connect the pad electrode PAD and the chip on film to each other are stably positioned, thereby preventing short circuits between the pad electrode PAD and the chip on film.

[0165] In one embodiment, a spray welding process can be used to electrically connect the pad electrode (PAD) to the chip on the film, thereby preventing damage to the display panel.

[0166] The second barrier layer BRL2 is located on the surfaces of the first barrier layer BRL1 and the pad electrode PAD. For example, the second barrier layer BRL2 can be located on the first barrier layer BRL1 and the pad electrode PAD. The second barrier layer BRL2 can cover the upper surface of the first barrier layer BRL1 and the upper surface of the pad electrode PAD.

[0167] The second barrier layer BRL2 may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) and such as aluminum oxide (AlO) x The second barrier layer BRL2 may be configured as a single layer or multiple layers, comprising at least one metal oxide of silicon nitride (SiN). x ) and silicon dioxide (SiO) x The double layer consists of silicon nitride (SiN). The second barrier layer, BRL2, is made of silicon nitride (SiN). x The first layer made can have approximately The thickness of the second barrier layer BRL2 is that it is made of silicon oxide (SiO2). x The second layer made can have approximately The thickness of the second barrier layer BRL2 is not limited to this. However, the disclosure is not limited to this. The second barrier layer BRL2 may include various materials and have various thicknesses.

[0168] The first substrate layer BSL1, buffer layer BFL, pixel circuit layer PCL, display element layer DPL, light conversion layer LCL, and film layer FIL may be sequentially located on the second barrier layer BRL2. However, the disclosure is not limited thereto. In some embodiments, at least one of the buffer layer BFL, light conversion layer LCL, and film layer FIL may be omitted.

[0169] Reference Figure 8 Prepare a substrate layer (BSL) and form at least one metal part (MET) on the surface of the substrate layer (BSL). The at least one metal part (MET) can be formed by depositing a metal material on the substrate layer (BSL) and patterning the deposited metal material by a photolithography process including exposure, development, wet etching, etc.

[0170] The metal part MET may include metallic materials. For example, the metal part MET may include materials such as titanium (Ti), but the disclosure is not limited thereto.

[0171] The metal part MET is used to form a first groove GRO1 on the lower surface of the first barrier layer BRL1. The metal part MET can be formed to correspond to the position, shape, size, etc. of the first groove GRO1. For example, as Figure 8 As shown, three metal parts METs are positioned adjacent to each other, and two metal parts METs are positioned spaced apart from the three adjacent metal parts METs. However, the disclosure is not limited thereto. In some embodiments, the position, shape, size, etc., of the metal parts METs can be varied.

[0172] Reference Figure 9 A first barrier layer BRL1, a pad electrode PAD, and a second barrier layer BRL2 can be sequentially formed on the substrate layer BSL and the metal part MET.

[0173] First, by completely depositing the first barrier layer BRL1 on the substrate layer BSL and the metal part MET, and patterning the deposited first barrier layer BRL1 through photolithography processes including exposure, development, wet etching, etc., a second opening OPN2 can be formed in the first barrier layer BRL1.

[0174] A pad electrode (PAD) can be formed by depositing a pad electrode material on a first barrier layer (BRL1) and patterning the deposited pad electrode material using photolithography processes including exposure, development, and wet etching. The pad electrode (PAD) can be located in a second opening (OPN2) of the first barrier layer (BRL1), and the lower surface of the pad electrode (PAD) formed in the second opening (OPN2) of the first barrier layer (BRL1) can contact the top surface of the substrate layer (BSL).

[0175] Subsequently, a second barrier layer BRL2 can be deposited to cover the surface of the first barrier layer BRL1 and the pad electrode PAD (or to be superimposed on the surface of the first barrier layer BRL1 and the pad electrode PAD).

[0176] Reference Figure 10 The first substrate layer BSL1, buffer layer BFL, pixel circuit layer PCL, display element layer DPL, light conversion layer LCL and film layer FIL can be sequentially formed on the second barrier layer BRL2.

[0177] The method for forming the first substrate layer BSL1, buffer layer BFL, pixel circuit layer PCL, display element layer DPL, light conversion layer LCL, and film layer FIL is substantially the same as or similar to the manufacturing method of a general display device, and therefore its detailed description will be omitted.

[0178] Return to reference Figure 7 A first opening OPN1 is formed in the substrate layer BSL, a first groove GRO1 is formed on the lower surface of the first barrier layer BRL1 by removing the metal portion MET, and a second groove GRO2 is formed on the lower surface of the pad electrode PAD by removing a portion of the pad electrode PAD. In this case, an atmospheric pressure plasma process can be used.

[0179] In this embodiment, when the metal portion MET disposed on the bottom of the first barrier layer BRL1 is removed by an atmospheric pressure plasma process, a first groove GRO1 can be formed on the lower surface of the first barrier layer BRL1. When the first layer PADa of the pad electrode PAD disposed in the second opening OPN2 of the first barrier layer BRL1 is removed by an atmospheric pressure plasma process, a second groove GRO2 can be formed on the lower surface of the pad electrode PAD disposed in the second opening OPN2 of the first barrier layer BRL1.

[0180] In the following text, reference will be made to Figures 11 to 13 The description describes the state in which the chip on the film is attached to the display device according to an embodiment.

[0181] Figure 11 This is a schematic cross-sectional view showing the state in which the chip on the film is attached to the display device according to an embodiment. Figure 12 This is a schematic rear view showing the state in which a first opening is formed in the substrate layer of the display device according to an embodiment. Figure 13 This is a schematic rear view showing the state in which the chip on the film is attached to the display device according to an embodiment.

[0182] First, refer to Figure 11 The display device according to the embodiment may further include Figure 7The display device shown includes a chip on film (COF) and a connecting ball (SB).

[0183] A chip-on-film (COF) can include a flexible film (FF) and a lead part (LDP) disposed on the flexible film FF. The COF can electrically connect the pad electrode (PAD) of a display device to the flexible printed circuit board.

[0184] The flexible film FF and the guide portion LDP can be located on the surface of the first barrier layer BRL1 and the surface of the pad electrode PAD. The flexible film FF can be positioned such that at least a portion of the flexible film FF overlaps with the lower surface of the first barrier layer BRL1, and can also be positioned such that at least a portion of the flexible film FF overlaps with the lower surface of the pad electrode PAD.

[0185] Although the flexible film FF is in direct contact with the lower surface of the first barrier layer BRL1, the flexible film FF can prevent a step difference between the flexible film FF and the display panel by means of the first groove GRO1 formed on the lower surface of the first barrier layer BRL1, which may occur when the lower surface of the first barrier layer BRL1 and the flexible film FF are in direct contact with each other.

[0186] The connecting ball SB is positioned such that at least a portion of the connecting ball SB is stacked with the lower surface of the pad electrode PAD and the on-film chip COF. The connecting ball SB may be disposed on the side surface of the on-film chip COF. The connecting ball SB contacts both the pad electrode PAD and the on-film chip COF to electrically connect the pad electrode PAD and the on-film chip COF to each other.

[0187] In the spray welding process, the connecting ball SB can be placed on the lower surface of the pad electrode PAD to correspond to the second groove GRO2.

[0188] In this embodiment, since the second groove GRO2 is formed on the lower surface of the pad electrode PAD, the location of the connecting ball SB during the spray welding process can be easily detected, and the connecting ball SB can be prevented from being arbitrarily distributed on the lower surface of the display device. Therefore, the connecting ball SB, which electrically connects the pad electrode PAD to the chip on film COF, is stably positioned, thereby preventing short circuits between the pad electrode PAD and the chip on film COF.

[0189] Reference Figure 12 The rear view of the display device according to the embodiment shows that it is viewed from a third-party upward perspective. Figure 2 The state shown in the display device is such that the first barrier layer BRL1, the pad electrode PAD, the second barrier layer BRL2, and the second substrate layer BSL2 are attached to the lower surface of the display panel DP.

[0190] The substrate layer BSL (or the second substrate layer BSL2) can be a rigid substrate or a flexible substrate. For example, when the second substrate layer BSL2 is a rigid substrate, it can be a glass substrate, a quartz substrate, a glass-ceramic substrate, a crystalline glass substrate, etc. When the second substrate layer BSL2 is a flexible substrate, it can be a polymer organic substrate including polyimide, polyamide, etc., a plastic substrate, etc.

[0191] The base layer (BSL) may include a gate pad portion 100 and a data pad portion 200. At least one pad electrode may be located in the gate pad portion 100. At least one pad electrode may be located in the data pad portion 200.

[0192] The gate pad 100 can be disposed on one side of the substrate layer BSL. The gate pad 100 can be electrically connected to Figure 2 and Figure 3 The scan line Si and control line CLI are shown. The gate pad portion 100 can be electrically connected to the fan-out line (not shown) disposed in the fan-out region FAN.

[0193] The data pad 200 can be disposed on one side of the substrate layer BSL. The data pad 200 can be electrically connected to... Figure 2 and Figure 3 The data line Dj and the sensing line SENj are shown. The data pad 200 can be electrically connected to the fan-out line provided in the fan-out area FAN.

[0194] The substrate layer BSL may include a first opening OPN1. Each first opening OPN1 may surround the gate pad 100 and the data pad 200. For example, the gate pad 100 may be disposed in the first opening OPN1, and the data pad 200 may be disposed in the first opening OPN1. The first opening OPN1 of the substrate layer BSL may be connected to... Figure 7 and Figure 11 The first opening shown corresponds to OPN1.

[0195] Reference Figure 13 The first opening OPN1 of the substrate layer BSL and the chip on film COF of the display device according to an embodiment are shown.

[0196] The first opening OPN1 can be with Figure 12 The first opening OPN1 shown corresponds to this. Therefore, Figures 7 to 11 The lower surface of the first barrier layer BRL1 and the lower surface of the pad electrode PAD shown are exposed in the first opening OPN1. A first groove GRO1 formed on the lower surface of the first barrier layer BRL1 is exposed in the first opening OPN1, and two second grooves GRO2 formed on the lower surface of the pad electrode PAD are exposed in the first opening OPN1.

[0197] The flexible film FF of the chip-on-film (COF) is positioned such that at least a portion of the flexible film FF is superimposed on the first opening OPN1. For example, the flexible film FF can be positioned to superimpose half the area of ​​the first opening OPN1.

[0198] The guide portion LDP of the chip-on-film (COF) is positioned such that a portion of the guide portion LDP overlaps with the second groove GRO2. For example, the width of the guide portion LDP of the COF may be smaller than the width of the second groove GRO2. The guide portion LDP can directly contact the lower surface of the pad electrode PAD (e.g., the second layer PADb) through the second groove GRO2.

[0199] The connecting ball SB can be positioned such that at least a portion of the connecting ball SB is stacked with each of the flexible film FF, the guide portion LDP, and the pad electrode PAD. For example, half the area of ​​the connecting ball SB can be positioned to be stacked with the flexible film FF and the guide portion LDP. The connecting ball SB can be positioned such that a majority of the connecting ball SB is stacked with the pad electrode PAD. Therefore, the connecting ball SB can electrically connect the pad electrode PAD to the on-film chip COF.

[0200] Since the connecting ball SB is set in the second groove GRO2 formed on the lower surface of the pad electrode PAD, the point where the connecting ball SB is set in the spray welding process can be easily detected, and the connecting ball SB can be prevented from being arbitrarily distributed in the first groove GRO1, etc.

[0201] Therefore, the connecting ball SB, which electrically connects the pad electrode PAD to the on-film chip COF, is stably positioned to prevent short circuits between the pad electrode PAD and the on-film chip COF.

[0202] According to the disclosure, a groove is formed on the lower surface of the pad electrode, and a connecting ball for electrically connecting the pad electrode to the chip on the film is stably disposed in the groove formed on the lower surface of the pad electrode, so as to prevent short circuit of the display device.

[0203] In addition, the use of spray welding to electrically connect the pad electrodes to the chips on the film prevents damage to the display panel.

[0204] Example embodiments have been disclosed herein, and although specific terminology has been used, they are used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art at the time of filing this application, features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly stated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope set forth in the claims.

Claims

1. A display device, the display device comprising: The first matrix layer includes a first opening; A first barrier layer is located on the top surface of the first substrate layer and includes a second opening; as well as A pad electrode, located on the first barrier layer, is superimposed on the second opening in a plan view, and includes a first layer and a second layer located on the first layer, wherein... At least one first groove is formed on the lower surface of the first barrier layer. The second groove is formed on the lower surface of the second layer, and The first opening exposes the at least one first groove and the second groove.

2. The display device according to claim 1, wherein, The pad electrode and the chip on the membrane are electrically connected to each other through the first opening.

3. The display device according to claim 2, wherein, The pad electrode and the chip on the membrane are electrically connected to each other via a connecting ball.

4. The display device according to claim 3, wherein, The connecting ball is located in the second groove formed in the pad electrode.

5. The display device according to claim 1, wherein, The first layer comprises titanium, and The second layer comprises copper.

6. The display device according to claim 1 or 5, further comprising: The second barrier layer is stacked on the upper surface of the first barrier layer and the upper surface of the pad electrode in the plan view; The second substrate layer is located on the second barrier layer; as well as The pixel circuit layer is located on the second substrate layer. The pixel circuit layer includes data lines.

7. The display device according to claim 6, wherein, The second substrate layer includes openings filled with a conductive material, and The data line is electrically connected to the pad electrode via the conductive material.

8. A method for manufacturing a display device, the method comprising the following steps: At least one metal portion is formed on the surface of the substrate layer; A first barrier layer is formed on the substrate layer and the at least one metal portion; A pad electrode is formed on the first barrier layer; A second barrier layer is formed on the first barrier layer and the pad electrode; as well as A first opening is formed in the substrate layer, a first groove is formed on the lower surface of the first barrier layer by removing at least one metal portion, and a second groove is formed on the lower surface of the pad electrode by partially removing the pad electrode.

9. The method according to claim 8, wherein, The steps of forming the first groove and forming the second groove include using an atmospheric pressure plasma process to form the first groove and the second groove.

10. The method according to claim 8, wherein, The steps for forming the first barrier layer include: Deposit the first barrier layer on the substrate layer and the at least one metal portion; and A second opening is formed in the first barrier layer.

11. The method according to claim 10, wherein, The steps for forming the pad electrode include: Depositing pad electrode material on the first barrier layer; and The pad electrode is formed such that a portion of the pad electrode overlaps with the second opening in a plan view.

12. The method according to claim 11, wherein, The second groove is formed on the lower surface of the pad electrode in the second opening.

13. The method according to claim 12, wherein, The connecting ball that electrically connects the chip on the film to the pad electrode is configured to correspond to the second groove.

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