Implement automatic rate control in the memory subsystem

Abstract

This application relates to implementing automatic rate control in a memory subsystem. A processing device in a memory system identifies a plurality of workload conditions associated with the memory device when the memory device is in a first state condition, wherein the plurality of workload conditions include data reflecting performance conditions of the memory device. The processing device determines a host rate for host system write performance of the memory device based on one or more of the plurality of workload conditions when the memory device is in the first state condition. The processing device determines that one or more of the plurality of workload conditions satisfy a first threshold criterion. In response to determining that the one or more of the plurality of workload conditions satisfy the first threshold criterion, the processing device detects a change in the condition of the memory device from the first state to a second state.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to implementing automatic rate control in memory subsystems. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this application provides a system comprising: a memory device; and a processing means operably coupled to the memory device to perform operations including: identifying a plurality of workload conditions associated with the memory device when the memory device is in a first state condition, wherein the plurality of workload conditions includes data reflecting performance conditions of the memory device; determining a host rate for host system write performance of the memory device based on one or more of the plurality of workload conditions when the memory device is in the first state condition; determining that one or more of the plurality of workload conditions satisfy a first threshold criterion; detecting a change in conditions of the memory device from the first state condition to a second state condition in response to determining that the one or more of the plurality of workload conditions satisfy the first threshold criterion; determining an adjusted host rate based on the host rate and a calculated adjustment value when the memory device is in the second state condition; and using the adjusted host rate to determine a credit consumption rate for host write operations of the memory device.

[0004] In another aspect, this application provides a method comprising: identifying a plurality of workload conditions associated with the memory device while the memory device is in a first state condition, wherein the plurality of workload conditions include data reflecting performance conditions of the memory device; determining a host rate for host system write performance of the memory device based on one or more of the plurality of workload conditions while the memory device is in the first state condition; determining that one or more of the plurality of workload conditions satisfy a first threshold criterion; detecting a change in the condition of the memory device from the first state condition to a second state condition in response to determining that the one or more of the plurality of workload conditions satisfy the first threshold criterion; determining an adjusted host rate based on the host rate and a calculated adjustment value while the memory device is in the second state condition; and using the adjusted host rate to determine a credit consumption rate for host write operations of the memory device.

[0005] On the other hand, this application provides a non-transitory computer-readable storage medium including instructions that, when executed by a processing device, cause the processing device to perform operations including: identifying a plurality of workload conditions associated with the memory device when the memory device is in a first state condition, wherein the plurality of workload conditions include data reflecting performance conditions of the memory device, and wherein the first state includes memory conditions in which the performance conditions of the memory device are unstable; determining a host rate for host system write performance of the memory device based on one or more of the plurality of workload conditions when the memory device is in the first state condition; determining one of the plurality of workload conditions. One or more workload conditions satisfy a first threshold criterion; in response to determining that one or more of the plurality of workload conditions satisfy the first threshold criterion, a change in the condition of the memory device from the first state to a second state is detected, wherein the second state includes memory conditions where the performance conditions of the memory device are stable; and the change in the condition of the memory device from the second state to the first state is detected, wherein detecting the change in the condition of the memory device from the second state to the first state includes determining that the current victim rate satisfies a second threshold criterion, wherein the current victim rate corresponds to a valid dataset on a block stripe of the memory device, wherein a garbage collection process is being performed on the block stripe. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1 An example computing system including a memory subsystem is shown according to some embodiments of the present disclosure.

[0008] Figure 2 This is an example graph showing the host rate and garbage collection rate over time during a first-state memory condition and a second-state memory condition of a memory device according to some embodiments of the present disclosure.

[0009] Figure 3 This is a flowchart illustrating an example method for implementing automatic rate control for a memory device according to some embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart illustrating an example method for implementing automatic rate control for a memory device according to some embodiments of the present disclosure.

[0011] Figure 5 A block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0012] Various aspects of this disclosure relate to implementing automatic rate control in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem, which includes one or more components, such as memory devices for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0013] The memory subsystem may include high-density non-volatile memory devices, where data is expected to be retained when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. (The following section combines...) Figure 1Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states related to the number of bits being stored. Logic states may be represented by binary values ​​such as “0” and “1” or combinations of such values.

[0014] When data is written to the memory subsystem, it is typically done at the page level, allowing entire pages or multiple pages to be written in a single operation. In a conventional memory subsystem, the host system provides the data to be written to the memory subsystem. When the memory subsystem is full and there is insufficient capacity to accept additional write operations from the host system, some data may be erased to free up space. However, when data is erased from the memory subsystem, this is typically done at the block level, allowing an entire block (containing multiple pages) to be erased in a single operation. Thus, for example, when updating a specific data segment on the memory subsystem, some pages in the block will have data that has been rewritten to different pages and / or is no longer needed. An entire block cannot be simply erased because each block is likely to still contain a certain number of valid data pages. Media management operations (e.g., garbage collection processes) can be performed, which involve moving those pages containing valid data from one block to another so that the current block can be erased and rewritten. Garbage collection is an automatic form of memory management that attempts to reclaim garbage, or memory occupied by expired data objects that are no longer used (e.g., because the data objects have been updated with new values). Garbage collection can be performed on block stripes, such as sets of blocks considered as units. A block stripe can be a single block or one or more blocks. Moving data from one block to another during the garbage collection process causes additional writes to the memory subsystem. The amount of valid data from each page that needs to be moved from one block to another is called the Physical Effective Transfer Cell Count (PVTC) rate. The lower the PVTC rate, the slower the garbage collection process needs to run.

[0015] In a conventional memory subsystem, the performance perceived by the host system depends on the speed of media management operations (e.g., garbage collection). If the host system issues write commands at a rate faster than the garbage collection process, the memory subsystem may not have enough free space remaining for writes and will therefore have to wait until the garbage collection process releases space. This uneven balance between the host system and the garbage collection process can lead to unstable performance if there are fluctuating workload conditions that affect the speed of both the host system and the garbage collection process. Host systems utilizing conventional memory subsystems are designed to perform as expected by the customer under stable or varying workload conditions. However, because the performance perceived by the host system depends on the speed of the garbage collection process, it may not meet customer expectations under stable or varying workload conditions.

[0016] The aspects of this disclosure address the above and other shortcomings by having a memory subsystem that implements automatic rate control to determine the host rate and garbage collection rate for the memory subsystem. In one embodiment, the memory subsystem may determine the host rate and garbage collection rate to control the flow of operations (e.g., write operations) from the host system and the garbage collection process. For example, the host rate and garbage collection rate may be used in a time-based credit mechanism that allocates a certain number of credits to both the host system and the garbage collection process to control the flow of operations from both. The host rate and garbage collection rate can be used to determine the rate at which the host system and the garbage collection process can consume each allocated credit. Either the host system or the garbage collection process may be allowed to operate only if it has a positive credit balance. If the host system or the garbage collection process has a zero or negative credit balance, then the credit balance may be replenished. In one embodiment, the memory subsystem may use two types of memory conditions—a first state and a second state memory condition—to determine the host rate and garbage collection rate. In one embodiment, while the memory device is in a first state memory condition, the memory subsystem identifies a set of workload conditions for the memory device. In one embodiment, the workload condition set may include host write performance statistics, garbage collection statistics, current drive conditions, and / or any other conditions or statistics. The memory subsystem determines the host rate for write operations performed by the host system based on the identified workload conditions of the memory device. When the memory subsystem determines that the identified workload conditions meet criteria, it detects a change in memory conditions from a first state memory condition to a second state memory condition. When in the second state memory condition, the memory subsystem adjusts the host rate for write operations performed by the host system and can use the adjusted host rate to determine the rate at which the host system can consume its allocated credits for write operations. In one embodiment, the memory subsystem determines the garbage collection rate for write operations performed by the garbage collection process when the memory device is in the first state memory condition. The memory subsystem may then use the garbage collection rate to determine the rate at which the garbage collection process can consume its allocated credits for write operations.

[0017] The advantages of this disclosure include, but are not limited to, improved performance of the memory subsystem. As described above, the memory subsystem must stabilize competing host systems and garbage collection processes because host systems and garbage collection processes can interfere with their respective performance in the presence of uneven balances between host rates and garbage collection rates. Implementing automatic rate control, for example, in a time-based credit mechanism as described above, would allow the memory subsystem to control the flow of the host system and garbage collection process by discovering the optimal host rate and garbage collection rate. This would enable the memory subsystem to maintain more stable host performance, even when there are fluctuations in workload conditions that affect the garbage collection process. Furthermore, the automatic rate control method can be configured for multiple types of memory subsystems with different workload capacities and memory conditions without sacrificing the performance of the memory subsystem.

[0018] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0019] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0020] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., included in a vehicle, industrial equipment or networked business device), or such computing device including memory and processing device.

[0021] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0022] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and read data from memory subsystem 110.

[0023] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0024] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0025] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory cells can perform bit storage based on changes in volume resistance by combining stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, cross-point non-volatile memories can perform in-place write operations, in which non-volatile memory cells can be programmed without prior erasing. NAND type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0026] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0027] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-type memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-type RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0028] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0029] The memory subsystem controller 115 may include a processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0030] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem).

[0031] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0032] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0033] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with a memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that is the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0034] The memory subsystem 110 includes a rate control component 113 capable of implementing automatic rate control. In some embodiments, the memory subsystem controller 115 includes at least a portion of the rate control component 113. In some embodiments, the rate control component 113 is part of the host system 120, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the rate control component 113 and is configured to perform the functionality described herein.

[0035] Rate control component 113 can implement automatic rate control for memory subsystem 110. In one embodiment, rate control component 113 can identify a set of workload conditions associated with memory device 130 when memory device 130 is in a first state memory condition. In one embodiment, the set of workload conditions includes data reflecting performance conditions of memory device 130. In one embodiment, the set of workload conditions includes data reflecting performance of host system 120 and garbage collection processes. In one embodiment, rate control component 113 can determine a host rate for write performance of host system 120 for memory device based on the identified set of workload conditions. Rate control component 113 can determine that one or more of the workload conditions meet a threshold criterion. Rate control component 113 can detect a change in conditions of memory device 130 from a first state memory condition to a second state memory condition. In one embodiment, rate control component 113 can determine an adjusted host rate to account for changes in free space when memory device 130 is in a second state memory condition. In one embodiment, rate control component 113 can use the adjusted host rate to determine the credit consumption rate of write operations for host system 120 for memory device. Further details regarding the operation of the rate control component 113 are described below.

[0036] Figure 2 This is an example graph showing the host rate and garbage collection rate over time during first-state memory conditions and second-state memory conditions of a memory device according to some embodiments of the present disclosure. In one embodiment, Figure 2 Describe for use by host systems (e.g., Figure 1The host system 120 and the garbage collection rate are the host rate and garbage collection rate of the write operations performed by the garbage collection process. For example, host rate 202 represents the rate at which host system 120 can issue memory access operations (e.g., multiple write commands issued in a certain time period), and garbage collection rate 204 represents the rate at which memory subsystem controller 115 can perform media management operations (e.g., multiple garbage collection operations performed in a certain time period). In one embodiment, a first state memory condition 210 is in which host rate 202 and garbage collection rate 204 are in an unstable search state. When host rate 202 and garbage collection rate 204 reach equilibrium (e.g., at time t1), the memory device detects a change in the conditions of the memory device from the first state memory condition 210 to a second state memory condition 220. During the second state memory condition 220, host rate 202 and garbage collection rate 204 are balanced and stabilized under stable workload conditions. In one embodiment, if any change occurs, for example, in the workload conditions, the memory device detects the change in its conditions from a second state memory condition to a first state memory condition (e.g., at time t2). Further details regarding the host rate and garbage collection rate during the first and second state memory conditions are described below.

[0037] Figure 3 This is a flowchart illustrating an example method 300 for implementing automatic rate control for a memory subsystem according to some embodiments of the present disclosure. Method 300 may be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1 The rate control component 113 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0038] At operation 304, the processing logic identifies a set of workload conditions associated with a memory device, such as memory device 130. In one embodiment, the processing logic identifies the set of workload conditions when the memory device is in a first state condition. The set of workload conditions may contain data reflecting the performance conditions of the memory device. In one embodiment, the set of workload conditions may include host write performance statistics, garbage collection statistics, current drive conditions, and / or any other conditions or statistics. For example, the set of workload conditions may include, but is not limited to, data generated by the host system (e.g., Figure 1 The host system 120) performs multiple host writes and multiple host reads, multiple write operations performed by the garbage collection process, the amount of free space, and the PVTC rate of the block stripe for the memory device currently being processed by the garbage collection process. In one embodiment, performance conditions may include stable or unstable host performance. For example, stable host performance may be a memory device that meets the expectations of a customer or user. A first state may be a memory condition in which the performance conditions of the memory device are in an unstable memory device state.

[0039] At operation 306, the processing logic determines the host rate for the memory device when the memory device is in a first state condition. In one embodiment, the host rate is the rate of write operations performed by the host system. In one embodiment, the processing logic determines the host rate based on one or more workload conditions from a set of workload conditions. In one embodiment, one or more workload conditions may include a garbage collection rate. The processing logic may determine the garbage collection rate for the current block stripe of the memory device being processed by the garbage collection process based on one or more workload conditions including the current host write count, the current host read count, and the total write margin count. The total write margin count is determined based on the maximum throughput of the memory device over a period of time. In one embodiment, one or more workload conditions may include a current victim rate (e.g., PVTC rate) corresponding to the valid dataset on the block stripe of the memory device. The block stripe may be a current block stripe that is being reclaimed by the garbage collection process. The processing logic may determine the current victim rate for the block stripe by identifying how much data needs to be reclaimed from the block stripe by the garbage collection process. In one embodiment, one or more workload conditions may include a target free space for the memory device. The target free space may be a set number stored in the memory device. In one embodiment, one or more workload conditions may include the current free space for the memory device. The processing logic may determine the current free space for the memory device based on calculating a plurality of free pages available on the memory device. The plurality of free pages may include pages on the memory device that are free, being erased, to be erased, or have been erased. In one embodiment, the processing logic may determine the host rate for the memory device based at least on the garbage collection rate, the current victim rate, the target free space, and the current free space. In one embodiment, the processing logic calculates a reference host rate based on the garbage collection rate and the current victim rate for the current block stripe. The processing logic determines the host rate based on the reference host rate and the current free space. For example, determining the host rate may include adjusting the reference host rate according to the current free space. In one embodiment, the processing logic uses the host rate to determine the credit consumption rate. In one embodiment, the credit consumption rate may be used for a time-based credit mechanism to control the rate at which the host system performs write operations for the memory device. In one embodiment, the credit consumption rate may be used to control the rate at which the host system performs read operations for the memory device. In one embodiment, the processing logic uses the garbage collection rate to determine the credit consumption rate for the garbage collection process, including any write operations performed by the garbage collection process.

[0040] At operation 308, the processing logic determines that one or more workload conditions in a set of workload conditions meet a threshold criterion. In one embodiment, the processing logic may determine the ratio between the expected garbage collection write count for the memory device and the expected host write count for the memory device. The expected garbage collection write count and the expected host write count may be calculated by the processing logic based on the current victim rate for the current block stripe. In one embodiment, the processing logic may determine the ratio between the actual garbage collection write count for the memory device and the actual host write count for the memory device. The processing logic may determine the ratio between the actual garbage collection write count and the actual host write count based on one or more of a set of workload conditions, such as host write performance statistics and garbage collection statistics. The processing logic may identify a match by comparing the ratio between the expected garbage collection write count and the expected host write count with the ratio between the actual garbage collection write count and the actual host write count. If the ratios are equal or close in range (e.g., within each other's threshold amounts), then the processing logic may determine that the ratios match. In one embodiment, the processing logic may determine a target free space for the memory device. The target free space may be a set number stored in the memory device. In one embodiment, the processing logic may determine the current free space for the memory device based on one or more of a set of workload conditions, such as the current driving condition. In one embodiment, the processing logic may determine that the current free space of the memory device is equal to or close in range to a target free space for the memory device. In one embodiment, if a match exists between two ratios and if the current free space of the memory device is equal to or close in range to the target free space for the memory device, then the processing logic determines that one or more of the workload conditions satisfy a threshold criterion.

[0041] At operation 310, the processing logic detects a change in the conditions of the memory device from a first state memory condition to a second state memory condition. In one embodiment, the processing logic detects a change in the host workload mode of the memory device from the first state memory condition to the second state memory condition. In one embodiment, the processing logic records a reference free space for the memory device, which reflects one or more free pages available on the memory device when the memory device changes from the first state memory condition to the second state memory condition. In one embodiment, the processing logic determines a current free space for the memory device when the memory device is in the second state memory condition, which reflects one or more free pages available on the memory device during the second state memory condition. In one embodiment, the processing logic determines an adjustment value when the memory device is in the second state based at least on the reference free space recorded during the first state memory condition and the current free space of the memory device when it is in the second state memory condition. In one embodiment, the second state may be a memory condition in which the performance conditions of the memory device are stable.

[0042] At operation 312, the processing logic determines the adjusted host rate. In one embodiment, the processing logic records the host rate when it first detects a change in the conditions of the memory device from a first state to a second state. In one embodiment, the processing logic determines the adjusted host rate based on the recorded host rate and the adjustment value. In one embodiment, the processing logic determines the garbage collection rate for the second state memory conditions. The processing logic may determine the garbage collection rate based on one or more workload conditions including the current host write count, the current host read count, and the total write margin. The write margin count is determined based on the maximum throughput of the memory device over a period of time.

[0043] At operation 314, the processing logic uses the adjusted host rate to determine the credit consumption rate. In one embodiment, the credit consumption rate can be used in a time-based credit mechanism to control the rate at which the host system performs write operations for the memory device. In one embodiment, the processing logic uses the garbage collection rate to determine the credit consumption rate for the garbage collection process. In one embodiment, the processing logic may detect a change in the conditions of the memory device from a second state memory condition to a first state memory condition. In one embodiment, detecting a change in the conditions of the memory device from the second state to the first state may include determining that the current victim rate (e.g., PVTC rate) satisfies a threshold criterion when the memory device is in the second state condition. In one embodiment, the current victim rate corresponds to a valid dataset on a block stripe of the memory device. The block stripe may be the current block stripe that is being recycled through the garbage collection process. In one embodiment, the threshold criterion may include a low PVTC rate. In one embodiment, detecting a change in the conditions of the memory device from the second state to the first state may include determining that the current free space for the memory device and the target free space for the memory device do not satisfy the threshold criterion. For example, the threshold criterion may include the range in which the current free space must be within the target free space. In one embodiment, detecting a change in the condition of the memory device from a second state to a first state may include determining a change in the workload associated with host write and read operations when the second-state memory condition is first input to the current workload. In one embodiment, detecting a change in the condition of the memory device from a second state to a first state may include determining low host write and / or host read utilization.

[0044] Figure 4 This is a flowchart illustrating an example method 400 of an automatic rate control method for a memory subsystem according to some embodiments of the present disclosure. Method 400 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The rate control component 113 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0045] At operation 404, the processing logic identifies a set of workload conditions associated with a memory device, such as memory device 130. In one embodiment, the processing logic identifies the set of workload conditions when the memory device is in a first state condition. The set of workload conditions may contain data reflecting the performance conditions of the memory device. In one embodiment, the set of workload conditions may include host write performance statistics, garbage collection statistics, current drive conditions, and / or any other conditions or statistics. For example, the set of workload conditions may include, but is not limited to, data generated by the host system (e.g., Figure 1 The host system 120) performs multiple host writes and multiple host reads, multiple write operations performed by the garbage collection process, the amount of free space, and the PVTC rate of the current block stripe of the memory device being processed by the garbage collection process. In one embodiment, performance conditions may include stable or unstable host performance. For example, stable host performance may be a memory device that meets the expectations of a customer or user. A first state may be a memory condition in which the performance conditions of the memory device are in an unstable memory device state.

[0046] At operation 406, the processing logic determines the garbage collection rate for the current block stripe. The processing logic may determine the garbage collection rate for the current block stripe based on one or more workload conditions, including the current host write count, the current host read count, and the total write margin count. The total write margin count is determined based on the maximum throughput of the memory device over a period of time.

[0047] At operation 408, the processing logic determines the current damage rate (e.g., PVTC rate) corresponding to the valid dataset on the current block stripe of the memory device. The processing logic determines the current damage rate for the current block stripe by identifying how much data needs to be recovered from the block stripe through the garbage collection process.

[0048] At operation 410, the processing logic determines the target free space for the memory device. The target free space can be a set number stored in the memory device.

[0049] At operation 412, the processing logic determines the current free space for the memory device. The processing logic may determine the current free space for the memory device based on calculating a plurality of free pages available on the memory device. These multiple free pages may include pages on the memory device that are free, being erased, to be erased, or have already been erased.

[0050] At operation 414, the processing logic determines the host rate for the memory device. In one embodiment, the host rate is the rate of write operations performed by the host system. In one embodiment, the processing logic determines the host rate based on one or more workload conditions from a set of workload conditions. In one embodiment, the one or more workload conditions include at least a garbage collection rate, a current victim rate, a target free space, and a current free space. In one embodiment, the processing logic calculates a reference host rate based on the garbage collection rate and the current victim rate for the current block stripe. The processing logic determines the host rate based on the reference host rate and the current free space. For example, determining the host rate may include adjusting the reference host rate according to the current free space. In one embodiment, the processing logic uses the host rate to determine a credit consumption rate. In one embodiment, the credit consumption rate may be used for a time-based credit mechanism to control the rate at which the host system performs write operations for the memory device. In one embodiment, the credit consumption rate may be used to control the rate at which the host system performs read operations for the memory device. In one embodiment, the processing logic uses the garbage collection rate to determine the credit consumption rate for the garbage collection process, including any write operations performed by the garbage collection process.

[0051] At operation 416, the processing logic determines that one or more workload conditions in the set of workload conditions satisfy a first threshold criterion. In one embodiment, the processing logic may determine the ratio between the expected garbage collection write count for the memory device and the expected host write count for the memory device. The expected garbage collection write count and the expected host write count may be calculated by the processing logic based on the current victim rate for the current block stripe. In one embodiment, the processing logic may determine the ratio between the actual garbage collection write count for the memory device and the actual host write count for the memory device. The processing logic may determine the ratio between the actual garbage collection write count and the actual host write count based on one or more of the set of workload conditions, such as host write performance statistics and garbage collection statistics. The processing logic may identify a match by comparing the ratio between the expected garbage collection write count and the expected host write count with the ratio between the actual garbage collection write count and the actual host write count. If the ratios are equal or close in range (e.g., within each other's threshold amounts), then the processing logic may determine that the ratios match. In one embodiment, the processing logic may determine a target free space for the memory device. The target free space may be a set number stored in the memory device. In one embodiment, the processing logic may determine the current free space for the memory device based on one or more of a set of workload conditions, such as the current driving condition. In one embodiment, the processing logic may determine that the current free space of the memory device is equal to or close in range to a target free space for the memory device. In one embodiment, if a match exists between two ratios and if the current free space of the memory device is equal to or close in range to the target free space for the memory device, then the processing logic determines that one or more of the workload conditions satisfy a threshold criterion.

[0052] At operation 418, the processing logic detects a change in the conditions of the memory device from a first state memory condition to a second state memory condition. In one embodiment, the processing logic records a reference free space for the memory device, which reflects one or more free pages available on the memory device when the memory device changes from the first state memory condition to the second state memory condition. In one embodiment, the processing logic determines an adjustment value when the memory device is in the second state condition, based at least on the recorded reference free space and the current free space of the memory device when it is in the second state memory condition. In one embodiment, the second state may be a memory condition in which the performance conditions of the memory device are in a stable state.

[0053] At operation 420, the processing logic determines the adjusted host rate. In one embodiment, the processing logic records the host rate when it first detects a change in conditions from a first state to a second state. In one embodiment, the processing logic determines the adjusted host rate based on the recorded host rate and the adjustment value. In one embodiment, the processing logic determines the garbage collection rate for the second-state memory conditions. The processing logic may determine the garbage collection rate based on one or more workload conditions including the current host write count, the current host read count, and the total write margin. The write margin count is determined based on the maximum throughput of the memory device over a period of time.

[0054] At operation 422, the processing logic uses the adjusted host rate to determine the credit consumption rate. In one embodiment, the credit consumption rate can be used in a time-based credit mechanism to control the rate at which the host system performs write operations for the memory device. In one embodiment, the credit consumption rate can be used to control the rate at which the host system performs read operations for the memory device. In one embodiment, the processing logic uses the garbage collection rate to determine the credit consumption rate for the garbage collection process, including any write operations performed by the garbage collection process.

[0055] At operation 424, the processing logic determines that the current victim rate meets a threshold criterion. In one embodiment, the threshold criterion may include a low PVTC rate when the memory device is in a second state.

[0056] At operation 426, if the current victim rate meets a threshold criterion, the processing logic may detect a change in the conditions of the memory device from a second-state memory condition to a first-state memory condition. In one embodiment, the processing logic may detect the change based on determining that the current free space for the memory device and the target free space for the memory device do not meet the threshold criterion. For example, the threshold criterion may include a range around the target free space in which the current free space must be located. In one embodiment, the processing logic may detect the change based on determining a change in the workload associated with host write and read operations when the second-state memory condition is first input to the current workload. In one embodiment, the processing logic may detect the change based on determining a low host write and / or host read utilization rate.

[0057] Figure 5An example machine of computer system 500 is shown, within which a set of instructions for causing the machine to perform any or more of the methods discussed herein is executable. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of rate control component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, corporate intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, qualifying as a server or client machine in a client-server network environment.

[0058] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any of the aforementioned machines capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is shown, the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0059] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM), static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518 that communicates with each other via a bus 530.

[0060] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communication via network 520.

[0061] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) on which one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein are stored. The instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0062] In one embodiment, instruction 526 includes instructions for implementing a rate control component (e.g., Figure 1 The machine-readable storage medium 524 is a single medium, although in the exemplary embodiment the machine-readable storage medium 524 is shown as a single medium, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0063] Some parts of the previously described descriptions have already been presented regarding the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. An algorithm herein, and generally, is considered a self-consistent series of operations that produce a desired result. These operations are those requiring physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0064] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0065] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0066] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0067] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes mechanisms for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0068] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, this specification and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A system comprising: Memory devices; as well as A processing device, operably coupled to the memory device, performs operations including: When the memory device is in a first state condition, identify multiple workload conditions associated with the memory device, wherein the multiple workload conditions include data reflecting the performance conditions of the memory device; When the memory device is in the first state condition, a host rate for host system write performance of the memory device is determined based on one or more of the plurality of workload conditions. Determine that one or more of the plurality of workload conditions satisfy a first threshold criterion; In response to determining that one or more of the plurality of workload conditions satisfy the first threshold criterion, a change in the condition of the memory device from the first state condition to the second state condition is detected; When the memory device is in the second state condition, the adjusted host rate is determined based on the host rate and the calculated adjustment value; as well as The adjusted host rate is used to determine the credit consumption rate for host write operations on the memory device.

2. The system of claim 1, wherein determining the host rate for the memory device based on one or more of the plurality of workload conditions comprises: Determine the garbage collection rate for the memory device; Determine the current victim rate corresponding to the valid dataset on the block stripe of the memory device, wherein a garbage collection process is being performed on the block stripe; Determine the target free space for the memory device; Determine the current free space for the memory device; as well as The host rate for the memory device is determined based at least on the garbage collection rate, the current victim rate, the target free space, and the current free space.

3. The system of claim 1, wherein determining that one or more of the plurality of workload conditions satisfy the first threshold criterion comprises: Determine a first ratio between the expected garbage collection write count for the memory device and the expected host write count for the memory device; Determine a second ratio between the actual garbage collection write count for the memory device and the actual host write count for the memory device; and Identify the match between the first ratio and the second ratio.

4. The system of claim 3, wherein determining that one or more of the plurality of workload conditions satisfy the first threshold criterion further comprises: Determine the target free space for the memory device; Determine the current free space for the memory device; as well as The current free space of the memory device is determined to be within a threshold amount for the target free space of the memory device.

5. The system of claim 1, wherein the processing device is configured to perform operations further comprising: Detecting a change in the conditions of the memory device from the second state to the first state, wherein detecting the change in the conditions of the memory device from the second state to the first state includes determining that the current damage rate satisfies a second threshold criterion, wherein the current damage rate corresponds to a valid dataset on a block stripe of the memory device, wherein a garbage collection process is being performed on the block stripe.

6. The system of claim 1, wherein the processing device is configured to perform operations further comprising: Detecting a change in the conditions of the memory device from the second state to the first state, wherein detecting the change in the conditions of the memory device from the second state to the first state includes determining that the current free space of the memory device and the target free space of the memory device do not satisfy a threshold range criterion.

7. The system of claim 1, wherein the processing device is configured to perform operations further comprising: In response to determining that the first threshold criterion is met, a reference free space for the memory device is determined when the memory device is in the first state condition, wherein the reference free space reflects one or more free pages of the memory device during the change of the condition of the memory device from the first state to the second state; In response to detecting the change in the condition of the memory device from the first state to the second state, a current free space for the memory device is determined when the memory device is in the second state condition, wherein the current free space reflects one or more free pages of the memory device; as well as When the memory device is in the second state condition, the calculated adjustment value is determined at least based on the reference free space and the current free space.

8. The system of claim 1, wherein the first state includes a memory condition in which the performance conditions of the memory device are unstable, and wherein the second state includes a memory condition in which the performance conditions of the memory device are stable.

9. A method comprising: When the memory device is in a first state condition, identify multiple workload conditions associated with the memory device, wherein the multiple workload conditions include data reflecting the performance conditions of the memory device; When the memory device is in the first state condition, a host rate for host system write performance of the memory device is determined based on one or more of the plurality of workload conditions. Determine that one or more of the plurality of workload conditions satisfy a first threshold criterion; In response to determining that one or more of the plurality of workload conditions satisfy the first threshold criterion, a change in the condition of the memory device from the first state condition to the second state condition is detected; When the memory device is in the second state condition, the adjusted host rate is determined based on the host rate and the calculated adjustment value; as well as The adjusted host rate is used to determine the credit consumption rate for host write operations on the memory device.

10. The method of claim 9, wherein determining the host rate for the memory device based on one or more of the plurality of workload conditions comprises: Determine the garbage collection rate for the memory device; Determine the current victim rate corresponding to the valid dataset on the block stripe of the memory device, wherein a garbage collection process is being performed on the block stripe; Determine the target free space for the memory device; Determine the current free space for the memory device; as well as The host rate for the memory device is determined based at least on the garbage collection rate, the current victim rate, the target free space, and the current free space.

11. The method of claim 9, wherein determining that one or more of the plurality of workload conditions satisfy the first threshold criterion comprises: Determine a first ratio between the expected garbage collection write count for the memory device and the expected host write count for the memory device; Determine a second ratio between the actual garbage collection write count for the memory device and the actual host write count for the memory device; and Identify the match between the first ratio and the second ratio.

12. The method of claim 11, wherein determining that one or more of the plurality of workload conditions satisfy the first threshold criterion further comprises: Determine the target free space for the memory device; Determine the current free space for the memory device; as well as The current free space of the multiple block stripes is determined to be within a threshold amount for the target free space of the memory device.

13. The method of claim 9, further comprising: Detecting a change in the condition of the memory device from the second state to the first state, wherein detecting the change in the condition from the second state to the first state includes determining that the current damage rate satisfies a second threshold criterion, wherein the current damage rate corresponds to a valid dataset on a block stripe of the memory device, wherein a garbage collection process is being performed on the block stripe.

14. The method of claim 9, further comprising: In response to determining that the first threshold criterion is met, a reference free space for the memory device is determined when the memory device is in the first state condition, wherein the reference free space reflects one or more free pages of the memory device during the change of the condition of the memory device from the first state to the second state; In response to detecting the change in the condition of the memory device from the first state to the second state, a current free space for the memory device is determined when the memory device is in the second state condition, wherein the current free space reflects one or more free pages of the memory device; as well as When the memory device is in the second state condition, the adjustment value is determined based at least on the reference free space and the current free space.

15. The method of claim 9, wherein the first state includes the memory condition of unstable performance conditions of the memory device, and wherein the second state includes the memory condition of stable performance conditions of the memory device.

16. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to perform operations including: When the memory device is in a first state condition, identify multiple workload conditions associated with the memory device, wherein the multiple workload conditions include data reflecting the performance conditions of the memory device, and wherein the first state includes memory conditions in which the performance conditions of the memory device are unstable. When the memory device is in the first state condition, a host rate for host system write performance of the memory device is determined based on one or more of the plurality of workload conditions. Determine that one or more of the plurality of workload conditions satisfy a first threshold criterion; In response to determining that one or more of the plurality of workload conditions satisfy the first threshold criterion, a change in the condition of the memory device from the first state to the second state is detected, wherein the second state includes memory conditions in which the performance conditions of the memory device are stable. as well as Detecting a change in the conditions of the memory device from the second state to the first state, wherein detecting the change in the conditions of the memory device from the second state to the first state includes determining that the current damage rate satisfies a second threshold criterion, wherein the current damage rate corresponds to a valid dataset on a block stripe of the memory device, wherein a garbage collection process is being performed on the block stripe.

17. The non-transitory computer-readable storage medium of claim 16, wherein the processing means is configured to perform operations further comprising: When the memory device is in the second state condition, the adjusted host rate is determined based on the host rate and the calculated adjustment value; and The adjusted host rate is used to determine the credit consumption rate for host write operations on the memory device.

18. The non-transitory computer-readable storage medium of claim 16, wherein determining that one or more of the plurality of workload conditions satisfy the first threshold criterion comprises: Determine a first ratio between the expected garbage collection write count for the memory device and the expected host write count for the memory device; Determine a second ratio between the actual garbage collection write count for the memory device and the actual host write count for the memory device; and Identify the match between the first ratio and the second ratio.

19. The non-transitory computer-readable storage medium of claim 18, wherein determining that one or more of the plurality of workload conditions satisfy the first threshold criterion further comprises: Determine the target free space for the memory device; Determine the current free space for the memory device; as well as The current free space of the memory device is determined to be within a threshold amount for the target free space of the memory device.

20. The non-transitory computer-readable storage medium of claim 17, wherein the processing means is configured to perform operations further comprising: In response to determining that the first threshold criterion is met, a reference free space for the memory device is determined when the memory device is in the first state condition, wherein the reference free space reflects one or more free pages of the memory device during the change of the condition of the memory device from the first state to the second state; In response to detecting a change in the condition of the memory device from the first state to the second state, a current free space for the memory device is determined when the memory device is in the second state condition, wherein the current free space reflects one or more free pages of the memory device; as well as When the memory device is in the second state condition, the adjustment value is determined based at least on the reference free space and the current free space.

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