Computer system and trusted computing method

Abstract

The present application provides a computer system and a trusted computing method. The processor includes a general core and a trusted core. The system memory includes a general memory and an isolated memory. The isolated memory is provided with a secure interrupt descriptor table corresponding to a plurality of secure interrupts initiated by secure peripherals. A first register in the trusted core stores a first address pointing to the secure interrupt descriptor table. A local advanced programmable interrupt controller in the trusted core is provided with an interrupt arbitrator to arbitrate interrupts from the peripherals via a chipset. When a target interrupt is a secure interrupt, the interrupt arbitrator sends a secure interrupt request signal and a secure interrupt vector to trigger the trusted core to find the secure interrupt descriptor table according to the first register, find a target interrupt descriptor, and execute a corresponding interrupt program.

Description

Technical Field

[0001] This invention relates to trusted computing, and more particularly to a secure peripheral for trusted computing. Background Technology

[0002] Trusted computing can improve computer system security through hardware partitioning. For example, the system memory of a computer system can be divided into isolated memory areas dedicated solely to trusted computing.

[0003] Designing secure peripherals for trusted computing is a major challenge in this field. Summary of the Invention

[0004] A computer system implemented according to one embodiment of this application includes a processor, a system memory, and a chipset. The processor includes a general-purpose core and a trusted core for trusted computing. The system memory provides general-purpose memory and isolated memory for trusted computing. The chipset is coupled to the processor, the system memory, and multiple peripherals, and is responsible for communication between the processor, the system memory, and the peripherals. The isolated memory has a secure interrupt descriptor table corresponding to secure interrupts initiated by secure peripherals. A first register in the trusted core stores a first address pointing to the secure interrupt descriptor table. A local high-level programmable interrupt controller in the trusted core provides an interrupt arbitrator to arbitrate interrupts transmitted from the peripherals via the chipset. When a target interrupt is determined to be a secure interrupt, the interrupt arbitrator issues a secure interrupt request signal and a secure interrupt vector, triggering the trusted core to find the secure interrupt descriptor table according to the first register, and then search the secure interrupt descriptor table to determine a target interrupt descriptor to execute the corresponding interrupt routine.

[0005] The aforementioned concepts are further used to implement a trusted computing method.

[0006] This application achieves isolation between security interrupt handling and general interrupt handling by setting a separate security interrupt controller in the chipset or by using Information Driven Interrupt (MSI) to add a separate security interrupt descriptor register (first register), security interrupt descriptor table, and corresponding security interrupt handling mechanism in the trusted core.

[0007] The present invention will be described in detail below with reference to specific embodiments and accompanying drawings. Attached Figure Description

[0008] Figure 1 A computer system 100 implemented according to one embodiment of this application;

[0009] Figure 2 Table 200 illustrates the contents of memory protection configuration information 124;

[0010] Figure 3 Table 300 shows the base address of isolated memory 116 and the address size of isolated memory 116;

[0011] Figure 4 According to one embodiment of this application, the diagram illustrates how processor 102 handles interrupts.

[0012] Figure 5 Details of a security interrupt controller 128 according to one embodiment of this application are illustrated;

[0013] Figure 6 Details of a safety interrupt controller 128 are illustrated according to another embodiment of this application;

[0014] Figure 7 According to one embodiment of this application, the detailed format of Information Driven Interrupt (MSI) is illustrated;

[0015] Figure 8 The diagram illustrates the communication management of the processor 102 with peripherals; and

[0016] Figure 9 This diagram illustrates the communication management of peripherals with processor 102.

[0017] [Symbol Explanation]

[0018] 100: Computer system;

[0019] 102: Processor;

[0020] 104: Chipset;

[0021] 106: System Memory

[0022] 108_1…108_n: General peripherals;

[0023] 110_1…110_m: Security peripherals;

[0024] 112: Trusted kernel;

[0025] p_int_1…p_int_m: Safe interrupt;

[0026] 114_1…114_k: General-purpose core;

[0027] 116: Isolated memory;

[0028] 120: General memory;

[0029] 122: Central communication controller;

[0030] 124: Memory protection configuration information;

[0031] 126: Monitor;

[0032] 128: Safety interrupt controller;

[0033] 200, 300: Tables;

[0034] 204, 206: Fields;

[0035] 404: Arbitrator interrupted;

[0036] 502: Programmable Interrupt Controller;

[0037] 504, 602: Safety interruption handling unit;

[0038] 702: Interrupt information address format;

[0039] 704: Interrupt information data format;

[0040] 802: Nuclear identification code;

[0041] 804, 904: Address;

[0042] 902: Peripheral Identifier Code;

[0043] CPUIF: Processor Interface;

[0044] HIF_APIC: Host Interface Advanced Programmable Interrupt Controller;

[0045] IDT, SIDT: General Interrupt Descriptor Table, Security Interrupt Descriptor Table;

[0046] IDTR, SIDTR: Registers;

[0047] INTA, SINTA: General interrupt response signal, safety interrupt response signal;

[0048] INTR and SINTR: General interrupt request signal and secure interrupt request signal, respectively.

[0049] IV, SIV: General interrupt vector, Security interrupt vector;

[0050] IO_APIC: Advanced Programmable Interrupt Controller for Input / Output;

[0051] Local_APIC: Local high-level programmable interrupt controller. Detailed Implementation

[0052] The following description illustrates various embodiments of the present invention. This description introduces the basic concepts of the invention and is not intended to limit its scope. The actual scope of the invention should be defined by the claims.

[0053] In trusted computing, a segment of system memory is typically isolated for its use, called isolated memory, which is different from general memory. Isolated memory does not allow access from non-trusted cores (also known as normal cores) or insecure input / output devices (also known as normal peripherals). It is only accessible to trusted cores (such as those using TPCM technology) and secure input / output devices (also known as secure peripherals) specifically designed for trusted computing.

[0054] This application defines a set of configurable memory protection configuration information in the chipset. Besides recording isolation information (e.g., indicating the location of isolated memory in system memory by the base address and size of each isolated memory range), it also records information about each peripheral (identified by a peripheral identification code), such as the peripheral type (e.g., general peripheral or security peripheral). In this way, based on the information recorded in the chipset's memory protection configuration information (including isolation information and peripheral information), the chipset will indeed reject access requests from general peripherals to the isolated memory. Conversely, the chipset will allow access requests from security peripherals to the isolated memory. The chipset can allow general peripherals to access general memory. In particular, the chipset can prohibit security peripherals from accessing general memory.

[0055] In addition, information such as the input / output range (I / Orange; the access instructions used are, for example, IN or OUT) or memory-mapped input / output range (MIMO range; the memory access instructions used are, for example, MOV) allocated by the operating system to each peripheral (including security peripherals and general peripherals) can also be recorded in the chipset (for example, recorded in the memory protection configuration information mentioned above).

[0056] When a regular core or trusted core requests access to a peripheral device, it sends a peripheral access request to the chipset. This request may include a core ID, allowing the chipset to identify whether the request originated from a regular core or a trusted core. Therefore, if a regular core requests access to a secure peripheral (i.e., the address it wants to access falls within the input / output range of a secure peripheral on the chipset, or the memory-mapped input / output range of that secure peripheral), the chipset will reject the request. Conversely, if a trusted core requests access to a secure peripheral, the chipset will allow it. If a regular core requests access to a regular peripheral, the chipset will allow it. If a trusted core requests access to a regular peripheral, the chipset may reject it. Further details will be provided later with accompanying diagrams.

[0057] When a peripheral device (general peripheral or security peripheral) requests access to system memory, it sends a system memory access request to the chipset. The system memory access request may include a peripheral identification code. Based on the peripheral information stored in the chipset and the peripheral identification code, the chipset can distinguish whether the request is from a general peripheral or a security peripheral. The system memory access request also includes an address to identify the address of the system memory the peripheral wants to access. Based on the isolation information stored in the chipset and the address in the system memory access request, the chipset can determine whether the peripheral is accessing general memory or isolated memory. Therefore, if a general peripheral requests access to isolated memory, the chipset will reject it. Conversely, if a security peripheral requests access to isolated memory, the chipset will allow it. If a general peripheral requests access to general memory, the chipset will allow it. If a security peripheral requests access to general memory, the chipset may reject it. Specific details will be described in detail later with accompanying diagrams.

[0058] This application provides a more secure peripheral design interruption technology.

[0059] Figure 1 A computer system 100 implemented according to one embodiment of this application includes a processor 102, a chipset 104, a system memory 106, and various peripherals (including general peripherals 108_1…108_n and security peripherals 110_1…110_m, where n and m are integers greater than or equal to 1).

[0060] Processor 102 is a multiprocessor, which can be homogeneous (i.e., they have the same structure). One of them is programmable as a trusted core 112 (for trusted computing), and the rest are general cores 114_1…114_k (where k is an integer greater than or equal to 1). Processor 102 is coupled to chipset 104, and chipset 104 is also coupled to system memory 106, general peripherals 108_1…108_n, and security peripherals 110_1…110_m. Chipset 104 is responsible for communication between processor 102, system memory 106, and these peripherals (108_1…108_n and 110_1…110_m).

[0061] System memory 106 can be dynamic access memory (DRAM) or static access memory (SRAM), and its space allocation includes: isolated memory 116 and general memory 120. Isolated memory 116 needs to be isolated from general cores 114_1…114_k and general peripherals 108_1…108_n, and is only accessible to trusted core 112 and secure peripherals 110_1…110_m for trusted computing. General memory 120 can be allocated to general cores 114_1…114_k.

[0062] Chipset 104 stores a set of memory protection configuration information 124 in the central traffic controller (responsible for data transmission between processor 102 and peripherals, and between peripherals and processor 102) 122, and provides a monitor 126. The memory protection configuration information 124 can be used to store the isolation information, peripheral information, etc., as described above. Based on the contents of the memory protection configuration information 124, monitor 126 can indeed exclude general peripherals 108_1…108_n from accessing isolated memory 116, while allowing secure peripherals 110_1…110_m to access isolated memory 116, and can allow general peripherals 108_1…108_n to access general memory 120. Specifically, based on the contents of the memory protection configuration information 124 (such as the isolation information, peripheral information, etc., as described above), monitor 126 can deny secure peripherals 110_1…110_m access to general memory 120. The specific details will be elaborated in the following sections in conjunction with Figures 2, 3, and 9.

[0063] The monitor 126 further prevents general cores 114_1…114_k from operating secure peripherals 110_1…110_m based on the contents of the memory protection configuration information 124 (such as the isolation information and peripheral information mentioned above). Based on the contents of the memory protection configuration information 124 (such as the isolation information and peripheral information mentioned above), the monitor 126 allows trusted cores 112 to operate secure peripherals 110_1…110_m, allows general cores 114_1…114_k to operate general peripherals 108_1…108_n, and can further prevent trusted cores 112 from operating general peripherals 108_1…108_n. Specific details will be elaborated later in conjunction with Figures 2 and 8.

[0064] The memory protection configuration information 124 may be stored in a set of registers of the chipset 104 or in a static random access memory, and the present invention is not limited thereto. The memory protection configuration information 124 may be configured as follows.

[0065] After the system powers on, the trusted core 112 runs before the general cores 114_1…114_k, verifying the trusted firmware (such as TPCM firmware) and the Basic Input / Output System (BIOS). After verification, the trusted core 112 runs the trusted firmware and configures the peripherals that the trusted core 112 can access. Different peripherals are distinguished by their device IDs. The trusted core 112 instructs the memory protection configuration information 124 to record the configured device IDs, I / Orange ranges 204, and MIMO ranges 206. The memory protection configuration information 124 can also record the peripheral type (security peripheral or general peripheral) for each peripheral. The memory protection configuration information 124 can also record the isolation information of the isolated memory 116, indicating the location of the isolated memory 116 within the system memory 106. In one embodiment, the isolated memory 116 is composed of multiple separate ranges, and the base address and size of each range can be carried in the memory protection configuration information 124 to fully identify the isolated memory 116.

[0066] In particular, only the trusted core 112 can modify the contents of the memory protection configuration information 124.

[0067] Figure 2 Explained in Table 200 Figure 1 The memory protection configuration information 124 includes a valid bit (e.g., 0: invalid content; 1: valid content), peripheral identification code (ID), peripheral type (e.g., 0: security peripheral; 1: general peripheral), input / output range (I / O range) 204, and memory-mapped input / output range (MIMO range) 206. Either the input / output range (I / O range) 204 or the memory-mapped input / output range (MIMO range) 206 can be filled in, representing a communication range between the peripheral and the processor. It should be noted that... Figure 2 The security peripheral with the identifier 5 listed is just one example. Figure 2 The table 200 shown may contain multiple entries for security peripherals, or multiple entries for general peripherals; this invention does not impose any restrictions on this.

[0068] Figure 3 Table 300 shows the base address and address size of isolated memory 116. It should be noted that... Figure 3 The isolated memory base address 20000 and isolated memory address size 100 listed are just examples. Different isolated memory base addresses and isolated memory address sizes can be set in this invention, and multiple entries can be set in Table 300 to indicate multiple isolated memories in system memory.

[0069] In one implementation, in response to a target peripheral's access request to the system memory 106 (with a peripheral identification code), the monitor 126 records the isolation information in the memory protection configuration information 124. Figure 3 Table 300) is compared with an access address of the access request to determine whether the access address falls within the isolated memory 116. When the target peripheral is a secure peripheral 110_1…110_m (e.g., ... Figure 2 As shown in Table 200 (this entry), the monitor 126 allows the execution of the access request falling into the isolated memory 116. When the target peripheral is a general peripheral 108_1…108_n, the monitor 126 prohibits the execution of the access request falling into the isolated memory 116. The monitor 126 further allows the execution of the access request falling into the general memory (the space outside the isolated memory 116) when the target peripheral is a general peripheral 108_1…108_n. The monitor 126 can further prohibit the execution of the access request falling into the general memory (the space outside the isolated memory 116) when the target peripheral is a secure peripheral 110_1…110_m.

[0070] In response to a peripheral access request (with a core identification code) issued by a target core of the processor 102, the monitor 126 can query the memory protection configuration information 124 based on the access address of the peripheral access request to find the matching communication range (by comparison). Figure 2 In fields 204 and 206), and based on the corresponding communication range, a target peripheral identification code and a target peripheral type are obtained from the memory protection configuration information 124, thereby determining what the target peripheral of the peripheral access request is and whether the target peripheral is a secure peripheral (e.g., ...). Figure 1 (Security peripherals 110_1, ..., or 110_m) or general peripherals (e.g., Figure 1 The general peripherals in the 108_1, ..., or 108_n series. For example, when a peripheral access request contains an input / output address (I / O address) with a value of 25, because... Figure 2 The peripheral with identification code 5 corresponds to an input / output range (field 204) of 23-26 (25 falls within this range). Monitor 126 determines that the peripheral's identification code is 5 and that it is a secure peripheral (because its peripheral type is 0). When a peripheral access request contains an access address that is a memory-mapped input / output address (MMIO address) with a value of 10050, because... Figure 2The memory-mapped input / output range (field 206) value corresponding to the peripheral with the peripheral identification code 5 is 10000-10100 (10050 falls within the range 10000-10100). The monitor 126 determines that the peripheral identification code is 5 and that the peripheral is a secure peripheral (because its peripheral type is 0).

[0071] The monitor 126 can determine whether the target core is a general core (e.g., based on the core ID of the target core) Figure 1 (General kernels 114_1, ..., or 114_k) or trusted kernels (e.g., ...) Figure 1 When the target core is a trusted core 112 and the target peripheral is a secure peripheral 110_1…110_m, the monitor 126 allows the target core to access the target peripheral. When the target core is a general core 114_1…114_k but the target peripheral is a secure peripheral 110_1…110_m, the monitor 126 prohibits the target core from accessing the target peripheral. When the target core is a general core 114_1…114_k and the target peripheral is a general peripheral 108_1…108_n, the monitor 126 allows the target core to access the target peripheral. When the target core is a trusted core 112 but the target peripheral is a general peripheral 108_1…108_n, the monitor 126 may prohibit the target core from accessing the target peripheral.

[0072] Back Figure 1 Regarding peripheral interrupts, chipset 104 provides an Advanced Programmable Interrupt Controller (APIC) for general peripherals 108_1…108_n, and also designs a security interrupt controller 128 for security peripherals 110_1…110_m. Each security peripheral 110_1…110_m is connected to the security interrupt controller 128 via a peripheral-chipset pin to issue security interrupt signals p_int_1…p_int_m. For example, security peripheral 110_1 is connected to the security interrupt controller 128 via a peripheral-chipset pin to issue security interrupt p_int_1; security peripheral 110_m is connected to the security interrupt controller 128 via a peripheral-chipset pin to issue security interrupt p_int_m, and so on. The security interrupts issued by security peripherals 110_1…110_m will be transmitted to processor 102 via security interrupt controller 128 and then handled by Local_APIC, a local high-level programmable interrupt controller paired with trusted core 112.

[0073] Security peripherals 110_1…110_m can also issue interrupts via messages. This embodiment does not require the use of the security interrupt controller 128. Security peripherals 110_1…110_m can issue message-signaled interrupts (MSIs), which are transmitted from chipset 104 to processor 102 via the processor interface CPUIF, and then handed over by the host interface high-level programmable interrupt controller HIF_APIC to the local high-level programmable interrupt controller Local_APIC paired with the trusted core 112 for processing.

[0074] The trusted core 112 includes the design of corresponding secure peripherals 110_1…110_m, and the associated local high-level programmable interrupt controller, Local_APIC, has also been adjusted accordingly. The isolated memory 116 also needs to store the corresponding secure interrupt descriptor table for the secure interrupts of the secure peripherals 110_1…110_m.

[0075] Figure 4 According to one embodiment of this application, the processor 102 terminal is illustrated in how to handle interrupts.

[0076] As previously described, system memory 106 includes general memory 120 and isolated memory 116. General memory 120 carries a general interrupt descriptor table (IDT). Isolated memory 116 carries a secure interrupt descriptor table (SIDT). The SIDT lists secure interrupt descriptors corresponding to secure interrupts initiated by the corresponding secure peripherals 110_1…110_m. Based on the secure interrupt descriptors, the trusted core 112 can locate and execute the interrupt routine corresponding to each secure interrupt. The general interrupt descriptors for general peripherals 108_1…108_n are carried in the IDT of general memory 120, corresponding to general interrupts initiated by the corresponding general peripherals 108_1…108_n. Based on the general interrupt descriptors, the general core or trusted core can locate and execute the interrupt routine corresponding to each general interrupt.

[0077] The trusted core 112 stores the address of the general interrupt descriptor table (IDT) in register IDTR and the address of the secure interrupt descriptor table (SIDT) in register SIDTR. The Local_APIC, designed for the trusted core 112, includes an interrupt arbiter 404. Based on the interrupt type (whether secure or not), the interrupt arbiter 404 determines the priority and sends an interrupt request signal (general interrupt request signal INTR or secure interrupt request signal SINTR) and an interrupt vector (general interrupt vector IV or secure interrupt vector SIV) to the trusted core 112, waiting for the trusted core 112's response interrupt response signal (general interrupt response signal INTA or secure interrupt response signal SINTA). For corresponding general interrupts, the trusted core 112 uses the general interrupt vector IV to query the general interrupt descriptor table (IDT) based on the address stored in register IDTR to obtain the corresponding general interrupt descriptor and execute the corresponding general interrupt routine. For the corresponding security interrupt, the trusted core 112 uses the security interrupt vector SIV to query the security interrupt descriptor table SIDT based on the address carried in the SIDTR register to obtain the corresponding security interrupt descriptor and execute the corresponding security interrupt program.

[0078] Figure 5 This application illustrates details of a security interrupt controller 128 according to one embodiment. The security interrupt controller 128 includes a programmable interrupt controller (PIC) 502 and a security interrupt handling unit 504. The peripheral-chipset pins of each of the security peripherals 110_1…110_m are connected to the PIC 502. The PIC 502 arbitrates security interrupts issued by the security peripherals 110_1…110_m, assigning the highest priority security interrupt, and generating a security interrupt request signal SINTR and a security interrupt vector SIV to the security interrupt handling unit 504, which then responds with a security interrupt response signal SINTA.

[0079] A secure interrupt handling unit 504 is coupled between the programmable interrupt controller 502 and the processor 102. The secure interrupt handling unit 504 is connected to the processor 102 via multiple chipset-processor pins corresponding to the secure peripherals 110_1…110_m, and sets corresponding pins among these chipset-processor pins according to the secure interrupt vector SIV provided by the programmable interrupt controller 502 to send secure interrupts p_int_1…p_int_m to the processor 102. Each secure peripheral corresponds to one peripheral-chipset pin and one chipset-processor pin. For example, secure peripheral 110_1 corresponds to one peripheral-chipset pin and one chipset-processor pin to send secure interrupt p_int_1 to the processor 102; secure peripheral 110_m corresponds to one peripheral-chipset pin and one chipset-processor pin to send secure interrupt p_int_m to the processor 102; and so on. As shown in the figure, the chipset-processor pins are connected to the Local_APIC of the trusted core 112. The Local_APIC of the trusted core 112 distinguishes which security peripheral corresponds to the security interrupt currently reporting to the processor 102 based on the chipset-processor pin settings. In one embodiment, when security interrupt p_int_1 is high and other security interrupts are low, the Local_APIC of the trusted core 112 determines that the security interrupt currently reporting to the processor 102 corresponds to security peripheral 110_1; when security interrupt p_int_m is high and other security interrupts are low, the Local_APIC of the trusted core 112 determines that the security interrupt currently reporting to the processor 102 corresponds to security peripheral 110_m; and so on.

[0080] Figure 6 Details of a safety interrupt controller 128 are illustrated according to another embodiment of this application. Compared to... Figure 5 The security interrupt handling unit 602 directly passes the security interrupt vector SIV provided by the programmable interrupt controller 502 to the processor 102, which is then received and processed by the local high-level programmable interrupt controller Local_APIC of the trusted core 112.

[0081] Figure 5 as well as Figure 6This technique using the secure interrupt controller 128 is called Programmable Interrupt Control Mode (PICmode). The secure interrupt controller 128 includes a Programmable Interrupt Controller (PIC) 502. Secure peripherals 110_1…110_m each send secure interrupts p_int_1…p_int_m to the secure interrupt controller 128 via a peripheral-chipset pin. These interrupts are then forwarded to the trusted core 112 for processing via the path of the Programmable Interrupt Controller (PIC) 502. How the trusted core 112 processes the received secure interrupts p_int_1…p_int_m has been discussed previously. Figure 4 Since this has already been explained, I won't repeat it here.

[0082] In one embodiment, such as Figure 1 As shown, the security peripherals 110_1…110_m do not require dedicated peripheral-chipset pins to connect to the security interrupt controller 128. Instead, they issue interrupts via information, a mode known as Advanced Programmable Interrupt Control (APIC) mode. The security peripherals 110_1…110_m can use the Peripheral Component Interconnect (PCI) standard to issue message-driven interrupts (MSI) to the chipset 104. The chipset 104 then transmits the MSI to the processor 102 via the CPUIF processor interface. Finally, the host interface advanced programmable interrupt controller (HIF_APIC) on the processor 102 hands the MSI to the local advanced programmable interrupt controller (Local_APIC) paired with the trusted core 112 for processing.

[0083] Figure 7 According to one embodiment of this application, an information-driven interrupt (MSI) 702 is illustrated. For example... Figure 7 As shown, the base address field value of the information-driven interrupt 702 received by the chipset 104 from the peripheral is generally 0xFEE. When the monitor 126 of the chipset 104 determines that this information-driven interrupt 702 originates from a secure peripheral, it changes its base address field to a specific value, such as 0xFEA, to mark this information-driven interrupt 702 as a secure interrupt. The information-driven interrupt 702 also includes other fields, such as interrupt vectors, etc., which will not be elaborated here. In another embodiment, after the monitor 126 of the chipset 104 determines that this information-driven interrupt 702 originates from a secure peripheral, it changes its base address field to another specific value, such as 0xFEB. This invention does not limit the specific value of the base address field of the information-driven interrupt originating from a secure peripheral, as long as it is different from 0xFEE.

[0084] Chipset 104 delegates Messenger Interrupts (MSIs) to the Host Interface High-Programmable Interrupt Controller (HIF_APIC). If the base address field of the Messenger Interrupt 702 is a specific value (e.g., 0xFEA or another value different from 0xFEE), the HIF_APIC will recognize it as a secure interrupt and delegate it to the Local High-Programmable Interrupt Controller (Local_APIC) paired with the Trusted Core 112 for processing. The method by which the Trusted Core 112 handles secure interrupts has been described above. Figure 4 Since an introduction has already been given, I won't go into details here.

[0085] Figure 8 , Figure 9 The detailed operation of the monitor 126 is further illustrated according to the embodiments of this application.

[0086] Figure 8 This diagram illustrates the communication management of processor 102 with peripherals. Please also refer to... Figure 1 and Figure 8 As mentioned earlier, when processor 102 requests access to a peripheral device, it sends a peripheral access request to chipset 104. This peripheral access request includes a core ID 802, an address 804, and data 806. Address 804 is either an I / O address or a memory-mapped I / O address. Data 806 contains operation commands (e.g., a command to reset the peripheral device) or data (e.g., data written to the peripheral device) sent by processor 102 to the peripheral device. The processor-to-peripheral channel contains multiple bits that label the core ID 802. As mentioned earlier, the monitor 126, located on the central communication controller 122 of chipset 104, can determine, based on this core ID 802, whether the current peripheral access request originates from trusted core 112 or general cores 114_1…114_k; the monitor 126 can determine, based on address 804, whether the peripheral requested by processor 102 is a general peripheral or a secure peripheral; thereby implementing the following access rules:

[0087] Rule 1: Only trusted core 112 can access secure peripherals 110_1…110_m; and

[0088] Rule 2: Only general cores 114_1…114_k can access general peripherals 108_1…108_n.

[0089] In one implementation, the monitor 126 queries table 200 of the memory protection configuration information 124 based on the requested access address (Addr) 804. Figure 2Based on the entries in Table 200 that match the I / O range 204 or MIMO range 206 for address 804, the type of peripheral to be accessed (0: security peripheral; 1: general peripheral) can be determined, thus confirming compliance with Rules 1 and 2. More specifically, when address 804 is an I / O address, monitor 126 compares address 804 with the I / O range 204 of the entries in Table 200 to obtain entries matching address 804. When address 804 is a MIMO address, monitor 126 compares address 804 with the MIMO range 206 of the entries in Table 200 to obtain entries matching address 804. More detailed comparison operations have been illustrated previously and will not be repeated here.

[0090] Figure 9 This diagram illustrates the communication management between peripherals and processor 102. Please also refer to... Figure 1 and Figure 9 As mentioned earlier, when a peripheral device requests access to system memory 106 (to read data from or write data to system memory 106), it sends an access request to chipset 104. This access request includes a peripheral identification code 902, an address 904, and data 906. When a peripheral device requests to write data to system memory 106, data 906 contains the data the peripheral device wants to write to system memory 106. The system memory access request issued by the peripheral device carries a peripheral identification code (device ID) 902. As mentioned earlier, the monitor 126, located on the central communication controller 122 of chipset 104, can determine whether the current access request originates from a general peripheral 108_1…108_n or a secure peripheral 110_1…110_m based on this peripheral identification code 902, and thus implement the following access rules:

[0091] Rule 3: Allow secure peripherals 110_1…110_m to access isolated memory 116;

[0092] Rule 4: Security peripherals 110_1…110_m are not allowed to access other system memory spaces (general memory 120) outside of isolated memory 116; and

[0093] Rule 5: General peripherals 108_1…108_n are allowed to access general memory 120, but general peripherals 108_1…108_n are not allowed to access isolated memory 116.

[0094] In one implementation, the monitor 126 queries table 200 in the memory protection configuration information 124 based on the peripheral identification code 902 carried in the access request. Figure 2 Based on the matching peripheral identification codes in Table 200, the type of the requesting peripheral is identified (0: security peripheral; 1: general peripheral). Monitor 126 will further query the address (Addr) 904 requested by the peripheral. Figure 3 Table 300 determines whether the peripheral device is requesting access to isolated memory 116. For example... Figure 3 As shown, when the isolated memory base address is 20000 and the isolated memory address size is 100, the represented memory space range is from 20000 to 20100. When the address (Addr) 904 requested by the peripheral device is 20050, since 20050 is greater than 20000 and less than 20100, the monitor 126 determines that the peripheral device is requesting access to isolated memory 116. Based on the above table lookup results, the monitor can determine whether the peripheral device's access request to system memory 106 conforms to rules 3, 4, and 5.

[0095] The following examples illustrate the use of various peripherals.

[0096] When a peripheral needs to access system memory 106, the high-speed peripheral uses Direct Memory Access (DMA) technology to exchange data with the processor 102. The configuration register space used to configure the high-speed peripheral can be a Memory-Mapped Input / Output (MIMO) space or an Input / Output (I / O) space. When a DMA, MIMO, or I / O operation is performed, a monitor 126 located within the chipset 104 checks whether the access is to isolated memory 116 or whether the target of the operation is a secure peripheral 110_1…110_m. Specifically, the secure interrupts used by secure peripherals 110_1…110_m differ from the general interrupts used by general peripherals 108_1…108_n. The corresponding handlers for the secure interrupts are stored in the trusted operating system and executed by the trusted core 112, thereby achieving isolation between secure peripherals 110_1…110_m and general peripherals 108_1…108_n.

[0097] Peripherals can actively request access to 106 units of system memory.

[0098] The network interface card (NIC) is a high-speed peripheral. When the NIC sends data, the processor 102 prepares the data in system memory 106 and notifies the NIC to retrieve the data via the NIC controller's configuration register (e.g., changing the value of a bit in the configuration register from 0 to 1). The NIC retrieves the data from system memory 106 using Direct Memory Access (DMA) and then notifies the processor 102 via an interrupt for further processing. When the NIC receives incoming data, it uses the memory address range pre-configured by the processor 102 in the NIC controller's configuration register to write the incoming data into system memory 106 using DMA, and then generates an interrupt to notify the processor 102 for further processing. In one embodiment, the NIC is a secure peripheral, operated by a trusted core 112, using isolated memory space 116, and employing secure interrupts.

[0099] Serial port (Universal Asynchronous Receiver / Transmitter, UART) devices—such as keyboards and mice—are low-speed peripherals. After receiving data, the serial port sends an interrupt to processor 102, causing processor 102 to retrieve the data from the corresponding serial port address using the IN instruction. Conversely, when sending data via the serial port, processor 102 configures the relevant configuration registers through input / output (I / O) operations and writes data to the corresponding serial port address using the OUT instruction. During I / O operations, the monitor 126 of chipset 104 checks whether the target of these operations is a secure peripheral 110_1…110_m, and whether the secure peripheral uses secure interrupts and is indeed isolated from general peripherals 108_1…108_n. How the monitor 126 of chipset 104 checks whether the target of these operations is a secure peripheral 110_1…110_m and how secure peripherals use secure interrupts has been described previously and will not be repeated here.

[0100] This application sets up a set of memory protection configuration information in the chipset to classify peripherals as general peripherals or secure peripherals, and divides system memory into general memory and isolated memory, thereby enabling only secure peripherals to access isolated memory and only general peripherals to access general memory. Furthermore, this application achieves isolation between secure interrupt handling and general interrupt handling by setting up a separate secure interrupt controller in the chipset, or by utilizing Information Driven Interrupts (MSI), and adding a separate secure interrupt descriptor register, secure interrupt descriptor table, and corresponding secure interrupt handling mechanism in the trusted core. Through the above design, the secure peripherals implemented in this application have a very high level of security.

[0101] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A computer system, comprising: Processors, including general-purpose cores and trusted cores used for trusted computing; System memory provides general memory as well as isolated memory for trusted computing; as well as The chipset is coupled to the processor, the system memory, and multiple peripherals, and is responsible for communication between the processor, the system memory, and the peripherals. in: The isolated memory is equipped with a secure interrupt descriptor table for secure interrupts initiated by secure peripherals in the peripherals. The first register in the trusted core stores the first address, which points to the security interrupt descriptor table; The trusted core's local high-level programmable interrupt controller provides an interrupt arbitrator to arbitrate interrupts transmitted from the peripherals via the chipset; and When the target interrupt determined by arbitration is a secure interrupt, the interrupt arbitrator sends a secure interrupt request signal and a secure interrupt vector, triggering the trusted core to find the secure interrupt descriptor table according to the first register, and then search the secure interrupt descriptor table to determine the target interrupt descriptor in order to execute the corresponding interrupt routine.

2. The computer system as claimed in claim 1, wherein: The general memory is equipped with a general interrupt descriptor table for general interrupts initiated by general peripherals in the peripherals. The second register in the trusted core stores a second address, which points to the general interrupt descriptor table; and When the target interrupt determined by the arbitration is a general interrupt, the interrupt arbitrator issues a general interrupt request signal and a general interrupt vector, triggering the trusted core to find the general interrupt descriptor table according to the second register, and then search the general interrupt descriptor table to determine the target interrupt descriptor in order to execute the corresponding interrupt routine.

3. The computer system as described in claim 1, wherein: The chipset forwards the information from the security peripheral to the processor, notifying the interrupt arbiter of the local high-level programmable interrupt controller of the trusted core that a security peripheral has initiated a security interrupt.

4. The computer system as described in claim 3, wherein: Information from a security peripheral drives an interrupt, which is marked as originating from the security peripheral by the chipset so that the host interface advanced programmable interrupt controller of the processor can identify it and decide to pass it to the interrupt arbitrator of the local advanced programmable interrupt controller of the trusted core.

5. The computer system as described in claim 4, wherein: This chipset modifies the base address field of the interrupt driven by information from a security peripheral to a specific value, indicating that it originates from the security peripheral.

6. The computer system as claimed in claim 1, wherein: The chipset includes a security interrupt controller, and each security peripheral is connected to the security interrupt controller via a peripheral-chipset pin to transmit the initiated security interrupt; The security interrupt controller is connected to the processor and, when a security peripheral initiates a security interrupt, notifies the interrupt arbitrator of the local high-level programmable interrupt controller of the trusted core.

7. The computer system as claimed in claim 6, wherein, The safety interrupt controller includes: A programmable interrupt controller arbitrates security interrupts from multiple security peripherals connected to the security interrupt controller to generate a security interrupt request signal and a security interrupt vector; and A security interrupt handling unit is coupled between the programmable interrupt controller and the processor. The security interrupt handling unit is connected to the processor via a plurality of chipset-processor pins corresponding to the security peripheral, and sets the corresponding pins among the chipset-processor pins according to the security interrupt vector provided by the programmable interrupt controller.

8. The computer system of claim 7, wherein: The chipset-processor pins are connected to the local advanced programmable interrupt controller of the trusted core.

9. The computer system as claimed in claim 6, wherein, The safety interrupt controller includes: A programmable interrupt controller arbitrates security interrupts from multiple security peripherals connected to the security interrupt controller to generate a security interrupt request signal and a security interrupt vector; and A secure interrupt handling unit is coupled between the programmable interrupt controller and the processor, wherein the secure interrupt handling unit passes the secure interrupt vector provided by the programmable interrupt controller to the processor.

10. The computer system of claim 9, wherein: The secure interrupt vector passed from the secure interrupt handling unit to the processor is received by the local high-level programmable interrupt controller of the trusted core.

11. A trusted computing method, comprising: The processor's trusted core interrupt arbitrator arbitrates interrupts transmitted from multiple peripherals via the chipset; and When the target interrupt determined by arbitration is a secure interrupt, the interrupt arbitrator sends a secure interrupt request signal and a secure interrupt vector, triggering the trusted core to find the secure interrupt descriptor table according to the first register, and then search the secure interrupt descriptor table to determine the target interrupt descriptor in order to execute the corresponding interrupt routine.

12. The trusted computing method as described in claim 11, further comprising: When the target interrupt determined by arbitration is a general interrupt, the interrupt arbitrator sends a general interrupt request signal and a general interrupt vector, triggering the trusted core to find the general interrupt descriptor table according to the second register, and then search the general interrupt descriptor table to determine the target interrupt descriptor in order to execute the corresponding interrupt routine.

13. The trusted computing method as described in claim 11, further comprising: The chipset transmits information from the security peripheral to the processor, which then notifies the trusted core's interrupt arbitrator that a security peripheral has initiated a security interrupt.

14. The trusted computing method as described in claim 13, wherein: Information from a security peripheral drives an interrupt, which is marked as originating from the security peripheral by the chipset so that the host interface advanced programmable interrupt controller of the processor can identify it and decide whether to pass it to the interrupt arbitrator of the trusted core.

15. The trusted computing method as described in claim 14, wherein: This chipset modifies the base address field of the interrupt driven by information from a security peripheral to a specific value, indicating that it originates from the security peripheral.

16. The trusted computing method as described in claim 11, wherein: The chipset includes a security interrupt controller, and each security peripheral is connected to the security interrupt controller via a peripheral-chipset pin to transmit the initiated security interrupt; The security interrupt controller is connected to the processor and notifies the interrupt arbitrator of the trusted core when a security peripheral initiates a security interrupt.

17. The trusted computing method as described in claim 16, wherein, The safety interrupt controller includes: A programmable interrupt controller arbitrates security interrupts from multiple security peripherals connected to the security interrupt controller to generate a security interrupt request signal and a security interrupt vector; and A security interrupt handling unit is coupled between the programmable interrupt controller and the processor. The security interrupt handling unit is connected to the processor via a plurality of chipset-processor pins corresponding to the security peripheral, and sets the corresponding pins among the chipset-processor pins according to the security interrupt vector provided by the programmable interrupt controller.

18. The trusted computing method as described in claim 17, wherein: The chipset-processor pins are connected to a local advanced programmable interrupt controller that is linked to the trusted core.

19. The trusted computing method as described in claim 16, wherein, The safety interrupt controller includes: A programmable interrupt controller arbitrates security interrupts from multiple security peripherals connected to the security interrupt controller to generate a security interrupt request signal and a security interrupt vector; and A secure interrupt handling unit is coupled between the programmable interrupt controller and the processor, wherein the secure interrupt handling unit passes the secure interrupt vector provided by the programmable interrupt controller to the processor.

20. The trusted computing method as described in claim 19, wherein: The security interrupt vector passed from the security interrupt handling unit to the processor is received by the local high-level programmable interrupt controller of the trusted core.

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