Fuse delay of commands in memory packages

Abstract

This application relates to fuse delays for commands in a memory package. A fuse can store different delay states to interleave command execution for different memory dies within the memory package. A fuse array can be included in the memory package and programmed such that command execution has different delays for different dies. The fuse array can be manufactured and then programmed to cause different delays for different dies.

Description

Technical Field

[0001] This disclosure generally relates to memory, and more specifically, to apparatus and methods associated with fuse delays of commands in a memory package. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory provides permanent data by retaining the stored data when no power is supplied and includes NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), etc.

[0003] Memory is also used as a volatile and non-volatile data storage device in a wide range of electronic applications, including (but not limited to) personal computers, Memory Sticks, digital cameras, cellular phones, portable music players (e.g., MP3 players, movie players), and other electronic devices. Memory cells can be arranged in arrays, wherein the arrays are used in memory devices. Summary of the Invention

[0004] This disclosure provides a method comprising: receiving a command at a primary die; providing the command from the primary die to a first auxiliary memory die and a second auxiliary memory die; executing the command on the first auxiliary memory die according to a first fuse-trimmed delay; and executing the command on the second auxiliary memory die according to a second fuse-trimmed delay.

[0005] Another aspect of this disclosure provides an apparatus comprising: a plurality of auxiliary memory dies, each including: a corresponding memory array; a corresponding fuse array; and a corresponding trimming circuit system coupled to the corresponding fuse array and the corresponding memory array; and a primary die coupled to the plurality of auxiliary memory dies, the primary die including control logic configured to distribute commands to the plurality of auxiliary memory dies; wherein each corresponding fuse array is programmed to have a different corresponding delay state; wherein each corresponding trimming circuit system is configured to: latch the different corresponding delay states from the corresponding fuse array; and delay the execution of the command on the corresponding auxiliary memory die according to the different corresponding delay states.

[0006] Another aspect of this disclosure provides an apparatus comprising: a plurality of auxiliary memory dies, each including: corresponding local control logic; and a corresponding memory array coupled to the corresponding local control logic; and a primary die coupled to the plurality of auxiliary memory dies, the primary die including: a fuse array programmed to have different corresponding delay states for each of the corresponding auxiliary memory dies; and a trimming circuitry configured to: latch the different corresponding delay states from the fuse array; and delay the distribution of a full-die command to the auxiliary memory dies according to the different corresponding delay states.

[0007] Another aspect of this disclosure provides a method comprising: manufacturing a plurality of primary dies; manufacturing a plurality of secondary memory dies, each of the plurality of secondary memory dies including a corresponding fuse array; coupling a subset of the plurality of secondary memory dies to a particular primary die; and programming the corresponding fuse array of the subset of the plurality of secondary memory dies to have a corresponding delay state for a command from the particular primary die for each of the subset of the plurality of secondary memory dies. Attached Figure Description

[0008] Figure 1A This is a block diagram of an apparatus in the form of a memory package comprising memory dies, each having a fuse array, according to several embodiments of the present disclosure.

[0009] Figure 1B This is a block diagram of a device in the form of a memory package having a fuse array, according to several embodiments of the present disclosure.

[0010] Figure 2 This is a block diagram of an apparatus, according to several embodiments of the present disclosure, in the form of a computing system comprising a memory package including a memory die having a fuse array.

[0011] Figure 3This is a flowchart of a method for operating a memory package according to several embodiments of the present disclosure.

[0012] Figure 4 This is a flowchart of a method for manufacturing one or more memory packages according to several embodiments of the present disclosure.

[0013] Figure 5 Illustrated example computer system, within which a set of instructions can be executed to cause the machine to perform the various methods discussed herein.

[0014] Figure 6 Examples of delayed paths according to several embodiments of this disclosure are described. Detailed Implementation

[0015] This disclosure includes apparatus and methods related to fuse delays for commands in a memory package. The commands are intended to be executed by more than one die in the memory package, such as a full die command. Typically, a full die command will be executed simultaneously by more than one die in the memory package. However, embodiments are not limited to full die commands, as some memory packages have multiple dies executing commands other than full die commands. The die refresh pump and die activation operations are typically aligned because they receive commands simultaneously. This can cause transient power spikes and high current draws in the memory package, which can also cause a drop in power supply.

[0016] The aspects of this disclosure address the aforementioned and other deficiencies. For example, fuse delays can be introduced into the memory die to cause interleaved execution of commands for different dies. One or more fuse arrays can be included in the memory package, the fuse arrays can be read, and the information stored therein can be used to cause command execution to be delayed by different amounts for different dies. The fuse arrays can be generally manufactured and then programmed to create different delays. Interleaved execution of commands can help reduce transient power spikes, current drawdowns, and supply drops.

[0017] As used herein, the singular forms “a” and “the” include both singular and plural indicators unless the content expressly indicates otherwise. Furthermore, the word “may” is used throughout this application in a permissive (i.e., possible, able) and not in a mandatory (i.e., required) sense. The term “comprising” and its derivatives mean “including (but not limited to)”. The term “coupled” means a direct or indirect connection.

[0018] The diagrams in this document follow a numbering convention, where the first one or a few digits correspond to the diagram number, and the remaining digits identify the elements or components within the diagram. Similar elements or components between different diagrams can be identified using similar digits. For example, 100 in... Figure 1A The element "00" can be referenced in the code, and similar elements are also available in the code. Figure 2This is referred to as 200. Similar elements within the diagram can be referenced using hyphens followed by additional numbers or letters. For example, see [reference 200]. Figure 1A The elements 134-0, 134-1, 134-2, and 134-N are used in the drawings. Such similar elements may generally be referred to without hyphens and additional numbers or letters. For example, elements 134-0, 134-1, 134-2, and 134-N may be collectively referred to as 134. As used herein, particularly with respect to reference numerals in the drawings, the indicators “N” and “Y” indicate the number of specific features thus specified. It will be understood that elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of the invention and should not be construed as limiting.

[0019] Figure 1A This is a block diagram of an apparatus according to several embodiments of the present disclosure, comprising a memory package 100 comprising memory dies 104, 106-1, 106-2, 106-N, each having a fuse array 134-0, 134-1, 134-2, ..., 134-N. Memory die 104 may be referred to as a primary die or primary memory die, and memory die 106 may be referred to as an auxiliary memory die because it receives commands, data, and / or other control signals from the primary die 104. The primary die 104 may also be referred to as a master die in the art. The auxiliary memory die 106 may also be referred to as a slave memory die in the art. The primary die 104 receives commands, data, and / or other control signals from an interface 102 to a host, which may be a memory controller. The term "host" as used herein includes a memory controller.

[0020] Figure 1B This is a block diagram of a device in the form of a memory package 100 having a fuse array 134, according to several embodiments of the present disclosure. Figure 1A In contrast, Figure 1B The memory package 100 contains a fuse array only in the main die 104, while the auxiliary memory dies 106-1, 106-2, ..., 106-N do not contain fuse arrays. Figure 1A and 1B The commonalities between them are described together, while the differences are described in individual details.

[0021] Memory package 100 is coupled to the host via interface 102. As used herein, for example, the host, memory package 100, or memory array 118 may also be considered as a "device" on its own. Memory package 100 may provide main memory to the host or may be used as additional memory or storage device for the host. An example of memory package 100 is a three-dimensional stacked (3DS) memory package.

[0022] Interface 102 enables the transmission of control, address, data, and other signals between memory package 100 and the host. Interface 102 may include a command bus (e.g., a command decoding circuitry 110 coupled to main control logic 108) and an address bus (e.g., coupled to address register 114). Main control logic 108 may also be referred to as command input and control circuitry (or more generally, a “control circuitry system”). Main control logic 108 may include a state machine, a sequencer, and / or some other type of control circuitry system, which may be implemented in hardware, firmware, or software, or any combination thereof.

[0023] Although described separately, interface 102 may include a data bus (e.g., coupled to input / output (I / O) circuitry 124); however, as illustrated, in some embodiments, I / O circuitry 124 is decoupled from interface 102. For example, interface 102 may be a controller interface, and the I / O circuitry may be coupled to a host different from the controller. In some embodiments, the command bus and address bus may consist of a common command / address bus. In some embodiments, the command bus, address bus, and data bus may be part of a common bus. Interface 102 may be a physical interface employing a suitable protocol. This protocol may be custom or proprietary, or interface 102 may employ a standardized protocol, such as Peripheral Component Interconnect Fast (PCIe), Gen-Z Interconnect, Cache Coherent Interconnect for Accelerators (CCIX), etc. In some cases, address register 114 may be embedded in mode register 112-0 on the main die 104.

[0024] The command bus can transmit signals between the host and the command decoding circuitry system 110, such as clock signals for timing, die select, write enable signals, and die select signals (for...). Figure 1AThe embodiments described herein, which may also be referred to as logical rank addresses (“C[1:0]”, which allows individual addressing of the primary die 104 and each auxiliary memory die 106), etc., are described. Command decoding circuitry 110 can decode signals provided by the host. Signals may be commands provided by the host. These commands can be used to control operations performed on the memory array 118. Such operations may include data read operations, data write operations, data erase operations, data move operations, etc. Commands can be decoded by command decoding circuitry 110 and forwarded to the memory array 118 via local control logic 116-0, 116-1, 116-2, ..., 116-N. Local control logic 116-0 on the primary die 104 is coupled to local control logic 116-1 on the auxiliary memory die 106-1. Local control logic 116-1 on the auxiliary memory die 106-1 is coupled to local control logic 116-2 on the auxiliary memory die 106-2. Local control logic 116-2 on auxiliary memory die 106-2 is coupled to local control logic 116-N on auxiliary memory die 106-N. Local control logic 116 of memory package 100 is coupled in a chain configuration. A common internal command bus 131 is coupled to main control logic 108, local control logic 116-0 on main die 104, and local control logic 116-1, 116-2, ..., 116-N on each auxiliary memory die 106.

[0025] As in Figure 1A As shown, the corresponding fuse array 134 is coupled to each local control logic 116. Specifically, the local control logic 116-0 of the main die 104 is coupled to fuse array 134-0, the local control logic 116-1 of the auxiliary memory die 106-1 is coupled to fuse array 134-1, the local control logic 116-2 of the auxiliary memory die 106-2 is coupled to fuse array 134-2, and the local control logic 116-N of the auxiliary memory die 106-N is coupled to fuse array 134-N.

[0026] As in Figures 1A to 1B As shown, the local control logic 116-0 of the main die 104 is coupled to the trimming circuit system 135-0, the local control logic 116-1 of the auxiliary memory die 106-1 is coupled to the trimming circuit system 135-1, the local control logic 116-2 of the auxiliary memory die 106-2 is coupled to the trimming circuit system 135-2, and the local control logic 116-N of the auxiliary memory die 106-N is coupled to the trimming circuit system 135-N. The trimming circuit system 135 is coupled to the fuse array 134 and the memory array 118.

[0027] As used herein, the term "fuse" includes both fuses and antifuses. A fuse is conductive in its initial state and, upon programming (e.g., by subjecting it to a large current), transitions to an insulating state (e.g., the conductive path is broken or "blown"). An antifuse is insulating in its initial state and, upon programming (e.g., by subjecting it to dielectric breakdown), transitions to a conductive state. After the transition, a fuse or antifuse cannot return to its initial state and is referred to as being one-time programmable. In some embodiments, a fuse may be a gate oxide fuse, which is one-time programmable by breaking the gate oxide in a metal-oxide-semiconductor device. Other examples of fuses include a resistor-transistor unit and a resistor-diode unit, etc.

[0028] Fuse array 134 is a collection of addressable fuses located somewhere on a die. In some embodiments, there is only one fuse array 134 per die. Fuse array 134 may store manufacturing settings (e.g., service address, voltage trimming, timing trimming, die identification, die configuration settings, speed settings, functions, etc.). Upon power-on or reset, a set of fuses is sensed at a time by a fuse logic circuitry system (not specifically described) and broadcast on fuse bus lines (not specifically described) around the die. The fuse state is then locally latched in a trimming circuitry system, such as trimming circuitry system 135. Fuse array 134 is physically separated from trimming circuitry system 135. Trimming circuitry system 135 may include fuse latches. A fuse latch is a latch / trigger that stores fuse data near the circuitry system that uses fuse data for trimming. According to at least one embodiment of this disclosure, the fuse latch may enable / disable delays in a command path based on the latched state from fuse array 134.

[0029] The main control logic 108 can be configured to distribute commands to auxiliary memory dies 106. Instance command types include die-specific commands and full-die commands. A full-die command is a command intended to be executed by each die 104, 106 in memory package 100. In contrast, a command intended to be executed by only one die may have an associated die select signal (e.g., "C[1:0]", as shown in the image). Figure 1A(As illustrated in the document). In some cases, multiple die-specific commands can be issued simultaneously to different dies. Commands can be received from the host via interface 102 or generated by the main control logic 108. Typically, all die commands are executed simultaneously; however, according to at least one embodiment of this disclosure, each fuse array 134 can be programmed to have a different corresponding delay state. Trimming circuitry 135 (e.g., fuse latches) can latch the different corresponding delay states from the respective fuse arrays 134 to delay the execution of all die commands differently for each of the auxiliary memory die 106 and the main die 104. In at least one embodiment, the fuse array 134-0 of the primary die 104 is not programmed to cause a delay in the execution of commands for the primary die 104. This may result in full die commands being executed on the primary die 104, but not on the secondary memory die 106. There is no fuse trimming delay attributable to the delay caused by the fuse arrays 134-1, 134-2, ..., 134-N and their corresponding fuse latches.

[0030] exist Figure 1B In the embodiment described herein, fuse array 134 is coupled to the main control logic 108 of the primary die 104, rather than to the local control logic 116 coupled to the primary die 104 and each secondary memory die 106. The main control logic 108 can be configured to distribute full-die commands (or all commands) to the secondary memory dies 106, regardless of their individual die select addresses. Fuse array 134 is programmed to delay full-die commands differently for each of the secondary memory dies 106. Fuse array 134 can be programmed to have different corresponding delay states for each of the respective secondary memory dies 106. Trimming circuitry system 135 can latch the different corresponding delay states from fuse array 134 and delay the distribution of full-die commands to the secondary memory dies according to the different corresponding delay states. The main control logic 108 can distribute full-die commands to the secondary memory dies 106 via trimming circuitry system 135. In at least one embodiment, the fuse array 134 is programmed to delay full-die commands differently for each of the primary die 104 and the secondary memory die 106.

[0031] Despite Figure 1A Not specifically described herein, but at least one embodiment includes an additional auxiliary memory die coupled to the stack of auxiliary memory dies 106 in a manner similar to that of auxiliary memory dies 106-N, the only difference being that the additional auxiliary memory dies are not configured to delay command execution, thereby causing full-die (or any other) commands sent to the additional memory dies to be executed without delay. For example, the fuse array 134 of the additional auxiliary memory dies may not be programmed to have a delayed state.

[0032] The address bus can transmit signals between the host and address register 114, such as memory row addresses, memory bank group addresses, and memory bank addresses within memory bank groups, and / or other logical addresses for memory arrays 118-0, 118-1, 118-2, and 118-N. Address register 114 can latch address signals provided through interface 102. Address signals can be decoded by the main control logic 108 and provided from there to the local control logic 116 for accessing memory array 118 via the common internal address bus 129. The common internal address bus 129 can also be used to operate mode registers 112-0, 112-1, 112-2, ..., 112-N on the main die 104 and auxiliary memory die 106. For example, mode register group commands can be transmitted via the common internal address bus 129.

[0033] Data can be read from memory array 118 by sensing voltage and / or current changes on sensing lines using a sensing circuit system controlled by read driver 122 on main die 104. For example, sensing circuit system 122 may include a sensing amplifier capable of reading and latching a page (e.g., row) of data from memory array 118. Sensing (e.g., reading) bits stored in memory cells may involve sensing a relatively small voltage difference on a pair of sensing lines, which may be referred to as digital lines or data lines. Read driver 122 may be coupled to memory array 118 along data line 126.

[0034] Data can be provided to and / or received from the memory array 118 via data line 126, which couples the memory array 118 to an input / output (I / O) circuitry 124 via read driver 122 and / or write driver and input logic 120. The I / O circuitry 124 can be used for bidirectional data communication with a host via an interface (e.g., interface 102 or a separate interface). The write driver and input logic 120 are used to write data to the memory array 118. The read driver 122 is used to read data from the memory array 118. In some embodiments, the data path 126 may bypass the main control logic 108.

[0035] Memory array 118 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digital lines or data lines). Each of the illustrated memory arrays 118 may represent more than one memory array. Each of the memory arrays 118 may be arranged in a memory bank. The memory cells of memory array 118 may be volatile memory cells and / or non-volatile memory cells. By way of example, memory array 118 may operate as double data rate (DDR) DRAM (e.g., DDR5), graphics DDRDRAM (e.g., GDDR6), or another type of memory. Other examples of memory array 118 include RAM, ROM, SDRAM, LPDRAM, PCRAM, RRAM, flash memory, and 3DXPoint (e.g., a non-volatile memory array that can perform bit storage based on changes in body resistance by combining a stackable cross-grid data access array).

[0036] Figure 2 This is a block diagram of a device, according to several embodiments of the present disclosure, comprising a memory package 200 including dies 204, 206-1, 206-2, 206-3, 206-N having fuse arrays 234-1, 234-2, 234-3, 234-N, in the form of a computing system 201. Auxiliary memory die 206 receives commands, data, and / or other control signals from primary die 204. Primary die 204 may also be referred to in the art as a base die, buffer die, or logic die. Auxiliary memory die 206 may also be referred to in the art as a memory die. In some embodiments, primary die 204 does not provide memory for memory package 200, while auxiliary memory die 206 provides memory for memory package 200. Although not specifically stated, auxiliary memory die 206 may include a memory bank, such as a DRAM memory bank. In at least one embodiment, auxiliary memory die 206 does not include local control logic (e.g., Figures 1A to 1B The local control logic 116 described herein. Alternatively, the auxiliary memory die 206 includes terminals (e.g., command terminals, address terminals, data terminals, etc.) for control by the primary die 204. The auxiliary memory die 206 is coupled to the primary die 204 via a through-silicon via (TSV) 232. The auxiliary memory dies 206 are bonded to each other and to the primary die, which is bonded to an interposer layer, which is also bonded to the controller 291 and the substrate 230 via conductive connections 231, which may be referred to in the art as bumps or balls. The conductive connections 231 may transmit signals, form terminals, provide ground connections, or simply serve as physical attachment points. Examples of computing systems 201 include high-bandwidth memory (HBM), hybrid memory cubes (HMC), etc.

[0037] The primary die 204 receives commands, data, and / or other control signals from a CPU, graphics processing unit (GPU), or on-chip system controller 291 via an interposer 228. Any of the CPU, GPU, or on-chip system controller 291 may be referred to as a host or memory controller. The primary die 204 can decode commands and send them to the secondary memory die 206 via a shared path via a TSV 232. All or more secondary memory dies 206 can execute commands. According to at least one embodiment of this disclosure, each secondary memory die 206 includes a corresponding fuse array 234 and trimming circuitry systems 235-1, 235-2, 235-3, 235-N (e.g., fuse latches), configured to... Figure 1A The described method delays commands in a different way for each auxiliary memory die 206 to interleave the execution of commands by the auxiliary memory die 206.

[0038] The fuse array 234 can be programmed prior to the deployment of the memory package 200. The fuse array 234 can be programmed by the provider of the corresponding memory system 201. The fuse array 234 can be programmed using a host and / or test circuitry system. The fuse array 234 can be programmed by selectively changing or not changing the state of one or more individual fuses. In other words, each fuse either remains in its initial state or is transitioned to a different state through programming operations.

[0039] In some embodiments, each memory die 206 in the memory package 200 may include a fuse array 234. The fuse array 234 may be fabricated on each die 206 in the same manner. However, each fuse array 234 may be programmed differently, for example by changing the state of different individual fuses in different ways to store different delayed states for each different fuse array 234 on different dies. Programming each of the fuse arrays 234 in different ways causes commands delivered to each die 206 in the memory package 200 to be executed at different times. Executing commands at different times helps to evenly distribute the power consumption of the memory dies 206, thereby reducing any corresponding power spikes in the memory package 200.

[0040] Figure 3 This is a flowchart illustrating a method for operating a memory package according to several embodiments of the present disclosure. The method may be performed by hardware (e.g., a processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.). For example, the method may be performed by a memory package (e.g.,... Figures 1A to 1BThe memory package 100 described herein is associated with a circuit system for execution. Although shown in a particular sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel.

[0041] At block 340, the method may include receiving commands at the primary die. For example, commands may be received from a host coupled to the primary die instead of at a first or second secondary memory die. The primary die may be a portion of a memory package that also includes one or more secondary memory dies. In such embodiments, commands may be received from the host only by the primary die, such that the secondary memory dies do not receive commands from the host.

[0042] At block 342, the method may include providing commands from the primary die to a first auxiliary memory die and a second auxiliary memory die. Commands may be provided from the primary die to additional auxiliary memory dies coupled to the primary die. Commands may be provided from the primary die to the auxiliary memory dies via a common command path within the memory package or via a separate internal command path for each auxiliary memory die.

[0043] At block 344, the method may include executing a command on a first auxiliary memory die according to a first fuse-trimmed delay. At block 346, the method may include executing a command on a second auxiliary memory die according to a second fuse-trimmed delay. Although not specifically stated, the method may include executing a command on a primary die according to a third fuse-trimmed delay. The execution of the command may be delayed in different ways for each auxiliary memory die coupled to the primary die.

[0044] In at least one embodiment, the method may include reading a first delay state and a second delay state from a fuse array associated with a primary die (e.g., as in...). Figure 1B (as shown in the diagram). The method may include latching a first delay state and a second delay state in a trimming circuit system, and providing a first fuse-trimmed delay and a second fuse-trimmed delay via the trimming circuit system.

[0045] In at least one embodiment, the method may include reading a first delay state from a first fuse array associated with a first auxiliary memory die, and reading a second delay state from a second fuse array associated with a second auxiliary memory die (e.g., as in...). Figure 1A or Figure 2(As described in the document). The method may include latching a first delay state in a first trimming circuit system associated with a first auxiliary memory die, and latching a second delay state in a second trimming circuit system associated with a second auxiliary memory die. The method may include providing a first fuse-trimmed delay via the first trimming circuit system and providing a second fuse-trimmed delay via the second trimming circuit system.

[0046] In some embodiments, the primary die may be able to independently address certain commands to the secondary memory die, eliminating the need for delays to avoid power spikes associated with simultaneous command execution by multiple dies. However, this memory package can also send and execute full-die commands, which are typically executed simultaneously by the secondary memory die (and in some cases, the primary die). At least one embodiment of this disclosure can help prevent simultaneous initiation and / or execution of full-die commands by more than one secondary memory die through different fuse-trimmed delay operations.

[0047] Figure 4 This is a flowchart illustrating methods for manufacturing one or more memory packages according to several embodiments of the present disclosure. The methods may be executed by processing logic, which may include hardware (e.g., processing devices, circuit systems, special-purpose logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. One or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0048] At block 450, the method may include manufacturing a primary die. At block 452, the method may include manufacturing secondary memory dies, each comprising a corresponding fuse array. The primary die and / or secondary memory dies may be mass-produced and then coupled to any number of memory packages as needed. The primary die may be manufactured with or without memory arrays and / or fuse arrays as needed. The secondary memory die contains a memory array. The fuse array on the secondary memory die may be generally manufactured (e.g., without specific programming) and later programmed with device-specific settings. The secondary memory die and / or primary memory die may be manufactured with latches configured to store settings programmed into the fuse arrays.

[0049] At block 454, the method may include coupling a subset of auxiliary memory dies to a specific primary die to form a memory package. Non-limiting examples of memory packages include 3DS, HBM, and HMC.

[0050] At block 456, the method may include programming a fuse array of an auxiliary memory die to have corresponding delayed states for each of a subset of auxiliary memory dies from a particular primary die. If the primary die is manufactured to have both a fuse array and a memory array, the fuse array on the primary die may be programmed to have delayed states different from the corresponding delayed states for each of the subsets of auxiliary memory dies. Programming the fuse array may involve changing the conductivity state of at least one element of the array (e.g., a fuse or antifuse). The fuse array may be programmed (e.g., by the memory package manufacturer or by an intermediary between the manufacturer and the end user) prior to shipping the memory package. This allows for the general fabrication (at least with respect to programmed delayed states) of the fuse array to facilitate efficient production. Subsequently, delayed states may be programmed into the fuse array as needed for any particular memory package or a series of memory packages (e.g., a series of products). The fuse array may also store other operational settings for the die.

[0051] Figure 5 An example computer system is described, within which a set of instructions can be executed to cause a machine to perform the various methods discussed herein. In various embodiments, computer system 590 may correspond to a system (e.g., regarding...) Figures 1A to 1B The described host system includes, is coupled to, or utilizes a memory subsystem (e.g., memory package 100 of FIG1), or can be used to perform operations of a control circuitry system. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0052] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0053] The example computer system 590 includes a processing device 591, a main memory 593 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 598 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 599, which communicate with each other via a bus 597.

[0054] Processing device 591 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 591 may also be one or more special-purpose processing devices, such as an Application-Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), a network processor, or the like. Processing device 591 is configured to execute instructions 592 for performing the operations and steps discussed herein. Computer system 590 may further include a network interface device 595 for communicating via network 596.

[0055] Data storage system 599 may include machine-readable storage medium 594 (also called computer-readable medium) on which one or more sets of instructions 592 or software embodying any or more of the methods or functions described herein are stored. During execution of instructions 592 by computer system 590, instructions 592 may also reside wholly or at least partially in main memory 593 and / or processing device 591, which also constitute machine-readable storage medium.

[0056] Executable instruction 592 is configured to carry out any of the embodiments described herein. For example, executable instruction 592 is configured to carry out a corresponding... Figures 1A to 1B The functionality of the host, memory package 100 and / or main control logic 108.

[0057] Although machine-readable storage medium 594 is shown as a single medium in the exemplary embodiments, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0058] Figure 6 An example of a delay path 670 according to several embodiments of the present disclosure is described. The delay path 670 includes an input 676 and an output 678. The input and output can be at any part of the command path. Between the input and output are three delay blocks 672-1, 672-2, and 672-3. The delay path 670 also includes a delay trimming input 680. The delay trimming input 680 represents a latched fuse state used to select the amount of delay in the command path. The delay trimming input 680 can select or activate any combination of delay blocks 672 via selector blocks 674-1, 672-2, and 674-3. The delay trimming input 680 is described as being connected to three different delay selector blocks 674-1, 674-2, and 671-3, and any combination thereof can be selected using the delay trimming input 680 to change the total delay applied between input 676 and output 678. As illustrated, eight different individual delays can be selected using the three different delay states 674. The implementation is not limited to three delay states, as other numbers of delay states are possible.

[0059] By way of example, delay block 672 can represent an inverter added in series to delay the signal; however, the embodiment is not limited to this example. Delay trimming input 680 can activate selector block 674, which can be multiplexed with delay block 672 to effectively create an addressable or selectable variable delay path between input 676 and output 678.

[0060] Although specific embodiments have been described and illustrated herein, those skilled in the art will understand that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of this disclosure. It should be understood that the foregoing description has been carried out in an illustrative rather than restrictive manner. Those skilled in the art will understand, upon reviewing the foregoing description, combinations of the foregoing embodiments and other embodiments not explicitly described herein. The scope of the various embodiments of this disclosure includes other applications using the above structures and methods. Therefore, the scope of the various embodiments of this disclosure should be determined with reference to the appended claims, together with the full scope of the equivalents granted thereto.

[0061] In the foregoing detailed embodiments, various features are grouped together in a single embodiment for the purpose of simplifying this disclosure. This approach of the disclosure should not be construed as reflecting an intention that the disclosed embodiments must use more features than expressly stated in each claim. Rather, as reflected in the appended claims, the subject matter of the invention exists in fewer than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is an independent, separate embodiment.

Claims

1. An apparatus comprising: Multiple auxiliary memory dies (106-1, 106-2, 106-N, 206), each containing: Corresponding memory arrays (118-1, 118-2, 118-N); Corresponding fuse arrays (134-1, 134-2, 134-N, 234-1, 234-2, 234-N); and The corresponding trimming circuit system (135-1, 135-2, 135-N, 235-1, 235-2, 235-N) is coupled to the corresponding fuse array and the corresponding memory array; and A primary die (104, 204) coupled to the plurality of secondary memory dies, the primary die containing control logic (108) configured to distribute commands to the plurality of secondary memory dies; Each corresponding fuse array is programmed to have a different corresponding delay state; Each corresponding trimming circuit system is configured such that: Latch the different corresponding delay states from the respective fuse arrays; and Depending on the different corresponding delay states, the command is executed on the corresponding auxiliary memory die with the delay.

2. The device of claim 1, wherein the primary die further comprises a memory array (118-0), a fuse array (134-0), and a trimming circuitry system (135-0) coupled to the fuse array; and The fuse array of the primary die is programmed to have a delay state different from the delay state of the corresponding fuse array of the auxiliary memory die; and The trimming circuitry system of the primary die is configured to: The delay state of the fuse array storing the main die; and The command to the primary die is delayed in a manner different from that of each of the plurality of auxiliary memory dies.

3. The device of claim 1, wherein the commands include full die commands and die-specific commands; and The control logic of the primary die is configured to distribute the full die command to the plurality of secondary memory dies and address the die-specific command to an individual secondary memory die.

4. The device of claim 1, wherein the control logic of the primary die is configured to distribute all commands to the plurality of secondary memory dies.

5. The device of claim 1, further comprising an additional auxiliary memory die coupled to the primary die; The additional auxiliary memory die includes a memory array, a fuse array, and a trimming circuit system coupled to the memory array and the fuse array; The fuse array of the additional auxiliary memory die is not programmed to have a delayed state; and The additional auxiliary memory die is configured to execute the command without delay.

6. The device of claim 1, wherein the primary die is coupled to the plurality of auxiliary memory dies via a through-silicon via (TSV) (232); and The device further includes: Intermediate layer (228), which is coupled to the main die; and A controller (291) is coupled to the intermediary layer.

7. An apparatus comprising: Multiple auxiliary memory dies (106-1, 106-2, 106-N), each containing: The corresponding local control logic (116-1, 116-2, 116-N); and The corresponding memory arrays (118-1, 118-2, 118-N) are coupled to the corresponding local control logic; and The main die (104, 204), coupled to the plurality of auxiliary memory dies, the main die comprising: A fuse array (134), programmed to have different corresponding delay states for each of the plurality of auxiliary memory dies; and The circuit system (135) is modified and configured as follows: Latch the different corresponding delay states from the fuse array; and Depending on the different corresponding delay states, the delay will distribute the full die command to the auxiliary memory die.

8. The device of claim 7, wherein the primary die further comprises primary control logic (108) coupled to the fuse array, the trimming circuit system, and the plurality of auxiliary memory dies; and The primary control logic is configured to distribute the full die command to the plurality of auxiliary memory dies via the trimming circuitry system.

9. The device of claim 8, wherein the primary die includes a host interface; and The main control logic is coupled to the host interface and configured to receive commands from the host interface.

10. The device of claim 8, wherein the main control logic is configured to generate the command.

11. The device of claim 7, wherein the primary die comprises a plurality of memory arrays (118-0) coupled to the local control logic; and Each of the plurality of auxiliary memory dies comprises a plurality of memory arrays (118-1, 118-2, 118-N) coupled to the respective local control logic (116-1, 116-2, 116-N).

12. A method comprising: Manufacturing (450) multiple main wafers; (452) Fabricate a plurality of auxiliary memory dies, each of which includes a corresponding fuse array; Couple (454) a subset of the plurality of auxiliary memory dies to a specific primary die; and The respective fuse arrays of the subset of the plurality of auxiliary memory dies are programmed (456) to have a corresponding delay state for each of the subsets of the plurality of auxiliary memory dies from the particular primary die.

13. The method of claim 12, further comprising fabricating a corresponding fuse array on the particular primary die; and The fuse array on the particular primary die is programmed to have a delay state that is different from the corresponding delay state for each of the subsets of the plurality of auxiliary memory dies.

14. The method of claim 12, wherein programming the respective fuse array comprises changing the conductivity state of at least one element of the respective fuse array.

15. The method of claim 12, wherein the subset of the particular primary die and the plurality of auxiliary memory dies constitutes a memory package; and Programming the corresponding fuse array includes programming the corresponding fuse array before shipping the memory package.

16. The method of claim 15, further comprising manufacturing an additional memory package by coupling different subsets of the plurality of auxiliary memory dies to different primary dies.

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