Memory sub-system for monitoring mixed mode blocks

Abstract

A device may include a block programmable erase count (PEC) component. The block PEC component can monitor the number of programmable erase counts (PECs) for each specific type of block in a non-volatile memory array. The block PEC component can further determine, based on the number of PECs, which block of the superblock will be written next to host data. The block PEC component can further write the host data to the determined block.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to memory subsystems for monitoring mixed-mode blocks. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] Embodiments of this disclosure provide an apparatus for monitoring mixed-mode blocks, comprising: a block program erase count (PEC) component configured to perform operations including: monitoring the number of program erase counts (PECs) for each specific type of block in a superblock for a non-volatile memory array; determining, based on the number of PECs, which block of the superblock should be written next; and writing the host data to the determined block.

[0004] Another embodiment of this disclosure provides a method for monitoring mixed-mode blocks, comprising: monitoring the number of program erase counts (PECs) of a plurality of blocks of a non-volatile memory array, wherein the plurality of blocks include: a portion of a single-level cell (SLC) block; a portion of a three-level cell (TLC) block; and a portion of a four-level cell (QLC) block; determining, based on the number of PECs, which of the plurality of blocks should be written next to host data; and writing the host data to the determined block.

[0005] Another embodiment of this disclosure provides an apparatus for monitoring mixed-mode blocks, comprising: a memory device including a plurality of memory blocks; and a processing means coupled to the memory device, the processing means performing operations including: monitoring the number of program erase counts (PECs) of a plurality of blocks of a non-volatile memory array, wherein the plurality of blocks include: a portion of a single-level cell (SLC) block; a portion of a three-level cell (TLC) block; and a portion of a four-level cell (QLC) block; determining one of the types of blocks into which a portion of a block, a TLC, or a QLC block will be written from host data received from a host; determining which block of a type of block will be written next based on the number of PECs of a portion of a block in a block of a type; and writing the host data into the determined block. Attached Figure Description

[0006] This disclosure will be more fully understood from the embodiments given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1 An example computing system including a memory subsystem is shown according to some embodiments of the present disclosure.

[0008] Figure 2 Examples of non-volatile memory arrays for monitoring mixed-mode blocks are shown according to some embodiments of the present disclosure.

[0009] Figure 3 An example flowchart of a monitoring hybrid mode block is shown, according to some embodiments of the present disclosure.

[0010] Figure 4 An example flowchart of a monitoring hybrid mode block is shown, according to some embodiments of the present disclosure.

[0011] Figure 5 An example method for monitoring a mixed-mode block is shown according to an embodiment of the present disclosure.

[0012] Figure 6 This is a block diagram of an example computer system in which embodiments of this disclosure may operate. Detailed Implementation

[0013] This disclosure pertains to media management operations for monitoring hybrid-mode blocks associated with a memory subsystem, and more specifically, to a memory subsystem including a block program erase count (PEC) component. The memory subsystem can be a storage device, a memory module, or a hybrid of a storage device and a memory module. An example of a memory subsystem is a storage system, such as a solid-state drive (SSD). The following description, in conjunction with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a "memory device" for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0014] Memory devices can be non-volatile memory devices. An example of a non-volatile memory device is a NAND flash memory device (also known as flash memory). The following section combines... Figure 1Other examples of non-volatile memory devices are described below. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Hereinafter, a block refers to a unit of memory device used to store data and may contain groups of memory cells, groups of word lines, word lines, or individual memory cells. For some memory devices, a block (also referred to below as a “memory block”) is the smallest erasable area. Pages cannot be erased individually; only the entire block can be erased.

[0015] Each memory device may contain one or more arrays of memory cells. Depending on the cell type, cells can be written to store one or more bits of binary information and have various logical states associated with the number of bits being stored. Logical states can be represented by binary values ​​such as "0" and "1" or combinations of these values. Various types of cells exist, such as single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC). For example, an SLC can store one bit of information and has two logical states.

[0016] Some NAND memory devices employ a floating gate architecture, where memory access is controlled based on the relative voltage variation between the bit lines and word lines. Other examples of NAND memory devices may employ an alternative gate architecture that may include a word line layout, which allows for the trapping of charges corresponding to data values ​​within the memory cell based on the properties of the materials used to construct the word lines.

[0017] The memory subsystem can use cache blocks to write host data for improved performance. In some instances, the cache blocks used for host data can be hybrid blocks. These hybrid blocks can be blocks that will be used in single-level cell (SLC), three-level cell (TLC), or four-level cell (QLC) modes. This means that while a particular block is currently being used as an SLC block, it can subsequently be used as a TLC or QLC block. When the host instructs the writing of additional data, the memory subsystem firmware can select a free block (e.g., a block that has not yet been written to or does not contain data that needs to be maintained or preserved). Several factors can help in selecting the next block to write data to. These factors may include, for example, wear leveling rules, block availability, block type, available idle time, program / erase count (PEC), etc.

[0018] Each block of memory in the memory subsystem may contain its own statistics regarding block usage. For example, a block statistic may include a PEC variable. This PEC variable monitors the number of program / erase (PE) cycles performed on a particular block. The PEC count may be incremented by one (1) for each erase operation performed on the block, regardless of whether the block is erased in SLC, TLC, or QLC mode. In some prior methods, it may be assumed that the wear ratio is 1:1, meaning that one (1) SLC erase operation is equal to one (1) TLC erase operation and equal to one (1) QLC erase operation performed on the block. The capacity to cycle blocks may be based on the minimum cycle capacity (e.g., based on SLC cycles for both TLC and QLC systems).

[0019] In some instances, memory subsystem usage can vary depending on the type of blocks used. For example, some uses may rely more on SLC cache performance, while others may prefer the stability of TLC caches. Different uses can result in a mix of SLC, TLC, and / or QLC block usage. The percentage of each type of block used can have a significant impact on block reliability. As an example, using a larger percentage of SLC mode blocks can more quickly degrade cell endurance and reliability compared to using TLC and / or QLC mode blocks. To ensure a threshold level of quality for block usage, the memory subsystem can be configured to operate in a worst-case scenario approach assuming 100% SLC utilization to avoid the possibility of the memory subsystem adapting to this usage if 100% SLC utilization is reached under any circumstances.

[0020] While maintaining minimum performance levels, this can unnecessarily stress the memory subsystem operation and reduce system performance because the memory subsystem uses less looping capability than it could otherwise achieve. In previous methods, which typically only monitor the PEC loop count of blocks rather than which type of block the PEC count is performed, it is impossible to determine the number of PEC loops performed for each type of block. In other words, in a specific number of PEC loops performed on a memory block, the memory subsystem does not know the number of loops performed for each SLC mode block, each TLC mode block, and each QLC mode block.

[0021] The aspects of this disclosure address the above and other shortcomings by monitoring which type of mixed-mode block (e.g., which type among SLC, TLC, and QLC mode blocks) has a specific PEC count. In this method, the PEC count of a specific type of block is incremented by one (1) whenever a block of that type is written to (e.g., programmed) or erased. For example, when an SLC block is written to or erased, the PEC count of the SLC block is incremented by one (1), when a TLC block is written to or erased, the PEC count of the TLC block is incremented, and so on. This allows for two different methods for determining the next block of host data to be written. A first method may involve determining the next block with the lowest PEC count for the type of block, as will be discussed below. Figure 3 Further description. The second method may include determining the next block with the lowest PEC ratio, such as combining... Figure 4 Further description.

[0022] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing power.

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0026] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0027] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple independent communication connections, and / or combinations of communication connections.

[0028] Memory devices 130 and 140 may include various combinations of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0030] Each of the memory devices 130 and 140 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), stores one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), store multiple bits per cell. In some embodiments, each memory device 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0031] Although a non-volatile memory assembly, such as a three-dimensional cross-point array of non-volatile memory cells and NAND-type memories (e.g., 2D NAND, 3D NAND), is described, memory device 130 may be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0034] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media locations) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access memory device 130 and / or memory device 140.

[0037] In some embodiments, memory device 130 includes a local media controller 135 that operates together with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] Memory subsystem 110 includes a block PEC component 113 (or, for simplicity, a “MM superblock component”), which is configured to schedule and / or perform operations to monitor mixed-mode blocks and determine the next block to write host data, and can do so using various components, data paths, and / or interfaces of memory subsystem 110. Block PEC component 113 may include various circuitry to facilitate superblock selection and control of data storage in memory cells of memory devices 130, 140. For example, block PEC component 113 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry or software and / or firmware, which allows block PEC component 113 to schedule and / or perform data storage operations related to monitoring mixed-mode blocks and determining the next block to write data, and to communicate with various components, data paths, and / or interfaces of memory subsystem 110.

[0039] Block PEC component 113 is communicatively coupled to memory devices 130, 140, and has access to the internal data paths of memory devices 130, 140, memory subsystem 110, and / or interfaces of memory subsystem 110 to perform the operations described herein and / or transfer stored data to additional elements of memory subsystem 110. In some embodiments, the operations performed by block PEC component 113 may be performed during the initialization or pre-initialization phase of data transfer within memory subsystem 110 and / or memory subsystem controller 115.

[0040] In some embodiments, the memory subsystem controller 115 includes at least a portion of the block PEC component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the block PEC component 113 is part of the host system 110 (not shown), an application, or an operating system.

[0041] According to some embodiments of this disclosure Figure 1 The memory devices 130 and 140 may comprise multiple physical blocks. For example, memory devices 130 and 140 may comprise NAND flash memory arrays comprising multiple physical blocks. However, embodiments of this disclosure are not limited to a particular type of memory or memory array. For example, the memory array may be a DRAM array, an RRAM array, or a PCRAM array, as well as other types of memory arrays. Furthermore, the memory array may be located on a specific semiconductor die along with various peripheral circuitry systems associated with its operation.

[0042] The memory cells of the memory array can be hybrid cells operable as SLC and / or XLC (e.g., extra-level cells, which can refer to cells that can operate at levels greater than SLC, are also called non-SLC mode cells, where three-level cells (TLC) and four-level cells (QLC) are non-SLC mode cells). The number of physical blocks in the memory array can be 128, 512, or 1,024 blocks, but embodiments are not limited to specific multiples of 128 or any specific number of physical blocks in the memory array. Furthermore, different portions of the memory can act as dynamic SLC caches for media management operations (e.g., garbage collection). For example, the size of different portions of the memory can dynamically increase and / or decrease as the demand for memory increases and / or decreases, with garbage collection more effectively addressing these demands.

[0043] Each physical block of the memory array may contain multiple physical rows of memory cells coupled to access lines (e.g., word lines). The number of rows (e.g., word lines) in each physical block may be 32, but embodiments are not limited to a specific number of rows per physical block. Furthermore, memory cells may be coupled to sensing lines (e.g., data lines and / or digital lines).

[0044] Each row may contain multiple pages (e.g., physical pages) of memory cells. A physical page refers to a programmed and / or sensed cell (e.g., multiple memory cells programmed and / or sensed together as a functional group). Each row may include one physical page of memory cells. However, embodiments of this disclosure are not limited thereto. For example, in several embodiments, each row may include multiple physical pages of memory cells (e.g., one or more even-numbered memory cell pages coupled to even-numbered bit lines, and one or more odd-numbered memory cell pages coupled to odd-numbered bit lines). Additionally, for embodiments including XLC, the physical pages of memory cells may store multiple pages of data (e.g., logical pages), such as upper data pages and lower data pages, wherein each cell stores one or more bits toward the upper data page and one or more bits toward the lower data page in the physical page.

[0045] In a non-limiting example, the device (e.g., computing system 100) may include a memory subsystem block PEC component 113. The memory subsystem block PEC component 113 may reside on a memory subsystem 110. As used herein, the term "resides on" means that something is physically located on a particular component. For example, "resides on memory subsystem 110" means that the hardware circuitry including the memory subsystem block PEC component 113 is physically located on memory subsystem 110. The term "resides on" may be used interchangeably with other terms such as "deployed on" or "located on," as mentioned herein.

[0046] The memory subsystem block PEC component 113 can be configured to monitor hybrid mode blocks. The memory subsystem block PEC component 113 can be configured based on the monitored PEC of each of a plurality of hybrid mode blocks, in conjunction with the following... Figures 3 to 4 Other parameters described determine which part of the host data will be written next.

[0047] Figure 2 A diagram illustrating a block PEC component 213 and a memory array 202 having physical blocks according to some embodiments of the present disclosure. The block PEC component 213 (which may be similar to...) Figure 1 The block PEC component 113 in the memory array 202 can be coupled to the memory array 202. For example, the memory array 202 can represent... Figure 1 The memory array 202 is a non-volatile memory device 130 / 140. The memory array 202 can be, for example, a NAND flash memory array. As an additional example, the memory array 202 can be an SCM array, such as a three-dimensional cross-point (3D cross-point) memory array, a ferroelectric RAM (FRAM) array, or a variable resistance memory array, such as a PCRAM, RRAM, or a spin torque transfer (STT) array, etc. Furthermore, although... Figure 2 Not shown, but the memory array 202 may be located on a specific semiconductor die along with various peripheral circuitry systems associated with its operation.

[0048] like Figure 2 As shown, the memory array 202 has multiple physical blocks 262-1 (BLOCK 1), 262-2 (BLOCK 2), ..., 262-B (BLOCKB) of memory cells. The memory cells can be programmed and pruned using various time-based methods. The multiple physical blocks 262 of the memory cells may be contained within a memory cell plane, and the multiple planes of the memory cells may be contained on a die. For example, in... Figure 2 In the example shown, each physical block 262 can be a portion of a single die. Figure 2 A portion of the memory array 202 shown may be a die of a memory cell and / or a logic cell.

[0049] like Figure 2 As shown, each physical block 262 contains multiple physical rows (e.g., rows 258-1, 258-2, ..., 258-R) of memory cells coupled to access lines (e.g., word lines). Furthermore, although... Figure 2Not shown, but memory cells may be coupled to sensing lines (e.g., data lines and / or digital lines). As those skilled in the art will appreciate, each row 258 may contain multiple memory cell pages (e.g., physical pages). A physical page refers to a cell that is programmed and / or sensed (e.g., multiple memory cells programmed and / or sensed together as a functional group). Figure 2 In the embodiments shown, each row 258 includes a physical page of a memory cell. However, embodiments of this disclosure are not limited thereto. For example, in embodiments, each row may include multiple physical pages of memory cells (e.g., one or more even-numbered memory cell pages coupled to even-numbered bit lines, and one or more odd-numbered memory cell pages coupled to odd-numbered bit lines). Additionally, for embodiments containing multi-level cells, the physical pages of memory cells may store multiple data logical pages (e.g., upper data pages and lower data pages, wherein each cell in a physical page stores one or more bits toward the upper data page and one or more bits toward the lower data page).

[0050] like Figure 2 As shown, row 258 of the memory cell may include multiple physical sectors 260-1, 260-2, ..., 260-S (e.g., subsets of the memory cell). Each physical sector 260 of the cell may store multiple logical sectors of data. Additionally, each logical sector of data may correspond to a portion of a specific data page. As an example, one logical sector of data stored in a specific physical sector may correspond to a logical sector corresponding to a data page, and another logical sector of data stored in a specific physical sector may correspond to another data page. Each physical sector 260 may store system data, user data, and / or overhead data, such as error correction code (ECC) data, LBA data, and metadata.

[0051] Figure 3 A flowchart 305 illustrates an example of a monitoring mixed-mode block associated with some embodiments of this disclosure. At operation 331, the memory subsystem may determine a new free block to be selected for storing received host data. The new free block may be a block that does not store data that needs to be saved. For example, if a free block has not yet been written to, the data in the free block is no longer valid, or the data in the free block is no longer needed by the memory subsystem and can be reallocated for writing additional data.

[0052] At operations 333-1, 333-2, or 333-3, the block PEC component (e.g., respectively) Figure 1The block PEC component 113 or 213 in step 2 can determine whether host data should be written to an SLC mode block (333-1), a TLC mode block (333-2), or a QLC mode block (333-3). As an example, the type of block to which host data should be written can be determined based on the host data itself. Alternatively, the type of block to which host data should be written can be determined based on the current PEC count of each type of block in the memory subsystem.

[0053] At operation 335-1, in response to determining that the new free block should be an SLC mode block, the PEC component can determine which SLC block in the SLC block pool has the lowest SLC PEC value. At operation 335-2, in response to determining that the new free block should be a TLC mode block, the PEC component can determine which TLC block in the TLC block pool has the lowest TLC PEC value. At operation 335-3, in response to determining that the new free block should be a QLC mode block, the PEC component can determine which QLC block in the QLC block pool has the lowest QLC PEC value.

[0054] At operation 337, the PEC component determines which free block to select from the free block pool. In one embodiment, the PEC component selects the free block with the lowest PEC value for the specific type of block. For example, in response to the need for an SLC block, the free SLC block with the lowest PEC value is selected. At operation 339, the determined block selected for writing host data can be returned by the PEC component for use in writing host data. Host data can be written to the determined block.

[0055] Figure 4 An example flowchart 407 is shown, illustrating an example of a monitoring mixed-mode block according to some embodiments of this disclosure. At operation 441, the memory subsystem may determine a new free block to be selected for storing received host data. The new free block may be a block that does not store data that needs to be saved. For example, if a free block has not yet been written to, the data in the free block is no longer valid, or the data in the free block is no longer needed by the memory subsystem and can be reallocated for writing additional data.

[0056] At operations 433-1, 433-2, or 433-3, the block PEC component (e.g., respectively) Figure 1 The block PEC component 113 or 213 in step 2 can determine whether host data should be written to an SLC mode block (433-1), a TLC mode block (433-2), or a QLC mode block (433-3). As an example, the type of block to which host data should be written can be determined based on the host data itself. Alternatively, the type of block to which host data should be written can be determined based on the current PEC count of each type of block in the memory subsystem.

[0057] At operation 443-1, in response to determining that a new free block should be an SLC mode block, the PEC component can determine the ratio of SLC PEC to the total PEC. For example, the SLC PEC of a specific block can be compared to the total PEC (SLC PEC + TLC PEC + QLC PEC) of the free block pool. The total PEC can be the sum of all PECs for each block type, and the ratio can be the SLC PEC of the specific block to the total PEC (SLC PEC / (SLC PEC + TLC PEC + QLC PEC)). At operation 445-1, the PEC component can determine which SLC block in the SLC block pool has the lowest SLC PEC ratio.

[0058] At operation 443-2, in response to determining that the new free block should be a TLC mode block, the PEC component can determine the ratio of TLC PEC to the total PEC. For example, the TLC PEC of a specific block can be compared to the total PEC (SLC PEC + TLC PEC + QLC PEC) of the free block pool. The total PEC can be the sum of all PECs for each block type, and the ratio can be the TLC PEC of the specific block to the total PEC (TLC PEC / (SLC PEC + TLC PEC + QLC PEC)). At operation 445-2, the PEC component can determine which TLC block in the TLC block pool has the lowest TLC PEC ratio.

[0059] At operation 443-3, in response to determining that the new free block should be a QLC mode block, the PEC component can determine the ratio of QLC PEC to the total PEC. For example, the QLC PEC of a specific block can be compared to the total PEC (SLC PEC + TLC PEC + QLC PEC) of the free block pool. The total PEC can be the sum of all PECs for each block type, and the ratio can be the QLC PEC of the specific block to the total PEC (QLC PEC / (SLC PEC + TLC PEC + QLC PEC)). At operation 445-3, the PEC component can determine which QLC block in the QLC block pool has the lowest QLC PEC ratio.

[0060] At operation 447, the PEC component determines which free block to select from the free block pool. In one embodiment, the PEC component selects the free block with the lowest PEC ratio for the specific type of block. For example, in response to the need for an SLC block, the free SLC block with the lowest PEC ratio is selected. At operation 449, the determined block selected for writing host data can be returned by the PEC component for use in writing host data. Host data can be written to the determined block.

[0061] Figure 5This is a flowchart corresponding to a method 550 for performing memory subsystem operations to monitor a hybrid mode block, according to some embodiments of this disclosure. The media management superblock component may be similar to... Figure 1 The media management threshold component in the process. Method 550 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 550 is performed by... Figure 1 The block PEC component 113 executes. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all operations are required in every embodiment. Other process flows are possible.

[0062] At operation 552, the number of Program Erase Counts (PECs) of multiple blocks in a non-volatile memory array can be monitored. The method may further include incrementing the number of PECs associated with a type of block to which host data is written by a PEC value of one. The multiple blocks may comprise a portion of a Single Level Cell (SLC) block, a portion of a Three Level Cell (TLC) block, and a portion of a Four Level Cell (QLC) block. The method may further include determining which type of block the host data will be written to. The method may further include, based on the determination of which type of block the host data will be written to, determining which block of the determined type has the lowest PEC for a portion of the determined type of block. Method 550 may further include determining a minimum PEC ratio by determining the ratio of the PEC count of a particular type of block to the sum of the PEC counts of portions of SLC, TLC, and QLC blocks. In a non-volatile memory array, portions of SLC, TLC, and QLC blocks may constitute a free block pool.

[0063] At operation 554, the number of PECs can be used to determine which of the multiple blocks the host data will be written to next. For example, the number of PECs can be used to determine the block of a specific block type that has the lowest PEC for that particular type of block. At operation 556, the host data can be written to the determined block. Writing host data may involve writing host data to the block with the lowest PEC. Host data may then be written to the determined block until the determined block has reached its capacity for writing data, or until a different type of block is determined to be written based on the host.

[0064] Figure 6 This is a block diagram of an example computer system 661 in which embodiments of the present disclosure may operate. For example, Figure 6An example machine of computer system 661 is shown, wherein a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 661 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 The operation of block PEC component 113. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment within the capacity of a server or client machine in a client-server network environment.

[0065] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is shown, it should also be understood that the term "machine" includes any collection of machines that individually or collectively execute (one or more) sets of instructions to perform any one or more of the methods discussed herein.

[0066] Example computer system 661 includes processing devices 602 that communicate with each other via bus 603, main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage system 618.

[0067] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 661 may further include a network interface device 608 for communication on network 611.

[0068] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) on which one or more instruction sets 626 or software embodying any one or more of the methods or functions described herein are stored. Instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 661, which also constitute the machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0069] In one embodiment, instruction 626 includes implementing a component corresponding to a media management superblock (e.g., Figure 1 The functional instructions of the block PEC component 113). Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions that can be executed by a machine and causing a machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0070] Some parts of the previously described algorithms and symbolic representations of operations on data bits in computer memory have been presented. These algorithms are described and represented in a way that those skilled in the art of data processing can most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and generally are, considered as a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical manipulation of a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for common use, it has proven convenient sometimes to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0071] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of a computer system into other data representing physical quantities similarly represented in the memory or registers or other such information storage systems of a computer system.

[0072] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including solid-state drives (SSDs), hard disk drives (HDDs), floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0073] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the teachings and procedures herein, or it may prove convenient to construct more specialized devices to execute the methods. Structures for various such systems will be presented as described below. Furthermore, embodiments of this disclosure are described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0074] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0075] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A device for monitoring mixed-mode blocks, comprising: The block programming erase counter (PEC) component is used to perform operations including the following: For each of the multiple free blocks, maintain multiple PECs corresponding to different block types. For each of the different corresponding types of blocks, determine the corresponding total PEC for the plurality of free blocks, wherein the corresponding total PEC is the sum of the PECs corresponding to each of the different corresponding types of blocks in all the plurality of free blocks; Determine the specific type of block to be written to the host; For each of the plurality of free blocks, a ratio is determined between the PEC corresponding to the corresponding free block and the total corresponding PEC of the plurality of free blocks to generate a corresponding ratio for the corresponding free block, wherein the corresponding free block is a block of a specific type to be written to the host data; Identify the free block with the lowest corresponding ratio among a plurality of free blocks; and The host data is written to the free block that has been determined to have the lowest corresponding ratio.

2. The device according to claim 1, wherein the type of block includes one of a single-level unit (SLC) block, a three-level unit (TLC) block, and a four-level unit (QLC) block.

3. The device of claim 2, wherein the type of block to be written to the host data includes an SLC block, a TLC block, or a QLC block.

4. The device according to claim 1, wherein the corresponding total PEC is determined for each of the plurality of free blocks.

5. The device of claim 4, wherein the operations performed by the block PEC component further include: After the host data is written, the PEC of the determined block is incremented by one.

6. The device of claim 1, wherein the plurality of free blocks are located within a NAND memory array residing on a mobile computing device.

7. The device of claim 1, wherein the operations performed by the block PEC component further include: The host data is written to free blocks that have been determined to have the lowest corresponding ratio, until it is determined that different types of blocks need to be written from the host.

8. A method for monitoring mixed-mode blocks, comprising: For each of the multiple free blocks, maintain multiple PECs corresponding to different block types. For each of the different corresponding types of blocks, determine the corresponding total PEC for the plurality of free blocks, wherein the corresponding total PEC is the sum of the PECs corresponding to each of the different corresponding types of blocks in all the plurality of free blocks; Determine the specific type of block to be written to the host; For each of the plurality of free blocks, a ratio is determined between the PEC corresponding to the corresponding free block and the total corresponding PEC of the plurality of free blocks to generate a corresponding ratio for the corresponding free block, wherein the corresponding free block is a block of a specific type to be written to the host data; Identify the free block with the lowest corresponding ratio among a plurality of free blocks; and The host data is written to the free block that has been determined to have the lowest corresponding ratio.

9. The method of claim 8, further comprising: The host data is written to free blocks that have been determined to have the lowest corresponding ratio, until it is determined that different types of blocks need to be written from the host.

10. The method of claim 8, wherein the type of block to be written to the host data includes an SLC block, a TLC block, or a QLC block.

11. The method of claim 10, wherein the type of block to be written to the host data includes an SLC block, a TLC block, or a QLC block.

12. The method of claim 8, further comprising, after writing the host data, incrementing the PEC of the determined block by a PEC value of one.

13. The method of claim 8, wherein the plurality of free blocks are located within a NAND memory array residing on a mobile computing device.

14. The method of claim 8, wherein the corresponding total PEC is determined for each of the plurality of free blocks.

15. An apparatus for monitoring mixed-mode blocks, comprising: Memory devices; as well as A processing device coupled to the memory device performs operations including the following: For each of the multiple free blocks, maintain multiple PECs corresponding to different block types. For each of the different corresponding types of blocks, determine the corresponding total PEC for the plurality of free blocks, wherein the corresponding total PEC is the sum of the PECs corresponding to each of the different corresponding types of blocks in all the plurality of free blocks; Determine the specific type of block to be written to the host; For each of the plurality of free blocks, a ratio is determined between the PEC corresponding to the corresponding free block and the total corresponding PEC of the plurality of free blocks to generate a corresponding ratio for the corresponding free block, wherein the corresponding free block is a block of a specific type to be written to the host data; Identify the free block with the lowest corresponding ratio among a plurality of free blocks; and The host data is written to the free block that has been determined to have the lowest corresponding ratio.

16. The apparatus of claim 15, wherein the processing means performs the following further operations: The host data is written to free blocks that have been determined to have the lowest corresponding ratio, until it is determined that different types of blocks need to be written from the host.

17. The device of claim 15, wherein the type of block comprises one of a single-level unit (SLC) block, a three-level unit (TLC) block, and a four-level unit (QLC) block.

18. The device of claim 15, wherein the type of block to be written to the host data includes an SLC block, a TLC block, or a QLC block.

19. The apparatus of claim 15, wherein the corresponding total PEC is determined for each of the plurality of free blocks.

20. The device of claim 17, wherein the processing means performs an operation further comprising: determining which block to write the host data to based on previous block usage history.

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