Back contact solar cell and method of manufacturing the same

Abstract

This invention relates to the field of photovoltaic technology, providing a back-junction solar cell and its fabrication method. The method includes: partially removing a first passivation layer on a first side of a silicon wafer to expose the wafer; providing an electron-carrying dopant source to the exposed area of ​​the silicon wafer and irradiating it with light to form a heavily doped region; and metallizing the heavily doped region to form a first metal grid line. This invention solves the problem in existing technologies where high-temperature doping during diffusion doping significantly reduces the silicon wafer's lifetime, affecting the photoelectric conversion efficiency of the back-junction solar cell. Because the holes generated by light irradiation in the exposed area of ​​the silicon wafer during the doping process of this invention can neutralize the electrons from the dopant source, thus generating heat and creating localized high temperatures in the exposed area, the entire silicon wafer does not need to undergo high temperatures, reducing the impact on the wafer's lifetime and ensuring the photoelectric conversion efficiency of the back-junction solar cell.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and in particular to a back-junction solar cell and its fabrication method. Background Technology

[0002] Solar cells can generate electricity using sunlight. There are many types of solar cells available today. Among them, back-junction solar cells are a type of solar cell with high efficiency potential. For example, P-type back-junction solar cells can achieve a photoelectric conversion efficiency of over 24.7%.

[0003] For back-junction solar cells, a certain doping concentration is required to form an ohmic contact in the metallization region on the front side. Therefore, local diffusion doping of the metallization region is necessary. However, the silicon wafer itself has limited characteristics. When it undergoes a high-temperature doping process, the silicon wafer's lifespan will be greatly reduced, which in turn affects the photoelectric conversion efficiency of the back-junction solar cell. Summary of the Invention

[0004] This invention provides a back-junction solar cell and its fabrication method, which solves the defect in the prior art where the silicon wafer lifespan is greatly reduced due to the high-temperature doping process during diffusion doping, thus affecting the photoelectric conversion efficiency of the back-junction solar cell. It achieves localized high-temperature doping, reduces the impact on the silicon wafer lifespan, and ensures the photoelectric conversion efficiency of the back-junction solar cell.

[0005] This invention provides a method for fabricating a back-junction solar cell, comprising:

[0006] Partially remove the first passivation layer on the first side of the silicon wafer to expose the silicon wafer;

[0007] An electron-containing dopant source is provided to the exposed area of ​​the silicon wafer and then illuminated to form a heavily doped region;

[0008] Metallization is performed in the heavily doped region to form a first metal gate line.

[0009] According to the back-junction solar cell fabrication method provided by the present invention, providing an electron-containing dopant source to the exposed region of the silicon wafer includes:

[0010] The sol containing the doped source is processed by an electron generating device, and the sol is sprayed onto the exposed area of ​​the silicon wafer using a nozzle.

[0011] According to the back-junction solar cell fabrication method provided by the present invention, the solar irradiance during illumination is at least 10 × 1 kW / m².

[0012] According to the back-junction solar cell fabrication method provided by the present invention, the step of partially removing the first passivation layer on the first side of the silicon wafer to expose the silicon wafer includes:

[0013] The first passivation layer on the first side of the silicon wafer is partially ablated by laser to expose the silicon wafer.

[0014] According to the back junction solar cell fabrication method provided by the present invention, the width of the heavily doped region is smaller than the width of the first metal grid line, and / or the width of the exposed region is smaller than the width of the first metal grid line.

[0015] According to the back junction solar cell fabrication method provided by the present invention, the width of the first metal grid line is 5-30 micrometers, and / or the width of the heavily doped region is 4-20 micrometers, and / or the width of the exposed region is 4-20 micrometers.

[0016] According to the back junction solar cell fabrication method provided by the present invention, the first metal grid line is a silver grid line.

[0017] According to the back junction solar cell fabrication method provided by the present invention, the first metal grid line is a silver grid line doped with aluminum, and the ratio of silver to aluminum in the first metal grid line is greater than or equal to 85:1.

[0018] The method for fabricating a back-junction solar cell according to the present invention further includes:

[0019] A tunneling oxide layer, a doped polysilicon layer, a second passivation layer, and a second metal gate line are sequentially formed on the second side of the silicon wafer.

[0020] The present invention also provides a back-junction solar cell, which is prepared by any of the back-junction solar cell preparation methods described above.

[0021] The back-junction solar cell fabrication method provided by this invention involves partially removing the first passivation layer on the first side of a silicon wafer to expose the wafer, and then providing an electron-carrying dopant source to the exposed area of ​​the wafer and irradiating it to form a heavily doped region. This achieves localized doping. During the doping process, holes generated in the exposed area of ​​the silicon wafer due to irradiation can neutralize electrons from the dopant source, thereby generating heat and creating localized high temperatures in the exposed area. This eliminates the need for the entire silicon wafer to experience high temperatures, reducing the impact on the wafer's lifespan and ensuring the photoelectric conversion efficiency of the back-junction solar cell. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a schematic flowchart of the back-junction solar cell fabrication method provided by the present invention;

[0024] Figure 2 This is a schematic diagram of the back junction solar cell provided by the present invention;

[0025] Figure label:

[0026] 201: Silicon wafer; 202: First passivation layer; 203: First metal gate line;

[0027] 204: Tunneling oxide layer; 205: Doped polysilicon layer; 206: Second passivation layer;

[0028] 207: Second metal gate line; 208: Heavily doped region. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0030] Back-junction solar cells have good conversion efficiency and have been widely used. Taking a back-junction solar cell based on a P-type silicon wafer as an example, it can achieve a photoelectric conversion efficiency of over 24.7%. At the same time, due to the use of a P-type silicon wafer, its manufacturing cost is significantly lower than that of an N-tunnel oxide passivated contact (TOPCon) cell. In this back-junction solar cell, a tunnel oxide layer (e.g., silicon dioxide layer) and an N-type polycrystalline silicon layer are formed on the back side of the silicon wafer to obtain a passivated contact structure. This reduces recombination and also plays a role in separating photogenerated carriers. Meanwhile, the front side of the silicon wafer can be freed from a diffused emitter, which greatly reduces doping-related Auger recombination.

[0031] For back-junction solar cells, forming ohmic contacts in the metallized region (i.e., the region forming the metal grid lines) on the front side of the silicon wafer requires a high doping concentration. Therefore, localized diffusion doping of the metallized region is necessary, such as boron doping. However, the high-temperature process of boron doping significantly reduces the minority carrier lifetime of the p-type silicon wafer, leading to a substantial increase in bulk recombination. This necessitates the use of higher-quality and lower-cost p-type silicon wafers, such as zone-melted silicon, significantly increasing costs. Furthermore, to achieve localized doping only in the metallized region, additional processes such as masking and cleaning are required, further increasing the manufacturing complexity. Various solutions offered in related technologies still face significant challenges in mass production. Most solutions utilize the properties of aluminum paste to address this issue. However, when using aluminum paste to achieve ohmic contacts, on the one hand, the poor linearity of the aluminum grid lines results in significant light-blocking losses; on the other hand, the high transmission resistance of aluminum itself leads to low photoelectric conversion efficiency.

[0032] For example, in one implementation, a burn-through aluminum paste is used on the front side of the silicon wafer. At the same time, the self-doping effect of the aluminum paste is used to form a P+ layer in the metallization region. In order to reduce the problem of high series resistance of aluminum gate lines, silver gate lines are overprinted on the aluminum gate lines to reduce the front-side transmission resistance. However, the burn-through effect of the burn-through aluminum paste is not easy to control, the ohmic contact performance is poor, aluminum oxide passivation cannot be used, and a passivation layer containing aluminum oxide cannot be achieved. In addition, the aluminum paste has poor plasticity, the aluminum gate line width is relatively wide, resulting in large light-shielding loss on the front side. The stacking of silver on aluminum causes the formation of silver-aluminum alloy, the recombination in the metallization region is extremely large, and the photoelectric conversion efficiency is reduced.

[0033] For example, in another implementation, laser grooving is used on the front side of the silicon wafer to avoid sintering, and aluminum paste is printed and sintered. At the same time, in order to reduce the problem of high series resistance of aluminum grid lines, a layer of low-temperature silver paste is printed and dried after aluminum paste sintering to solve the problems of poor aluminum paste burn-through and high aluminum paste transmission resistance. However, it requires two paste printing and sintering / drying processes, which are complex. The linearity of aluminum grid lines is still difficult to control, the light-shielding loss is large, and the low-temperature silver paste is expensive and the silver-aluminum paste has high contact resistance.

[0034] For example, in another implementation, laser grooving on the front side of the silicon wafer avoids sintering, and aluminum paste is printed and sintered. At the same time, in order to reduce the problem of high series resistance of aluminum gate lines, a transparent conductive oxide (TCO) layer is deposited after aluminum paste sintering. Silver paste is then prepared on the TCO layer to solve the problems of poor aluminum paste burn-through and high aluminum paste transmission resistance. However, it requires two paste printing and sintering / drying processes, which are complex. The TCO layer process is complex and costly. In addition, there are problems such as high cost of low-temperature silver paste, non-overlapping positions of aluminum paste and silver paste, increased optical blocking area, and large optical loss.

[0035] Therefore, this invention provides a method for fabricating a back-junction solar cell, which can optimize the fabrication process of the back-junction solar cell. The following is a detailed description... Figures 1 to 2 The present invention describes a method for fabricating a back-junction solar cell.

[0036] This embodiment provides a method for fabricating a back-junction solar cell, such as... Figure 1 As shown, it includes at least the following steps:

[0037] Step 101: Partially remove the first passivation layer on the first side of the silicon wafer to expose the silicon wafer.

[0038] Step 102: Provide an electron-containing dopant source to the exposed area of ​​the silicon wafer and irradiate it with light to form a heavily doped region.

[0039] Step 103: Metallize the heavily doped region to form a first metal gate line.

[0040] Here, the silicon wafer serves as the substrate. The silicon wafer can be p-type or n-type doped; that is, the silicon wafer in this embodiment can be a p-type wafer, but it can also be an n-type wafer. The silicon wafer includes a front side and a back side. The front side is the side that receives light, and the back side is the side that is not illuminated. The first side can be the front side, and the back side can be the second side. For example... Figure 2 As shown, the structure of a back junction solar cell may include a silicon wafer 201, a first passivation layer 202 located on the front side of the silicon wafer 201, a first metal grid line 203 that penetrates the first passivation layer 202 and contacts the front side of the silicon wafer 201, and also includes a tunneling oxide layer 204, a doped polycrystalline silicon layer 205, a second passivation layer 206, and a second metal grid line 207 that penetrates the second passivation layer 206 and contacts the doped polycrystalline silicon layer 205 located on the back side of the silicon wafer 201.

[0041] In this embodiment, the first metal gate line makes contact with the front side of the silicon wafer to form an ohmic contact. The area corresponding to the first metal gate line is a metallized region. To form an ohmic contact, the metallized region needs to be heavily doped. Since the doping methods in the prior art are not effective, this embodiment provides a new localized doping method. First, the silicon wafer undergoes pretreatment such as cleaning, polishing, and texturing. Then, a first passivation layer is formed on the first side of the silicon wafer. Next, the first passivation layer on the first side of the silicon wafer is partially removed to expose the silicon wafer, that is, to partially expose the silicon wafer. The pattern of the exposed area of ​​the silicon wafer corresponds to the pattern of the first metal gate line. Subsequently, a banding material is provided to the exposed area of ​​the silicon wafer. When an electron-doped source is introduced and illuminated, the silicon wafer, based on structures with carrier separation capabilities such as PN junctions, tunnel junctions, or high-low junctions, generates separated carriers, including holes and electrons, which drift to the front and back sides respectively. Holes drift to the front side, accumulating in the exposed areas of the silicon wafer. Since the doped source provided to these exposed areas carries electrons (with opposite charges to holes), the holes on the front side of the wafer neutralize the electrons from the doped source, generating heat and creating localized high temperatures in the exposed areas. The dopant element from the doped source then incorporates into these exposed areas, forming heavily doped regions 208. (See also...) Figure 2 In this way, local doping is achieved, and the pattern of the heavily doped region corresponds to the pattern of the first metal gate line. Based on this, metallization can be performed in the heavily doped region to form the first metal gate line. The first metal gate line contacts the heavily doped region of the silicon wafer to form an ohmic contact.

[0042] In the localized doping method provided in this embodiment, only a locally exposed area of ​​the silicon wafer experiences high temperatures, and this exposed area itself is a metallized region and is inherently prone to damage. Compared with existing doping methods, the entire silicon wafer does not need to undergo high temperatures, thus significantly reducing the impact on the wafer's lifespan and consequently reducing the impact on the photoelectric conversion efficiency of the back-junction solar cell. Furthermore, the doping method in this embodiment does not require additional processes such as masking and cleaning, making the process simpler and reducing its complexity, which overall contributes to improving the fabrication efficiency of the back-junction solar cell.

[0043] For P-type silicon wafers, the aforementioned electron-carrying dopant sources can include group III dopant elements, such as boron and gallium. For N-type silicon wafers, the aforementioned electron-carrying dopant sources can include group VA dopant elements, such as phosphorus.

[0044] In this embodiment, by partially removing the first passivation layer on the first side of the silicon wafer to expose the silicon wafer, and providing an electron-carrying dopant source to the exposed area of ​​the silicon wafer and irradiating it, a heavily doped region is formed, thus achieving localized doping. During the doping process, the holes generated in the exposed area of ​​the silicon wafer due to irradiation can neutralize the electrons in the dopant source and generate heat, thereby forming a local high temperature in the exposed area. This eliminates the need for the entire silicon wafer to undergo high temperatures, reducing the impact on the lifespan of the silicon wafer and thus ensuring the photoelectric conversion efficiency of the back junction solar cell.

[0045] In an exemplary embodiment, the provision of an electron-containing dopant source to the exposed area of ​​the silicon wafer may be specifically implemented by: processing a sol containing the dopant source through an electron generating device, and spraying the sol onto the exposed area of ​​the silicon wafer using a nozzle.

[0046] In practice, a dopant source can be added to the sol to obtain a sol with a dopant source.

[0047] The electron generating device here is used to generate electrons; for example, it could be an electron gun. A sol with a doped source can become electron-bearing by passing through this device. Of course, other methods can also be used to make the sol electron-bearing, which will not be listed here.

[0048] In this way, by automatically generating electrons through an electron generating device, the sol containing the dopant source can be quickly processed into an electron-containing sol. Then, the sol is sprayed onto the exposed area of ​​the silicon wafer using a nozzle, thereby accurately applying the electron-containing dopant source to the exposed area of ​​the silicon wafer. The doping method in this embodiment is very simple, without complex printing, drying and other processes. The electron generating device and nozzle are easy to control, which helps to improve process accuracy, simplify the process, and improve process efficiency.

[0049] In practical applications, strong light can be used for illumination to ensure that enough holes are generated in the silicon wafer and drift to the front side of the wafer. This allows enough holes to accumulate on the front side of the wafer to neutralize the electrons in the doping source band, thereby generating heat. In addition, the temperature of the strong light itself is also high. Under the combined effect, the temperature of the exposed area can meet the doping requirements.

[0050] In practice, since the non-exposed areas of the silicon wafer lack electron-carrying dopant sources (i.e., lack electrons), they cannot neutralize holes and generate heat. Therefore, even if light shines on these areas, it has no effect. Consequently, the entire front side of the silicon wafer can be illuminated, eliminating the need to individually irradiate each exposed area, making the process more convenient and simpler. In the exemplary embodiment, the solar irradiance during illumination is at least 10 × 1 kW / m². 2 Under this solar irradiance, the basic temperature requirements for doping can be met, thus ensuring the doping effect in the heavily doped region.

[0051] In an exemplary embodiment, the specific implementation of partially removing the first passivation layer on the first side of the silicon wafer to expose the silicon wafer may include: partially ablating the first passivation layer on the first side of the silicon wafer with laser to expose the silicon wafer.

[0052] Laser ablation uses a high-energy laser beam to transfer heat to the surface of a material, causing it to melt and vaporize, thereby removing the material.

[0053] In practical applications, the area to be removed from the first passivation layer is irradiated with a laser. The area to be removed from the first passivation layer is ablated by the laser, which is also called laser grooving. The exposed area of ​​the silicon wafer is the laser grooving location. Because the laser beam is precisely controlled, the local removal of the first passivation layer is more accurate. Moreover, the laser ablation method does not require printing, drying, cleaning and other processes. Removal can be achieved by laser irradiation, which further simplifies the manufacturing process.

[0054] Of course, other processes can also be used to partially remove the first passivation layer on the first side of the silicon wafer to expose the silicon wafer. For example, an etchant can be printed on the first passivation layer to partially remove the first passivation layer on the first side of the silicon wafer to expose the silicon wafer, and so on. These will not be listed here.

[0055] In an exemplary embodiment, the width of the exposed region can be smaller than the width of the first metal gate line, and the width of the heavily doped region can be smaller than the width of the first metal gate line. For example, the width of the first metal gate line is 5-30 micrometers (μm), and / or the width of the heavily doped region is 4-20 μm. The width of the exposed region is 4-20 μm. In the process of achieving localized doping, the formed heavily doped region can be narrower, and correspondingly, the laser grooving position can be narrower. Thus, the laser grooving position can be completely covered by the first metal gate line to form an ohmic contact. From this perspective, the width of the heavily doped region can be smaller than the width of the first metal gate line. In this way, a portion of the first metal gate line forms an ohmic contact with the heavily doped region, thereby effectively utilizing the laser grooving area to form as much ohmic contact area as possible, thereby reducing contact resistance. The redundant region of the first metal gate line (i.e., the region wider than the heavily doped region) will not directly contact the silicon wafer due to the obstruction of the first passivation layer, thus avoiding unnecessary recombination.

[0056] In an exemplary embodiment, the first metal gate line can be a silver gate line. In practice, silver paste can be used to print the silver gate line on the heavily doped region of the front side of the silicon wafer. Since the silver powder particles in silver paste are smaller than those in aluminum paste, they can pass smoothly through the screen during the printing process. Therefore, silver paste has excellent shaping effect, better linearity, and can achieve extremely low front-side light-shielding loss, as well as low transmission resistance and low electrical loss. Furthermore, in this embodiment, no silver-aluminum alloy is formed on the front side, eliminating the extremely high recombination current loss in the silver-aluminum contact area, and simultaneously eliminating contact resistance loss when the two metals are in contact.

[0057] The aforementioned silver grid line can be a pure silver grid line or a silver grid line doped with aluminum. The ratio of silver to aluminum in the first metal grid line is greater than or equal to 85:1, that is, silver is the main component, which can improve conductivity. A small amount of aluminum can also be added, since aluminum itself can be used as a dopant element, which can improve the ohmic contact effect while ensuring conductivity.

[0058] The materials of the first passivation layer and the second passivation layer can be set according to actual needs.

[0059] For example, the first passivation layer may include one or more of the following layers: an aluminum oxide layer, a silicon nitride layer, and a silicon oxide layer. The total number of layers can also be set according to actual needs. For example, a total number of layers greater than or equal to 2 results in better passivation. Considering that aluminum oxide has a better and more stable passivation effect on the front side, in one implementation, the first passivation layer includes at least an aluminum oxide layer. As mentioned earlier, the burn-through effect of burn-through aluminum paste is difficult to control, and the ohmic contact performance is poor. Therefore, aluminum oxide passivation cannot be used, and a passivation layer containing aluminum oxide cannot be achieved. However, in this embodiment, the first metal gate line is a silver gate line, and silver paste is used instead of aluminum paste. Therefore, a passivation layer including aluminum oxide can be deposited, improving the passivation effect.

[0060] Similarly, the second passivation layer may include one or more of the following layers: an aluminum oxide layer, a silicon nitride layer, and a silicon oxide layer. The total number of layers can also be set according to actual needs. For example, the total number of layers is greater than or equal to one, and it can be a single layer or multiple layers to meet passivation requirements. Considering that silicon nitride has a better passivation effect on the back side, in one implementation, the second passivation layer includes at least a silicon nitride layer.

[0061] It is understood that, in an exemplary embodiment, the back junction solar cell fabrication method may further include: sequentially forming a tunneling oxide layer, a doped polycrystalline silicon layer, a second passivation layer, and a second metal grid line on the second surface of the silicon wafer.

[0062] The tunneling oxide layer can be a silicon oxide layer, such as a silicon dioxide (SiO2) layer. The thickness of the tunneling oxide layer can be less than a set threshold, that is, the tunneling oxide layer is relatively thin, for example, it can be an ultrathin SiO2 layer.

[0063] The doping concentration of the polysilicon layer can be 5 × 10⁻⁶. 20 -2×10 21 Number of atoms per cubic centimeter (atoms / cm) 3 To meet doping requirements.

[0064] The second side here is the back side of the silicon wafer.

[0065] In this embodiment, a back junction solar cell can be fabricated by sequentially forming a tunneling oxide layer, a doped polycrystalline silicon layer, a second passivation layer, and a second metal grid line on the back side of a silicon wafer. The silicon wafer, the tunneling oxide layer, and the doped polycrystalline silicon layer form a passivation contact structure, which helps to reduce back recombination and also plays a role in separating photogenerated carriers.

[0066] The following section uses a P-type back-junction solar cell as an example to illustrate the preparation method of the back-junction solar cell provided by this invention in more detail.

[0067] Step 1: Cleaning and polishing.

[0068] Specifically, the P-type monocrystalline silicon wafer is cleaned in a solution of alkali and hydrogen peroxide, and then double-sided polishing is performed in a solution of alkali and appropriate additives.

[0069] Step 2: Preparation of back-side passivation contacts.

[0070] Specifically, an ultrathin silicon oxide layer, a doped polycrystalline silicon layer, and another silicon oxide layer are sequentially fabricated on the back side of the silicon wafer. The doping concentration of the doped polycrystalline silicon layer is 5 × 10⁻⁶. 20 -2×10 21 atoms / cm 3 .

[0071] Step 3: Single-sided pile fabrication.

[0072] Specifically, under the protection of the silicon oxide layer on the back of the silicon wafer, the front of the silicon wafer is texturized in an alkali and corresponding additive solution.

[0073] Step 4: Deposition of the front passivation layer.

[0074] The number of layers in the front passivation layer (i.e., the first passivation layer) is ≥2, and it must include an aluminum oxide layer.

[0075] Specifically, an aluminum oxide (AlOx) layer, a first silicon nitride (SiNx) layer, a second silicon nitride (SiNx) layer, and a silicon oxide (SiOx) layer are sequentially deposited on the front side of the silicon wafer.

[0076] Step 5: Deposition of the back passivation layer.

[0077] The back passivation layer (i.e., the second passivation layer) has at least one layer, which must include a silicon nitride layer. Specifically, an AlOx layer, a first SiNx layer, a second SiNx layer, and a SiOx layer are deposited sequentially on the back side of the silicon wafer.

[0078] Step 6: Front laser film opening.

[0079] Specifically, laser ablation is used to partially remove the passivation layer on the front side, exposing the silicon wafer. This process is known as laser delamination, and the delamination pattern corresponds to the gate line pattern. The width of the delamination pattern is 4-20 μm.

[0080] Step 7: Localized doping on the front side.

[0081] Specifically, an electron-doped source (such as boron or gallium) is applied to the exposed area on the front side of the silicon wafer, and the entire front side is irradiated with strong light to form a heavily doped region. The surface concentration of the dopant is ≥1×10⁻⁶. 16 atoms / cm 3 The junction depth is 0.1-1μm.

[0082] Step 8: Printing and drying the grid lines on the back.

[0083] Specifically, a second metal grid pattern is printed on the back passivation layer.

[0084] Step 9: Front grid line printing and drying.

[0085] Specifically, a first metal gate pattern is printed on the front passivation layer. The width of the first metal gate is 5-30 μm, which is greater than the width of the heavily doped region in step seven, and is directly above the heavily doped region.

[0086] Step 10: Sintering.

[0087] Specifically, sintering is carried out at a peak temperature of 820℃.

[0088] Step 11: Electroinjection.

[0089] Specifically, electro-injection is performed at a process temperature of 200-400℃ and an injection current of 10-20A.

[0090] The back-junction solar cell can be fabricated using the above-described method, and it offers the following advantages:

[0091] 1. First, laser ablation of the front passivation layer exposes the silicon wafer. Then, an electron-containing doping source and strong light are applied to form localized heavy doping based on the above mechanism. This eliminates the need for the entire silicon wafer to undergo high temperatures, thereby greatly reducing the impact on the lifespan of the silicon wafer and consequently reducing the impact on the photoelectric conversion efficiency of the back junction solar cell.

[0092] 2. Ideal linearity of the front electrode (i.e., the first metal grid line): The first metal grid line on the front side is made entirely of silver paste, which has excellent shaping properties and can achieve extremely low front shading loss.

[0093] 3. Ideal front electrode resistance: The first metal grid line on the front side is made entirely of silver paste, which has low transmission resistance and low electrical loss.

[0094] 4. Low metallization area recombination: Since there is no silver-aluminum contact on the front side as in related technologies, the extremely high recombination current loss in the silver-aluminum contact area is eliminated, and the contact resistance loss when the two metals are in contact is also eliminated.

[0095] The present invention also provides a back-junction solar cell, which is prepared by the back-junction solar cell preparation method provided in the above embodiments.

[0096] The back-junction solar cell provided in this embodiment can be a P-type back-junction solar cell, which has a higher photoelectric conversion efficiency.

[0097] The specific implementation of the back-junction solar cell provided in this embodiment can be referred to the relevant embodiments of the back-junction solar cell preparation method above, which can achieve similar effects, and will not be described in detail here.

[0098] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0099] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a back-junction solar cell, characterized in that, include: Partially remove the first passivation layer on the first side of the silicon wafer to expose the silicon wafer; An electron-containing dopant source is provided to the exposed area of ​​the silicon wafer and then illuminated to form a heavily doped region; Metallization is performed in the heavily doped region to form a first metal gate line; under illumination, the silicon wafer generates separated charge carriers, and holes accumulate on the first surface of the silicon wafer. The holes recombine with electrons in the dopant source band to generate heat, and the heat causes the dopant element in the dopant source to diffuse into the silicon wafer to form the heavily doped region. Providing an electron-containing dopant source to the exposed area of ​​the silicon wafer includes: processing a sol containing the dopant source through an electron generating device, and spraying the sol onto the exposed area of ​​the silicon wafer using a nozzle.

2. The method for fabricating a back-junction solar cell according to claim 1, characterized in that, The solar irradiance during illumination is at least 10 × 1 kW / m².

3. The method for fabricating a back-junction solar cell according to any one of claims 1 to 2, characterized in that, The step of partially removing the first passivation layer on the first side of the silicon wafer to expose the silicon wafer includes: The first passivation layer on the first side of the silicon wafer is partially ablated by laser to expose the silicon wafer.

4. The method for fabricating a back-junction solar cell according to any one of claims 1 to 2, characterized in that, The width of the heavily doped region is less than the width of the first metal gate line, and / or the width of the exposed region is less than the width of the first metal gate line.

5. The method for fabricating a back-junction solar cell according to claim 4, characterized in that, The width of the first metal gate line is 5-30 micrometers, and / or the width of the heavily doped region is 4-20 micrometers, and / or the width of the exposed region is 4-20 micrometers.

6. The method for fabricating a back-junction solar cell according to any one of claims 1 to 2, characterized in that, The first metal gate line is a silver gate line.

7. The method for fabricating a back-junction solar cell according to claim 6, characterized in that, The first metal grid line is a silver grid line doped with aluminum, and the ratio of silver to aluminum in the first metal grid line is greater than or equal to 85:

1.

8. The method for fabricating a back-junction solar cell according to any one of claims 1 to 2, characterized in that, Also includes: A tunneling oxide layer, a doped polysilicon layer, a second passivation layer, and a second metal gate line are sequentially formed on the second side of the silicon wafer.

9. A back-junction solar cell, characterized in that, The back-junction solar cell is prepared using the back-junction solar cell preparation method as described in any one of claims 1 to 8.

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