Switching control circuit and switching control method thereof

Abstract

A switching control circuit and a switching control method thereof are disclosed. The switching control circuit includes a load connected in series to an input power source, an inductor, a control switch, and a sensing resistor; an integrator that integrates a sensing voltage and a load current set voltage to generate an integrated signal; a comparator that compares the integrated signal and a bias voltage; a switch driver that controls the control switch based on an output of the comparator and an output of an off-time controller; and a gate sensor that outputs a gate sensing signal to the integrator, the gate sensor sensing a timing at which an input of a gate terminal of the control switch becomes low. When the input of the gate terminal becomes high, an integration operation is started from a position at which the integrated signal is lower than the bias voltage.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0094272, filed on July 19, 2021, with the Korean Intellectual Property Office pursuant to 35U.SC§119, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0003] The following description relates to switch control circuits and their switch control methods. Background Technology

[0004] A switch control circuit can consist of a control switch that controls the current flowing to a load (e.g., a light-emitting diode (LED) device), a sensing circuit that senses the load current, and a control circuit that controls the control switch based on the load current. Figure 1 An example of a switch control circuit is shown in the figure.

[0005] Figure 1 A typical switching control circuit operating in Continuous Conduction Mode (CCM) peak mode is shown, and Figure 2 It shows Figure 1 The operation timing diagram. Ideally, in Figure 2 In the operation of the switch control circuit, the control switch should be turned off when the VCS voltage and the ADIM voltage (target) become the same. VCS voltage refers to... Figure 1 ADIM voltage is the voltage on the opposite side of the sensing resistor (RCS) connected to the control switch (or the voltage at the CS terminal), and ADIM voltage refers to the voltage of the LED device set to control the load.

[0006] However, in reality, because Figure 1 The propagation delay between the comparator's output terminal (OUT) and gate terminal (GATE) causes the VCS voltage to exceed the ADIM voltage, similar to... Figure 2 The diagram shows that the timing of turning off the control switch is slowed down by up to the time corresponding to ΔVCS. Therefore, compared with... Figure 2 Similar to the previous scenario, the gate turn-on timing becomes longer, extending into the t1–t2 period (t4–t5 period), and the inductor current also increases. Therefore, the LED current flowing through the load will exceed the initial setting, leading to errors.

[0007] To eliminate the increase in inductor current, methods such as... are typically proposed. Figure 3 The method shown. Figure 3 A switch control circuit operating in CCM average mode is shown, and Figure 4 It shows Figure 3The timing diagram. (Similar to...) Figure 1 The method shown for comparing VCS voltage and ADIM voltage differs by creating a 'HALF ADIM voltage,' which is half the ADIM voltage. Figure 3 The integral value (Bias) of the HALF ADIM voltage is compared with the integral value (integrated signal) of the VCS voltage. Here, the 'HALF ADIM voltage' signal is generated by the integrator that receives the ADIM voltage.

[0008] Reference Figure 4 ,Right now Figure 3 The timing diagram shows that the HALF ADIM voltage and VCS voltage are integrated by an integrator. When the bias voltage (Bias) and the integration signal, which serve as the integral value, become identical (t2, t6), the comparator outputs a high-level OUT signal. Therefore, the control switch is turned off. Additionally, Figure 3 The switch control circuit may include a turn-off time controller that calculates the turn-off time from the timing when the control switch is turned off or the comparator output goes high. The turn-off time controller can turn the control switch on after a predetermined turn-off time, and the user can set the turn-off time through a specific program or through an external output of the RT-OFF (TOFF) terminal.

[0009] However, in this method, a propagation delay may still occur between the comparator's output terminal and gate terminal, thus delaying the turn-off timing of the control switch by as much as t2 to t3 (t6 to t7). Therefore, this method may not be able to solve the problem of increased inductor current. Summary of the Invention

[0010] This invention is provided to introduce a series of concepts in a simplified form, which are further described below in the detailed description. This invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter.

[0011] In general, a switch control circuit includes: a load, an inductor, a control switch, and a sensing resistor connected in series with an input power supply; an integrator configured to integrate a sensed voltage (VCS) and a load current set voltage (ADIM) to generate an integrated signal; a comparator configured to compare the integrated signal with a bias voltage; a switch driver configured to control the control switch based on the output of the comparator and the output of a turn-off time controller; and a gate sensor configured to output a gate sensing signal to the integrator, the gate sensor sensing the timing of an input to the gate terminal of the control switch going low, wherein when the input to the gate terminal goes high, the integration operation begins from the position where the integrated signal is below the bias voltage.

[0012] The integrator may include: a current source configured to be based on a reference voltage (V REF The current is provided by the difference between the current source and the sensed voltage (VCS); a first switch electrically connected to the current source, a capacitor, a bias voltage as a voltage source; a logic element electrically connected to the first switch; and a second switch connected to the opposite side of the capacitor and configured to receive the output signal of the switch control logic unit.

[0013] Reference voltage (V) REF It can be half of the load current setting voltage (ADIM).

[0014] The logic element can be an SR latch, wherein the 'S' terminal of the SR latch can be configured to receive the output signal of the off-time controller, the 'R' terminal of the SR latch can be configured to receive the output signal of the gate sensor, and the 'Q' terminal of the SR latch can be configured to output the output signal to the first switch.

[0015] The switch control logic unit may include an inverting buffer.

[0016] Starting at the same timing as the bias voltage, the integral signal can decrease until the input at the gate terminal goes low, and the decrease of the integral signal can be stopped when the gate sensor outputs a gate sensing signal to the integrator.

[0017] The reduced value of the integral signal can be lower than the bias voltage, and the integral signal is held until the input at the gate terminal goes high.

[0018] The integrated load current setting voltage can be the integral of half the load current setting voltage (HALF ADIM).

[0019] The switching control circuit can be configured to operate in either Continuous Conduction Mode (CCM) or Boundary Conduction Mode (BCM).

[0020] The switching control circuit operated by the BCM can be a quasi-resonant (QR) buck converter.

[0021] The quasi-resonant buck converter may also include a zero-current detection circuit (ZCD circuit), which is configured to detect the timing when the inductor current becomes 0.

[0022] A zero-current detection circuit (ZCD circuit) may include a capacitor and two resistors connected in series.

[0023] In general, the switching control method of the switching control circuit includes: comparing an integral signal that integrates the sensed voltage with a bias voltage; reducing the integral signal to below the bias voltage during a decreasing segment of the integral signal; stopping the reduction of the integral signal and maintaining the integral signal for a predetermined time; and starting the integration operation of the sensed voltage from a position below the bias voltage when the input of the gate terminal becomes high again.

[0024] The switch control circuit can be configured to operate in either continuous conduction mode (CCM) or boundary conduction mode (BCM).

[0025] The integration signal can be decreased from the time when the output of the comparison is high until the input at the gate terminal becomes low.

[0026] When the gate terminal input is detected to be low and a gate sensing signal is output, the decrease of the integration signal can be stopped.

[0027] The reduced value of the integrated signal can be maintained until the input at the gate terminal goes high again.

[0028] In general, the switch control circuit includes: a load, an inductor, a control switch, and a sensing resistor connected in series with an input power supply; and a switch controller configured to control the operation of the control switch, wherein the switch controller includes: an integrator configured to receive a reference current and a current measured by the sensing resistor, and generate an integrated signal; an amplifier configured to compare the integrated signal with a bias voltage; a turn-off time controller configured to generate a control signal for turning on the control switch after a predetermined time period; an SR latch configured to control the control switch based on the output of the amplifier and the output of the turn-off time controller; and a gate sensor configured to send a gate sensing signal to the integrator.

[0029] The integral signal can be generated during the period when the control switch is on.

[0030] The gate sensor can also be configured to sense the timing of the input at the gate terminal going low and send the sensing result to the integrator.

[0031] Other features and aspects will become apparent from the following detailed description, drawings, and claims. Attached Figure Description

[0032] Figure 1 A typical switch control circuit diagram operating in CCM peak mode is shown.

[0033] Figure 2 It shows Figure 1 The operation timing diagram.

[0034] Figure 3 A typical switch control circuit diagram operating in CCM average mode is shown.

[0035] Figure 4 It shows Figure 3 The operation timing diagram.

[0036] Figure 5 An example switch control circuit diagram operating in CCM according to one or more embodiments is shown.

[0037] Figure 6 It shows Figure 5 The internal circuit diagram of the integrator.

[0038] Figure 7 A switch control circuit diagram operating in BCM according to one or more embodiments is shown.

[0039] Figure 8 It shows Figure 5 The operation timing diagram of the circuit diagram.

[0040] Figure 9 It shows Figure 7 The operation timing diagram of the circuit diagram.

[0041] Throughout the accompanying drawings and detailed description, the same reference numerals refer to the same elements. The drawings may not be drawn to scale, and for clarity, illustration, and convenience, the relative dimensions, scale, and depiction of the elements in the drawings may be exaggerated. Detailed Implementation

[0042] The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatus, and / or systems described herein. However, after understanding the disclosure of this application, various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will become apparent. For example, the sequence of operations described herein is merely illustrative and is not limited to the sequence of operations set forth herein, but can be changed as will become apparent after understanding the disclosure of this application, except for operations that must occur in a certain order. Furthermore, for the sake of clarity and conciseness, descriptions of features known after understanding the disclosure of this application may be omitted; note that the omission of features and their descriptions is not intended to acknowledge their general knowledge.

[0043] The features described herein may be implemented in various forms and are not to be construed as limited to the examples described herein. Rather, the examples described herein are provided merely to illustrate some of the many possible ways of implementing the methods, apparatus, and / or systems described herein that will become apparent upon understanding the disclosure of this application.

[0044] Throughout the specification, when an element such as a layer, region, or substrate is described as "on another element," "connected to," or "coupled to" another element, it may be directly on, connected to, or coupled to that other element, or one or more other elements may be present between it and the other element. In contrast, when an element is described as "directly on another element," "directly connected to," or "directly coupled to" another element, there may be no other elements between it and the other element.

[0045] As used herein, the term “and / or” includes any one of the associated listed items and any combination of any two or more.

[0046] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, without departing from the teachings of the examples described herein, the first component, part, region, layer, or section mentioned in the examples may also be referred to as the second component, part, region, layer, or section.

[0047] For ease of description, spatial relative terms such as “above,” “above,” “below,” and “under” are used herein to describe the relationship between one element and another shown in the accompanying drawings. Such spatial relative terms are intended to cover different orientations of the device in use or operation, in addition to the orientations depicted in the drawings. For example, if the device in the drawings is flipped, an element described as “above” or “above” relative to another element is “below” or “under” relative to the others. Thus, depending on the spatial orientation of the device, the term “above” encompasses both the orientation above and the orientation below. The device may also be oriented in other ways (e.g., rotated 90 degrees or rotated in other directions), and the spatial relative terms used herein shall be understood accordingly.

[0048] The terminology used herein is for the purpose of describing various examples only and is not intended to limit the scope of this disclosure. Unless the context clearly indicates otherwise, the articles “a,” “an,” and “the” are also intended to include plural forms. The terms “comprising,” “including,” and “having” specify the presence of the stated features, numbers, operations, components, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, components, elements, and / or combinations thereof.

[0049] Variations in the shapes shown in the figures can occur due to manufacturing techniques and / or tolerances. Therefore, the examples described herein are not limited to the specific shapes shown in the figures, but include shape variations that may occur during manufacturing.

[0050] As will be apparent upon understanding the disclosure of this application, the features of the examples described herein can be combined in various ways. Furthermore, as will be apparent upon understanding the disclosure of this application, although the examples described herein have various configurations, other configurations are also possible.

[0051] The target problem of this disclosure is not limited to the problems mentioned above, and other problems can be understood by those skilled in the art based on the following description.

[0052] This disclosure addresses the aforementioned problems by providing a switching control circuit and a switching control method for compensating for errors in load current that may arise due to propagation delay.

[0053] One or more examples relate to a switching control circuit and a switching control method thereof for compensating for errors in the current flowing to the load of the switching control circuit.

[0054] The following is a detailed description of one or more examples based on the examples shown in the accompanying drawings.

[0055] In one or more examples, the switching control circuitry can be applied to all switching control circuits operating in either Continuous Conductive Mode (CCM) or Boundary Conductive Mode (BCM). The difference lies in the starting point for increasing the inductor current, and both CCM and BCM have circuitry components that control the turn-off time. The turn-off time controller in a BCM operates via the output of an input zero-current detection circuit (ZCD circuit), which is described below.

[0056] Figure 5 An example switch control circuit diagram operating in CCM according to one or more embodiments is shown.

[0057] Reference Figure 5 One or more light-emitting devices 100 are connected in series with the input voltage terminal (VIN). Additionally, the system may include: a capacitor 101 connected in parallel with one or more light-emitting devices 100; a diode 102 that carries current input through one or more light-emitting devices 100 and the capacitor 101; and an inductor 103 connected in series with one or more light-emitting devices 100 and the capacitor 101. A control switch (MOSFET) 110 and a sensing resistor 120 may be connected between the inductor 103 and ground.

[0058] Inductor 103 can be implemented to store energy supplied by the input power supply or release the stored energy according to the operation of control switch 110. Inductor 103 can sense a voltage proportional to the change in current flowing through it, suppress rapid changes in current, and store energy proportional to the square of the amount of current flowing. As the capacitance of inductor 103 changes, the on and off cycles of control switch 110 can be changed to correspond to the capacitance of inductor 103. Therefore, the operating frequency of control switch 110 can be changed to correspond to the capacitance of inductor 103.

[0059] In the example, diode 102 may be a freewheeling diode, and when releasing energy from inductor 103, diode 102 may form a current-moving loop capable of supplying energy to a load (e.g., one or more light-emitting devices 100).

[0060] In the example, control switch 110 can be connected in series with inductor 103 and the amount of current flowing to one or more light-emitting devices 100 can be controlled by repeatedly performing on and off operations.

[0061] The sensing resistor 120 can be connected between one end of the control switch 110 and a reference potential. Based on the voltage on the opposite side of the sensing resistor 120 (or the voltage at the CS terminal), the current flowing to one or more light-emitting devices 100 can be measured.

[0062] according to Figure 5 A switch controller 200 is provided to control the operation of the control switch 110. The switch controller 200 may include an integrator 210, a comparator 220, an off-time controller 230, a switch driver 240, and a gate sensor 250.

[0063] In this example, integrator 210 can receive a current measured by sensing resistor 120 and a predetermined reference current, and perform integration operations on the two received currents respectively. The reference current can be set during manufacturing operations, or it can be changed via a specific program or a pin mounted externally to integrator 210. Integrator 210 can perform integration operations during the period when control switch 110 is on, and integrator 210 can be reset when control switch 110 is off.

[0064] exist Figure 6 The internal circuitry of integrator 210 is shown in the figure.

[0065] Reference Figure 6 The integrator 210 may include: a current source 211, which is based on a reference voltage (V REF ) and sensed voltage (V CS The difference between ) provides the current (gm*(V)REF -V CS ); First switch 212; Capacitor 213; Bias source 214, which is a voltage source connected in series with current source 211. One end of bias source 214 can be grounded.

[0066] The SR latch 216 can be connected to the first switch 212. The 'S' terminal of the SR latch 216 can receive the output signal of the off-time controller 230, and the 'R' terminal of the SR latch 216 can receive the output signal of the gate sensor 250. The 'Q' terminal of the SR latch 216 can apply the output signal to the first switch 212.

[0067] The second control switch 217 can be connected to the opposite side of the capacitor 213. The second switch 217 can be connected to receive the output signal of the switch control logic unit, and the switch control logic unit may include an inverting buffer 218.

[0068] Refer again Figure 5 Comparator 220 can compare the integrated signal, integrated in integrator 210, with a bias voltage. In one or more examples, the bias voltage may have the form that increases with a specific tilt. In one or more examples, comparator 220 may be implemented as an amplifier, and specifically a differential amplifier. The bias voltage (Bias) may be applied to the '+' terminal of comparator 220, and the integrated signal may be applied to the '-' terminal.

[0069] The turn-off time controller 230 can generate a control signal to turn on the control switch 110 after a certain period of time has elapsed since the control switch 110 was turned off. The control switch 110 can form a current flow loop in which current can flow to the light-emitting device 100 via the input power and through the control switch 110. In other words, the turn-off time controller 230 can calculate a predetermined turn-off time from the turn-off time of the control switch 110, and the turn-off time can be the time during which the control switch 110 remains in the off state from the turn-off time. The user can set the turn-off time via the TOFF terminal. During the turn-off time, the turn-off time controller 230 can output a low-level signal, and the turn-off time controller 230 can output a high-level signal when the turn-off time has elapsed. Similarly, the switch control circuit of the CCM includes components for controlling the turn-off time.

[0070] The switch driver 240 can control the control switch 110 based on the outputs of the comparator 220 and the off-time controller 230. In the example, the switch driver 240 can be implemented as an SR latch, which performs logic operations on the outputs of the comparator 220 and the off-time controller 230. When the switch driver 240 is implemented as an SR latch, the outputs of the off-time controller 230 and the comparator 220 can be input to the input terminals 'S' and 'R' of the SR latch, respectively. When a high-level signal (e.g., 1) is input to the 'S' terminal of the SR latch, a 'set' mode can be entered, and a control signal for turning on the control switch 110 can be output through the 'Q' terminal. Subsequently, when a high-level signal (e.g., 1 or a positive signal) is input to the 'R' terminal according to the output of the comparator 220, the SR latch 240 can enter a 'reset' mode, and it can output a control signal for turning off the control switch 110 through the 'Q' terminal.

[0071] In one or more examples of the switch control circuit, a gate sensor 250 is also included. The gate sensor 250 can sense the input level state of the gate terminal and output the sensed gate sensing signal (GATE_S) to the integrator 210. The gate sensing signal (GATE_S) can be applied to the 'R' terminal of the SR latch 216 in the integrator 210. That is, the gate sensor 250 can sense the timing of the gate terminal input going low and can add components to feed the sensing result back to the integrator 210. Therefore, when the gate terminal input goes high, the integration operation of the integrator 210 can begin below the bias voltage, thus eliminating load current errors by controlling the VCS voltage to be no higher than the target voltage.

[0072] Figure 7 A switch control circuit diagram operating with a BCM is shown according to one or more embodiments. (As shown in the diagram...) Figure 5 Compared to the CCM-operated switch control circuit shown, as Figure 7 The switch control circuit diagram shown is a component of the sensing control switch 110, and may include a capacitor 130, a first resistor 140, and a second resistor 150. These components allow for the adjustment of the timing for turning on the control switch by detecting the timing when the drain voltage becomes 0 and providing this information to the turn-off time controller 230. Figure 7 The other components shown can be used with Figure 5 The components shown are the same.

[0073] In the example switch control circuit operating with BCM, the biggest difference compared to the typical circuit configuration is the gate sensor 250 that senses the input level state of the gate terminal.

[0074] Next, we will use Figure 8 and Figure 9 The timing diagram describes the operation of the switch control circuit.

[0075] Reference Figure 8 and Figure 9 The only difference is the starting point of the sensed voltage (VCS) and inductor current (IL); all other waveforms are identical. Therefore, only the following is described. Figure 8 .

[0076] When the input at the gate terminal goes high, the control switch 110 can be turned on, and the inductor current (IL) and sensed voltage (VCS) increase. In one or more examples, the integral signal can increase or decrease depending on the sensed voltage (VCS) and the half-adim voltage. Therefore, the integral signal increases in the region where the sensed voltage (VCS) is lower than the half-adim voltage (t0~t1, t4~t5). On the other hand, the integral signal decreases in the region where the sensed voltage (VCS) is higher than the half-adim voltage (t1~t3, t5~t7).

[0077] Integrator 210 can output an integrated signal and a bias voltage to comparator 220 according to the integration operation. Comparator 220 can then continuously compare the integrated signal and the bias voltage, and at a time (P) when the integrated signal becomes less than the bias voltage, comparator 220 can output a high-level signal (c). In this example, the integrated signal continues to decrease. The integrated signal can continue to decrease until the output of comparator 220 is high and the input at the gate terminal is high.

[0078] When the gate sensor 250 senses a low-level input at the gate terminal, it outputs a gate sensing signal (GATE_S) to the integrator 210. When the gate sensing signal (GATE_S) is output, the integration operation of the integrator 210 is stopped, and the decrease of the integration signal is halted. The integration operation remains stopped (t3~t4, t7~t8) until the gate terminal input goes high again.

[0079] Later, when the input at the gate terminal goes high (t4, t8), the integrator 210 can resume integration. Integration can be performed only during the time the control switch 110 is on.

[0080] In the example of restarting the integration operation, the starting point of the integration operation can be increased from a point where the voltage is lower than the bias voltage. In the diagram, this is 'S' at t4. Therefore, the sensed voltage (VCS) will not increase beyond the ADIM voltage (target). Thus, by reducing the integration signal during the propagation delay from the output terminal to the gate terminal of comparator 220, the error of the load current can be compensated.

[0081] According to one or more examples of switch control circuits and switch control methods, in a switch control circuit operating with CCM or BCM, the integral signal can be reduced below the bias voltage by up to the propagation delay time occurring between the comparator and the gate terminal, and the integral signal can be restarted with the reduced value.

[0082] Therefore, the error in load current caused by the increased gate conduction time due to propagation delay in conventional switching control circuits can be resolved.

[0083] While this disclosure includes specific examples, it will be apparent upon understanding the disclosure of this application that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein should be considered descriptive only and not for limiting purposes. The description of features or aspects in each example should be considered applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and / or if components in the described system, architecture, apparatus, or circuit are combined in different ways and / or replaced or supplemented by other components or their equivalents. Therefore, the scope of this disclosure is not limited by the detailed description but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents should be construed as included in this disclosure.

Claims

1. A switch control circuit, comprising: The load, inductor, control switch, and sensing resistor are connected in series with the input power supply. An integrator configured to integrate the sensed voltage and the load current set voltage to generate an integrated signal; A comparator configured to compare the integrated signal with a bias voltage; A switch driver configured to control the control switch based on the output of the comparator and the output of the off-time controller; as well as A gate sensor is configured to output a gate sensing signal to the integrator, the gate sensing signal indicating that the input to the gate terminal of the control switch has gone low. Specifically, after outputting the gate sensing signal, when the input of the gate terminal becomes high, the integrator starts the integration operation from the time point when the integration signal is lower than the bias voltage.

2. The switch control circuit according to claim 1, in, The integrator includes: A current source configured to provide current based on the difference between a reference voltage and the sensed voltage; A first switch, a capacitor, and a bias voltage are electrically connected to the current source as a voltage source; Logic elements electrically connected to the first switch; and A second switch is connected to the opposite side of the capacitor and is configured to receive the output signal of the switch control logic unit.

3. The switch control circuit according to claim 2, in, The reference voltage is half of the load current setting voltage.

4. The switch control circuit according to claim 2, in, The logic element is an SR latch. The 'S' terminal of the SR latch is configured to receive the output signal of the off-time controller, the 'R' terminal of the SR latch is configured to receive the output signal of the gate sensor, and the 'Q' terminal of the SR latch is configured to output the output signal to the first switch.

5. The switch control circuit according to claim 2, wherein, The switch control logic unit includes an inverting buffer.

6. The switch control circuit according to claim 1, in, Starting from the same timing as the bias voltage, the integral signal decreases until the input at the gate terminal goes low, and Specifically, when the gate sensor outputs the gate sensing signal to the integrator, the reduction of the integration signal is stopped.

7. The switch control circuit according to claim 6, in, The reduced value of the integral signal is lower than the bias voltage, and the integral signal is held until the input at the gate terminal becomes high.

8. The switch control circuit according to claim 1, wherein, The integrated load current setting voltage is the integral of half of the load current setting voltage.

9. The switch control circuit according to claim 1, wherein, The switch control circuit is configured to operate in one of a continuous conduction mode and a boundary conduction mode.

10. The switch control circuit according to claim 9, wherein, The switch control circuit operating in the boundary conduction mode is a quasi-resonant buck converter.

11. The switch control circuit according to claim 10, wherein, The quasi-resonant buck converter also includes a zero-current detection circuit configured to detect the timing when the inductor current becomes 0.

12. The switch control circuit according to claim 11, wherein, The zero-current detection circuit includes a capacitor and two resistors connected in series.

13. A switching control method for a switching control circuit, the method comprising: The integrated signal, which integrates the sensed voltage, is compared with the bias voltage. When the integrated signal crosses the bias voltage, the integrated signal is reduced to below the bias voltage in the decreasing segment of the integrated signal; When the input of the gate terminal is detected to be low and a gate sensing signal is output, the decrease of the integral signal is stopped and the integral signal is maintained for a predetermined time. as well as When the input at the gate terminal goes high, the integration operation of the sensed voltage begins from a time point below the bias voltage.

14. The method according to claim 13, wherein, The switch control circuit is configured to operate in one of a continuous conduction mode and a boundary conduction mode.

15. The method according to claim 13, wherein, The integration signal decreases from the time when the output of the comparison is high until the input of the gate terminal becomes low.

16. The switching control method according to claim 15, in, The reduced value of the integrated signal is maintained until the input at the gate terminal goes high again.

17. A switch control circuit, comprising: The load, inductor, control switch, and sensing resistor are connected in series with the input power supply. as well as A switch controller configured to control the operation of the control switch. The switch controller includes: An integrator configured to receive a reference current and a current measured by the sensing resistor, and to generate an integrated signal; An amplifier configured to compare the integrated signal with a bias voltage; A shutdown time controller, configured to generate a control signal for turning on the control switch after a predetermined time period, and An SR latch, configured to control the control switch based on the output of the amplifier and the output of the turn-off time controller, and A gate sensor configured to send a gate sensing signal to the integrator.

18. The switch control circuit according to claim 17, wherein, The integral signal is generated during the period when the control switch is turned on.

19. The control circuit according to claim 17, wherein, The gate sensor is also configured to sense the timing of the input at the gate terminal going low and send the sensing result to the integrator.

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