A control method for a multi-output synchronous buck converter

Abstract

This application discloses a control method for a multi-output synchronous buck converter. The converter control method includes: controlling the switching circuit in FCCM mode within one control cycle T of the multi-output synchronous buck converter; and controlling the multi-output synchronous buck converter in DCM mode when all the switches in the switching circuit are turned off within the control cycle T. The output current directions of the primary-side output sub-units of the multi-output synchronous buck converter are opposite in FCCM mode and in DCM mode. By using both FCCM and DCM modes to control the multi-output synchronous buck converter within one control cycle T, the technical problem of reduced conversion efficiency under light load is solved, and good load regulation of the isolated output is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of direct current conversion technology, and particularly relates to a control method for a multi-output synchronous buck converter. BACKGROUND

[0002] With the rapid development of power electronics technology, people's demand for various electronic products is also increasing, and the demand for direct current power supply is also increasing. For example, many special equipment requires multiple isolated power supplies to be opened and run synchronously, such as ground data terminal machines, radio frequency controllers, etc. In many fields, the technical problem of synchronous opening equipment or synchronous opening power supply is required. In the prior art, the multi-output synchronous buck converter generally adopts the forced current continuous conduction mode (FCCM) mode, however, in the FCCM mode, under light load conditions, the switching frequency remains unchanged, the ratio of switching loss to total loss increases, and the efficiency decreases. If the controller is operated at a lower frequency as the load decreases in order to improve the light load efficiency, it will result in insufficient conduction time of the lower tube, the output capacitor charge on the isolation side is less than the charge consumption, and the output voltage on the isolation side is unstable, and even cannot meet the requirements. SUMMARY

[0003] The technical problem solved by the present application is the low power conversion efficiency of the multi-output synchronous buck converter in the FCCM mode under light load conditions.

[0004] According to a first aspect, in an embodiment, a multi-output synchronous buck converter is provided, comprising a loop control logic output circuit and an isolated multi-output synchronous buck circuit;

[0005] The loop control logic output circuit is configured to send an upper tube drive signal HG and a lower tube drive signal LG to a switch tube circuit in the isolated multi-output synchronous buck circuit, so as to realize switching control of a power switch tube in the switch tube circuit.

[0006] The isolated multi-output synchronous buck circuit further comprises a primary side output subunit and n secondary side output subunits, n being a natural number; the switch tube circuit comprises an upper switch tube Q1 and a lower switch tube Q2; the switching control poles of the upper switch tube Q1 and the lower switch tube Q2 are respectively responsive to the upper tube drive signal HG and the lower tube drive signal LG to realize switching control, so as to output the power of the first direct current Vin to the primary side output subunit and each secondary side output subunit.

[0007] The primary side output subunit is configured to convert the power output by the switch tube circuit to the primary side output subunit into a second direct current Vout0 and then output.

[0008] Each of the auxiliary side output sub-units is configured to convert the power output by the switch tube circuit to the auxiliary side output sub-unit into a third direct current Vout1 and output the third direct current Vout1.

[0009] The upper tube driving signal HG comprises an upper tube conducting level signal and an upper tube closing level signal, the upper switch tube Q1 is turned on when the upper tube driving signal HG keeps at the upper tube conducting level signal, and the upper switch tube Q1 is turned off when the upper tube driving signal HG keeps at the upper tube closing level signal.

[0010] The lower tube driving signal LG comprises a lower tube conducting level signal and a lower tube closing level signal, the lower switch tube Q2 is turned on when the lower tube driving signal LG keeps at the lower tube conducting level signal, and the lower switch tube Q2 is turned off when the lower tube driving signal LG keeps at the lower tube closing level signal.

[0011] At any time, when the upper tube driving signal HG is the upper tube conducting level signal, the lower tube driving signal LG cannot be the lower tube conducting level signal, so as to ensure that the upper switch tube Q1 and the lower switch tube Q2 cannot be turned on at the same time.

[0012] In each signal period T, the upper tube driving signal HG comprises a continuous upper tube conducting duration period and a continuous upper tube closing duration period, the upper tube driving signal HG keeps at the upper tube conducting level signal in the upper tube conducting duration period, and the upper tube driving signal HG keeps at the upper tube closing level signal in the upper tube closing duration period.

[0013] In the signal period T, the lower tube driving signal LG comprises a continuous first lower tube conducting duration period and a continuous second lower tube conducting duration period, the lower tube driving signal LG keeps at the lower tube conducting level signal in the first lower tube conducting duration period and the second lower tube conducting duration period.

[0014] In the signal period T, the upper tube conducting duration period and the first lower tube conducting duration period are continuous in time, and when the upper tube driving signal HG is in the upper tube conducting duration period and the lower tube driving signal LG is in the first lower tube conducting duration period, the direction of the current output by the primary side output sub-unit is a first direction; when the lower tube driving signal LG is in the second lower tube conducting duration period, the direction of the current output by the primary side output sub-unit is a second direction, and the first direction and the second direction are opposite.

[0015] According to a second aspect, an embodiment provides a control method of a transformer, applied to the multi-output synchronous step-down transformer as described in the first aspect, the control method comprising:

[0016] In a control period T of the switch tube circuit, the switch tube circuit is controlled in the FCCM mode, so that the original side output subunit outputs current in the second direction.

[0017] In the control period T, when the upper switch tube Q1 and the lower switch tube Q2 of the switch tube circuit are both turned off, the switch tube circuit is controlled in the DCM mode, so that the original side output subunit outputs current in the first direction, wherein the first direction and the second direction are opposite.

[0018] In an embodiment, the transformer control method further comprises:

[0019] In each control period T, the DCM mode is set before or after the FCCM mode.

[0020] According to the transformer control method of the above embodiment, in a control period T, the FCCM and DCM modes are used to control the multi-output synchronous buck converter, so that the technical problem of low conversion efficiency of the multi-output synchronous buck converter at light load is solved, and the output of the isolation side has good load regulation. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 It is a structure block diagram of the multi-output synchronous buck converter in an embodiment;

[0022] Figure 2 It is a circuit connection schematic diagram of the isolation multi-output synchronous buck circuit in an embodiment;

[0023] Figure 3 It is a circuit connection schematic diagram of the loop control logic output circuit in an embodiment;

[0024] Figure 4 It is a circuit connection schematic diagram of the feedback signal acquisition circuit in an embodiment;

[0025] Figure 5 It is a logic control schematic diagram of the switch tube circuit in an embodiment;

[0026] Figure 6 It is a waveform schematic diagram of the switch tube control signal of the switch tube circuit in an embodiment;

[0027] Figure 7 It is a logic control schematic diagram of the switch tube circuit in another embodiment;

[0028] Figure 8 It is a logic control schematic diagram of the switch tube circuit in an embodiment of the first additional conduction time setting mode;

[0029] Figure 9 Fig. 4 is a logic control diagram of a switch tube circuit for a second additional conduction time setting mode in an embodiment;

[0030] Figure 10 Fig. 5 is a logic control diagram of a switch tube circuit for a third additional conduction time setting mode in an embodiment;

[0031] Figure 11 Fig. 6 is a flow diagram of a converter control method in an embodiment. DETAILED DESCRIPTION

[0032] The application will be further described in details with specific embodiments and the accompanying drawings. In different embodiments, similar elements are designated by similar reference numerals. In the following embodiments, many details are described in order to make the application better understood. However, one skilled in the art can easily recognize that some features can be omitted in different cases, or replaced by other elements, materials, methods. In some cases, some operations related to the application are not shown or described in the specification, in order to avoid the core of the application being overwhelmed by too many descriptions, and it is not necessary to describe these operations in detail for one skilled in the art, who can fully understand the operations according to the description in the specification and general technical knowledge in the art.

[0033] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various embodiments. Meanwhile, the steps or actions in the method description can also be sequentially adjusted or adjusted in a manner that one skilled in the art can easily see. Therefore, the various sequences in the specification and drawings are only for the purpose of clearly describing a certain embodiment, and do not mean that the sequence is necessary, unless otherwise stated that a certain sequence must be followed.

[0034] In this paper, the serial numbers of components, such as "first", "second", etc., are only used to distinguish the described objects, and do not have any sequence or technical meaning. Unless otherwise specified, the "connection" and "coupling" in this application include direct and indirect connection (coupling).

[0035] The multi-output synchronous step-down converter disclosed in the embodiments of the present application comprises a loop control logic output circuit and an isolated multi-output synchronous step-down circuit. The loop control logic output circuit is used to output an upper transistor drive signal HG and a lower transistor drive signal LG to an upper switch transistor Q1 and a lower switch transistor Q2 of a switch transistor circuit in the synchronous step-down circuit for switch control, so as to output the electric energy of a first direct current Vin to a primary side output subunit and each secondary side output subunit of the isolated multi-output synchronous step-down circuit. In one control period T of the switch transistor circuit, the lower switch transistor Q2 is additionally turned on for a period of time under the premise that the output voltage of each secondary side output subunit on the isolated side is ensured to be within a preset output range, so as to supplement the charge of the output capacitor of each secondary side output subunit, thereby achieving the purpose of improving the electric energy conversion efficiency of the multi-output synchronous step-down converter when the multi-output synchronous step-down converter works in a light load condition.

[0036] Embodiment one

[0037] Please refer to Figure 1 Fig. 1 is a structural block diagram of a multi-output synchronous step-down converter in an embodiment. The multi-output synchronous step-down converter comprises a loop control logic output circuit 100 and an isolated multi-output synchronous step-down circuit 200. The loop control logic output circuit 100 is used to send an upper transistor drive signal HG and a lower transistor drive signal LG to a switch transistor circuit in the isolated multi-output synchronous step-down circuit 200, so as to realize the switch control of the power switch transistor of the switch transistor circuit.

[0038] Please refer to Figure 2Fig. 1 is a schematic diagram of a circuit connection of an isolated multi-output synchronous buck circuit in an embodiment. The isolated multi-output synchronous buck circuit 200 includes a switch tube circuit 210, a primary side output subunit 220, and n secondary side output subunits 230, where n is a natural number. The switch tube circuit 210 includes an upper switch tube Q1 and a lower switch tube Q2. The switch control poles of the upper switch tube Q1 and the lower switch tube Q2 are respectively responsive to an upper tube drive signal HG and a lower tube drive signal LG to achieve switch control, so as to output the electric energy of a first direct current Vin to the primary side output subunit 220 and each secondary side output subunit 230. The primary side output subunit 220 includes a primary side inductor L0, a primary side output capacitor C0, and a primary side output end for outputting a second direct current Vout0. One end of the primary side inductor L0 is connected to the switch tube circuit 210, and the other end is connected to the primary side output end. One end of the primary side output capacitor C0 is connected to the primary side output end, and the other end is grounded. The primary side output subunit 220 is configured to output the electric energy converted from the electric energy output by the switch tube circuit 210 to the primary side output subunit 220 to the second direct current Vout0. Each secondary side output subunit 230 includes a secondary side inductor L1, a secondary side diode D1, a secondary side output capacitor C1, and a secondary side output end for outputting a third direct current Vout1. One end of the secondary side inductor L1 is connected to the anode of the secondary side diode D1, and the other end is grounded. The secondary side inductor L1 is configured to obtain the electric energy from the switch tube circuit 210 through the primary side inductor L0 by using the mutual inductance principle. The cathode of the secondary side diode D1 is connected to the secondary side output end. One end of the secondary side output capacitor C1 is connected to the secondary side output end, and the other end is grounded. Each secondary side output subunit 230 is configured to output the electric energy converted from the electric energy output by the switch tube circuit 210 to the secondary side output subunit 230 to the third direct current Vout1. The upper switch tube Q1 and the lower switch tube Q2 of the switch tube circuit 210 each include a control pole, a first connection pole, and a second connection pole. The first connection pole of the upper switch tube Q1 is configured to be connected to the first direct current Vin. The second connection pole of the upper switch tube Q1 is connected to the first connection pole of the lower switch tube Q2. The second connection pole of the lower switch tube Q2 is grounded. The second connection pole of the upper switch tube Q1 is also connected to one end of the primary side inductor L0 of the primary side output subunit 220.

[0039] Please refer to Figure 3Fig. 1 is a schematic diagram of a circuit connection of a loop control logic output circuit in an embodiment. The loop control logic output circuit 100 comprises an On-Time generation circuit 110, a feedback signal acquisition circuit 120, a switch trigger signal generation circuit 130 and a control signal output circuit 140. The On-Time generation circuit 110 is connected with the control signal output circuit 140, and the On-Time generation circuit 110 is configured to generate a switch tube driving signal HSD_OFF to the control signal output circuit 140. The feedback signal acquisition circuit 120 is connected with the primary side output subunit 220 and the switch trigger signal generation circuit 130 respectively, and the feedback signal acquisition circuit 120 is configured to sample a second direct current Vout0 output by the primary side output subunit 220 and output a feedback signal acquired by sampling to the switch trigger signal generation circuit 130. The switch trigger signal generation circuit 130 is connected with the control signal output circuit 140, and the switch trigger signal generation circuit 130 is configured to output a switch trigger signal HSD_ON to the control signal output circuit 140 according to the feedback signal. The control signal output circuit 140 is configured to send an upper tube driving signal HG and a lower tube driving signal LG to the switch tube circuit 210 according to the switch tube driving signal HSD_OF and the switch trigger signal HSD_ON.

[0040] In an embodiment, the switch trigger signal generation circuit 130 comprises a ripple generation circuit 131, an error amplifier 132, a comparator 133 and a slope generation circuit 134. The error amplifier 132 is connected with the feedback signal acquisition circuit 120, and the error amplifier 132 is configured to amplify the feedback signal. The ripple generation circuit 131 is configured to generate a ripple signal, the slope generation circuit 134 is configured to generate a slope signal, and the comparator 133 is configured to compare a signal synthesized by the ripple signal and the feedback signal with a signal synthesized by the slope signal and the amplified feedback signal, and send a comparison result signal acquired by comparison as the switch trigger signal HSD_ON to the control signal output circuit 140.

[0041] Please refer to Figure 4 Fig. 2 is a schematic diagram of a circuit connection of a feedback signal acquisition circuit in an embodiment. The feedback signal acquisition circuit 120 comprises a sampling input end, a sampling output end, a first resistor R1 and a second resistor R2. The sampling input end is connected with the primary side output subunit 220 for input of the second direct current Vout0. The sampling output end is connected with the switch trigger signal generation circuit 130 for output of the feedback signal to the switch trigger signal generation circuit 130. One end of the first resistor R1 is connected with the sampling input end, and the other end is connected with the sampling output end. One end of the second resistor R2 is connected with the sampling output end, and the other end is grounded.

[0042] As Figure 2As shown in the output synchronous buck converter, the second DC voltage Vout0 output by the primary output subunit 220 is in closed-loop control, and the third DC voltage Vout1 output by each secondary output subunit 230 on the isolation side is in an open-loop state, and the output voltage accuracy is difficult to guarantee. The common practice at present is to operate the output side (primary side) of the second DC voltage Vout0 in a forced continuous conduction mode (FCCM), but the forced continuous conduction mode has low efficiency at light load and is not suitable for all working scenarios.

[0043] Please refer to Figure 5 and Figure 6 , which are a logic control schematic diagram of a switch tube circuit and a waveform schematic diagram of a switch tube control signal in an embodiment, respectively. After the initialization of the multi-output synchronous buck converter is completed, if there is no error, the switch trigger signal HSD_ON will trigger the conduction of the upper switch tube Q1. At this time, the secondary diode D1 of each secondary output subunit 230 on the isolation side is in a cut-off state, the secondary inductor current IS1 of the secondary output subunit 230 on the isolation side is 0, and the output current of the secondary output subunit 230 on the isolation side is provided by the secondary output capacitor C1. On the non-isolation side, the first DC voltage Vin and the second DC voltage Vout0 are superimposed on both ends of the primary inductor L0, and the inductor current rises linearly; the switch tube drive signal HSD_OFF triggers the upper switch tube Q1 to be turned off, at which time the lower switch tube Q2 is in an off state, and the inductor current flows through the body diode of the lower switch tube Q2; after the dead time ends (both the upper switch tube Q1 and the lower switch tube Q2 are turned off), the lower switch tube Q2 is turned on, and the inductor current flows through the lower switch tube Q2, at which time the secondary diode D1 of the secondary output subunit 230 on the isolation side is in a forward conduction state, and the secondary output capacitor C1 of the secondary output subunit 230 on the isolation side is charged; the primary inductor current IP is equal to the sum of each secondary inductor current IS1 and the primary excitation current multiplied by the turns ratio coefficient of the transformer; during this process, the inductor current is in a forced conduction state, which is called a forced current continuous conduction mode (FCCM); in this mode, the charge on each secondary output capacitor C1 on the isolation side is supplemented during the conduction of the lower switch tube Q2, and the output voltage of the secondary output subunit 230 on the isolation side is basically stable.

[0044] In an embodiment of the present application, the multi-output synchronous buck converter operates in a hybrid control mode (FCCM+DCM) at light load, solves the problem of reduced efficiency at light load, and realizes good load regulation of the output on the isolation side.

[0045] Please refer to Figure 7For another embodiment of the logic control diagram of the switch tube circuit, the upper tube driving signal HG includes an upper tube conducting level signal and an upper tube closing level signal, the upper switch tube Q1 is turned on when the upper tube driving signal HG keeps at the upper tube conducting level signal, and the upper switch tube Q1 is turned off when the upper tube driving signal HG keeps at the upper tube closing level signal; the lower tube driving signal LG includes a lower tube conducting level signal and a lower tube closing level signal, the lower switch tube Q2 is turned on when the lower tube driving signal LG keeps at the lower tube conducting level signal, and the lower switch tube Q2 is turned off when the lower tube driving signal LG keeps at the lower tube closing level signal. At any time, when the upper tube driving signal HG is the upper tube conducting level signal, the lower tube driving signal LG cannot be the lower tube conducting level signal, so as to ensure that the upper switch tube Q1 and the lower switch tube Q2 cannot be turned on at the same time. In each signal period T, the upper tube driving signal HG includes continuous upper tube conducting duration and continuous upper tube closing duration, the upper tube driving signal HG keeps at the upper tube conducting level signal in the upper tube conducting duration, and the upper tube driving signal HG keeps at the upper tube closing level signal in the upper tube closing duration. In the signal period T, the lower tube driving signal LG includes continuous first lower tube conducting duration and continuous second lower tube conducting duration, the lower tube driving signal LG keeps at the lower tube conducting level signal in the first lower tube conducting duration and the second lower tube conducting duration. In the signal period T, the upper tube conducting duration and the first lower tube conducting duration are continuous in time, and when the upper tube driving signal HG is in the upper tube conducting duration and the lower tube driving signal LG is in the first lower tube conducting duration, the direction of the output current of the primary side output subunit is the second direction. When the lower tube driving signal LG is in the second lower tube conducting duration, the direction of the output current of the primary side output subunit is the first direction, and the first direction and the second direction are opposite.

[0046] In an embodiment, the second lower tube conducting duration is continuous in time with the upper tube conducting duration, and before the upper tube conducting duration.

[0047] In an embodiment, the second lower tube conducting duration is continuous in time with the first lower tube conducting duration, and after the first lower tube conducting duration.

[0048] In an embodiment, the second lower tube conducting duration is not continuous in time with the first lower tube conducting duration and the upper tube conducting duration, and between the first lower tube conducting duration and the upper tube conducting duration.

[0049] In the above embodiments, in order to realize the logic control of the above switch tube circuit, a variable k can be input through an external pin or a built-in control, which can be an analog input or a digital input, so that the controller can work in FCCM mode, PFM mode or CCM+DCM mixed mode (frequency higher than a certain value). The multifunctional input variable k is used as a mixed working mode, which sets the controller switching period to be shorter than T. By additionally turning on the lower switch tube Q2 for a period of time, the controller working in the discontinuous current mode (DCM) is realized. The setting method of the additional conduction time includes:

[0050] 1) After the current of the primary side output subunit on the non-isolation side passes zero, the lower switch tube Q2 is turned on for a period of time t;

[0051] Please refer to Figure 8 , which is a switch tube circuit logic control schematic diagram of the first additional conduction time setting method in an embodiment. The switch tube circuit logic control schematic diagram can realize that the second lower tube conduction duration period is continuous with the first lower tube conduction duration period and after the first lower tube conduction duration period.

[0052] 2) When the upper switch tube Q1 and the lower switch tube Q2 are both off, an additional conduction time t is turned on;

[0053] Please refer to Figure 9 , which is a switch tube circuit logic control schematic diagram of the second additional conduction time setting method in an embodiment. The switch tube circuit logic control schematic diagram can realize that the second lower tube conduction duration period is not continuous with the first lower tube conduction duration period and the upper tube conduction duration period, and between the first lower tube conduction duration period and the upper tube conduction duration period.

[0054] 3) Before the lower switch tube Q2 is turned on, an additional conduction time t is turned on.

[0055] Please refer to Figure 10 , which is a switch tube circuit logic control schematic diagram of the third additional conduction time setting method in an embodiment. The switch tube circuit logic control schematic diagram can realize that the second lower tube conduction duration period is continuous with the upper tube conduction duration period and before the upper tube conduction duration period.

[0056] In the three additional conduction periods of the lower switch Q2 as described above, the direction of the inductor current of the primary side output subunit on the non-isolated side is the second DC Vout to the switch circuit direction (second direction), and the rectifier diode (secondary diode D1) of the secondary side output subunit on the isolated side is in the forward conduction state, and the output capacitor (secondary output capacitor C1) is charged to maintain the output voltage stable. When the lower switch Q2 is closed, the inductor current of the primary side output subunit on the non-isolated side cannot be abruptly changed, and continues to flow through the body diode of the upper switch Q1 or the upper switch Q1 is turned on, and the rectifier diode of the secondary side output subunit on the isolated side continues to be in the forward conduction state, and the output capacitor is charged. In this embodiment, by adjusting the input variable k, the longest switching period of the controller is always less than a value T0, which ensures that the voltage output by each secondary side output subunit on the isolated side is within the required range. The duration t of the second lower tube conduction duration is related to the capacity value of the capacitor in the primary side output subunit.

[0057] Please refer to Figure 11 , a flowchart of a converter control method in an embodiment, in an embodiment of the present application, a converter control method is also disclosed, which is applied to the multi-output synchronous buck converter as described above, and the control method comprises:

[0058] Step 1000, using FCCM mode control.

[0059] In a control cycle T of the switch circuit, the switch circuit is controlled by FCCM mode to make the direction of the output current of the primary side output subunit be the first direction.

[0060] Step 2000, using DCM mode control.

[0061] In the control cycle T, and when the upper switch Q1 and the lower switch Q2 of the switch circuit are both cut off, the switch circuit is controlled by DCM mode to make the direction of the output current of the primary side output subunit be the second direction, wherein the first direction and the second direction are opposite.

[0062] In an embodiment, in each control cycle T, the DCM mode is set before or after the FCCM mode.

[0063] The converter control method disclosed in the application is to control the switch tube circuit in FCCM mode in one control period T of the multi-output synchronous buck converter, and to control the multi-output synchronous buck converter in DCM mode when the switch tubes of the switch tube circuit of the multi-output synchronous buck converter are all off in the control period T, wherein the directions of the primary side output subunit current of the multi-output synchronous buck converter are opposite to each other when controlled in FCCM mode and when controlled in DCM mode. Since the multi-output synchronous buck converter is controlled in FCCM mode and DCM mode respectively in one control period T, the technical problem that the conversion efficiency of the multi-output synchronous buck converter is reduced at light load is solved, and the isolated side output can have a good load regulation.

[0064] The above application of specific examples to the application is described, only to help understand the application, and not to limit the application. For those skilled in the art to which the application belongs, according to the idea of the application, a number of simple deductions, deformations or substitutions can be made.

Claims

1. A control method for a multiple output synchronous buck converter, characterized by, The multi-output synchronous buck converter comprises a loop control logic output circuit and an isolated multi-output synchronous buck circuit; The loop control logic output circuit is configured to send an upper tube driving signal HG and a lower tube driving signal LG to a switch tube circuit in the isolated multi-output synchronous buck circuit, so as to realize switch control of power switch tubes in the switch tube circuit; The isolated multi-output synchronous buck circuit further comprises a primary side output subunit and n secondary side output subunits, and n is a natural number; the switch tube circuit comprises an upper switch tube Q1 and a lower switch tube Q2; the switch control poles of the upper switch tube Q1 and the lower switch tube Q2 are respectively responsive to the upper tube driving signal HG and the lower tube driving signal LG to realize switch control, so as to output electric energy of a first direct current Vin to the primary side output subunit and each secondary side output subunit; The primary side output subunit is configured to output electric energy converted from the electric energy output by the switch tube circuit to the primary side output subunit as a second direct current Vout0; Each secondary side output subunit is configured to output electric energy converted from the electric energy output by the switch tube circuit to the secondary side output subunit as a third direct current Vout1; The upper tube driving signal HG comprises an upper tube on level signal and an upper tube off level signal; when the upper tube driving signal HG is kept at the upper tube on level signal, the upper switch tube Q1 is turned on; when the upper tube driving signal HG is kept at the upper tube off level signal, the upper switch tube Q1 is turned off; The lower tube driving signal LG comprises a lower tube on level signal and a lower tube off level signal; when the lower tube driving signal LG is kept at the lower tube on level signal, the lower switch tube Q2 is turned on; when the lower tube driving signal LG is kept at the lower tube off level signal, the lower switch tube Q2 is turned off; At any time, when the upper tube driving signal HG is the upper tube on level signal, the lower tube driving signal LG cannot be the lower tube on level signal, so as to ensure that the upper switch tube Q1 and the lower switch tube Q2 cannot be turned on at the same time; In each signal period T, the upper tube driving signal HG comprises a continuous upper tube on duration period and a continuous upper tube off time period; in the upper tube on duration period, the upper tube driving signal HG is kept at the upper tube on level signal; in the upper tube off time period, the upper tube driving signal HG is kept at the upper tube off level signal; In the signal period T, the lower tube driving signal LG comprises a continuous first lower tube on duration period and a continuous second lower tube on duration period; in the first lower tube on duration period and the second lower tube on duration period, the lower tube driving signal LG is kept at the lower tube on level signal; In the signal period T, the upper tube conduction duration period and the first lower tube conduction duration period are continuous in time, and when the upper tube drive signal HG is in the upper tube conduction duration period and the lower tube drive signal LG is in the first lower tube conduction duration period, the direction of the current output by the primary side output subunit is the first direction; when the lower tube drive signal LG is in the second lower tube conduction duration period, the direction of the current output by the primary side output subunit is the second direction, and the first direction and the second direction are opposite directions; The loop control logic output circuit includes an On-Time generation circuit, a feedback signal acquisition circuit, a switch trigger signal generation circuit, and a control signal output circuit; The On-Time generation circuit is connected with the control signal output circuit, and is configured to generate a switch tube drive signal HSD_OFF to the control signal output circuit; The feedback signal acquisition circuit is connected with the primary side output subunit and the switch trigger signal generation circuit respectively, and is configured to sample a second direct current Vout0 output by the primary side output subunit, and output a feedback signal acquired by sampling to the switch trigger signal generation circuit; The switch trigger signal generation circuit is connected with the control signal output circuit, and is configured to output a switch trigger signal HSD_ON to the control signal output circuit according to the feedback signal; The control signal output circuit is configured to send the upper tube drive signal HG and the lower tube drive signal LG to the switch tube circuit according to the switch tube drive signal HSD_OFF and the switch trigger signal HSD_ON; The control method comprises: In one control period T of the switch tube circuit, the FCCM working mode control is adopted for the switch tube circuit, so that the direction of the current output by the primary side output subunit is the second direction; In the control period T, when the upper switch tube Q1 and the lower switch tube Q2 of the switch tube circuit are both cut off, the DCM working mode control is adopted for the switch tube circuit, so that the direction of the current output by the primary side output subunit is the first direction.

2. The control method according to claim 1, characterized by, Further comprising: In each control period T, the DCM working mode is arranged before or after the FCCM working mode.

3. The control method according to claim 1, characterized by, The second lower tube conduction duration period is continuous in time with the upper tube conduction duration period, and is before the upper tube conduction duration period.

4. The control method according to claim 1, characterized by, The second lower tube conduction duration period is continuous in time with the first lower tube conduction duration period, and is after the first lower tube conduction duration period.

5. The control method according to claim 1, characterized by, The second lower tube conduction duration period is not continuous in time with the first lower tube conduction duration period and the upper tube conduction duration period, and is between the first lower tube conduction duration period and the upper tube conduction duration period.

6. The control method according to claim 1, characterized by, The duration t of the second lower tube conduction duration period is related to the capacity value of the capacitor in the primary side output subunit.

7. The control method according to claim 1, characterized by, The feedback signal acquisition circuit comprises a sampling input end, a sampling output end, a first resistor R1 and a second resistor R2; The sampling input end is connected with the primary side output subunit and is used for input of the second direct current Vout0; The sampling output end is connected with the switch trigger signal generation circuit and is used for output of the feedback signal to the switch trigger signal generation circuit; One end of the first resistor R1 is connected with the sampling input end, and the other end is connected with the sampling output end; One end of the second resistor R2 is connected with the sampling output end, and the other end is grounded.

Images