A cross-coupled charge pump circuit

Abstract

The application discloses a cross-coupled charge pump circuit, comprising: a first charge-discharge circuit, which is used for charging and discharging a first capacitor under the control of a zero clock and a first clock to generate a first high-voltage pulse; a second charge-discharge circuit, which is used for charging and discharging a second capacitor under the control of an inverted zero clock and a second clock to generate a second high-voltage pulse; a first transmission circuit, which is used for transmitting the first high-voltage pulse generated by the first charge-discharge circuit to a load under the control of an inverted second clock; a second transmission circuit, which is used for transmitting the second high-voltage pulse generated by the second charge-discharge circuit to the load under the control of an inverted first clock; a four-phase non-overlapping clock generation circuit, which is used for converting an input clock source into the non-overlapping zero clock, the inverted zero clock, the first clock, the inverted first clock, the second clock and the inverted second clock; and the load. By the application, the efficiency of the charge pump structure can be greatly improved.

Description

Technical Field

[0001] This invention relates to a cross-coupled charge pump circuit, and more particularly to a cross-coupled charge pump circuit employing a four-phase non-overlapping clock. Background Technology

[0002] The charge pump circuit is one of the most important circuits in the entire Flash memory, determining the area and power consumption of the Flash memory.

[0003] Existing charge pump circuits such as Figure 1 As shown, the circuit includes: a clock circuit 10, a charging / discharging circuit 20, a substrate voltage adjustment circuit 30, a transmission circuit 40, and a load 50. The clock circuit 10 consists of a clock source CLK, inverters I1, I2, and I3, used to generate an output clock CLKK and an inverted output clock CLKKB. The charging / discharging circuit 20 consists of NMOS transistors MN1 and MN2 and charging / discharging capacitors C1 and C2, used to generate pulsed high voltage through the charging and discharging of capacitors C1 and C2 under the control of the output clock. The transmission circuit 40 consists of PMOS transistors MP3 and MP4, used to transmit the pulsed high voltage generated by the charging / discharging circuit 20 to the load 50. The substrate voltage adjustment circuit 30 consists of PMOS transistors MP1 and MP2, used to adjust the substrate voltage of the transmission transistors MP3 and MP4 to reduce substrate bias. The load 50 consists of a load resistor RL and a load capacitor CL, used to simulate the load of a charge pump.

[0004] Figure 2 , Figure 3 The figures show the power supply current waveform during clock transitions in an existing charge pump circuit, as well as the output voltage and efficiency curves as a function of load current. It is evident that in existing charge pump circuits, the clock signal is strictly inverted, resulting in short-term simultaneous conduction of MOSFETs. Consequently, efficiency is relatively low and power consumption is relatively high. To meet output load requirements, the wafer area used inevitably increases, raising chip costs. Summary of the Invention

[0005] To overcome the shortcomings of the existing technology, the present invention aims to provide a cross-coupled charge pump circuit that can significantly improve the efficiency of the charge pump structure.

[0006] To achieve the above and other objectives, the present invention proposes a cross-coupled charge pump circuit, comprising:

[0007] The first charging and discharging circuit is used to charge and discharge the first capacitor (C1) under the control of the zero clock (clk) and the first clock (clk1) to generate a first high voltage pulse;

[0008] The second charging and discharging circuit is used to charge and discharge the second capacitor (C2) under the control of the inverted zero clock (clkb) and the second clock (clk2) to generate a second high voltage pulse;

[0009] The first transmission circuit is used to transmit the first high-voltage pulse generated by the first charging and discharging circuit to the load under the control of the inverted second clock (clk2b);

[0010] The second transmission circuit is used to transmit the second high-voltage pulse generated by the second charging and discharging circuit to the load under the control of the inverted first clock (clk1b);

[0011] A four-phase non-overlapping clock generation circuit is used to convert the input clock source into non-overlapping zeroth clock (clk), inverted zeroth clock (clkb), first clock (clk1), inverted first clock (clk1b), second clock (clk2), and inverted second clock (clk2b); and

[0012] load.

[0013] Optionally, the four-phase non-overlapping clock generation circuit is connected to an input clock source to generate the zeroth clock (clk), the first clock (clk1), and the inverted second clock (clk2b) with high levels that do not overlap, as well as the inverted zeroth clock (clkb), the second clock (clk2), and the inverted first clock (clk1b) with high levels that do not overlap.

[0014] Optionally, the four-phase non-overlapping clock generation circuit includes a first NOR gate (NR1), second to sixth NOT gates, a seventh AND gate (AD7), an eighth OR gate (OR8), a tenth NOT gate (I10), an eleventh NOR gate (NR11), twelfth to sixteenth NOT gates, a seventeenth AND gate (AD7), an eighteenth OR gate (OR8), and a third capacitor (C3), a fourth capacitor (C4), a thirteenth capacitor (C13), and a fourteenth capacitor (C14). One input terminal of the first NOR gate (NR1) and the input terminal of the tenth NOT gate (I10) are connected to form the input terminal of the four-phase non-overlapping clock generation circuit and connected to the input clock source. The output terminal of the tenth NOT gate (I10) is connected to the eleventh OR gate. One input terminal of NOT gate (NR11) is connected to the input terminal of the first NOR gate (NR1). The output terminal of the second NOT gate (I2) is connected to the input terminal of the third NOT gate (I3) and one end of the third capacitor (C3). The output terminal of the third NOT gate (I3) is connected to the input terminal of the fourth NOT gate (I4), one input terminal of the seventh AND gate (AD7), one input terminal of the eighth OR gate (OR8), and the other input terminal of the eleventh NOR gate (NR11). The output terminal of the eleventh NOR gate (NR11) is connected to the input terminal of the twelfth NOT gate (I12). The output terminal of the twelfth NOT gate (I12) is connected to the input terminal of the thirteenth NOT gate (I13) and the thirteenth capacitor (C13). At one end, the output of the thirteenth NOT gate (I13) is connected to the input of the fourteenth NOT gate (I14), one input of the seventeenth AND gate (AD17), one input of the eighteenth OR gate (OR18), and the other input of the first NOR gate (NR1). The output of the fourth NOT gate (I4) is connected to the input of the fifth NOT gate (I5) and one end of the fourth capacitor (C4). The output of the fifth NOT gate (I5) is connected to the other input of the seventh AND gate (AD7) and the other input of the eighth OR gate (OR8). The output of the fourteenth NOT gate (I14) is connected to the input of the fifteenth NOT gate (I15) and one end of the fifth capacitor (C5). The output of the fifteenth NOT gate (I15) is connected to... The other input of the seventeenth AND gate (AD17) and the other input of the eighteenth OR gate (OR18), the output of the seventh AND gate (AD7) of the second clock (clk2) is connected to the input of the sixth NOT gate (I16), the output of the sixth NOT gate (I6) of the inverted second clock (clk2b), the output of the eighth OR gate (OR8) of the zero clock (clk), the output of the seventeenth AND gate (AD17) of the first clock (clk1) is connected to the input of the sixteenth NOT gate (I16), the output of the sixteenth NOT gate (I16) of the inverted first clock (clk1b), and the output of the eighteenth OR gate (OR18) of the inverted zero clock (clkb).

[0015] Optionally, the first charging / discharging circuit and the second charging / discharging circuit are symmetrical circuits.

[0016] Optionally, the first charging and discharging circuit includes a first NMOS transistor (MN1), a third NMOS transistor (MN3), a first capacitor (C1), and a first auxiliary capacitor (Ca1). The zero clock (clk) is connected to one end of the first capacitor (C1), and the first clock (clk1) is connected to one end of the first auxiliary capacitor (Ca1). The source and substrate of the first NMOS transistor (MN1) and the source and substrate of the third NMOS transistor (MN3) are connected to a power supply (Vin). The gate of the first NMOS transistor (MN1), the drain of the third NMOS transistor (MN3), and the other end of the first auxiliary capacitor (Ca1) form node vn1. The drain of the first NMOS transistor (MN1), the gate of the third NMOS transistor (MN3), the other end of the first capacitor (C1), and the source of the first PMOS transistor (MP1) form node A.

[0017] Optionally, the second charging and discharging circuit includes a second NMOS transistor (MN2), a fourth NMOS transistor (MN4), a second capacitor (C2), and a second auxiliary capacitor (Ca2). The inverting zero-order clock (clkb) is connected to one end of the second capacitor (C2), and the second clock (clk2) is connected to one end of the second auxiliary capacitor (Ca2). The source and substrate of the second NMOS transistor (MN2) and the source and substrate of the fourth NMOS transistor (MN4) are connected to the power supply (Vin). The drain of the second NMOS transistor (MN2), the gate of the fourth NMOS transistor (MN4), the other end of the second capacitor (C2), and the source of the second PMOS transistor (MP2) form node B. The gate of the second NMOS transistor (MN2), the drain of the fourth NMOS transistor (MN4), and the other end of the second auxiliary capacitor (Ca2) form node vn2.

[0018] Optionally, the first transmission circuit and the second transmission circuit are symmetrical circuits.

[0019] Optionally, the first transmission circuit includes a fifth NMOS transistor (MN5), a first PMOS transistor (MP1), and a third auxiliary capacitor (Cb1). The inverting second clock (clk2b) is connected to one end of the third auxiliary capacitor (Cb1). The source, substrate, and gate of the fifth NMOS transistor (MN5) are connected to the power supply Vin. The drain of the fifth NMOS transistor (MN5), the gate of the first PMOS transistor (MP1), and the other end of the third auxiliary capacitor (Cb1) form a node Vp1. The drain and substrate of the first PMOS transistor (MP1) are connected to the second transmission circuit to form an output node Vout. The output node Vout is connected to the load.

[0020] Optionally, the second transmission circuit includes a sixth NMOS transistor (MN6), a second PMOS transistor (MP2), and a fourth auxiliary capacitor (Cb2). The inverting first clock (clk1b) is connected to one end of the fourth auxiliary capacitor (Cb2). The source, substrate, and gate of the sixth NMOS transistor (MN6) are connected to the power supply Vin. The drain of the sixth NMOS transistor (MN6), the gate of the second PMOS transistor (MP2), and the other end of the fourth auxiliary capacitor (Cb2) form a node Vp2. The drain and substrate of the second PMOS transistor (MP2) and the drain and substrate of the first PMOS transistor (MP1) are connected to form the output node.

[0021] Optionally, the load includes a load resistor (RL) and a load capacitor (CL), the output node (Vout) is connected to one end of the load resistor (RL) and one end of the load capacitor (CL), and the other end of the load resistor (RL) and the other end of the load capacitor (CL) are grounded.

[0022] Compared with the prior art, the cross-coupled charge pump circuit of the present invention has no high-level overlap between the zero clock clk and the first clock clk1 generated by the four-phase non-overlapping clock generation circuit, and between the inverted zero clock clkb and the second clock clk2. The high-level "1" of the inverted second clock clk2b and the inverted first clock clk1b, which are responsible for closing the discharge path, is wider, avoiding short circuits, thereby effectively improving the efficiency of the charge pump. Attached Figure Description

[0023] Figure 1 This is a circuit diagram of a prior art charge pump circuit;

[0024] Figure 2 The waveform of the power supply current during clock transitions for an existing charge pump circuit;

[0025] Figure 3 The graph shows the output voltage and efficiency of an existing charge pump circuit as a function of load current.

[0026] Figure 4 This is a circuit structure diagram of a cross-coupled charge pump circuit according to the present invention;

[0027] Figure 5 This is a circuit structure diagram of a four-phase non-overlapping clock generation circuit in a specific embodiment of the present invention;

[0028] Figure 6 This is a waveform diagram of the power supply current during the four-phase non-overlapping clock and voltage conversion of the present invention. Detailed Implementation

[0029] The following describes the embodiments of the present invention through specific examples and in conjunction with the accompanying drawings. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Figure 4 This is a circuit diagram of a cross-coupled charge pump circuit according to the present invention. Figure 4 As shown, the present invention discloses a cross-coupled charge pump circuit, comprising: a first charge-discharge circuit 10, a second charge-discharge circuit 20, a first transmission circuit 30, a second transmission circuit 40, a four-phase non-overlapping clock generation circuit 50, and a load 60.

[0031] The first charging / discharging circuit 10 includes a first NMOS transistor MN1, a third NMOS transistor MN3, a first capacitor C1, and a first auxiliary capacitor Ca1, used to charge and discharge the first capacitor C1 under the control of the zero clock clk and the first clock clk1 to generate a first high-voltage pulse; the second charging / discharging circuit 20 includes a second NMOS transistor MN2, a fourth NMOS transistor MN4, a second capacitor C2, and a second auxiliary capacitor Ca2, used to charge and discharge the second capacitor C2 under the control of the inverted zero clock clkb and the second clock clk2 to generate a second high-voltage pulse; the first transmission circuit 30 includes a fifth NMOS transistor MN5, a first PMOS transistor MP1, and a third auxiliary capacitor Cb1, used to transmit the first high-voltage pulse generated by the first charging / discharging circuit 10 to the load 60 under the control of the inverted second clock clk2b; the second transmission circuit 40 includes a sixth NMOS transistor MN6, a second PMOS transistor MP2, and a fourth auxiliary capacitor Cb2, used to transmit the second high-voltage pulse generated by the second charging / discharging circuit 20 under the control of the inverted first clock clk1b. Pulse transmission to load 60; a four-phase non-overlapping clock generation circuit 50, including: a first NOR gate NR1, second to sixth NOT gates I2-I6, a seventh AND gate AD7, an eighth OR gate OR8, a tenth NOT gate, an eleventh NOR gate NR11, twelfth to sixteenth NOT gates I12-I16, a seventeenth AND gate AD7, an eighteenth OR gate OR8, and a third capacitor C3, a fourth capacitor C4, a thirteenth capacitor C13, and a fourteenth capacitor C14, used to convert the input clock source clkin into a zero-th clock clk, an inverted zero-th clock clkb, and a first clock. clk1, inverted first clock clk1b, second clock clk2, and inverted second clock clk2b ensure that the high levels of the three clock signals used in the upper branch—zero clock clk, first clock clk1, and inverted second clock clk2b—do not overlap (non-overlapping clocks), and the high levels of the three clock signals used in the lower branch—inverted zero clock clkb, second clock clk2, and inverted first clock clk1b—do not overlap (non-overlapping clocks); the load 60 includes: load resistor RL and load capacitor CL, used to simulate the load of a charge pump.

[0032] Specifically, the zeroth clock clk is connected to one end of the first capacitor C1, the inverted zeroth clock clkb is connected to one end of the second capacitor C2, the first clock clk1 is connected to one end of the first auxiliary capacitor Ca1, and the second clock clk2 is connected to one end of the second auxiliary capacitor Ca2; the source and substrate of the first NMOS transistor MN1, the source and substrate of the third NMOS transistor MN3, the source and substrate of the second NMOS transistor MN2, and the source and substrate of the fourth NMOS transistor MN4 are connected to the power supply Vin, and the gate of the first NMOS transistor MN1 is connected to the gate of the third NMOS transistor MN3. The drain of the first NMOS transistor MN1 and the other end of the first auxiliary capacitor Ca1 form node vn1. The drain of the first NMOS transistor MN1, the gate of the third NMOS transistor MN3, the other end of the first capacitor C1, and the source of the first PMOS transistor MP1 form node A. The drain of the second NMOS transistor MN2, the gate of the fourth NMOS transistor MN4, the other end of the second capacitor C2, and the source of the second PMOS transistor MP2 form node B. The gate of the second NMOS transistor MN2, the drain of the fourth NMOS transistor MN4, and the other end of the second auxiliary capacitor Ca2 form node vn2.

[0033] The inverted second clock clk2b is connected to one end of the third auxiliary capacitor Cb1, and the inverted first clock clk1b is connected to one end of the fourth auxiliary capacitor Cb2. The source, substrate, and gate of the fifth NMOS transistor MN5 and the source, substrate, and gate of the sixth NMOS transistor MN6 are connected to the power supply Vin. The drain of the fifth NMOS transistor MN5, the gate of the first PMOS transistor MP1, and the other end of the third auxiliary capacitor Cb1 form node Vp1. The drain of the sixth NMOS transistor MN6, the gate of the second PMOS transistor MP2, and the other end of the fourth auxiliary capacitor Cb2 form node Vp2. The drain and substrate of the first PMOS transistor MP1 and the drain and substrate of the second PMOS transistor MP2 are connected to form output node Vout. Output node Vout is connected to one end of the load resistor RL and one end of the load capacitor CL. The other end of the load resistor RL and the other end of the load capacitor CL are grounded.

[0034] The input clock source clkin is connected to the input terminal of the four-phase non-overlapping clock generation circuit 50. The output of the four-phase non-overlapping clock generation circuit 50 is the zero clock clk, the inverted zero clock clkb, the first clock clk1, the inverted first clock clk1b, the second clock clk2, and the inverted second clock clk2b.

[0035] Specifically, the detailed structure of the four-phase non-overlapping clock generation circuit 50 is as follows: Figure 5As shown, one input terminal of the first NOR gate NR1 and the input terminal of the tenth NOT gate I10 are connected to form the input terminal of the four-phase non-overlapping clock generation circuit 50 and connected to the input clock source clkin. The output terminal of the tenth NOT gate I10 is connected to one input terminal of the eleventh NOR gate NR11.

[0036] The output of the first NOR gate NR1 is connected to the input of the second NOT gate I2. The output of the second NOT gate I2 is connected to the input of the third NOT gate I3 and one end of the third capacitor C3. The output of the third NOT gate I3 is connected to the input of the fourth NOT gate I4, one input of the seventh AND gate AD7, one input of the eighth OR gate OR8, and the other input of the eleventh NOR gate NR11. The output of the eleventh NOR gate NR11 is connected to the input of the twelfth NOT gate I12. The output of the twelfth NOT gate I12 is connected to the input of the thirteenth NOT gate I13 and one end of the thirteenth capacitor C13. The output of the thirteenth NOT gate I13 is connected to the input of the fourteenth NOT gate I14, one input of the seventeenth AND gate AD17, one input of the eighteenth OR gate OR18, and the other input of the first NOR gate NR1.

[0037] The output of the fourth NOT gate I4 is connected to the input of the fifth NOT gate I5 and one end of the fourth capacitor C4. The output of the fifth NOT gate I5 is connected to the other input of the seventh AND gate AD7 and the other input of the eighth OR gate OR8. The output of the fourteenth NOT gate I14 is connected to the input of the fifteenth NOT gate I15 and one end of the fifth capacitor C5. The output of the fifteenth NOT gate I15 is connected to the other input of the seventeenth AND gate AD17 and the other input of the eighteenth OR gate OR18.

[0038] The output of the seventh AND gate AD7, i.e. the second clock clk2, is connected to the input of the sixth NOT gate I16. The output of the sixth NOT gate I6 is the inverted second clock clk2b. The output of the eighth OR gate OR8 is the zero clock clk. The output of the seventeenth AND gate AD17, i.e. the first clock clk1, is connected to the input of the sixteenth NOT gate I16. The output of the sixteenth NOT gate I16 is the inverted first clock clk1b. The output of the eighteenth OR gate OR18 is the inverted zero clock clkb.

[0039] Figure 6 This is a waveform diagram of the power supply current during the four-phase non-overlapping clock and voltage transition of this invention. In this invention, because... Figure 4 Since this is a symmetrical circuit, the following will only use the upper half as an example. Figure 4 and Figure 6 Explanation of the working principle of this invention:

[0040] After power-on, nodes A, vn1, and Vp1 are pre-charged to Vin-Vthn. The source and gate of the fifth NMOS transistor MN5 are shorted, which is equivalent to a diode. Therefore, the pre-charge voltage of node Vp1 is also Vin-Vthn. Vthn is the threshold voltage of NMOS transistors MN1 / MN3 / MN5. Assume that the threshold voltages of NMOS transistors MN1-MN6 are all Vthn, the threshold voltages of PMOS transistors MP1-MP2 are Vthp, and the voltage of the high level "1" of all clocks is Vh.

[0041] When clk is low ("0"), when clk1 changes from "0" to "1", since the voltage of the first auxiliary capacitor Ca1 cannot change abruptly, the voltage of node vn1, i.e., the gate voltage of the first NMOS transistor MN1, is boosted to Vh+(Vin-Vthn), thus turning on the first NMOS transistor MN1. The first capacitor C1 is charged, and the voltage of node A, i.e., the gate voltage of the third NMOS transistor MN3, is pre-charged to Vin-Vthn. The third NMOS transistor MN3 is turned off, further stabilizing the voltage of node vn1. When clk2b changes from "0" to "1", since the voltage of the third auxiliary capacitor Cb1 cannot change abruptly, the voltage of node Vp1 is boosted to Vh+(Vin-Vthn), and the first PMOS transistor M... P1 is turned off to further prevent charge loss at node A. When clk1 goes low to "0", node vn1 drops to Vin-Vthn, and the first NMOS transistor MN1 is turned off. Then, when clk changes from "0" to "1", since the voltage of the first capacitor C1 cannot change abruptly, the gate voltage of node A, i.e., the third NMOS transistor MN3, is raised to Vh+(Vin-Vthn), so the third NMOS transistor MN3 is turned on, and the voltage of node vn1 is stabilized at Vin-Vthn. At the same time, clk2b jumps to low to "0", the voltage of node Vp1 drops, the first PMOS transistor MP1 is turned on, and the charge of node A moves to the load RL / CL through the first PMOS transistor MP1, i.e., the first capacitor C1 is discharged.

[0042] The clock signals in the lower half are out of phase with those in the upper half; that is, clk and clkb are out of phase, clk2 and clk1 are out of phase, and clk1b and clk2b are out of phase. When clk changes from "0" to "1", the first capacitor C1 in the upper half of the circuit discharges to the load RL / CL. Due to the out of phase, the lower half of the circuit is charging the second capacitor C2. When clkb changes from "0" to "1", the second capacitor C2 in the lower half of the circuit discharges to the load RL / CL. Due to the out of phase, the upper half of the circuit is charging the first capacitor C1.

[0043] Since there is no high-level overlap between clock clk and clk1, and between clkb and clk2, the high-level "1" of clock clk2b and clk1b, which are responsible for shutting down the discharge path, is relatively wide, thus avoiding short circuits and effectively improving the efficiency of the charge pump.

[0044] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can make modifications and changes to the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the claims.

Claims

1. A cross-coupled charge pump circuit, comprising: The first charging and discharging circuit is used to charge and discharge the first capacitor (C1) under the control of the zero clock (clk) and the first clock (clk1) to generate a first high voltage pulse; The second charging and discharging circuit is used to charge and discharge the second capacitor (C2) under the control of the inverted zero clock (clkb) and the second clock (clk2) to generate a second high voltage pulse; The first transmission circuit is used to transmit the first high-voltage pulse generated by the first charging and discharging circuit to the load under the control of the inverted second clock (clk2b); The second transmission circuit is used to transmit the second high-voltage pulse generated by the second charging and discharging circuit to the load under the control of the inverted first clock (clk1b); A four-phase non-overlapping clock generation circuit is used to convert the input clock source into the zeroth clock (clk), the inverted zeroth clock (clkb), the first clock (clk1), the inverted first clock (clk1b), the second clock (clk2), and the inverted second clock (clk2b). The high levels of the zeroth clock (clk) and the first clock (clk1) do not overlap; the high levels of the zeroth clock (clk) and the inverted second clock (clk2b) do not overlap; the high levels of the inverted zeroth clock (clkb) and the second clock (clk2) do not overlap; and the high levels of the inverted zeroth clock (clkb) and the inverted first clock (clk1b) do not overlap. load; The first charging and discharging circuit includes a first NMOS transistor (MN1), a third NMOS transistor (MN3), a first capacitor (C1), and a first auxiliary capacitor (Ca1). The zero clock (clk) is connected to one end of the first capacitor (C1), and the first clock (clk1) is connected to one end of the first auxiliary capacitor (Ca1). The source and substrate of the first NMOS transistor (MN1) and the source and substrate of the third NMOS transistor (MN3) are connected to the power supply Vin. The gate of the first NMOS transistor (MN1), the drain of the third NMOS transistor (MN3), and the other end of the first auxiliary capacitor (Ca1) form node vn1. The drain of the first NMOS transistor (MN1), the gate of the third NMOS transistor (MN3), the other end of the first capacitor (C1), and the source of the first PMOS transistor (MP1) form node A. The second charging and discharging circuit includes a second NMOS transistor (MN2), a fourth NMOS transistor (MN4), a second capacitor (C2), and a second auxiliary capacitor (Ca2). The inverting zero-order clock (clkb) is connected to one end of the second capacitor (C2), and the second clock (clk2) is connected to one end of the second auxiliary capacitor (Ca2). The source and substrate of the second NMOS transistor (MN2) and the source and substrate of the fourth NMOS transistor (MN4) are connected to the power supply Vin. The drain of the second NMOS transistor (MN2), the gate of the fourth NMOS transistor (MN4), the other end of the second capacitor (C2), and the source of the second PMOS transistor (MP2) form node B. The gate of the second NMOS transistor (MN2), the drain of the fourth NMOS transistor (MN4), and the other end of the second auxiliary capacitor (Ca2) form node vn2. The first transmission circuit includes a fifth NMOS transistor (MN5), a first PMOS transistor (MP1), and a third auxiliary capacitor (Cb1). The inverting second clock (clk2b) is connected to one end of the third auxiliary capacitor (Cb1). The source, substrate, and gate of the fifth NMOS transistor (MN5) are connected to the power supply Vin. The drain of the fifth NMOS transistor (MN5), the gate of the first PMOS transistor (MP1), and the other end of the third auxiliary capacitor (Cb1) form a node Vp1. The drain and substrate of the first PMOS transistor (MP1) are connected to the second transmission circuit to form an output node Vout. The output node Vout is connected to the load. The second transmission circuit includes a sixth NMOS transistor (MN6), a second PMOS transistor (MP2), and a fourth auxiliary capacitor (Cb2). The inverting first clock (clk1b) is connected to one end of the fourth auxiliary capacitor (Cb2). The source, substrate, and gate of the sixth NMOS transistor (MN6) are connected to the power supply Vin. The drain of the sixth NMOS transistor (MN6), the gate of the second PMOS transistor (MP2), and the other end of the fourth auxiliary capacitor (Cb2) form a node Vp2. The drain and substrate of the second PMOS transistor (MP2) and the drain and substrate of the first PMOS transistor (MP1) are connected to form the output node Vout.

2. The cross-coupled charge pump circuit as described in claim 1, characterized in that, The four-phase non-overlapping clock generation circuit includes a first NOR gate (NR1), second to sixth NOT gates, a seventh AND gate (AD7), an eighth OR gate (OR8), a tenth NOT gate (I10), an eleventh NOR gate (NR11), twelfth to sixteenth NOT gates, a seventeenth AND gate (AD7), an eighteenth OR gate (OR8), and a third capacitor (C3), a fourth capacitor (C4), a thirteenth capacitor (C13), and a fourteenth capacitor (C14). One input terminal of the first NOR gate (NR1) and the input terminal of the tenth NOT gate (I10) are connected to form the input terminal of the four-phase non-overlapping clock generation circuit and connected to the input clock source. The output terminal of the tenth NOT gate (I10) is connected to one input terminal of the eleventh NOR gate (NR11). The first NOR gate (NR1)... The output of R1 is connected to the input of the second NOT gate (I2). The output of the second NOT gate (I2) is connected to the input of the third NOT gate (I3) and one end of the third capacitor (C3). The other end of the third capacitor (C3) is grounded. The output of the third NOT gate (I3) is connected to the input of the fourth NOT gate (I4), one input of the seventh AND gate (AD7), one input of the eighth OR gate (OR8), and the other input of the eleventh NOR gate (NR11). The output of the eleventh NOR gate (NR11) is connected to the input of the twelfth NOT gate (I12). The output of the twelfth NOT gate (I12) is connected to the input of the thirteenth NOT gate (I13) and one end of the thirteenth capacitor (C13). The other end of the thirteenth NOT gate (I13) is grounded. The output of the thirteenth NOT gate (I13) is connected to the input of the fourteenth NOT gate (I14), one input of the seventeenth AND gate (AD17), one input of the eighteenth OR gate (OR18), and the other input of the first NOR gate (NR1). The output of the fourth NOT gate (I4) is connected to the input of the fifth NOT gate (I5) and one end of the fourth capacitor (C4), with the other end of the fourth capacitor (C4) grounded. The output of the fifth NOT gate (I5) is connected to the other input of the seventh AND gate (AD7) and the other input of the eighth OR gate (OR8). The output of the fourteenth NOT gate (I14) is connected to the input of the fifteenth NOT gate (I15) and one end of the fourteenth capacitor (C14), with the other end of the fourteenth capacitor (C14) grounded. The terminal is grounded. The output of the fifteenth NOT gate (I15) is connected to the other input of the seventeenth AND gate (AD17) and the other input of the eighteenth OR gate (OR18). The output of the seventh AND gate (AD7) is the second clock (clk2), which is connected to the input of the sixth NOT gate (I16). The sixth NOT gate (I6) outputs the inverted second clock (clk2b). The eighth OR gate (OR8) outputs the zeroth clock (clk). The output of the seventeenth AND gate (AD17) is the first clock (clk1), which is connected to the input of the sixteenth NOT gate (I16). The sixteenth NOT gate (I16) outputs the inverted first clock (clk1b). The eighteenth OR gate (OR18) outputs the inverted zeroth clock (clkb).

3. The cross-coupled charge pump circuit as described in claim 1, characterized in that, The load includes a load resistor (RL) and a load capacitor (CL). The output node Vout is connected to one end of the load resistor (RL) and one end of the load capacitor (CL). The other end of the load resistor (RL) and the other end of the load capacitor (CL) are grounded.

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