A neutral point clamped multi-level converter

Abstract

The application discloses a neutral point clamped type multi-level converter, and the neutral point clamped type multi-level converter with a half-bridge cascade input is a single-phase neutral point clamped type multi-level converter with a half-bridge cascade input, the topological structure of which is composed of two-phase bridge arms and half-bridge submodule bridge arms, the half-bridge submodule bridge arms are composed of 2N identical half-bridge submodules in cascade, the two-phase bridge arms are each composed of four IGBTs and two diodes connected with a midpoint, wherein N is an integer not less than 1. The application can eliminate the operation range limitation of a three-level NPC converter, eliminate the midpoint potential imbalance problem caused by a midpoint capacitor, make the heat generation of each transistor uniform, and improve the stability and service life of the converter.

Description

Technical Field

[0001] This invention belongs to the field of multilevel converter technology, specifically relating to a neutral point clamping type multilevel converter. Background Technology

[0002] See Figure 6 The diagram shows an existing three-level neutral point clamped (NPC) converter. It uses two capacitors connected in series at the DC bus, employs two-phase bridge arms, and each phase arm has four IGBTs (Insulated Gate Bipolar Transistors). Two clamping diodes are connected across the IGBTs on the bridge arm, and finally, the midpoints of the diodes are connected to the midpoints of the capacitors. This allows the converter to output an additional zero level, bringing the total number of output levels to three. This converter circuit has a simple structure and is easy to control, and is widely used in new high-efficiency systems such as distributed power grids and medium- and high-voltage DC power systems.

[0003] The inventors discovered during their research that the three-level topology achieves multi-level output by switching in different power supplies. However, because the voltage divider capacitors cannot be adjusted in real time, the number of levels is limited. Furthermore, only four IGBTs are involved in the control of each phase arm, and since SX1 and SX3, and SX2 and SX4 are logically NOT, there are only three valid states, resulting in only three output levels. However, for certain operating conditions, a wider range of output level variations is required to meet different operational requirements. Therefore, the three-level NPC converter cannot meet these application requirements. Summary of the Invention

[0004] This invention provides a neutral point clamping type multilevel converter to achieve multilevel output and expand the application range.

[0005] To solve the above-mentioned technical problems, the present invention provides a neutral point clamping multilevel converter. The neutral point clamping multilevel converter with half-bridge cascaded input is a single-phase neutral point clamping multilevel converter with half-bridge cascaded input. Its topology consists of two-phase bridge arms and half-bridge submodule bridge arms. The half-bridge submodule bridge arms are composed of 2N identical half-bridge submodules cascaded together. Each of the two-phase bridge arms consists of 4 IGBTs and two diodes connected to the midpoint, where N is any integer not less than 1.

[0006] Furthermore, the half-bridge submodule arm is composed of 2N half-bridge submodules, wherein the number of half-bridge submodules in the upper arm and the lower arm are equal. A point on the connection line between the SM(N) and SM(N+1) submodules is taken as the midpoint of the half-bridge submodule arm, and connected to the midpoint of the diode branch of the A-phase and B-phase arms respectively to form the midpoint potential line.

[0007] The present invention also provides a neutral point clamping multilevel converter. The neutral point clamping multilevel converter with half-bridge cascaded input is a three-phase neutral point clamping multilevel converter with half-bridge cascaded input. Its topology consists of three-phase bridge arms and half-bridge submodule bridge arms. The half-bridge submodule bridge arms are composed of 2N identical half-bridge submodules cascaded together. Each of the three-phase bridge arms consists of 4 IGBTs and two diodes connected to the midpoint, where N is any integer not less than 1.

[0008] Furthermore, the half-bridge submodule arm is composed of 2N half-bridge submodules, wherein the number of half-bridge submodules in the upper arm and the lower arm are equal. A point on the connection line between the SM(N) and SM(N+1) submodules is taken as the midpoint of the half-bridge submodule arm, and connected to the midpoint of the diode branch of the A(U) phase, B(V) phase, and C(W) phase arm respectively to form the midpoint potential line.

[0009] Furthermore, the half-bridge submodule includes two series-connected switching transistors Si1 and Si2 and a DC power supply. The collector of Si1 is connected to the positive terminal of the DC power supply, and the emitter of Si2 is connected to the negative terminal of the DC power supply. Here, i is the number of the half-bridge submodule SM(i).

[0010] Furthermore, the number of output levels is determined by the number of half-bridge sub-modules, 2N, where N is any integer not less than 1, and the maximum number of output levels is 2×2N+1.

[0011] Furthermore, the neutral point clamping type multilevel converter adopts a carrier phase-shift modulation strategy, specifically: the modulating wave is compared with 2N carriers to generate 2N modulating signals, the 2N modulating signals are summed to obtain a multilevel modulated signal, and the state of each switch is determined according to the output level value. Here, the carrier is a triangular wave, and the phase of each modulating wave is (i-1)×(2π / 2N) in sequence, i=1,2,……,2N.

[0012] Furthermore, the determination of the state of each switch based on the output level value specifically involves: for the half-bridge submodule arm, the upper switch and the lower switch are logically NOT; for the two-phase or three-phase arm, the switches Sx1 and Sx3, and Sx2 and Sx4 are logically NOT; the state of the upper switch of each half-bridge submodule and the state of the upper switch of the two-phase or three-phase arm are determined, and the corresponding switch states are inverted, where x represents phases A, B, and C.

[0013] Furthermore, a point on the connection line between the SM(N) and SM(N+1) submodules on the half-bridge submodule arm is used as the midpoint potential of the half-bridge submodule arm. Each submodule outputs a level of 0 or 1, resulting in the level of the upper half-bridge arm being X, where X = 0, 1, 2, ..., N. When the level of the upper half-bridge arm is X, the upper switches of the first X submodules are turned on, and the upper switches of the last NX submodules are turned off. The level of the lower half-bridge arm is Y, where Y = 0, 1, 2, ..., N. When the level of the lower half-bridge arm is Y, the upper switches of the first Y submodules are turned on, and the upper switches of the last NY submodules are turned off.

[0014] Furthermore, by controlling the on / off states of the four IGBTs in each phase of a two- or three-phase bridge arm, the positive or negative value of the output level of that phase is determined. For each phase bridge arm, when Sx1 is on and Sx2 is on, that phase forms a path with the upper half of the half-bridge module bridge arm, and the level Ux is X. When Sx1 is off and Sx2 is on, it does not form a path with the half-bridge module bridge arm, and the level Ux is 0. When Sx1 is off and Sx2 is off, that phase forms a path with the lower half of the half-bridge module bridge arm, and the level Ux is -Y, where x represents phases A, B, and C.

[0015] Implementing this invention has the following beneficial effects: Compared with the existing three-level NPC converter, this invention increases the number of output levels, which can eliminate the operating range limitation of the three-level NPC converter. At the same time, it can eliminate the problem of midpoint potential imbalance caused by midpoint capacitor, making the heating of each transistor uniform and improving the stability and service life of the converter. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the topology of a single-phase neutral point clamped multilevel converter according to an embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of the topology of the half-bridge submodule SMi used in an embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram of the topology of a three-phase neutral point clamping multilevel converter according to an embodiment of the present invention.

[0020] Figure 4(a) is a schematic diagram of the modulation strategy of the neutral point clamping multilevel converter with half-bridge cascaded input in an embodiment of the present invention; Figure 4(b) is a nine-level carrier waveform diagram of the neutral point clamping multilevel converter with half-bridge cascaded input in an embodiment of the present invention; Figure 4(c) is a nine-level modulation signal waveform diagram of the neutral point clamping multilevel converter with half-bridge cascaded input in an embodiment of the present invention.

[0021] Figure 5(a) shows the AC output point levels and AC voltage waveforms of the single-phase neutral point clamping multilevel converter with half-bridge cascaded input in an embodiment of the present invention. Figure 5(b) shows the output line voltage waveform and the voltage and current waveforms of the load connected between phases of the three-phase neutral point clamping multilevel converter with half-bridge cascaded input in an embodiment of the present invention.

[0022] Figure 6 This is a schematic diagram of an existing three-level NPC converter topology. Detailed Implementation

[0023] The following description of the embodiments is taken with reference to the accompanying drawings, which illustrate specific embodiments in which the invention can be implemented.

[0024] Please refer to Figure 1 As shown, this embodiment of the invention provides a neutral point clamping multilevel converter, which is a single-phase neutral point clamping multilevel converter with half-bridge cascaded input. Its topology includes two-phase bridge arms and half-bridge submodule bridge arms. The half-bridge submodule bridge arms are composed of 2N identical half-bridge submodules cascaded together. Each of the two-phase bridge arms consists of 4 IGBTs and two diodes connected to the midpoint, where N is any integer not less than 1.

[0025] Specifically, the half-bridge submodule bridge arm is composed of the A and B phase bridge arms. The half-bridge submodule bridge arm is composed of 2N identical half-bridge submodules cascaded together. Both the A and B phase bridge arms consist of 4 IGBTs and two diodes connected to the midpoint. The output SM1+ of the first half-bridge submodule SM1 of the half-bridge submodule bridge arm is connected to the positive terminal A+ of the A phase bridge arm and the positive terminal B+ of the B phase bridge arm. The output SM2N- of the 2Nth half-bridge submodule SM(2N) of the half-bridge submodule bridge arm is connected to the negative terminal A- of the A phase bridge arm and the negative terminal B- of the B phase bridge arm. The midpoint of the inner tubes SA2 and SA3 of the A phase bridge arm is the output point a, and the midpoint of the inner tubes SB2 and SB3 of the B phase bridge arm is the output point b. The midpoint of the connection line between the SM(N) and SM(N+1) submodules of the half-bridge submodule bridge arm is connected to the midpoint of the diode branch of the A phase bridge arm and the B phase bridge arm, respectively, to form a zero-level line. Where N is any integer not less than 1. The midpoint of the inner tube of the A and B phase bridge arms is led out as the two-phase output AC bus.

[0026] In one embodiment, the half-bridge submodule includes two series-connected switching transistors Si1 and Si2 and a DC power supply. The emitter of Si1 is connected to the collector of Si2 and serves as the positive terminal of the half-bridge submodule, connected to the positive terminals of phase A and phase B bridge arms. The collector of Si1 is connected to the positive terminal of the DC power supply, and the emitter of Si2 is connected to the negative terminal of the DC power supply and serves as the negative terminal of the half-bridge submodule, connected to the positive terminal of the adjacent half-bridge submodule. The negative terminal of the SM(2N) submodule is connected to the negative terminals of phase A and phase B bridge arms, where i is the number of the half-bridge submodule SM(i).

[0027] In one embodiment, the positive end of the half-bridge submodule SM1 is connected to the positive end A+ of the A-phase bridge arm and the positive end B+ of the B-phase bridge arm, and the negative end of the half-bridge submodule SM(2N) is connected to the negative end A- of the A-phase bridge arm and the negative end B- of the B-phase bridge arm.

[0028] The working principle of the neutral point clamping multilevel converter in this embodiment is explained below:

[0029] In the half-bridge submodule arm, the upper and lower arms each have N half-bridge submodules. Each half-bridge submodule can only output two levels: 0 and positive. Therefore, the number of output levels is (2×2N+1), with the extra level being the midpoint potential. The converter has a total of (2×2N+8) switching transistors, each with two states, so there are a total of 2... 2×2N+8 There are several possible combinations of states, but not all states are allowed. Only the possible combinations of switching states and their corresponding outputs are listed when the converter is working normally.

[0030] For ease of understanding, when N is 2, the operation of the single-phase neutral-point clamped nine-level converter with half-bridge cascaded input is described in detail. The four half-bridge sub-modules of the half-bridge sub-module arm are SM1, SM2, SM3, and SM4, with two switches from top to bottom, Si1 and Si2, where i corresponds to the half-bridge sub-module number. The two phase arms are named A-phase and B-phase, with switches from top to bottom, Sx1, Sx2, Sx3, and Sx4, where x is either A or B. The two diodes in phase A are D1 and D2, and the two diodes in phase B are D3 and D4. During operation, the states of the two switches within the same half-bridge sub-module are complementary. Within phase A and phase B arms, SA1 and SA3, SA2 and SA4, SB1 and SB3, and SB2 and SB4 are complementary. The effective operating states and output levels of each switch are shown in Table 1 below.

[0031] Table 1 Switching Status Table of Single-Phase Neutral-Point Clamping Multilevel Converter with Half-Bridge Cascaded Input

[0032] Uab 0 1 2 3 4 0 -1 -2 -3 -4 Ua 0 1 2 2 2 0 0 0 -1 -2 Ub 0 0 0 -1 -2 0 1 2 2 2 SA1 0 1 1 1 1 0 0 0 0 0 SA2 1 1 1 1 1 1 1 1 0 0 SA3 1 0 0 0 0 1 1 1 1 1 SA4 0 0 0 0 0 0 0 0 1 1 SB1 0 0 0 0 0 0 1 1 1 1 SB2 1 1 1 0 0 1 1 1 1 1 SB3 1 1 1 1 1 1 0 0 0 0 SB4 0 0 0 1 1 0 0 0 0 0 S11 0 1 1 1 1 0 1 1 1 1 S12 1 0 0 0 0 1 0 0 0 0 S21 0 0 1 1 1 0 0 1 1 1 S22 1 1 0 0 0 1 1 0 0 0 S31 0 0 0 1 1 0 0 0 1 1 S32 1 1 1 0 0 1 1 1 0 0 S41 0 0 0 0 1 0 0 0 0 1 S42 1 1 1 1 0 1 1 1 1 0

[0033] Please refer to the following: Figure 3 As shown, a topology of a three-phase neutral-point clamped multilevel converter with cascaded half-bridge input is disclosed. Based on a single-phase neutral-point clamped multilevel converter with cascaded half-bridge input, a single-phase bridge arm C is added. The half-bridge submodule bridge arm is connected to the midpoint of the diode branch of the three-phase bridge arm. The midpoints of the inner tubes of the three-phase bridge arms are led out as three-phase output terminals. The midpoints of the inner tubes of the A, B, and C phase bridge arms are led out as three-phase output AC buses. The number of half-bridge submodules in the upper and lower bridge arms of the half-bridge submodule bridge arm is equal. A point on the connection line between the SM(N) and SM(N+1) submodules is taken as the midpoint of the half-bridge submodule bridge arm, and connected to the midpoints of the diode branches of the A, B, and C phase bridge arms respectively, forming the midpoint potential line. For the specific topology of the single-phase modular multilevel half-bridge converter, see [link to relevant documentation]. Figure 1 As shown.

[0034] The half-bridge submodule includes two series-connected switching transistors Si1 and Si2 and a DC power supply. The emitter of Si1 is connected to the collector of Si2, serving as the positive terminal of the half-bridge submodule and connected to the positive terminals of the A, B, and C phase bridge arms. The collector of Si1 is connected to the positive terminal of the DC power supply, and the emitter of Si2 is connected to the negative terminal of the DC power supply, serving as the negative terminal of the half-bridge submodule and connected to the positive terminal of the adjacent half-bridge submodule. The negative terminal of the SM(2N) submodule is connected to the negative terminals of the A, B, and C phase bridge arms, where i is the number of the half-bridge submodule SM(i).

[0035] The working principle of this embodiment is as follows: Figure 3 As shown, compared to a single-phase neutral-point clamped multilevel converter with cascaded half-bridge input, the three-phase modular multilevel half-bridge converter adds a C-phase bridge arm, resulting in a total of (2×2N+12) switching transistors. Each switching transistor has two states, so there are a total of 2 2×2N+12 There are several possible combinations of states, but not all states are allowed. Only the possible combinations of switching states and three-phase line voltage output states are listed when the converter is operating normally.

[0036] Please refer to Figure 4 again. Figure 4(a) discloses a comprehensive modulation strategy for a neutral point clamped multilevel converter with a half-bridge cascaded input. Figure 4(b) discloses the nine-level carrier waveform of the neutral point clamped multilevel converter with a half-bridge cascaded input in this embodiment of the invention. Figure 4(c) discloses the nine-level modulation signal waveform of the neutral point clamped multilevel converter with a half-bridge cascaded input in this embodiment of the invention. Specifically, the modulation strategy is a carrier phase-shift modulation strategy. The number of carriers is determined to be 2N based on the number of half-bridge sub-modules, 2N. The modulating wave is compared with 2N carriers to generate 2N modulation signals. The 2N modulation signals are summed to obtain the multilevel modulation signal. The state of each switch is determined based on the output level value. The carrier is a triangular wave, and the phase of each modulation wave is (i-1)×(2π / 2N), i=1,2,……,2N. The aforementioned integrated control strategy can modulate both a three-phase neutral-point clamping multilevel converter with half-bridge cascaded input and a single-phase neutral-point clamping multilevel converter with half-bridge cascaded input.

[0037] Specifically, determining the state of each switch based on the output level value is as follows: For the half-bridge submodule arm, the upper switch and the lower switch are logically NOT related; for the two-phase (or three-phase) arm, the switches Sx1 and Sx3, and Sx2 and Sx4 are logically NOT related. Therefore, it is only necessary to determine the state of the upper switch of each half-bridge submodule and the state of the upper switch of the two-phase (or three-phase) arm, and invert the corresponding switch state, where x represents phases A, B, and C.

[0038] A point on the connection line between the SM(N) and SM(N+1) submodules on the half-bridge submodule arm is taken as the midpoint potential of the half-bridge submodule arm. Each submodule outputs a level of 0 or 1. Therefore, the level of the upper half-bridge arm is X (X = 0, 1, 2, ..., N). When the level of the upper half-bridge arm is X, the upper switches of the first X submodules are required to be turned on, and the upper switches of the last NX submodules are required to be turned off. The level of the lower half-bridge arm is Y (Y = 0, 1, 2, ..., N). When the level of the lower half-bridge arm is Y, the upper switches of the first Y submodules are required to be turned on, and the upper switches of the last NY submodules are required to be turned off.

[0039] The positive or negative value of the output level of each phase is determined by the on and off states of the four IGBTs in each phase of a two-phase (or three-phase) bridge arm. For each phase bridge arm, when Sx1 is on and Sx2 is on, the phase forms a path with the upper half of the half-bridge module bridge arm, and the level Ux is X. When Sx1 is off and Sx2 is on, it does not form a path with the half-bridge module bridge arm, and the level Ux is 0. When Sx1 is off and Sx2 is off, the phase forms a path with the lower half of the half-bridge module bridge arm, and the level Ux is -Y, where x represents phases A, B, and C.

[0040] Please refer to Figures 5(a) and 5(b) again, which disclose the voltage levels and AC voltage Uab waveforms of the two AC output points a and b of a single-phase neutral-point clamped multilevel converter with half-bridge cascaded input; the voltage waveform of Uab of a three-phase neutral-point clamped multilevel converter with half-bridge cascaded input when the line voltage is 400V and the voltage and current waveforms of the 30Ω load connected between phases A and B, with line voltages Ubc and Uca lagging by 120° and 240° respectively.

[0041] As can be seen from the above description, compared with the prior art, the beneficial effects of the present invention are as follows: Compared with the existing three-level NPC converter, the present invention increases the number of output levels, which can eliminate the operating range limitation of the three-level NPC converter. At the same time, it can eliminate the problem of midpoint potential imbalance caused by midpoint capacitor, so that each transistor heats up evenly, and improves the stability and service life of the converter.

[0042] The above description is merely a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A neutral-point clamping type multilevel converter, characterized in that, The neutral point clamping multilevel converter with half-bridge cascaded input is a three-phase neutral point clamping multilevel converter with half-bridge cascaded input. Its topology consists of three-phase bridge arms and half-bridge submodule bridge arms. The half-bridge submodule bridge arms are composed of 2N identical half-bridge submodules cascaded together. Each of the three-phase bridge arms consists of 4 IGBTs and two diodes connected to the neutral point, where N is any integer not less than 1. The half-bridge submodule arm consists of 2N half-bridge submodules, wherein the number of half-bridge submodules in the upper arm and the lower arm are equal. A point on the connection line between the SM(N) and SM(N+1) submodules is taken as the midpoint of the half-bridge submodule arm, and connected to the midpoint of the diode branch of the A(U) phase, B(V) phase, and C(W) phase arm respectively to form the midpoint potential line. The half-bridge submodule includes two series-connected switching transistors Si1 and Si2 and a DC power supply; wherein the collector of Si1 is connected to the positive terminal of the DC power supply, and the emitter of Si2 is connected to the negative terminal of the DC power supply, and i is the number of the half-bridge submodule SM(i). The neutral point clamping type multilevel converter adopts a carrier phase-shift modulation strategy, specifically: the modulating wave is compared with 2N carriers to generate 2N modulating signals, the 2N modulating signals are summed to obtain a multilevel modulated signal, and the state of each switch is determined according to the output level value. The carrier is a triangular wave, and the phase of each modulating wave is (i-1)×(2π / 2N) in sequence, i=1,2,……,2N.

2. The neutral point clamping multilevel converter as described in claim 1, characterized in that, The number of output levels is determined by the number of half-bridge sub-modules, 2N, where N is any integer not less than 1, and the maximum number of output levels is 2×2N+1.

3. The neutral-point clamping multilevel converter according to claim 2, characterized in that, The process of determining the state of each switch based on the output level value is as follows: For the half-bridge submodule arm, the upper switch and the lower switch are logically NOT related; for the three-phase arm, the switches Sx1 and Sx3, and Sx2 and Sx4 are logically NOT related. The states of the upper switches of each half-bridge submodule and the states of the upper switches of the three-phase arm are determined, and the corresponding switch states are inverted, where x represents phases A, B, and C.

4. The neutral-point clamping multilevel converter according to claim 3, characterized in that, A point on the connection line between the SM(N) and SM(N+1) submodules on the half-bridge submodule arm is used as the midpoint potential of the half-bridge submodule arm. Each submodule outputs a level of 0 or 1, resulting in the level of the upper half-bridge arm being X, where X = 0, 1, 2, ..., N. When the level of the upper half-bridge arm is X, the upper switches of the first X submodules are turned on, and the upper switches of the last NX submodules are turned off. The level of the lower half-bridge arm is Y, where Y = 0, 1, 2, ..., N. When the level of the lower half-bridge arm is Y, the upper switches of the first Y submodules are turned on, and the upper switches of the last NY submodules are turned off.

5. The neutral-point clamping multilevel converter according to claim 4, characterized in that, The positive and negative values ​​of the output level of each phase are determined by the on and off states of the four IGBTs in each phase of the three-phase bridge arm. For each phase, when Sx1 is on and Sx2 is on, the phase forms a path with the upper half of the half-bridge module arm, and the level Ux is X. When Sx1 is off and Sx2 is on, it does not form a path with the half-bridge module arm, and the level Ux is 0. When Sx1 is off and Sx2 is off, the phase forms a path with the lower half of the half-bridge module arm, and the level Ux is -Y, where x represents phases A, B, and C.

Images