Sampling clock delay phase determination method, apparatus, system, and storage medium

Abstract

Embodiments of the present application disclose a sampling clock delay phase determination method, device and system and a storage medium. The sampling clock delay phase determination method comprises, for example, obtaining a reference clock signal and a low-voltage differential signal sent by a sending end device; performing conversion processing on the low-voltage differential signal to obtain a single-ended signal; performing delay processing on the single-ended signal according to a current phase to obtain serial data; performing buffering processing on the reference clock signal to obtain a high-speed sampling clock signal; converting the serial data according to the high-speed sampling clock signal to obtain parallel data; and determining a target delay phase of the delay processing according to the current phase, the reference clock signal and the parallel data. Embodiments of the present application can automatically find the best sampling clock delay phase of data through automatic cyclic training, and have high reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method, apparatus, system, and storage medium for determining the phase delay of a sampling clock. Background Technology

[0002] High-speed data recovery requires sampling the data using a clock. If dual-edge sampling is used, the data must be stable on both the rising and falling edges of the clock. If the data is at a boundary of variation, sampling errors will occur. Traditional LVDS data transmission typically includes one accompanying clock and several data channels. Physically, this adds a clock channel, increasing the complexity of the external circuitry. Furthermore, it requires manual adjustment of the clock or data channel delays to ensure data accuracy, making it inflexible and unreliable. In addition, without an accompanying clock, traditional LVDS data transmission requires sampling the data using four phase clocks (0°, 90°, 180°, 270°) or oversampling the data using a clock several times the data channel rate to recover the data. These solutions involve complex clock systems, high circuit complexity, and high cost. Summary of the Invention

[0003] Therefore, in view of the technical problems existing in the prior art, the present invention proposes a sampling clock delay phase determination method, a sampling clock delay phase determination device, a sampling clock delay phase determination system, and a storage medium, which can automatically find the optimal sampling clock delay phase of the data through automatic cyclic training, and has high reliability.

[0004] On one hand, an embodiment of the present invention proposes a sampling clock delay phase determination method, which includes, for example: acquiring a reference clock signal and a low-voltage differential signal emitted by a transmitting device; performing conversion processing on the low-voltage differential signal to obtain a single-ended signal; performing delay processing on the single-ended signal according to the current phase to obtain serial data; performing buffer processing on the reference clock signal to obtain a high-speed sampling clock signal; converting the serial data according to the high-speed sampling clock signal to obtain parallel data; and determining the target delay phase of the delay processing according to the current phase, the reference clock signal, and the parallel data.

[0005] In one embodiment of the present invention, determining the target delay phase of the delay processing based on the current phase, the reference clock signal, and the parallel data includes: down-clocking the reference clock signal to obtain a parallel data clock signal; determining a plurality of delay phase ranges based on the current phase, the parallel data clock signal, and the parallel data; and determining the target delay phase based on the plurality of delay phase ranges.

[0006] In one embodiment of the present invention, determining multiple delay phase ranges based on the current phase, the parallel data clock signal, and the parallel data includes: acquiring first parallel data and second parallel data under the current phase in two adjacent parallel data clock signal cycles, combining the first parallel data and the second parallel data to obtain a first combined parallel data, comparing the first combined parallel data and reference data to obtain a first comparison result, incrementing the correct phase count by 1 when the first comparison result indicates that the current phase is correct; repeating until the correct phase count reaches a first threshold, adjusting the current phase according to the phase adjustment step size to obtain a first adjusted phase, and clearing the correct phase count; using the first adjusted phase as the current phase, repeating the first two steps until a loop end instruction is received to obtain multiple delay phase ranges including the first adjusted phase.

[0007] In one embodiment of the present invention, determining the target delay phase based on the plurality of delay phase ranges includes: obtaining the maximum delay phase and the minimum delay phase of the delay phase range with the largest width among the plurality of delay phase ranges; and determining the target delay phase based on the maximum delay phase and the minimum delay phase.

[0008] On the other hand, an embodiment of the present invention provides a sampling clock delay phase determination device, which includes, for example: a signal acquisition module for acquiring a reference clock signal and a low-voltage differential signal emitted by a transmitting device; a first signal conversion module for converting the low-voltage differential signal to obtain a single-ended signal; a delay processing module for delaying the single-ended signal according to the current phase to obtain serial data; a buffer processing module for buffering the reference clock signal to obtain a high-speed sampling clock signal; a second signal conversion acquisition module for converting the serial data according to the high-speed sampling clock signal to obtain parallel data; and a phase determination module for determining the target delay phase of the delay processing according to the current phase, the reference clock signal, and the parallel data.

[0009] In one embodiment of the present invention, the phase determination device includes: a parallel signal determination unit, configured to down-clock the reference clock signal to obtain a parallel data clock signal; a phase range determination unit, configured to determine a plurality of delay phase ranges based on the parallel data clock signal and the parallel data; and a target phase determination unit, configured to determine the target delay phase based on the plurality of delay phase ranges.

[0010] In one embodiment of the present invention, the phase range determination unit includes: an adjustment phase determination subunit, configured to acquire first parallel data and second parallel data under the current phase in two adjacent parallel data clock signal cycles, combine the first parallel data and the second parallel data to obtain a first combined parallel data, compare the first combined parallel data and reference data to obtain a first comparison result, and increment the correct phase count by 1 when the first comparison result indicates that the current phase is correct; repeat until the correct phase count reaches a first threshold, adjust the current phase according to the phase adjustment step size to obtain a first adjusted phase, and clear the correct phase count; and a phase range determination subunit, configured to use the first adjusted phase as the current phase, repeat the previous step until a loop end instruction is received to obtain multiple delay phase ranges including the first adjusted phase.

[0011] In one embodiment of the present invention, the target phase determination unit includes: a phase boundary determination subunit, configured to obtain the maximum and minimum delay phases of the delay phase range with the largest width among the plurality of delay phase ranges; and a target phase determination subunit, configured to determine the target delay phase based on the maximum and minimum delay phases.

[0012] In another aspect, an embodiment of the present invention provides a sampling clock delay phase determination system, comprising: a processor and a memory connected to the processor; wherein the memory stores instructions executed by the processor, and the instructions cause the processor to perform an operation to perform the sampling clock delay phase determination method as described in any of the preceding claims.

[0013] In another aspect, embodiments of the present invention provide a storage medium, which is a non-volatile memory and stores a computer program for executing the sampling clock delay phase determination method as described in any of the preceding claims.

[0014] As can be seen from the above, the various technical solutions of the present invention can have one or more of the following beneficial effects: The sampling clock delay phase determination method provided by the embodiments of the present invention automatically determines the target delay phase of the data based on the current phase, the reference clock signal, and the parallel data to obtain the optimal sampling phase. Furthermore, it simplifies the complexity and circuitry of the clock system and increases system reliability. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart illustrating a sampling clock delay phase determination method provided in the first embodiment of the present invention.

[0017] Figure 2 for Figure 1 The detailed flowchart of step S60 is shown in the figure.

[0018] Figure 3 for Figure 2 The detailed flowchart of step S630 is shown in the figure.

[0019] Figure 4 for Figure 2 The detailed flowchart of step S650 is shown in the figure.

[0020] Figure 5 This is a schematic diagram of the structure of a programmable logic device according to the first embodiment of the present invention.

[0021] Figure 6 for Figure 5 A schematic diagram of the state flow of the phase determination unit in the diagram.

[0022] Figure 7 This is a schematic diagram of the sampling clock delay phase determination device according to the second embodiment of the present invention.

[0023] Figure 8 for Figure 7 The diagram shows the structure of the phase determination module.

[0024] Figure 9 for Figure 8 The diagram shows the structure of the phase range determination unit.

[0025] Figure 10 for Figure 8 The diagram shows the structure of the target phase determination unit.

[0026] Figure 11 This is a schematic diagram of a sampling clock delay phase determination system according to a third embodiment of the present invention.

[0027] Figure 12 This is a schematic diagram of the structure of a storage medium according to the fourth embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. The specific structural and functional details disclosed herein are merely representative and are intended to describe exemplary embodiments of the present invention. However, the present invention can be implemented in many alternative forms and should not be construed as being limited solely to the embodiments set forth herein. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0029] like Figure 1 As shown, this embodiment of the invention provides a method for determining the sampling clock delay phase. Specifically, the method for determining the sampling clock delay phase includes, for example, the following steps: S10: Obtain the reference clock signal and the low-voltage differential signal sent by the transmitting device; S20: The low-voltage differential signal is converted to obtain a single-ended signal; S30: Delay the single-ended signal according to the current phase to obtain serial data; S40: Buffer the reference clock signal to obtain a high-speed sampling clock signal; S50: Convert the serial data to parallel data according to the high-speed sampling clock signal; S60: Determine the target delay phase for the delay processing based on the current phase, the reference clock signal, and the parallel data.

[0030] The sampling clock delay phase determination method provided in this invention automatically determines the target delay phase of the data based on the current phase, the reference clock signal, and the parallel data to obtain the optimal sampling phase. Furthermore, it simplifies the complexity and circuitry of the clock system and increases system reliability.

[0031] Specifically, such as Figure 2 As shown, step S60 includes, for example: S610: The reference clock signal is down-clocked to obtain a parallel data clock signal; S630: Determine multiple delay phase ranges based on the current phase, the parallel data clock signal, and the parallel data; and S650: Determine the target delay phase based on the plurality of delay phase ranges.

[0032] In addition, such as Figure 3 As shown, step S630 includes, for example, the following steps: S631: In two adjacent parallel data clock signal cycles, acquire the first parallel data and the second parallel data under the current phase respectively, combine the first parallel data and the second parallel data to obtain the first combined parallel data, compare the first combined parallel data and the reference data to obtain the first comparison result, when the first comparison result indicates that the current phase is correct, increment the correct phase count by 1; repeat until the correct phase count reaches the first threshold, adjust the current phase according to the phase adjustment step size to obtain the first adjusted phase, and clear the correct phase count. S633: Using the first adjusted phase as the current phase, repeat the first two steps until a loop end instruction is received to obtain multiple delay phase ranges including the first adjusted phase.

[0033] Specifically, such as Figure 4 As shown, step S650 specifically includes: S651: Obtain the maximum and minimum delay phase of the delay phase range with the largest width among the plurality of delay phase ranges; S653: Determine the target delay phase based on the maximum delay phase and the minimum delay phase.

[0034] To facilitate understanding of this invention, the following will be combined with Figures 5 to 6 The sampling clock delay phase determination method of this embodiment will be described in detail.

[0035] The sampling clock delay phase determination method provided in this invention is applicable, for example, to a receiving module for Low-Voltage Differential Signaling (LVDS) within a programmable logic device. The programmable logic device is, for example, a Field-Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD). Specifically, such as... Figure 5 As shown, the programmable logic device includes, for example, a data processing module and a receiving module. The receiving module receives low-voltage differential signals, such as LVDS signals, sent to be transmitted, performs serial-to-parallel conversion on the low-voltage differential signals to obtain parallel data, and sends the parallel data to the data processing module for further processing.

[0036] Furthermore, the receiving module includes, for example, a phase-locked loop (PLL), a clock divider (ioclkdiv), a clock buffer (ioclkbuf), a phase determination unit (IDDELEAY_TRAINNING), a single-ended signal conversion unit (INBUFGDS), a delay unit (IODELAY), and a serial-to-parallel conversion unit (ISERDES). The sampling clock delay phase determination method of this embodiment will be described in detail below.

[0037] First, the single-ended signal conversion unit of the receiving module of the programmable logic device acquires the low-voltage differential signals data_p_i and data_n_i sent by the transmitting device. In addition, the phase-locked loop unit of the receiving module also acquires the externally input reference clock signal ref_clk. The reference clock ref_clk and the clock of the transmitting device must be from the same source to avoid frequency deviation between the receiving module and the transmitting device.

[0038] The single-ended signal conversion unit converts the low-voltage differential signals data_p_i and data_n_i to obtain the single-ended signal data_in. The single-ended signal, for example, uses "ground" as a reference point and expresses the signal using changes in voltage relative to ground. The single-ended signal conversion unit is, for example, a signal conversion module in the prior art, which will not be described further here.

[0039] The delay unit delays the single-ended signal `data_in` according to the current phase to obtain the serial data `data_in_dly`. By configuring different step parameters, the amount of delay between the output signal and the input signal, i.e., the delay phase, can be adjusted. The output signal and input signal of the delay unit have the same frequency; only the phase is delayed. The delay unit can dynamically adjust the phase difference between the input and output signals via an external port. For example, the adjustable number of steps for the delay unit is 247 steps, with each step approximately 10 ps.

[0040] The phase-locked loop (PLL) unit configures the frequency of its output clock signal hs_clk to be half the data rate of the low-voltage differential signal transmitted by the transmitting device, based on the reference clock signal. The clock divider unit divides the output clock signal hs_clk by 5 to obtain the parallel data clock signal byte_clk. The clock buffer unit buffers the output clock signal hs_clk from the PLL unit to obtain the high-speed sampling clock signal ioclk.

[0041] The serial-to-parallel conversion unit converts the serial data data_in_dly into parallel data rx_data[9:0] based on the high-speed sampling clock signal ioclk. Specifically, the serial data data_in_dly is sampled on both edges by the high-speed sampling clock signal ioclk, converted into 10-bit parallel data rx_data, and synchronized to the clock domain of the low-speed parallel clock signal byte_clk.

[0042] The phase determination unit determines the target delay phase for the delay processing based on the current phase, the reference clock signal, and the parallel data. This target delay phase is the optimal delay phase for the delay processing unit.

[0043] Further, see Figure 6 It shows the state flow diagram of the phase determination unit (IODELAY_TRAINNING).

[0044] Specifically, firstly, the transmitting device sends a continuous commacode pattern as the byte boundary alignment code for the receiving end during idle or power-on initialization. Here, a 10-bit code pattern 0011111010 is used as an example as the commacode. The commacode can be reconfigured through parameters. During idle or power-on initialization, the transmitting device cyclically sends 0011111010 or its complement 1100000101. The commacode or its complement is used as reference data, for example. The configuration parameter ONE_LOOP_TIMES (single loop count) is 1000 times, and the total loop count LOOP_TIME is 5 times. Other circuit parameters can be reconfigured by the user. The number of data channels is reconfigured through parameters; each channel is independent. This embodiment uses one channel as an example.

[0045] During system initialization, the phase determination unit enters an idle state (IDLE). When the phase determination unit detects that the start_train signal is high, it begins the automatic training process (i.e., the phase determination process). Afterwards, the system enters the FIND_COMMA state. Each byte_clk of the phase determination unit receives one 10-bit rx_data data, and two byte_clk units receive two 10-bit parallel data (the first parallel data and the second parallel data). Then, the phase determination unit concatenates (also called combines) the two 10-bit data into one 20-bit data (i.e., combined parallel data), and determines whether a 10-bit comma code or its complement can be extracted from this 20-bit data. In other words, the 20-bit data is compared with the comma code. For example, if two adjacent 10-bit data are 1111101000 and 0011110000, the lower two bits (00) of the second 10-bit data and the higher 8 bits (11111010) of the first 10-bit data can be combined to form a 10-bit comma code (0011111010), representing the data sent from the receiver. The fact that a comma code can be extracted from the 20-bit bitstream indicates that the receiving module can correctly recover the data sent by the transmitting device. If possible, enter the LOOP_FIND1 state and increment loop_cnt1 by 1; otherwise, it indicates that the current high-speed sampling clock is sampling parallel data with errors, and enter the PHASE_ADJ state for phase adjustment.

[0046] When in the LOOP_FIND1 state, if the counter loop_cnt1 equals 1000, it means that 1000 comma codes have been found. The counter loop_cnt2 is incremented by 1, and the system enters the LOOP_FIND2 state. If the counter loop_cnt1 does not equal 1000, the system enters the FIND_COMMA state to continue searching for comma codes.

[0047] When in the LOOP_FIND2 state, the counter loop_cnt1 is cleared to 0. If the counter loop_cnt2 equals 5, it means that 5 × 1000 comma codes have been found for this phase, that is, the number of correct phases has reached 5000 (the first threshold), so the current phase is considered correct, and the system enters the PHASE_ADJ state. If the counter loop_cnt2 does not equal 5, the system enters the FIND_COMMA state to continue searching for comma codes.

[0048] In the PHASE_ADJ state, the counter loop_cnt2 is cleared to 0, and the delay unit is adjusted by 5 steps (approximately 10ps per step, 5 steps approximately 50ps). This is the phase adjustment step size, meaning the phase difference between the high-speed clock ioclk and data_in is adjusted by 50ps. After adjusting 5 steps, the system enters the TRAIN_END state. The delay unit can be adjusted by a maximum of 247 steps.

[0049] When in the TRAIN_END state, check if the boundary_end signal is high. If it is high, it indicates that training is complete and the loop has ended, i.e., whether a loop end command has been received. The prerequisite for boundary_end to be high is: finding two consecutive correct phase segments, or the delay value of the IODELAY unit has been adjusted to the maximum value (247 steps).

[0050] Upon receiving the loop end command, the phase determination unit finds all correct phase values, i.e., multiple phase ranges, or multiple phase windows. Based on these multiple delayed phase ranges, it calculates the target sampling phase, i.e., the optimal sampling phase, for use in data sampling across the entire system. If the level is low, meaning no loop end command has been received, it enters the FIND_COMMA state. A correct sampling phase is determined by finding 5*1000 consecutive comma codes or their complements; an incorrect sampling phase is determined by not finding a comma code or its complement within two bytes_clk.

[0051] The target phase or optimal phase is calculated as follows: the median value of the largest consecutive correct window is taken as the optimal IODELAY unit delay value. For example, assuming steps 0-30 are correct phases, steps 31-49 are incorrect phases, and steps 50-100 are correct phases, then steps 50-100 are considered the largest consecutive correct window, or the widest delay phase range. (50+100) / 2=75 is taken as the optimal delay phase for the IODELAY unit. This means the optimal delay phase is obtained by weighting the maximum and minimum delay phases, ensuring correct and reliable data sampling by the clock.

[0052] In summary, the sampling clock delay phase determination method provided by this invention automatically determines the target delay phase of the data based on the current phase, the reference clock signal, and the parallel data to obtain the optimal sampling phase. Furthermore, it simplifies the complexity and circuitry of the clock system and increases system reliability.

[0053] like Figure 7As shown, a second embodiment of the present invention provides a sampling clock delay phase determination device 10. The sampling clock delay phase determination device 10 includes, for example, a signal acquisition module 100, a first signal conversion module 200, a delay processing module 300, a buffer processing module 400, a second signal conversion and acquisition module 500, and a phase determination module 600.

[0054] Specifically, the signal acquisition module 100 is used to acquire a reference clock signal and a low-voltage differential signal emitted by the transmitting device; the first signal conversion module 200 is used to convert the low-voltage differential signal to obtain a single-ended signal; the delay processing module 300 is used to delay the single-ended signal according to the current phase to obtain serial data; the buffer processing module 400 is used to buffer the reference clock signal to obtain a high-speed sampling clock signal; the second signal conversion and acquisition module 500 is used to convert the serial data according to the high-speed sampling clock signal to obtain parallel data; and the phase determination module 600 is used to determine the target delay phase of the delay processing according to the current phase, the reference clock signal, and the parallel data.

[0055] In addition, such as Figure 8 As shown, the model building and training module 60 includes: a parallel signal determination unit 610, a phase range determination unit 630, and a target phase determination unit 650. Specifically, the parallel signal determination unit 610 is used to down-clock the reference clock signal to obtain a parallel data clock signal; the phase range determination unit 630 is used to determine multiple delay phase ranges based on the parallel data clock signal and the parallel data; and the target phase determination unit 650 is used to determine the target delay phase based on the multiple delay phase ranges.

[0056] Furthermore, such as Figure 9 As shown, the phase range determination unit 630 further includes: an adjustment phase determination subunit 631 and a phase range determination subunit 633. Specifically, the adjustment phase determination subunit 631 is used to acquire the first parallel data and the second parallel data under the current phase in two adjacent parallel data clock signal cycles, combine the first parallel data and the second parallel data to obtain the first combined parallel data, compare the first combined parallel data and the reference data to obtain the first comparison result, and when the first comparison result indicates that the current phase is correct, increment the correct phase count by 1; repeat until the correct phase count reaches the first threshold, adjust the current phase according to the phase adjustment step size to obtain the first adjusted phase, and clear the correct phase count; the phase range determination subunit 633 is used to take the first adjusted phase as the current phase, repeat the previous step until a loop end instruction is received to obtain multiple delay phase ranges including the first adjusted phase.

[0057] In addition, such as Figure 10 As shown, the target phase determination unit 650 includes a phase boundary determination subunit 651 and a target phase determination subunit 653. The phase boundary determination subunit 651 is used to obtain the maximum and minimum delayed phase of the largest delayed phase range among the plurality of delayed phase ranges; the target phase determination subunit 653 is used to determine the target delayed phase based on the maximum and minimum delayed phases.

[0058] The specific working process and technical effects of each module in the sampling clock delay phase determination device 10 in this embodiment are described in the relevant steps of the first embodiment above, and will not be repeated here.

[0059] like Figure 11 As shown, a third embodiment of the present invention provides a sampling clock delay phase determination system 20. The sampling clock delay phase determination system 20 includes, for example, a memory 22 and a processor 21 connected to the memory 22. The memory 22 may be, for example, a non-volatile memory storing instructions. The processor 21 may include, for example, an embedded processor or a central processing unit. When the processor 21 executes the instructions, it performs the sampling clock delay phase determination method provided in the first embodiment described above.

[0060] like Figure 12 As shown, the fourth embodiment of the present invention provides a storage medium 30 storing a computer program for executing the sampling clock delay phase determination method as described in the first embodiment above. The storage medium 30 is, for example, a non-volatile memory, including: magnetic media (such as hard disks, floppy disks, and magnetic tapes), optical media (such as CD-ROMs and DVDs), magneto-optical media (such as optical discs), and hardware devices specifically configured for storing and executing computer-executable instructions (such as read-only memory (ROM), random access memory (RAM), flash memory, etc.). The storage medium 30 can be executed by one or more processors or processing devices to execute the computer program.

[0061] Furthermore, it is understood that the foregoing embodiments are merely illustrative examples of this utility model. Provided that there are no technical feature conflicts, structural contradictions, or violations of the inventive purpose of this utility model, the technical solutions of the various embodiments can be arbitrarily combined and used.

[0062] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between devices or units through some interfaces, and may be electrical, mechanical, or other forms.

[0063] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0064] Furthermore, in the various embodiments of this utility model, the functional units can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A method for determining the phase delay of a sampling clock, characterized in that, include: Acquire the reference clock signal and the low-voltage differential signal sent by the transmitting device; The low-voltage differential signal is converted to obtain a single-ended signal; The single-ended signal is delayed based on the current phase to obtain serial data; The reference clock signal is buffered to obtain a high-speed sampling clock signal; The serial data is converted into parallel data based on the high-speed sampling clock signal; The target delay phase for the delay processing is determined based on the current phase, the reference clock signal, and the parallel data. The step of determining the target delay phase of the delay processing based on the current phase, the reference clock signal, and the parallel data includes: down-clocking the reference clock signal to obtain a parallel data clock signal; determining multiple delay phase ranges based on the current phase, the parallel data clock signal, and the parallel data; and determining the target delay phase based on the multiple delay phase ranges. The step of determining multiple delay phase ranges based on the current phase, the parallel data clock signal, and the parallel data includes: acquiring first parallel data and second parallel data under the current phase in two adjacent parallel data clock signal cycles, combining the first parallel data and the second parallel data to obtain a first combined parallel data, comparing the first combined parallel data with reference data to obtain a first comparison result, incrementing the correct phase count by 1 when the first comparison result indicates that the current phase is correct; repeating until the correct phase count reaches a first threshold, adjusting the current phase according to the phase adjustment step size to obtain a first adjusted phase, and clearing the correct phase count; using the first adjusted phase as the current phase, repeating the first two steps until a loop end command is received to obtain multiple delay phase ranges including the first adjusted phase.

2. The sampling clock delay phase determination method according to claim 1, characterized in that, Determining the target delay phase based on the plurality of delay phase ranges includes: Obtain the maximum and minimum delay phase of the delay phase range with the largest width among the plurality of delay phase ranges; and The target delay phase is determined based on the maximum delay phase and the minimum delay phase.

3. A sampling clock delay phase determination device, characterized in that, include: The signal acquisition module is used to acquire the reference clock signal and the low-voltage differential signal emitted by the transmitting device; The first signal conversion module is used to convert the low-voltage differential signal to obtain a single-ended signal; A delay processing module is used to perform delay processing on the single-ended signal according to the current phase to obtain serial data; A buffer processing module is used to buffer the reference clock signal to obtain a high-speed sampling clock signal; The second signal conversion and acquisition module is used to convert the serial data into parallel data according to the high-speed sampling clock signal; A phase determination module is used to determine the target delay phase of the delay processing based on the current phase, the reference clock signal, and the parallel data. The phase determination device includes: a parallel signal determination unit, a phase range determination unit, and a target phase determination unit; the parallel signal determination unit is used to down-clock the reference clock signal to obtain a parallel data clock signal; the phase range determination unit is used to determine multiple delay phase ranges based on the current phase, the parallel data clock signal, and the parallel data; the target phase determination unit is used to determine the target delay phase based on the multiple delay phase ranges. The phase range determination unit includes an adjustment phase determination subunit and a phase range determination subunit. The adjustment phase determination subunit is used to acquire first parallel data and second parallel data under the current phase in two adjacent parallel data clock signal cycles, combine the first parallel data and the second parallel data to obtain a first combined parallel data, compare the first combined parallel data and reference data to obtain a first comparison result, and increment the correct phase count by 1 when the first comparison result indicates that the current phase is correct. This process is repeated until the correct phase count reaches a first threshold, and the current phase is adjusted according to the phase adjustment step size to obtain a first adjusted phase. The correct phase count is then cleared. The phase range determination subunit is used to take the first adjusted phase as the current phase and repeat the previous step until a loop end instruction is received to obtain multiple delay phase ranges including the first adjusted phase.

4. The sampling clock delay phase determination device according to claim 3, characterized in that, The target phase determination unit includes: A phase boundary determination subunit is used to obtain the maximum and minimum delay phase of the delay phase range with the largest width among the plurality of delay phase ranges; and The target phase determination subunit is used to determine the target delay phase based on the maximum delay phase and the minimum delay phase.

5. A sampling clock delay phase determination system, characterized in that, include: A processor and a memory connected to the processor; wherein the memory stores instructions executed by the processor, and the instructions cause the processor to perform an operation to perform the sampling clock delay phase determination method as described in claim 1 or 2.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium is a non-volatile memory and stores a computer program for executing the sampling clock delay phase determination method as described in claim 1 or 2.

Images