Transmitter and its method for generating additional parity checks

Abstract

A transmitter and a method thereof for generating additional parity are provided. The transmitter includes: a low-density parity-check (LDPC) encoder configured to encode input bits to generate an LDPC codeword comprising input bits and parity bits to be transmitted to a receiver in the current frame; a repeater configured to repeat at least some bits of the LDPC codeword in the LDPC codeword, such that the repeated bits will be transmitted in the current frame; a truncation unit configured to truncate some of the parity bits; and an additional parity generator configured to select at least some bits of the LDPC codeword including the repeated bits and generate additional parity bits to be transmitted in a previous frame of the current frame.

Description

[0001] This application is a divisional application of the invention patent application filed on March 2, 2016, with application number "201680025625.0" and titled "Transmitter and Method Thereof for Generating Additional Parity Check". Technical Field

[0002] The apparatus and method consistent with exemplary embodiments of the inventive concept relates to a transmitter and a method for generating additional parity checks for signal transmission. Background Technology

[0003] In the information-driven society of the 21st century, broadcast communication services are entering an era of digitalization, multi-channeling, increased bandwidth, and high quality. Specifically, with the widespread distribution of high-definition digital television (TV) and portable broadcast signal receiving devices, the demand for digital broadcast services to support various receiving schemes is growing.

[0004] Based on this need, the standards group established broadcast communication standards to provide various signal transmission and reception services to meet user needs. However, a better method is still needed to provide users with further improved performance. Summary of the Invention

[0005] [Technical Issues]

[0006] Exemplary embodiments of the inventive concept can overcome the disadvantages of related signal transmitters, receivers, and methods. However, it is not required that these embodiments overcome such disadvantages, or that these embodiments may not overcome such disadvantages.

[0007] An exemplary embodiment provides a transmitter, a receiver, and a method for generating additional parity checks for broadcast signals.

[0008] [Technical Solution]

[0009] According to one aspect of an exemplary embodiment, a transmitter is provided, the transmitter comprising: a low-density parity-check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including input bits and parity bits to be transmitted to a receiver in a current frame; a repeater configured to repeat at least some bits of the LDPC codeword in the LDPC codeword, such that the repeated bits will be transmitted in the current frame; a truncation unit configured to truncate some parity bits from the parity bits; and an additional parity generator configured to select at least some bits of the LDPC codeword including the repeated bits and generate additional parity bits to be transmitted in a previous frame of the current frame.

[0010] A repeater can repeat at least some of the parity bits in an LDPC codeword after the input bits.

[0011] An additional parity generator can select at least some of the repeated bits to be added after the input bits based on the number of additional parity bits and the number of parity bits that are truncated, in order to generate additional parity bits.

[0012] When the number of additional parity bits is greater than the number of truncated parity bits, the additional parity generator can select all the truncated parity bits and, starting from the first bit among the repeated bits, select the same number of bits as obtained by subtracting the number of truncated parity bits from the number of additional parity bits to generate additional parity bits.

[0013] When the repeater does not perform repetition and the number of additional parity bits is greater than the number of truncated parity bits, the additional parity generator can select all the truncated parity bits and select from the parity bits, starting from the first bit, the same number of bits as obtained by subtracting the number of truncated parity bits from the number of additional parity bits, to generate additional parity bits.

[0014] According to another aspect of an exemplary embodiment, a method for generating additional parity in a transmitter is provided. The method may include: encoding input bits to generate an LDPC codeword comprising input bits and parity bits to be transmitted to a receiver in a current frame; repeating at least some bits of the LDPC codeword in the LDPC codeword such that the repeated bits will be transmitted in the current frame; truncating some of the parity bits; selecting at least some bits of the LDPC codeword including the repeated bits; and generating additional parity bits to be transmitted in a previous frame of the current frame.

[0015] In the repeated steps, at least some of the parity bits from the parity bits can be added to the LDPC codeword after the input bits.

[0016] In the step of generating additional parity bits, at least some bits may be selected from the repeated bits added after the input bits based on the number of additional parity bits and the number of parity bits that are truncated, in order to generate additional parity bits.

[0017] In the step of generating additional parity bits, when the number of additional parity bits is greater than the number of truncated parity bits, all truncated parity bits can be selected, and from the repeated bits, starting from the first bit, the same number of bits as obtained by subtracting the number of truncated parity bits from the number of additional parity bits can be selected to generate additional parity bits.

[0018] In the step of generating additional parity bits, when the repetition is not performed and the number of additional parity bits is greater than the number of truncated parity bits, all truncated additional parity bits may be selected, and the same number of bits may be selected from the parity bits starting from the first bit as obtained by subtracting the number of truncated parity bits from the number of additional parity bits to generate additional parity bits.

[0019] [Beneficial effects of the invention]

[0020] As described above, according to an exemplary embodiment of the inventive concept, some of the parity bits may be sent additionally to obtain coding gain and diversity gain. Attached Figure Description

[0021] The above and / or other aspects of exemplary embodiments will now be described with reference to the accompanying drawings, wherein:

[0022] Figure 1 This is a block diagram used to describe the configuration of a transmitter according to an exemplary embodiment;

[0023] Figure 2 and Figure 3 It is a diagram used to describe the parity check matrix according to an exemplary embodiment;

[0024] Figures 4 to 7 This is a block diagram illustrating repetition according to an exemplary embodiment;

[0025] Figures 8 to 11 This is a block diagram illustrating deletion according to an exemplary embodiment;

[0026] Figures 12 to 17 This is a diagram illustrating a method for generating additional parity bits according to an exemplary embodiment;

[0027] Figure 18 It is a diagram used to describe the frame structure according to an exemplary embodiment;

[0028] Figure 19 and Figure 20 This is a block diagram used to describe the detailed configuration of a transmitter according to an exemplary embodiment;

[0029] Figures 21 to 34This is a diagram illustrating a method for processing signaling according to an exemplary embodiment;

[0030] Figure 35 and Figure 36 This is a block diagram used to describe the configuration of a receiver according to an exemplary embodiment;

[0031] Figure 37 and Figure 38 This is a diagram illustrating an example of combining LLR values ​​in a receiver according to an exemplary embodiment;

[0032] Figure 39 This is a diagram illustrating an example of providing information related to the length of L1 signaling according to an exemplary embodiment;

[0033] Figure 40 This is a flowchart describing a method for generating additional parity checks according to an exemplary embodiment;

[0034] Figure 41 This is a diagram illustrating the coding gain and diversity gain that can be obtained when using additional parity checks according to an exemplary embodiment. Detailed Implementation

[0035] [Best Implementation Method for Carrying Out the Invention]

[0036] -

[0037] [Implementation Methods of the Invention]

[0038] In the following description, exemplary embodiments will be described in more detail with reference to the accompanying drawings.

[0039] Figure 1 This is a block diagram illustrating the configuration of a transmitter according to an exemplary embodiment. (Refer to...) Figure 1 The transmitter 100 includes a low-density parity check (LDPC) encoder 110, a repeater 120, a truncate 130, and an additional parity check generator 140.

[0040] The LDPC encoder 110 can encode input bits that may include various types of data. In other words, the LDPC encoder 110 can perform LDPC encoding on the input bits to produce parity bits, i.e., LDPC parity bits.

[0041] Specifically, the input bits are LDPC information bits used for LDPC encoding, and may include externally encoded bits and zero bits (i.e., bits with a value of 0). Here, the externally encoded bits include information bits and parity bits (or parity check bits) generated by externally encoding the information bits.

[0042] Here, the information bits may be signaling (optionally referred to as "signaling bits" or "signaling information") or the information bits may refer only to signaling. The signaling may include information required by the receiver 200 (as shown in Figure 58 or Figure 59) to process service data (e.g., broadcast data) transmitted from the transmitter 100.

[0043] Additionally, external encoding is an encoding operation performed before internal encoding in a concatenated encoding operation, and various encoding schemes can be used, such as BCH (Bose, Chaudhuri, Hocquenghem) encoding and / or Cyclic Redundancy Check (CRC) encoding. In this case, the internal encoding can be LDPC encoding.

[0044] For LDPC encoding, a predetermined number of LDPC information bits are required, depending on the code rate and code length. Therefore, when the number of externally encoded bits generated by externally encoding the information bits is less than the required number of LDPC information bits, an appropriate number of zero bits are padded to meet the required number of LDPC information bits for encoding. Thus, the externally encoded bits and the padded zero bits can configure the LDPC information bits to be as many as the number of bits required for LDPC encoding.

[0045] Since the padding zero bits are only needed to satisfy a predetermined number of bits for LDPC encoding, the padding zero bits are LDPC encoded and then not sent to receiver 200. Thus, the process of padding zero bits, or padding zero bits and then not sending them to receiver 200, can be called reduction. In this case, the padding zero bits can be called reduced bits (or reduced bits).

[0046] For example, suppose the number of information bits is K. sig And when M outer The number of bits added to the information bits via external encoding (i.e., the number of externally encoded bits including both information bits and parity bits) is N. outer (=K sig +M outer ).

[0047] In this case, when the number of externally encoded bits N outer The number of information bits less than LDPC, K ldpc At that time, K ldpc -N outer A number of zero bits are padded so that the externally encoded bits and the padded zero bits can together form LDPC information bits.

[0048] The example described above, where zero bits are filled, is just one example.

[0049] When the information bits are signaling for data or service data, the length of the information bits can vary depending on the amount of data. Therefore, when the number of information bits exceeds the number of LDPC information bits required for LDPC encoding, the information bits can be segmented into values ​​below a certain threshold.

[0050] Therefore, when the number of information bits or the number of segmented information bits is less than the number of parity bits generated by external encoding subtracted from the number of LDPC information bits (i.e., M... outer When the number of bits obtained is equal to the number obtained by subtracting the number of externally encoded bits from the number of LDPC information bits, the same number of zero bits are filled, so that the LDPC information bits can be formed by externally encoded bits and filled zero bits.

[0051] However, when the number of information bits or the number of segmented information bits is equal to the number obtained by subtracting the number of parity bits generated by external encoding from the number of LDPC information bits, LDPC information bits can be formed from externally encoded bits without including padding zero bits.

[0052] Furthermore, the foregoing example describes information bits being externally encoded, which is merely an example. However, information bits may not be externally encoded and may be used together with padding zero bits to form LDPC information bits, or only information bits may be used to form LDPC information bits without separately padding zero bits.

[0053] For ease of description, the external encoding will be described below under the assumption that the external encoding is performed via BCH encoding.

[0054] Specifically, the input bits will be described under the following assumptions: the input bits include BCH-encoded bits and zero bits, and the BCH-encoded bits include information bits and BCH parity bits (or BCH parity bits) generated by BCH encoding the information bits.

[0055] In other words, assuming the number of information bits is K sig And when M outer The number of bits added to the information bits via BCH encoding when BCH parity bits are used (i.e., the number of BCH-encoded bits including both information bits and BCH parity bits) is N. outer (=K sig +M outer Here, M outer =168.

[0056] Furthermore, the foregoing example describes filling in the zero bits to be reduced, which is merely an example. That is, since the zero bits are bits with a value preset by the transmitter 100 and the receiver 200 and are filled only to form LDPC information bits together with information bits that include information to be subsequently sent to the receiver 200, bits with another value (e.g., 1) preset by the transmitter 100 and the receiver 200, replacing the zero bits, can be filled in order to reduce the zero bits.

[0057] The LDPC encoder 110 can systematically encode LDPC information bits to generate LDPC parity bits and output LDPC codewords (or bits after LDPC encoding) formed by LDPC information bits and LDPC parity bits. That is, LDPC code is a systematic code, therefore, LDPC codewords can be formed by LDPC information bits before LDPC encoding and LDPC parity bits generated by LDPC encoding.

[0058] For example, the LDPC encoder 110 can be used for K ldpc LDPC information bits Perform LDPC encoding to generate N ldpc_parity LDPC parity bits And output by N inner (=K ldpc +N ldpc_parity LDPC codeword formed by ) bits

[0059] In this case, the LDPC encoder 110 can perform LDPC encoding on the input bits at various code rates to produce LDPC codewords of a specific length.

[0060] For example, the LDPC encoder 110 can perform LDPC encoding on 3240 input bits at a code rate of 3 / 15 to produce an LDPC codeword of 16200 bits. As another example, the LDPC encoder 110 can perform LDPC encoding on 6480 input bits at a code rate of 6 / 15 to produce an LDPC codeword of 16200 bits.

[0061] Simultaneously, the LDPC encoding process involves generating LDPC codewords that satisfy H.C. T The parity check matrix is ​​used to handle 0, therefore, the LDPC encoder 110 can use the parity check matrix to perform LDPC encoding. Here, H represents the parity check matrix, and C represents the LDPC codeword.

[0062] In the following description, the structure of a parity check matrix according to various exemplary embodiments will be described with reference to the accompanying drawings. In the parity check matrix, all elements except 1 are 0.

[0063] For example, the parity check matrix according to an exemplary embodiment may have the following characteristics: Figure 2 The structure shown in the figure.

[0064] Reference Figure 2 The parity check matrix 20 can be formed by five submatrices A, B, C, Z, and D. In the following text, each matrix structure will be described in order to illustrate the structure of the parity check matrix 20.

[0065] Submatrix A consists of K columns and g rows, and submatrix C consists of K+g columns and NKg rows. Here, K (or K... ldpc ) represents the length of the LDPC information bits, N (or N inner ) indicates the length of the LDPC codeword.

[0066] Additionally, in submatrixes A and C, when the LDPC codeword length is 16200 and the code rate is 3 / 15, the index of the row containing column 1 in column 0 of the i-th column group can be determined based on Table 1. The number of columns belonging to the same column group can be 360.

[0067] [Table 1]

[0068]

[0069] In the following text, the position of the row containing 1 in submatrix A and submatrix C will be described in detail with reference to, for example, Table 1.

[0070] When the length of the LDPC codeword is 16200 and the code rate is 3 / 15, the encoding parameters M1, M2, Q1 and Q2 based on the parity check matrix 200 are 1080, 11880, 3 and 33 respectively.

[0071] Here, Q1 represents the size of the cyclic shift of columns belonging to the same column group in submatrix A, and Q2 represents the size of the cyclic shift of columns belonging to the same column group in submatrix C.

[0072] Additionally, Q1 = M1 / L, Q2 = M2 / L, M1 = g, M2 = NKg, and L represents the interval (i.e., the number of columns belonging to the same column group (e.g., 360)), where the column pattern is repeated at this interval in submatrix A and submatrix C respectively.

[0073] The index of the row containing 1 in submatrix A and submatrix C can be determined based on the value of M1.

[0074] For example, in Table 1 above, since M1 = 1080, the position of the row where 1 is located in the 0th column of the i-th column group in submatrix A can be determined based on the index values ​​in Table 1 above that are less than 1080. The position of the row where 1 is located in the 0th column of the i-th column group in submatrix C can be determined based on the index values ​​in Table 1 above that are greater than or equal to 1080.

[0075] Specifically, in Table 1 above, the sequence corresponding to column 0 is "8 372 841 4522 5253 74308542 9822 10550 11896 11988". Therefore, in column 0 of column 0 in submatrix A, 1 can be located in row 8, row 372, and row 841 respectively. Similarly, in column 0 of column 0 in submatrix C, 1 can be located in row 4522, row 5253, row 7430, row 8542, row 9822, row 10550, row 11896, and row 11988 respectively.

[0076] In submatrix A, when the position of 1 is confined to the 0th column of each column group, the position of 1 can be cyclically shifted by Q1 to confined to the row where 1 is located in the other columns of each column group. In submatrix C, when the position of 1 is confined to the 0th column of each column group, the position of 1 can be cyclically shifted by Q2 to confined to the row where 1 is located in the other columns of each column group.

[0077] In the previous example, in column 0 of column 0 of submatrix A, 1 is located in rows 8, 372, and 841. In this case, since Q1 = 3, the index of the row where 1 is located in column 1 of column 0 could be 11 (= 8 + 3), 375 (= 372 + 3), and 844 (= 841 + 3), and the index of the row where 1 is located in column 2 of column 0 could be 14 (= 11 + 3), 378 (= 375 + 3), and 847 (= 844 + 3).

[0078] In the 0th column of the 0th column group of submatrix C, 1 is located in rows 4522, 5253, 7430, 8542, 9822, 10550, 11896, and 11988. In this case, since Q2 = 33, the index of the row where 1 is located in the 1st column of the 0th column group can be 4555 (=4522+33), 5286 (=5253+33), 7463 (=7430+33), 8575 (=8542+33), 9855 (=9822+33), 10583 (=10550+33), 11929 (=11896+33), and 12021 (=11896+33). 988+33), and the index of the row where 1 is located in the second column of the 0th column group can be 4588 (=4555+33), 5319 (=5286+33), 7496 (=7463+33), 8608 (=8575+33), 9888 (=9855+33), 10616 (=10583+33), 11962 (=11929+33) and 12054 (=12021+33).

[0079] According to this scheme, the position of the row containing 1 in all column groups of submatrix A and submatrix C can be defined.

[0080] Submatrix B is a doubly diagonal matrix, submatrix D is an identity matrix, and submatrix Z is a zero matrix.

[0081] As a result, such Figure 2 The structure of the parity check matrix 20 shown can be defined by submatrices A, B, C, D and Z, which have the above structure.

[0082] The following will describe the method used by the LDPC encoder 110 based on, for example... Figure 2 The parity check matrix 20 shown in the figure performs LDPC encoding.

[0083] LDPC codes can be used to process information blocks S = (s0, s1, ..., S...). K-1 Encoding is performed. In this case, to generate an LDPC codeword Λ = (λ0, λ1, ..., λ2) of length N = K + M1 + M2, N-1 ), parity check block from information block S It can be systematically encoded.

[0084] As a result, LDPC codewords can be

[0085] Here, M1 and M2 each represent the size of the parity submatrix corresponding to the diagonal submatrix B and the identity submatrix D, respectively, where M1 = g and M2 = NKg.

[0086] The process of calculating the parity bits can be represented as follows. In the following text, for ease of explanation, the parity matrix 20 will be described as an example, defined according to Table 1 above.

[0087] Step 1) Initialize to λ i =S i (i = 0, 1, ..., K-1), p j =0(j=0,1,...,M1+M2-1).

[0088] Step 2) Add the first information bit λ0 to the parity check bit address specified in the first row of Table 1 above.

[0089] Step 3) For the next L-1 information bits λ m (m = 1, 2, ..., L-1), let λ m The result is added to the parity bit address calculated based on Equation 1 below.

[0090]

[0091] In Equation 1 above, x represents the address of the parity bit accumulator corresponding to the first information bit λ0. Furthermore, Q1 = M1 / L and Q2 = M2 / L.

[0092] In this case, since the length of the LDPC codeword is 16200 and the code rate is 3 / 15, M1 = 1080, M2 = 11880, Q1 = 3, Q2 = 33, and L = 360.

[0093] Step 4) Since the parity bit address in the second row of Table 1 above is assigned to the Lth information bit λ L Similar to the aforementioned scheme, the method described in step 3 above is used to calculate λ for the next L-1 information bits. m The parity bit address (m = L+1, L+2, ..., 2L-1). In this case, x represents the parity bit address relative to the information bit λ. L The address of the corresponding parity bit accumulator can be obtained based on the second row of Table 1 above.

[0094] Step 5) For each group of L new information bits, set the new row of Table 1 above to the address of the parity bit accumulator, and thus repeat the above process.

[0095] Step 6) From codeword bits λ0 to λ K-1 After repeating the above process, calculate the value of Equation 2 below sequentially starting from i=1.

[0096]

[0097] Step 7) Calculate the parity check bit λ corresponding to the double diagonal submatrix B based on Equation 3 below. K to

[0098] λ K+L×t+s =p Q1×s+t (0≤s<L, 0≤t<Q1)....(3)

[0099] Step 8) Calculate the L new codeword bits λ for each group based on the new row of Table 1 and Equation 1 above. K to The address of the parity bit accumulator.

[0100] Step 9) In the codeword bit λ K to After being applied, the parity bits corresponding to submatrix D are calculated based on Equation 4 below. to

[0101] λ K+M1+L×t+s =p M1+Q2×s+t (0≤s<L, 0≤t<Q2)....(4)

[0102] As a result, the parity bit can be calculated using the above scheme. However, this is merely an example, and therefore, it is not applicable to systems based on... Figure 2 The scheme for calculating parity bits using the parity check matrix shown can be limited in various ways.

[0103] Thus, the LDPC encoder 110 can perform LDPC encoding based on Table 1 above to generate LDPC codewords.

[0104] Specifically, the LDPC encoder 110 can perform LDPC encoding on 3240 input bits (i.e., LDPC information bits) at a code rate of 3 / 15 based on Table 1 above to generate 12960 LDPC parity bits, and output the LDPC parity bits and the LDPC codeword formed by the LDPC parity bits. In this case, the LDPC codeword can be formed by 16200 bits.

[0105] As another example, the parity check matrix according to the exemplary embodiment may have the following characteristics: Figure 3 The structure shown.

[0106] Reference Figure 3 The parity check matrix 30 is formed by the information submatrix 31 and the parity check submatrix 32, wherein the information submatrix 31 is the submatrix corresponding to the information bits (i.e., LDPC information bits), and the parity check submatrix 32 is the submatrix corresponding to the parity check bits (i.e., LDPC parity check bits).

[0107] Information submatrix 31 includes K ldpc The parity check submatrix consists of N columns and N columns. ldpc_parity =N inner -K ldpc The number of rows in parity matrix 30 is equal to the number of columns in parity submatrix 32, N. ldpc_parity =N inner -K ldpc .

[0108] Additionally, in parity check matrix 30, N inner K represents the length of the LDPC codeword. ldpc N represents the length of the information bits. ldpc_parity =N inner -K ldpc This indicates the length of the parity check bits.

[0109] The structure of information submatrix 31 and parity submatrix 32 will be described below.

[0110] Information submatrix 31 includes K ldpc Columns (i.e., column 0 to column (K)) ldpc A matrix of -1 columns, and subject to the following rules.

[0111] First, K, which constitutes information submatrix 31 ldpc In each of the M columns, every M quantities belong to the same group and are divided into a total of K. ldpc / M column groups. Columns belonging to the same column group have a cyclic shift Q between them. ldpc The relationship. That is to say, Q ldpc It can be regarded as the cyclic shift parameter value for the column group in the information submatrix that constitutes the parity check matrix 30.

[0112] Here, M represents the interval at which the column pattern in information submatrix 31 is repeated (e.g., M = 360), Q ldpc M is the magnitude of the cyclic shift of each column in the information submatrix 31. inner and K ldpc The common divisor of Q is determined and made so that Q ldpc =(N inner -K ldpc ) / M is established. Here, M and Qldpc It is an integer, K ldpc / M also becomes an integer. M and Q ldpc It can have various values ​​depending on the length and code rate of the LDPC codeword.

[0113] For example, when M = 360, the length N of the LDPC codeword inner It's 16200, the bitrate is 6 / 15, and the Q value is... ldpc It could be 27.

[0114] Second, if the i-th (i = 0, 1, ..., K) ldpc The degree of column 0 in the group / M-1 (where degree is the number of values ​​1 in the column, and all columns belonging to the same group have the same degree) is set to D. i And the position (or index) of 1 in each row of the 0th column of the i-th column group is set to Then the index of the row containing the k-th 1 in the j-th column of the i-th column group. This is determined based on Equation 5 below.

[0115]

[0116] In equation 5 above, k = 0, 1, 2, ..., D i -1; i = 0, 1, ..., K ldpc / M-1; j=1,2,...,M-1.

[0117] Meanwhile, Equation 5 above can be expressed as Equation 6 below.

[0118]

[0119] In Equation 10 above, k = 0, 1, 2, ..., D i -1; i = 0, 1, ..., K ldpc / M-1; j=1,2,...,M-1. In Equation 6 above, since j=1,2,...,M-1, (j mod M) can be regarded as j.

[0120] In these equations, N represents the index of the row containing the k-th 1 in the j-th column of the i-th column group. inner K represents the length of the LDPC codeword. ldpc D represents the length of the information bits. i Let Q represent the degree of a column belonging to the i-th column group, M represent the number of columns belonging to a column group, and Q... ldpc This indicates the magnitude of the cyclic displacement of each column group.

[0121] As a result, referring to the equation above, if If the value is known, then the index of the row containing the k-th 1 in the j-th column of the i-th column group is... This can be known. Therefore, when the index value of the row containing the k-th 1 in the 0th column of each column group is stored, in the case of... Figure 3 The column and row positions of 1 in the parity check matrix 30 (i.e., the information submatrix 31 of the parity check matrix 30) can be checked.

[0122] According to the aforementioned rules, the degree of all columns belonging to the i-th column group is D. i Therefore, according to the aforementioned rules, the LDPC code that stores information related to the parity check matrix can be briefly represented as follows.

[0123] For example, when N inner It's 30, K ldpc It is 15, and Q ldpc When it is 3, the position information of the row where 1 is located in the 0th column of the 3 column groups can be represented by the sequence that can be named "weight-1 position sequence" as shown in Equation 7 below.

[0124]

[0125] In equation 7 above, This represents the index of the row containing the k-th 1 in the j-th column of the i-th column group.

[0126] The weighted -1 position sequence of Equation 7 above, which represents the row index of column 1 in column 0 of each column group, can be more concisely represented as Table 2 below.

[0127] [Table 2]

[0128]

[0129] Table 2 above shows the positions of elements with a value of 1 in the parity check matrix. The i-th weight-1 position sequence is represented by the index of the row where 1 is located in the 0th column of the i-th column group.

[0130] The information submatrix 31 of the parity check matrix according to the exemplary embodiment described above can be defined based on Table 3 below.

[0131] Here, Table 3 below shows the index of the row where 1 is located in the 0th column of the i-th column group of the information submatrix 31. That is, the information submatrix 31 is formed by multiple column groups, wherein each of the multiple column groups includes M columns, and the position of 1 in the 0th column of each of the multiple column groups can be defined by Table 3 below.

[0132] For example, when the length N of the LDPC codeword inner When the bitrate is 6 / 15 and M is 360, the index of the row where 1 is located in the 0th column of the i-th column group in the information submatrix 31 is shown in Table 3 below.

[0133] [Table 3]

[0134]

[0135] Since even if the order of the numbers in the sequence corresponding to each column group in Table 3 above is changed, it is still a parity check matrix with the same code. Therefore, even if the order of the values ​​in the sequence corresponding to each column group in Table 3 above is changed, it can also be an example of the code considered in this invention.

[0136] Furthermore, since the cyclic characteristics and algebraic characteristics of degree distribution on the code map are not changed even when the order of the sequences corresponding to each column group in Table 3 above is changed, the case of changing the order of the sequences shown in Table 3 above can also be an example.

[0137] Additionally, as Q is used as a basis for further research, the following is a summary of the relevant information. ldpc The sum of multiples of Q and all sequences corresponding to any column group in Table 3 above does not alter features such as ring characteristics and algebraic characteristics of degree distribution on the codemap, thus equivalently representing Q. ldpc The result of adding multiples of Q to all the sequences shown in Table 3 above can also be an example. Here, it is important to note that when Q is... ldpc The value obtained by adding a multiple of a given sequence to N is equal to or greater than N. inner -K ldpc At that time, the value needs to be changed by adjusting N. inner -K ldpc The value obtained by performing a modulo operation is then applied.

[0138] If the position of 1 in the row of the 0th column of the i-th column group in information submatrix 31, as shown in Table 3 above, is defined, then it can be determined according to Q. ldpc It is cyclically shifted, and therefore the position of the row where 1 is located in the other columns of each column group can be defined.

[0139] For example, as shown in Table 3, since the sequence corresponding to the 0-th column of the 0-th column group of the information submatrix 31 is "27430 519 828 1897 1943 2513 2600 2640 3310 3415 4266 5044 5100 5328 5483 5928 6204 6392 6416 6602 7019 7415 7623 8112 8485 8724 8994 9445 9667", therefore, in the case of the 0-th column of the 0-th column group in the information submatrix 31, 1 is located at the 27-th row, the 430-th row, the 519-th row, ....

[0140] In this case, since Q ldpc =(N inner -K ldpc ) / M=(16200-6480) / 360=27, therefore, the indexes of the rows where 1 is located in the 1st column of the 0-th column group can be 54(=27+27), 457(=430+27), 546(=519+27), ..., 81(=54+27), 484(=457+27), 573(=546+27), ....

[0141] Through the above solution, the indexes of the rows where 1 is located among all rows of each column group can be defined.

[0142] Hereinafter, a method for performing LDPC encoding based on the parity check matrix 30 as shown in Figure 3 will be described.

[0143] First, the information bits to be encoded are set as and the code bits output from LDPC encoding are set as

[0144] In addition, since LDPC codes are systematic, for k(0≤k<K ldpc -1), c k is set as i k . At the same time, the remaining code bits are set as

[0145] Hereinafter, a method for calculating parity check bits p k will be described.

[0146] Hereinafter, q(i,j,0) represents the j-th item of the i-th row in the index list in Table 3 above, for 0<i<360, q(i,j,l) is set as q(i,j,l)=q(i,j,0)+Q ldpc ×l(mod N inner -K ldpcMeanwhile, all accumulations can be achieved through addition in the Galois field (GF)(2). Furthermore, in Table 3 above, since the LDPC codeword length is 16200 and the code rate is 6 / 15, Q... ldpc It is 27.

[0147] Meanwhile, when q(i,j,0) and q(i,j,1) are constrained as described above, the process of calculating the parity check bit is as follows.

[0148] Step 1) Initialize the parity bit to "0". That is, for 0 ≤ k <N inner -K ldpc p k =0.

[0149] Step 2) For 0≤k <K ldpc For all values ​​of k, set i and l to And l:=k(mod 360). Here It is the largest integer not greater than x.

[0150] Next, for all i, i k Accumulated to p q(i,j,l) In other words, calculating p q(i,0,l) =p q(i,0,l) +i k ,p q(i,1,l) =p q(i,1,l) +i k ,p q(i,2,l) =p q(i,2,l) +i k ,...,p q(i,w(i)-1,l) =p q(i,w(i)-1,l) +i k .

[0151] Here, w(i) represents the number of values ​​(elements) in the i-th row of the index list as shown in Table 3 above, and represents the parity check matrix corresponding to i. k The number of 1s in the corresponding column. Additionally, in Table 3 above, q(i,j,0) as the j-th item in the i-th row is the index of the parity bit, and indicates the position of the parity bit in the parity matrix corresponding to i. k The position of row 1 in the corresponding column.

[0152] Specifically, in Table 3 above, q(i,j,0) as the j-th item in the i-th row represents the position of the row where 1 is located in the first (i.e., the 0th) column of the i-th column group in the parity check matrix of the LDPC code.

[0153] q(i,j,0) can also be viewed as allowing real devices to implement i for all i. k Accumulate to pq(i,j,l) The method in the scheme is to use the index of the parity bits generated by LDPC encoding, and can also be regarded as an index in another form when another encoding method is implemented. However, this is just an example, and therefore, it is obvious that an equivalent result to LDPC encoding can be obtained regardless of what encoding method is applied, where the LDPC encoding result can be obtained from the parity matrix of the LDPC code, where the parity matrix of the LDPC code can be generated essentially based on the q(i,j,0) values ​​in Table 3 above.

[0154] Step 3) By targeting 0 <k<N inner -K ldpc All k calculate p k =p k +p k-1 To calculate the parity check bit p k .

[0155] Accordingly, all code bits can be obtained.

[0156] As a result, the parity bit can be calculated using the above scheme. However, this is merely an example, and therefore, it is not applicable to systems based on... Figure 3 The scheme for calculating parity bits using the parity matrix shown can be constrained in various ways.

[0157] Thus, the LDPC encoder 110 can perform LDPC encoding based on Table 3 above to generate LDPC codewords.

[0158] Specifically, the LDPC encoder 110 can perform LDPC encoding on 6480 input bits (i.e., LDPC information bits) at a code rate of 6 / 15 based on Table 3 above, to generate 9720 LDPC parity bits, and output the LDPC parity bits and the LDPC codeword including the LDPC parity bits. In this case, the LDPC codeword can be formed from 16200 bits.

[0159] As described above, the LDPC encoder 110 can encode the input bits at various bit rates to produce LDPC codewords formed by the input bits and LDPC parity bits.

[0160] Repeater 120 causes at least some bits of the LDPC codeword to be repeated in the LDPC codeword, such that these bits are repeated in the current frame to be transmitted. Here, the bits repeated in the LDPC codeword are called repeating bits or repeated bits. Additionally, repeater 120 can output the repeated LDPC codeword (i.e., the repeated LDPC codeword, where the repeated LDPC codeword refers to the LDPC codeword including the repeating bits) to truncation unit 130. Furthermore, repeater 120 can output the repeated LDPC codeword to additional parity generator 140 and provide repeating information related to the repeating bits (e.g., the number, position, etc. of the repeating bits) to additional parity generator 140.

[0161] Specifically, repeater 120 can repeat a predetermined number of LDPC codeword bits (e.g., N) at predetermined positions within the LDPC codeword. repeat (100 LDPC parity bits) are repeated. In this case, the number of repeated bits can have various values ​​depending on the system including transmitter 100 and / or receiver 200.

[0162] For example, repeater 120 may add (or append) a predetermined number of LDPC parity bits after the LDPC information bits in an LDPC codeword that includes LDPC information bits and LDPC parity bits. That is, repeater 120 may add at least some parity bits after the input bits (i.e., LDPC information bits).

[0163] Additionally, the repeater 120 may add a predetermined number of LDPC parity bits after the LDPC parity bits, add the predetermined number of LDPC parity bits to a predetermined position between the LDPC information bits, or add the predetermined number of LDPC parity bits to a predetermined position between the LDPC parity bits.

[0164] Therefore, since a predetermined number of LDPC parity bits within the repeated LDPC codeword can be repeated and additionally sent to the receiver 200, the aforementioned operation can be referred to as repetition.

[0165] In the following description, examples of bit repetition according to various exemplary embodiments will be described with reference to the accompanying drawings.

[0166] When the number of bits to be repeated is N repeat When the number of LDPC parity bits in the LDPC codeword is equal to or less than the number of LDPC parity bits, the repeater 120 may add N bits from the first LDPC parity bit after the LDPC information bits. repeat 1 bit.

[0167] For example, when Nrepeat Equal to or less than N ldpc_parity When, that is, when N repeat ≤N ldpc_parity At times, such as Figure 4 As shown, repeater 120 can be used in LDPC information bits Then add LDPC parity bits The first N in repeat bits .

[0168] Therefore, the first bit to the Nth bit in the LDPC parity check bits repeat One bit is added after the LDPC information bit, and N repeat The bits are located between the LDPC information bits and the LDPC parity bits, such as .

[0169] When the number of bits to be repeated is N repeat When the number of LDPC parity bits is greater than the number of LDPC information bits, repeater 120 may add all LDPC parity bits as part of the repeat bits after the LDPC information bits, adding up to the number of bits obtained by subtracting the number of LDPC parity bits from the number of repeat bits after the earlier added LDPC parity bits.

[0170] In this case, repeater 120 may add up to a number of bits from the existing LDPC parity bits (i.e., LDPC parity bits generated by LDPC encoding) after the first added LDPC parity bits, rather than from the first bit of the repeated LDPC parity bits, by subtracting the number of LDPC parity bits from the number of repeated bits.

[0171] For example, when N repeat Greater than N ldpc_parity When, that is, when N repeat >N ldpc_parity At times, such as Figure 5 As shown, repeater 120 in LDPC information bits Then add N ldpc_parity LDPC parity bits As part of the repeating bits. Additionally, repeater 120 can be used in earlier increments of N. ldpc_parity After the LDPC parity bits, an additional N is added to the LDPC parity bits. repeat -N ldpc_parity bits .

[0172] Therefore, N ldpc_parity One LDPC parity bit can be added after the LDPC information bits, and N bits starting from the first LDPC parity bit... repeat -N ldpc_parity Each bit can be added earlier in N. ldpc_parity An additional LDPC parity bit is added after the first bit.

[0173] Therefore, N repeat The bits are located between the LDPC information bits and the LDPC parity bits, such as .

[0174] The foregoing example describes the addition of repeating bits after the LDPC information bits, which is merely an example. According to another exemplary embodiment, repeater 120 may add repeating bits after the LDPC parity bits.

[0175] For example, when N repeat Equal to or less than N ldpc_parity When, that is, when N repeat ≤N ldpc_parity At times, such as Figure 6 As shown, repeater 120 can be used for LDPC parity bits. Then add N to the LDPC parity bits. repeat bits .

[0176] Therefore, the first bit to the Nth bit in the LDPC parity check bits repeat Bits can be added after the LDPC parity bits, and N repeat The bits are located after the LDPC parity bits, such as .

[0177] Additionally, when N repeat Greater than N ldpc_parity When, that is, when N repeat >N ldpc_parity At times, such as Figure 7 As shown, repeater 120 can add N bits after the LDPC parity check bits generated by LDPC encoding. ldpc_parity LDPC parity bits Additionally, repeater 120 can increase N ldpc_parity After the LDPC parity bits, additional N bits from the first N LDPC parity bits are added. repeat -N ldpc_parity bits .

[0178] Therefore, N ldpc_parity One LDPC parity bit can be added as part of the repeating bits after the LDPC parity bit, and N in the LDPC parity bit repeat -N ldpc_parity Each bit can be added earlier in N. ldpc_parity After the LDPC parity check bits, an additional bit is added as a repeating bit.

[0179] Therefore, according to In the form of N repeat The bits are located after the LDPC parity bits.

[0180] The foregoing example describes the repetition of the LDPC parity bits in the preceding portion, which is merely an example. According to another exemplary embodiment, repeater 120 can repeat LDPC parity bits present in various locations, such as the latter and middle portions of the LDPC parity bits.

[0181] The foregoing example describes the repetition of only the LDPC parity bit in the LDPC codeword. This is merely an example. According to another exemplary embodiment, the LDPC information bit or some of the LDPC information bits and some of the LDPC parity bits may also be repeated.

[0182] The foregoing example illustrates that repetition is performed; this is merely an example. In some cases, repetition can also be omitted. In this case, some of the LDPC parity bits included in the LDPC codeword can be truncated by the truncation 130, which will be described below. Whether to perform repetition can be predetermined by the system.

[0183] The truncation unit 130 can truncate some bits from the LDPC parity bits in the LDPC codeword. Additionally, the truncation unit 130 outputs the truncated LDPC codeword (i.e., the truncated LDPC codeword), where the truncated LDPC codeword refers to the remaining bits in the LDPC codeword excluding the truncated bits. Furthermore, the truncation unit 130 can provide information related to the truncated LDPC parity bits (e.g., the number and position of the truncated bits) to the additional parity generator 140.

[0184] Here, truncation means that some of the LDPC parity bits are not sent to the receiver 200. In this case, the truncation unit 130 can remove the truncated LDPC parity bits or only output the remaining bits in the LDPC codeword except for the truncated LDPC parity bits.

[0185] Specifically, the truncation unit 130 can truncate a predetermined number of bits (e.g., N) in the LDPC parity bits. punc The bits N are truncated. punc It can be 0 or a positive integer, and can have various values ​​depending on the system. N punc =0 means that the deletion was not executed.

[0186] In this case, truncation 130 can truncate a predetermined number of bits following the LDPC parity bits. For example, truncation 130 can sequentially truncate N bits starting from the last LDPC parity bit. punc One LDPC parity bit.

[0187] However, this is merely an example; the position where bits are truncated in LDPC parity bits can be changed in various ways. For example, truncator 130 can truncate N bits at the beginning or middle of the LDPC parity bits. punc One LDPC parity bit or N bits at a predetermined position in the LDPC parity bit are removed. punc One LDPC parity bit.

[0188] In addition, when repetition is performed, the pruner 130 may prune a predetermined number of bits from the LDPC parity bits generated by LDPC encoding without pruning the repetitive bits.

[0189] For example, suppose repetition is performed to add N after the LDPC information bits. repeat One LDPC parity bit.

[0190] In this case, the repeated LDPC codeword includes repeating bits and LDPC parity bits generated through LDPC encoding. In this case, the repeating bits are located between the LDPC information bits and the LDPC parity bits generated through LDPC encoding, and therefore, the truncation unit 130 can truncate N bits from the last LDPC parity bit in the LDPC parity bits generated through LDPC encoding. punc 1 bit.

[0191] The following text will refer to the attached document. Figures 8 to 11 This describes the deletion method according to various exemplary embodiments. Figures 8 to 11 Showing the description when such Figures 4 to 7 The example shown illustrates the truncation method when it is repeatedly executed.

[0192] First, such as Figure 4 As shown in the figure, assume N repeatOne LDPC parity bit is added by repetition after the LDPC information bits and before the LDPC parity bit generated by LDPC encoding.

[0193] In this case, such as Figure 8 As shown, the cutter 130 can cut N. ldpc_parity N LDPC parity bits starting from the last LDPC parity bit punc 1 bit.

[0194] Therefore, the number of LDPC parity bits in the repeated and truncated codeword is N. ldpc_parity +N repeat -N punc And can be made by To express.

[0195] As another example, such as Figure 5 As shown in the figure, assume N repeat One LDPC parity bit is added after the LDPC information bits and before the LDPC parity bit generated by LDPC encoding.

[0196] In this case, such as Figure 9 As shown, the cutter 130 can cut N. ldpc_parity N LDPC parity bits starting from the last LDPC parity bit punc 1 bit.

[0197] Therefore, the number of LDPC parity bits in the repeated and truncated LDPC codeword is N. ldpc_parity +N repeat -N punc And can be made by To express.

[0198] As another example, such as Figure 6 As shown in the figure, assume N repeat Each LDPC parity bit is incremented by repeating the LDPC parity bit generated through LDPC encoding.

[0199] In this case, such as Figure 10 As shown, the cutter 130 can cut N. ldpc_parity N LDPC parity bits starting from the last LDPC parity bit punc 1 bit.

[0200] Therefore, the number of LDPC parity bits in the repeated and truncated LDPC codeword is N. ldpc_parity+N repeat -N punc And can be made by To express.

[0201] As another example, such as Figure 7 As shown in the figure, assume N repeat Each LDPC parity bit is incremented by repeating the LDPC parity bit generated through LDPC encoding.

[0202] In this case, such as Figure 11 As shown, the cutter 130 can cut N. ldpc_parity N LDPC parity bits starting from the last LDPC parity bit punc 1 bit.

[0203] Therefore, the number of LDPC parity bits in the repeated and truncated LDPC codeword is N. ldpc_parity +N repeat -N punc And can be made by To express.

[0204] Additional parity generator 140 can select at least some of the parity bits to generate additional parity bits that will be sent in the previous frame.

[0205] In this case, additional parity bits can be selected from LDPC parity bits generated based on the information bits sent in the current frame and sent to receiver 200 through the previous frame (i.e., the previous frame).

[0206] Specifically, the input bits, including the information bits, are LDPC encoded, and the LDPC parity bits generated by the LDPC encoding are added to the input bits to form an LDPC codeword.

[0207] Additionally, the LDPC codewords are repeated, truncated, and reduced, and the repeated, truncated, and reduced LDPC codewords (i.e., LDPC codeword bits including the repeated bits, excluding the truncated and reduced bits) can be mapped to the frames to be sent to receiver 200. However, when repetition is not performed, the truncated and reduced LDPC codewords can be mapped to the frames to be sent to receiver 200.

[0208] In this configuration, the information bits corresponding to each frame can be sent to the receiver 200 along with the LDPC parity bits in each frame. For example, the repeated, truncated, and reduced LDPC codewords including the information bits corresponding to the (i-1)th frame can be mapped to the (i-1)th frame to be sent to the receiver 200, and the repeated, truncated, and reduced LDPC codewords including the information bits corresponding to the i-th frame can be mapped to the i-th frame to be sent to the receiver 200.

[0209] Additional parity generator 140 can select at least some of the LDPC parity bits generated based on the information bits transmitted in the i-th frame to generate additional parity bits.

[0210] Specifically, some LDPC parity bits generated by LDPC encoding of information bits are truncated and subsequently not sent to receiver 200. In this case, additional parity generator 140 may select some or all of the truncated LDPC parity bits generated by LDPC encoding of information bits transmitted in the i-th frame to generate additional parity bits.

[0211] Additionally, the additional parity generator 140 may select at least some of the LDPC parity bits sent to the receiver 200 via the i-th frame to generate additional parity bits.

[0212] Specifically, the LDPC parity bits included in the repeated, truncated, and reduced LDPC codeword mapped to the i-th frame can be formed by the LDPC parity bits generated by LDPC encoding and the repeated LDPC parity bits.

[0213] In this scenario, the additional parity generator 140 may select at least some of the LDPC parity bits included in the repeated, truncated, and reduced LDPC codeword to be mapped to the i-th frame to generate additional parity bits. However, when repetition is omitted, the additional parity generator 140 may select at least some of the LDPC parity bits included in the truncated and reduced LDPC codeword to be mapped to the i-th frame to generate additional parity bits.

[0214] Additional parity bits can be sent to receiver 200 via frames preceding the i-th frame (i.e., the (i-1)-th frame).

[0215] In other words, the transmitter 100 can not only transmit the repeated, truncated and reduced LDPC codeword including the information bits corresponding to the (i-1)th frame, but also transmit the additional parity bits generated from the LDPC parity bits selected from them to the receiver 200 through the (i-1)th frame, wherein the LDPC parity bits are generated based on the information bits transmitted in the i-th frame.

[0216] The foregoing example describes the additional parity bit being sent to receiver 200 via frame (i-1), which is merely an example. Therefore, the additional parity bit could be sent to receiver 200 via a frame that is sent before frame i in time.

[0217] The following section will describe in detail a method for generating additional parity bits by selecting bits from the LDPC parity bits.

[0218] The additional parity generator 140 can select up to a number of additional parity bits in the LDPC parity bits to generate additional parity bits.

[0219] Specifically, when the number of truncated LDPC parity bits is equal to or greater than the number of additional parity bits, the additional parity generator 140 can select as many bits as the number of additional parity bits from the first LDPC parity bit among the truncated LDPC parity bits to generate additional parity bits.

[0220] When the number of truncated LDPC parity bits is less than the number of additional parity bits, the additional parity generator 140 may first select all the truncated LDPC parity bits, and then select additional bits from the first bit of the LDPC parity bits included in the LDPC codeword, the same number of bits as obtained by subtracting the number of truncated LDPC parity bits from the number of additional parity bits, to generate additional parity bits.

[0221] Specifically, when repetition is not performed, the LDPC parity bits included in the LDPC codeword are LDPC parity bits generated by LDPC encoding.

[0222] In this case, the additional parity generator 140 may first select all the truncated LDPC parity bits, and select the same number of bits as obtained by subtracting the number of truncated LDPC parity bits from the number of additional parity bits to generate additional parity bits, starting from the first LDPC bit among the LDPC parity bits generated by LDPC encoding.

[0223] Here, the LDPC parity bits generated by LDPC encoding are divided into undisturbed LDPC parity bits and truncated LDPC parity bits. Therefore, when truncation is performed starting from the last bit of the LDPC parity bits generated by LDPC encoding, if bits are selected starting from the first bit of the LDPC parity bits generated by LDPC encoding to be used for additional parity bits, the bits can be selected in the order of undisturbed LDPC parity bits and truncated LDPC parity bits.

[0224] When repetition is performed, the additional parity generator 140 can select at least some bits from the repeated LDPC codeword to generate additional parity bits.

[0225] As described above, the LDPC parity bits of the repeated LDPC codeword include the repeating bits and the LDPC parity bits generated by LDPC encoding. In this case, the additional parity generator 140 may first select all the truncated LDPC parity bits, and from the repeating bits and the LDPC parity bits generated by LDPC encoding, select an additional number of bits, starting from the first bit, equal to the number obtained by subtracting the number of truncated LDPC parity bits from the number of additional parity bits, to generate additional parity bits.

[0226] Therefore, when an additional number of bits are selected, equal to the number obtained by subtracting the number of truncated LDPC parity bits from the number of additional parity bits, repeated bits are selected first. Furthermore, when the number obtained by subtracting the number of truncated LDPC parity bits from the number of additional parity bits exceeds the number of repeated bits, bits can also be selected from the LDPC parity bits generated through LDPC encoding. In this case, when bits are also selected from the LDPC parity bits generated through LDPC encoding, the first bit among the LDPC parity bits generated through LDPC encoding can be selected first.

[0227] As mentioned above, the repeated bit can be located at various positions within the repeated LDPC codeword.

[0228] In the following text, the method for generating additional parity when repeated execution is described in more detail with reference to, for example, the LDPC parity bit being repeated between the LDPC information bit and the LDPC parity bit generated by LDPC encoding.

[0229] In this case, it is assumed that the repeater 120 selects at least some of the LDPC parity bits and adds the selected parity bits after the LDPC information bits, and the truncater 130 performs truncation starting from the last bit of the LDPC parity bits, which includes the repeated LDPC parity bits and the LDPC parity bits generated by encoding.

[0230] In this case, the additional parity generator 140 can select at least some bits from the repeating bits added after the input bits (i.e., the LDPC information bits) based on the number of additional parity bits and the number of truncated LDPC parity bits to generate additional parity bits.

[0231] Specifically, when the number of additional parity bits is greater than the number of truncated LDPC parity bits, the additional parity generator 140 selects all the truncated LDPC parity bits and selects bits from the first bit of the repeated bits that correspond to the number obtained by subtracting the number of truncated LDPC parity bits from the number of additional parity bits to generate additional parity bits.

[0232] Here, regarding the additional parity bits, when bits are selected starting from the first bit in the LDPC parity bits, they can be selected in the order of repeating bits and LDPC parity bits generated by LDPC encoding. Additionally, within the LDPC parity bits generated by LDPC encoding, the additional bits can be selected in the order of undisturbed LDPC parity bits and truncated LDPC parity bits.

[0233] Thus, when up to a preset number of additional parity bits are generated, the truncated bits are selected with the highest priority. Furthermore, when more than the number of truncated bits are selected, the repeated LDPC parity bits among the LDPC parity bits are selected with priority based on whether repetition is performed.

[0234] This results in coding gain because truncated bits not transmitted in the current frame are selected and transmitted as additional parity bits. Furthermore, after the truncated bits are selected, repeated LDPC parity bits that are considered relatively more important are selected to form additional parity bits. Additionally, the LDPC parity bits are arranged according to the truncating order, and therefore can be considered as being arranged according to the priority of the parity bits. Details related to the truncating order will be described below.

[0235] When truncation is not performed, that is, when the number of bits truncated is 0, the additional parity generator 140 can select at least some bits from the LDPC codeword or the repeated LDPC codeword to generate additional parity bits.

[0236] First, when repetition is not performed, the additional parity generator 140 can select as many bits as the number of additional parity bits, starting from the first bit of the LDPC parity bits, to generate additional parity bits. That is, when the number of truncated bits is 0 and the number of repeated bits is 0, the additional parity generator 140 can select as many bits as the number of additional parity bits, starting from the first bit of the LDPC parity bits generated by LDPC encoding, to generate additional parity bits.

[0237] When the repetition is performed, the additional parity generator 140 can select as many bits as the number of additional parity bits from the first bit of the repeated LDPC parity bits to generate additional parity bits.

[0238] In other words, when the number of truncated bits is 0 and the number of repeated bits is 1 or greater, the additional parity generator 140 can select as many bits as the number of additional parity bits from the first bit of the repeated bits and the LDPC parity bits generated by LDPC encoding to generate additional parity bits.

[0239] Therefore, when repeated bits are selected first, and the number obtained by subtracting the number of repeated bits from the number of additional parity bits exceeds the number of repeated bits, bits can be additionally selected from the LDPC parity bits generated by LDPC encoding. In this case, when bits are additionally selected from the LDPC parity bits generated by LDPC encoding, the first bit among the LDPC parity bits generated by LDPC encoding can be selected first.

[0240] The truncated bits refer to the bits that are removed from the truncated LDPC codewords that will be sent in the frame where the information bits are sent.

[0241] The number of additional parity bits (hereinafter referred to as N) AP In the aforementioned example where the number of truncated LDPC parity bits is greater than the number of truncated LDPC parity bits, after all truncated LDPC parity bits are selected as the initial append bits, the remaining append bits (i.e., the number obtained by subtracting the number of truncated LDPC parity bits from the number of append parity bits) are (N). AP -N puncThe corresponding bit is selected starting from the first bit in the repeating bits; this is just one example. That is, the additional parity generator 140 can also select N bits starting from the first information bit or the first externally encoded bit. AP -N punc 1 bit.

[0242] Additionally, when the LDPC parity bits are not truncated, the additional parity generator 140 can select N bits starting from the first bit of the repeated bits. AP Each bit is used to generate an additional parity bit.

[0243] The method for calculating the number of additional parity bits will be described below.

[0244] First, the additional parity generator 140 calculates the temporary number N of additional parity bits based on the following equation 8. AP_temp .

[0245]

[0246] In equation 8 above,

[0247] In addition, N ldpc_parity N is the number of LDPC parity bits. punc This is the number of LDPC parity bits that were truncated. Additionally, N... outer This represents the number of bits that have undergone external encoding. Here, when external encoding is performed using BCH codes, N... outer This indicates the number of bits encoded by BCH. Additionally, N... repeat N represents the number of repeated bits; when repetition is not performed, N is... repeat =0.

[0248] Therefore, N ldpc_parity -N punc +N repeat N is the total number of LDPC parity bits transmitted in the current frame in which the information bits are transmitted (i.e., the total number of LDPC parity bits included in the LDPC codeword after duplication, truncation, and reduction), and N outer +N ldpc_parity -N punc +N repeat It is the total number of LDPC codeword bits transmitted in the current frame (i.e., the total number of LDPC codeword bits after duplication, pruning, and reduction).

[0249] Additionally, K represents the ratio of the number of additional parity bits to half the total number of bits constituting the repeated, truncated, and reduced LDPC codeword. Here, when K=2, the number of additional parity bits is equal to the total number of LDPC codewords transmitted in the current frame.

[0250] Thus, the number of additional parity bits can be determined based on the total number of bits transmitted in the current frame.

[0251] Reference Figure 12 According to an exemplary embodiment, when calculating the length of the additional parity bits, all of the truncated bits, repeated bits, and LDPC parity bits are selected considering performance and complexity, and subsequently no longer selected for the additional parity bits. That is, as... Figure 12 As shown, the length of the additional parity bits is equal to or less than N. AP_max (=N ldpc_parity +N punc +N repeat In other words, the length of the additional parity bits is no greater than N. AP_max (=N ldpc_parity +N punc +N repeat ).

[0252] For example, when the number of truncated LDPC parity bits is 3200 and K=2, assume the number of additional parity bits is 13000 (=N). outer +N ldpc_parity -N punc =6480+9720-3200).

[0253] In this case, since the number of truncated LDPC parity bits is 3200, the number of bits selected is 12920 (=3200+9720) when all LDPC parity bits truncated for the additional parity bits are selected and all LDPC parity bits are selected. Therefore, 80 bits can still be selected when there is no separate limit. However, as shown in Equation 12 below, when the maximum length of the additional parity bits is limited to N... ldpc_parity +N punc +N repeat At that time, the number of additional parity bits is limited to 12920, and 80 bits do not need to be selected additionally.

[0254] However, this limitation on the maximum length of the additional parity bit is merely an example, and when the length of the additional parity bit is not limited, the temporary N of the additional parity bit... AP_temp It can be calculated based on Equation 9 below.

[0255] N AP_temp =0.5XKx(N) outer +N Idpc_parity -N punc +N repeat ), K = 0, 1, 2 …(9)

[0256] When the length of the additional parity bits is not limited, the additional parity generator 140 can calculate the temporary N of the additional parity bits based on Equation 9. AP_temp .

[0257] The additional parity generator 140 can be based on the temporary number N of additional parity bits. AP_temp To calculate the number of additional parity bits N AP The number of temporary parity bits is calculated based on Equation 8 or Equation 9 above.

[0258] Specifically, the additional parity generator 140 can calculate the number N of additional parity bits based on the following equation 10. AP .

[0259] Thus, the number of additional parity bits N AP The temporary number N can be based on the additional parity bits. AP_temp To calculate, the number of temporary bits N for additional parity bits. AP_temp It is calculated based on Equation 8 or Equation 9 above, and specifically, the number N of additional parity bits. AP It can be calculated based on Equation 10 below.

[0260]

[0261] In equation 10 above, η MOD It refers to the modulation order. For example, in quadrature phase shift keying (QPSK), 16-quadrature amplitude modulation (QAM), 64-QAM, and 256-QAM, η MOD The possible values ​​are 2, 4, 6, and 8.

[0262] Therefore, the number of additional parity bits can be an integer multiple of the modulation order. That is, since the additional parity bits are modulated separately from the information bits that will be mapped to constellation symbols, the number of additional parity bits can be determined to be an integer multiple of the modulation order, as in Equation 10 above.

[0263] In this case, equation 8 above can be expressed as equation 11 below, and the above equations...

[0264] Equation 9 can be expressed as Equation 12 below.

[0265]

[0266]

[0267] In equations 11 and 12 above, α can be equal to 0.5.

[0268] Thus, the number of additional parity bits can be determined based on the number of externally encoded bits transmitted in the current frame and the number of remaining parity bits after truncation.

[0269] Here, when repetition is performed, the number of additional parity bits can be determined based on the number of externally encoded bits sent in the current frame, the number of remaining parity bits after truncation, and the number of bits repeated in the current frame.

[0270] The following text describes how the bitrate changes depending on the use of an additional parity bit.

[0271] If the code rate R when the additional parity bit is not sent is equal to k / n, then the code rate R when the additional parity bit is sent is... ap Equals k / (n+N) AP And N AP It depends on the value of K and has a value of 1 / 2×n or n. Therefore, the code rate R is 1 / 2×n when an additional parity bit is sent. ap This equals k / (3 / 2×n)=2 / 3R or k / (2×n)=1 / 2R, and therefore the code rate is reduced to 2 / 3 or 1 / 2 compared to the case where the additional parity bit is not sent, thus achieving coding gain. Furthermore, the bits other than the additional parity bit, and the fact that the additional parity bit is sent in other frames, result in graded gain. This allows maintaining the characteristic of changing the code rate according to the input length in response to changes in the code rate without considering the input length (i.e., the length of the input information bits), as described above.

[0272] The method for generating additional parity bits by selecting additional bits from LDPC parity bits will be described in detail below with reference to the accompanying drawings.

[0273] The additional parity generator 140 can select as many bits as calculated to generate additional parity bits in the LDPC parity bits.

[0274] Specifically, when the number of additional parity bits is equal to or less than the number of truncated LDPC parity bits, the additional parity generator 140 can select as many bits as calculated from the first bit of the truncated LDPC parity bits to generate additional parity bits.

[0275] For example, LDPC parity bits are added after LDPC information bits by repetition, and thus, the repeated LDPC codeword is composed of LDPC information bits, repeated LDPC parity bits, and LDPC parity bits generated by LDPC encoding in that order.

[0276] ) can be Figure 13 The diagram shown is used to represent this.

[0277] Specifically, when N AP Equal to or less than N punc (that is, N) AP ≤N punc When, such as Figure 14 and Figure 15 As shown, the additional parity generator 140 can select N bits from the first bit of the truncated LDPC parity bits. AP Each bit is used to generate additional parity bits.

[0278] Therefore, for the additional parity bits, It can be selected.

[0279] When the number of additional parity bits is greater than the number of truncated LDPC parity bits, the additional parity generator 140 selects all the truncated LDPC parity bits and selects bits from the first bit of the repeated bits that correspond to the number obtained by subtracting the number of truncated LDPC parity bits from the number of additional parity bits to generate additional parity bits.

[0280] For example, when N AP Greater than N punc (that is, N) AP >N punc When, such as Figure 16 and Figure 17 As shown, the additional parity generator 140 can first select all the truncated LDPC parity bits. Therefore, firstly, It can be selected.

[0281] Additionally, the additional parity generator 140 can select N bits from the first bit of the LDPC parity bits, which include the repeated LDPC parity bits and the LDPC parity bits generated by LDPC encoding. AP -N punc 1 bit.

[0282] In this case, LDPC parity bits can be added after LDPC information bits by repetition, and thus, the repeated parity bits and the LDPC parity bits generated by LDPC encoding are arranged sequentially to form the LDPC parity bits in the LDPC codeword.

[0283] Therefore, the additional parity generator 140 can additionally select, starting from the first bit of the repeated LDPC parity bits, the same number of bits as obtained by subtracting the number of truncated LDPC parity bits from the number of additional parity bits. In this case, since the additional parity bits are selected starting from the first bit of the repeated LDPC parity bits, when N AP -N punc The number N greater than the number of repeated LDPC parity bits repeat At the same time, at least some of the LDPC parity bits generated by LDPC encoding can also be selected as additional parity bits.

[0284] therefore, It can be selected additionally.

[0285] As a result, regarding the additional parity bits, and It can be selected.

[0286] Transmitter 100 can send bits output from censor 130 and bits output from additional parity generator 140 to receiver 200.

[0287] In this case, transmitter 100 can send LDPC codeword bits (i.e., the repeated, truncated and reduced LDPC codeword output from truncator 130 with no padding zero bits) to receiver 200.

[0288] Specifically, the transmitter 100 can modulate the repeated, truncated and reduced LDPC codeword bits and the additional parity check bits respectively, map the modulated bits to constellation symbols, map the symbols to frames, and send the frames to the receiver 200.

[0289] However, when repetition is omitted, transmitter 100 can send LDPC codeword bits (i.e., truncated and reduced LDPC codewords with no padding zero bits) to receiver 200.

[0290] In this case, the transmitter 100 can use QPSK, 16-QAM, 64-QAM, 256-QAM, etc. to modulate the repeated, truncated and reduced LDPC codeword bits (or truncated and reduced LDPC codeword bits) and additional parity bits.

[0291] The transmitter 100 can map additional parity bits generated based on the information bits transmitted in the current frame to frames prior to the current frame.

[0292] In other words, the transmitter 100 can map the truncated and reduced LDPC codeword, which includes the information bits corresponding to the (i-1)th frame, to the (i-1)th frame, and additionally map the additional parity bits generated based on the information bits corresponding to the i-th frame to the (i-1)th frame for transmission to the receiver 200.

[0293] Therefore, the information bits corresponding to the (i-1)th frame, the parity bits generated based on the information bits corresponding to the (i-1)th frame, and the additional parity bits generated based on the information bits corresponding to the i-th frame can be mapped to the (i-1)th frame.

[0294] Since the information bits are signaling that includes signaling information about the data to be provided, the transmitter 100 can map the data along with the signaling used to process the data into a frame and send the mapped data to the receiver 200.

[0295] Specifically, transmitter 100 can process data in a specific scheme to generate constellation symbols and map the generated constellation symbols to the data symbols of each frame. Additionally, transmitter 100 can map signaling for the data mapped to each frame to the frame preamble. For example, transmitter 100 can map signaling including signaling information for the data mapped to the i-th frame to the i-th frame.

[0296] As a result, receiver 200 can use signaling obtained from the frame to acquire and process data from the frame.

[0297] According to an exemplary embodiment, the aforementioned information bits can be implemented by L1-detail signaling. Therefore, the transmitter 100 can generate additional parity bits for the L1-detail signaling using the aforementioned method and send the generated additional parity bits to the receiver 200.

[0298] Here, L1-detail signaling can be the signaling defined in the Advanced Television Systems Committee (ATSC) 3.0 standard.

[0299] Specifically, there are seven (7) modes for processing L1-detail signaling. The transmitter 100 according to this exemplary embodiment can generate additional parity bits for L1-detail signaling according to these seven modes.

[0300] In addition to L1-detail signaling, the ATSC 3.0 standard also defines L1-basic signaling. Transmitter 100 can process L1-basic and L1-detail signaling using a specific scheme and send the processed L1-basic and L1-detail signaling to receiver 200.

[0301] The detailed methods for processing L1-basic signaling and L1-detail signaling will be described below.

[0302] Transmitter 100 can map L1-basic signaling and L1-detail signaling to the preamble of a frame and map data to the data symbols of the frame, and then send the frame to receiver 200.

[0303] Reference Figure 18 A frame can consist of three parts: a bootstrap section, a preamble section, and a data section.

[0304] The bootstrapping section is used for initial synchronization and provides the basic parameters required by the receiver 200 to decode L1 signaling. In addition, the bootstrapping section may include information related to the mode in which the transmitter 100 processes L1-basic signaling (i.e., information related to the mode used by the transmitter 100 for processing L1-basic signaling).

[0305] The preamble includes L1 signaling and can consist of two parts: L1 basic signaling and L1 detailed signaling.

[0306] Here, L1 basic signaling may include information related to L1 detailed signaling, and L1 detailed signaling may include information related to data. Here, the data is broadcast data used to provide broadcast services and can be transmitted through at least one physical layer channel (PLP).

[0307] Specifically, L1-basic signaling includes information required by receiver 200 to process L1-detail signaling. This information includes, for example, information related to the mode in which transmitter 100 processes L1-detail signaling (i.e., information related to the mode used by transmitter 100 for processing L1-detail signaling), information related to the length of L1-detail signaling, information related to the additional parity mode (i.e., information related to the K value used by transmitter 100 to generate additional parity bits using L1B_L1_Detail_additional_parity_mode) (here, when L1B_L1_Detail_additional_parity_mode is set to "00", K = 0 and additional parity bits are not used), and information related to the total length of cells. Additionally, L1-basic signaling may include basic signaling information related to the system including transmitter 100, such as the Fast Fourier Transform (FFT) size, guard interval, and pilot pattern.

[0308] In addition, L1-detail signaling includes the information required by receiver 200 to decode PLP, such as the start position of the cell mapped to each PLP data symbol, PLP identifier (ID), PLP size, modulation scheme, code rate, etc.

[0309] Therefore, receiver 200 can obtain frame synchronization, obtain L1-basic signaling and L1-detail signaling from the preamble, and use L1-detail signaling to receive the service data required by the user from the data symbols.

[0310] The methods for processing L1-basic signaling and L1-detail signaling will be described in more detail below with reference to the accompanying drawings.

[0311] Figure 19 and Figure 20 This is a block diagram used to describe the detailed configuration of the transmitter 100 according to an exemplary embodiment.

[0312] Specifically, such as Figure 19 As shown, in order to process L1-basic signaling, transmitter 100 may include scrambler 211, BCH encoder 212, zero filler 213, LDPC encoder 214, parity permuter 215, repeater 216, truncate 217, zero remover 219, bit demultiplexer 219, and constellation mapper 221.

[0313] In addition, such as Figure 20As shown, in order to process L1-detail signaling, transmitter 100 may include a splitter 311, a scrambler 312, a BCH encoder 313, a zero-padding unit 314, an LDPC encoder 315, a parity permuter 316, a repeater 317, a truncation unit 318, an additional parity generator 319, a zero remover 321, bit demultiplexers 322 and 323, and constellation mappers 324 and 325.

[0314] Here, such as 19 and Figure 20 The components shown are for performing encoding and modulation of L1-basic signaling and L1-detail signaling; this is merely an example. According to another exemplary embodiment, Figure 19 and Figure 20 Some components shown can be omitted or changed, and other components can be added. Additionally, the positions of some components can be changed. For example, repeater 216 and repeater 317 can be positioned after truncate 217 and truncate 318, respectively.

[0315] Figure 19 The LDPC encoder 315, repeater 317, truncate 318, and additional parity generator 319 shown can each perform the functions of the encoder 315, repeater 317, truncate 318, and additional parity generator 319, respectively. Figure 1 The operations performed by the LDPC encoder 110, repeater 120, truncate 130, and additional parity generator 140 shown in the figure.

[0316] In the Figure 19 and Figure 20 In the description, for convenience, components that perform common functions will be described together.

[0317] L1-basic signaling and L1-detail signaling can be protected by concatenating the BCH external code and the LDPC internal code. However, this is merely an example. Therefore, as an external code performed before the internal code in the concatenated encoding, another code such as CRC encoding, besides BCH encoding, can be used. Alternatively, L1-basic signaling and L1-detail signaling can be protected solely by the LDPC internal code without the external code.

[0318] First, L1-basic signaling and L1-detail signaling can be scrambled. Additionally, L1-basic and L1-detail signaling are BCH encoded, and therefore, the BCH parity bits of the L1-basic and L1-detail signaling generated from the BCH encoding can be added to the L1-basic and L1-detail signaling respectively. Furthermore, the concatenated signaling and BCH parity bits can be additionally protected using truncated and reduced 16KLDPC codes.

[0319] To provide various robustness levels suitable for a wide signal-to-noise ratio (SNR) range, the protection levels for L1-basic signaling and L1-detail signaling can be divided into seven (7) modes. That is, the protection levels for L1-basic signaling and L1-detail signaling can be divided into seven modes based on the LDPC code, modulation order, reduction / truncation parameter (i.e., the ratio of the number of bits to be truncated to the number of bits to be reduced), and the number of bits to be substantially truncated (i.e., the number of bits to be substantially truncated when the number of bits to be reduced is 0). In each mode, at least one different combination of LDPC code, modulation order, constellation, and reduction / truncation mode can be used.

[0320] The signaling processing mode of transmitter 100 can be preset according to the system. Therefore, transmitter 100 can determine the parameters for processing the signaling (e.g., modulation and code rate for each mode, parameters for BCH encoding, parameters for zero-padding, reduction mode, code rate / code length of LDPC code, group-wise interleaving mode, parameters for repetition, parameters for truncation, and modulation scheme, etc.) based on the preset parameters, and can process the signaling based on these parameters and transmit the processed signaling to receiver 200. For this purpose, transmitter 100 can pre-store the signaling processing parameters according to the mode.

[0321] The modulation and code rate configurations (ModCod configurations) for the seven modes used to process L1-basic signaling and the seven modes used to process L1-detail signaling are shown in Table 4 below. Transmitter 100 can encode and modulate the signaling according to the corresponding mode based on the ModCod configuration defined in Table 4 below. That is, transmitter 100 can determine the encoding and modulation scheme for the signaling in each mode based on Table 4 below, and can encode and modulate the signaling according to the determined scheme. In this case, even when modulating L1 signaling with the same modulation scheme, transmitter 100 can use different constellations.

[0322] [Table 4]

[0323]

[0324] In Table 4 above, K sig This indicates the number of information bits in the coded block. In other words, since the length is K... sig The L1 signaling bits are encoded to produce a coded block, so the length of the L1 signaling in a coded block becomes K. sig Therefore, the size is K. sig The L1 signaling bits can be considered to correspond to an LDPC coded block.

[0325] Referring to Table 4 above, for L1-basic signaling K sig The value is fixed at 200. However, due to the change in the amount of L1-detail signaling bits, K for L1-detail signaling... sig The value changes.

[0326] Specifically, in the case of L1-detail signaling, the number of L1-detail signaling bits changes, and therefore when the number of L1-detail signaling bits is greater than a preset value, the L1-detail signaling can be segmented to have a length equal to or less than the preset value.

[0327] In this case, each size of the segmented L1-detail signaling block (that is, a fragment of L1-detail signaling) can have K as defined in Table 4 above. sig Value. Additionally, the size is K. sig Each of the segmented L1-detail signaling blocks can correspond to an LDPC coded block.

[0328] However, when the number of L1 signaling bits is equal to or less than a preset value, the L1-detail signaling may not be segmented. In this case, the size of the L1-detail signaling may have the K value defined in Table 4 above. sig Value. Additionally, the size is K. sig The L1-detail signaling can correspond to an LDPC coded block.

[0329] The method for segmenting L1-detail signaling will be described in detail below.

[0330] The divider 311 can divide L1-detail signaling. Specifically, since the length of L1-detail signaling changes, when the length of L1-detail signaling is greater than a preset value, the divider 311 can divide the L1-detail signaling into bits with a number of bits equal to or less than the preset value, and output each of the divided L1-detail signaling bits to the scrambler 312.

[0331] However, when the length of the L1-detail signaling is equal to or less than the preset value, the splitter 311 does not perform a separate splitting operation.

[0332] The method for segmenting L1-details, executed by segmenter 311, is as follows.

[0333] The number of L1-detail signaling bits varies and depends primarily on the number of PLPs. Therefore, at least one forward error correction (FEC) frame is required to transmit all bits of the L1-detail signaling. Here, the FEC frame can represent the encoded form of the L1-detail signaling, and thus, parity bits are added to the L1-detail signaling according to the encoding.

[0334] Specifically, when the L1-detail signaling is not segmented, it is BCH-encoded and LDPC-encoded to generate one FEC frame, and therefore, L1-detail signaling transmission requires one FEC frame. On the other hand, when the L1-detail signaling is segmented into at least two segments, each segment is BCH-encoded and LDPC-encoded to generate at least two FEC frames, and therefore, L1-detail signaling transmission requires at least two FEC frames.

[0335] Therefore, the segmenter 311 can calculate the number N of FEC frames for L1-detail signaling based on the following equation 13. L1D_FECFRAME In other words, the number of FEC frames for L1-detail signaling can be determined based on Equation 13 below.

[0336]

[0337] In equation 13 above, It represents the smallest integer that is equal to or greater than x.

[0338] Furthermore, in equation 13 above, such as Figure 21 As shown, K L1D_ex_pad This indicates the length of the L1-detail signaling excluding the L1 padding bits, and can be determined by the value of the L1B_L1_Detail_size_bits field included in the L1-basic signaling.

[0339] In addition, K seg K represents the number of information bits (i.e., LDPC information bits) output to the LDPC encoder 315. ldpc The number of thresholds for segmentation is limited. Additionally, K... seg It can be limited based on the number of BCH parity bits in the BCH code and multiples of 360.

[0340] K seg It is determined such that, after the L1-detail signaling is segmented, the number K of information bits in the coded block is [value missing]. sig Set to be equal to or less than K ldpc -M outer Specifically, when L1-detail signaling is based on K... seg When segmented, the length of the segmented L1-detail signaling does not exceed K. seg Therefore, when K seg When configured as shown in Table 5 below, the length of the segmented L1-detail signaling is set to be less than or equal to K. ldpc -M outer .

[0341] Here, M outer and Kldpc See Tables 6 and 7 below. For sufficient robustness, K is used for L1-detail signaling mode 1. seg The value can be set to K. ldpc -M outer -720.

[0342] K for each mode of L1-detail signaling seg It can be defined as shown in Table 5 below. In this case, the divider 311 can determine K according to the corresponding pattern shown in Table 5 below. seg .

[0343] [Table 5]

[0344]

[0345] like Figure 21 As shown, the entire L1-detail signaling can be formed by L1-detail signaling and L1 padding bits.

[0346] In this case, the splitter 311 can calculate the length of the L1_PADDING field of the L1-detail signaling (i.e., the number of L1 padding bits) based on the following equation 14. L1D_PAD ).

[0347] However, K is calculated based on the following equation 18. L1D_PAD This is just one example. That is, the segmenter 311 can be based on K. L1D_ex_pad Value and N L1D_FECFRAME The value is used to calculate the length of the L1_PADDING field in the L1-detail signaling (i.e., the number of L1 padding bits K). L1D_PAD As an example, K L1D_PAD The value can be obtained based on Equation 14 below. That is, Equation 14 below is only used to obtain K. L1D_PAD An example of a value-based approach, based on K L1D_ex_pad Value and N L1D_FECFRAME Another method of value can be applied to obtain equivalent results.

[0348]

[0349] Additionally, the divider 311 can use K L1D_PAD The L1_PADDING field is filled with zero bits (i.e., bits with a value of 0). Therefore, as Figure 21 As shown, K L1D_PAD Zero bits can be filled into the L1_PADDING field.

[0350] Thus, by calculating the length of the L1_PADDING field and filling the L1_PADDING field with zero bits of the calculated length, the L1-detail signaling can be divided into multiple blocks of the same number of bits when the L1-detail signaling is segmented.

[0351] Next, the splitter 311 can calculate the final length K of the entire L1-detail signaling, including the zero-padding bits, based on Equation 15 below. L1D .

[0352] K L1D =K L1D_ex_pad +K L1D_PAD ...(15)

[0353] Additionally, the divider 311 can calculate N based on the following equation 16. L1D_FECFRAME The number of information bits in each block of the blocks, K sig .

[0354] K sig =K L1D / N L1D_FECFRAME ...(16)

[0355] Next, the divider 311 can be accessed via K sig The number of bits is used to segment the L1-detail signaling.

[0356] Specifically, such as Figure 21 As shown, when N L1D_FECFRAME When the value is greater than 1, the divider 311 can handle the number of bits K. sig Segment the L1-detail signaling to divide it into N segments. L1D_FECFRAME Each block.

[0357] Therefore, L1-detail signaling can be segmented into N L1D_FECFRAME Blocks, N L1D_FECFRAME The number of L1-detail signaling bits in each block of a block can be K. sig Additionally, each segmented L1-detail signaling is encoded. As a result of the encoding, coded blocks (i.e., FEC frames) are formed, such that N L1D_FECFRAME The number of L1-detail signaling bits in each coding block can be K. sig .

[0358] However, when L1-detail signaling is not segmented, K sig =K L1D_ex_pad .

[0359] The segmented L1-detail signaling blocks can be encoded through the following process.

[0360] Specifically, the size is K sig All bits of each L1-detail signaling block in the L1-detail signaling block can be scrambled. Then, each of the scrambled L1-detail signaling blocks can be encoded by concatenating the BCH external code and the LDPC internal code.

[0361] Specifically, each L1-detail signaling block is encoded by the BCH, therefore M outer (=168) BCH parity bits can be added to each block's K. sig Each block contains L1-detail signaling bits, and the concatenation of the L1-detail signaling bits and BCH parity bits for each block can be encoded using a reduced and truncated 16K LDPC code. Details of the BCH and LDPC codes will be described below. However, the exemplary embodiment only describes M... outer =168, but it is clear that M outer It can be changed to a suitable value according to the needs of the system.

[0362] Scramblers 211 and 312 can scramble L1-basic signaling and L1-detail signaling, respectively. Specifically, scramblers 211 and 312 can randomize L1-basic signaling and L1-detail signaling, and output the randomized L1-basic signaling and L1-detail signaling to BCH encoder 212 and BCH encoder 313, respectively.

[0363] In this case, scramblers 211 and 312 can be K sig Scrambling is performed on information bits in units of scrambling.

[0364] In other words, since the number of L1-basic signaling bits sent to receiver 200 per frame is 200, scrambler 211 can be configured according to K... sig (=200) Scramble the L1-basic signaling bits.

[0365] Because the number of L1-basic signaling bits sent to receiver 200 per frame varies, in some cases, L1-detail signaling can be segmented by segmenter 311. Additionally, segmenter 311 can be segmented by K... sig The L1-detail signaling, formed by L1-detail signaling blocks of bits or segments, is output to scrambler 312. As a result, scrambler 312 can output L1-detail signaling in increments of K bits or segments. sig The L1-detail signaling bits output from the splitter 311 are scrambled.

[0366] BCH encoders 212 and 313 can perform BCH encoding on L1-basic signaling and L1-detail signaling to produce BCH parity bits.

[0367] Specifically, BCH encoder 212 and BCH encoder 313 can perform BCH encoding on the L1-basic signaling and L1-detail signaling output from scrambler 211 and scrambler 313 respectively to generate BCH parity bits, and output the BCH-encoded bits to zero-filler 213 and zero-filler 314 respectively, wherein the BCH parity bits are added to each of the L1-basic signaling and L1-detail signaling in the BCH-encoded bits.

[0368] For example, BCH encoders 212 and 313 input K sig Each bit is BCH encoded to produce M. outer (that is, K) sig =K payload ) BCH parity bits and will be determined by N outer (=K sig +M outer The bits formed by the BCH encoding are output to the zero-filler 213 and the zero-filler 314 respectively.

[0369] The parameters for BCH encoding can be defined as shown in Table 6 below.

[0370]

[0371] Reference Figure 19 and Figure 20 It is understandable that LDPC encoder 214 and LDPC encoder 315 can be set after BCH encoder 212 and BCH encoder 313, respectively.

[0372] Therefore, L1-basic signaling and L1-detail signaling can be protected by concatenating the BCH external code and the LDPC internal code.

[0373] Specifically, L1-basic signaling and L1-detail signaling are BCH encoded, and therefore, BCH parity bits for L1-basic signaling can be added to L1-basic signaling, and BCH parity bits for L1-detail signaling can be added to L1-detail signaling. Furthermore, the concatenated L1-basic signaling and BCH parity bits can be additionally protected by LDPC codes, and the concatenated L1-detail signaling and BCH parity bits can also be additionally protected by LDPC codes.

[0374] Here, assuming the LDPC code is a 16K LDPC code, therefore, in BCH encoder 212 and BCH encoder 213, for N innerThe systematic BCH code = 16200 (that is, the code length of the 16K LDPC code is 16200, and the LDPC codeword generated by LDPC encoding can be formed by 16200 bits) can be used for external encoding of L1-basic signaling and L1-detail signaling.

[0375] Zero-paffers 213 and 314 fill in zero bits. Specifically, for LDPC codes, a predetermined number of LDPC information bits are required, determined by the code rate and code length. Therefore, when the number of bits encoded by BCH is less than the number of LDPC information bits, zero-paffers 213 and 314 can fill in zero bits for the LDPC encoding to generate the predetermined number of LDPC information bits formed by the BCH-encoded bits and zero bits, and output the generated bits to LDPC encoders 214 and 315 respectively. When the number of bits encoded by BCH is equal to the number of LDPC information bits, zero bits do not need to be filled.

[0376] Here, the zero bits filled by zero filler 213 and zero filler 314 are filled for LDPC encoding, so the zero bits filled by the reduction operation are not sent to receiver 200.

[0377] For example, when the number of LDPC information bits in a 16K LDPC code is K ldpc In order to form K ldpc Each LDPC information bit is filled with zero bits.

[0378] Specifically, when the number of bits encoded by BCH is N outer At that time, the number of LDPC information bits in a 16K LDPC code is K. ldpc And N outer <K ldpc Zero-filler 213 and zero-filler 314 can fill K ldpc -N outer zero bits and N outer The remaining bits, encoded by BCH, are used as the LDPC information bits to generate the K... ldpc LDPC information bits are formed from N bits. However, when N outer =K ldpc When zero bits are filled, they are not filled.

[0379] For this purpose, zero-filler 213 and zero-filler 314 can divide LDPC information bits into multiple bit groups.

[0380] For example, zero-filler 213 and zero-filler 314 can be based on equation 17 or equation 18 below to fill K. ldpc LDPC information bits Divide into N info_group (=K ldpc / 360) bit groups. That is, zero-filler 213 and zero-filler 314 can divide LDPC information bits into multiple bit groups, such that each bit group contains 360 bits.

[0381]

[0382] Z j ={i k |360×j≤k<360×(j+1)}, where 0≤j<N info_group ...(18)

[0383] In equations 17 and 18 above, Z j This represents the j-th bit group.

[0384] Parameter N for zero-padding for L1-basic signaling and L1-detail signaling outer K ldpc and N info_group They can be defined as shown in Table 7 below. In this case, the parameters for zero-filler 213 and zero-filler 314 can be determined according to the corresponding mode, as shown in Table 7 below.

[0385] [Table 7]

[0386]

[0387] Additionally, for 0≤j<N info_group ,like Figure 22 Each bit group Z shown j It can be formed by 360 bits.

[0388] Specifically, Figure 22 This illustrates the data format after L1-basic signaling and L1-detail signaling are encoded by LDPC, respectively. Figure 22 In, increase to K ldpc The LDPC FEC of LDPC information bits represents the LDPC parity bits generated by LDPC encoding.

[0389] Reference Figure 22 K ldpc The LDPC information bits are divided into N info_group Each bit group can consist of 360 bits.

[0390] When the number N bits of L1-basic signaling and L1-detail signaling are BCH encoded outer (=K sig +Mouter (less than K) ldpc (that is, N) outer (=K sig +M outer ) < K ldpc When ), for LDPC encoding, K ldpc Each LDPC information bit can be used by N outer The BCH-encoded bits and K ldpc -N outer The zero-filled bits are used to fill the gaps. In this case, the zero-filled bits are not sent to receiver 200.

[0391] The reduction process performed by zero-filler 213 and zero-filler 314 will be described in more detail below.

[0392] Zero-padding units 213 and 314 can calculate the number of zero bits to be padded. That is, in order to fill the number of bits required for LDPC encoding, zero-padding units 213 and 314 can calculate the number of zero bits to be padded.

[0393] Specifically, zero-padding units 213 and 314 can calculate the number of zero bits to be padded by the difference between the number of LDPC information bits and the number of bits encoded by BCH. That is, for a given N... outer Zero-filler 213 and zero-filler 314 can calculate the number of zero bits to be filled as K. ldpc -N outer .

[0394] Additionally, zero-filler 213 and zero-filler 314 can calculate the number of bit groups in which all bits are filled. That is, zero-filler 213 and zero-filler 314 can calculate the number of bit groups in which all bits in the bit groups are filled with zero bits.

[0395] Specifically, zero-filler 213 and zero-filler 314 can calculate the number N of all bit-filled groups based on Equation 19 or Equation 20 below. pad .

[0396]

[0397]

[0398] Next, zero-filler 213 and zero-filler 314 can determine the bit groups in which zero bits are to be filled among multiple bit groups based on the reduction pattern, and can fill all bits in some bit groups and some bits in the remaining bit groups of the determined bit groups with zero bits.

[0399] In this case, the reduction mode of the padded bit group can be defined as shown in Table 8 below. In this case, zero-painter 213 and zero-painter 314 can determine the reduction mode according to the corresponding mode as shown in Table 8 below.

[0400] [Table 8]

[0401]

[0402] Here, π s (j) is the index of the j-th filled bit group. That is, π s (j) represents the reduction pattern order of the j-th bit group. Additionally, N info_group It is the number of bit groups that make up the LDPC information bits.

[0403] Specifically, zero-filler 213 and zero-filler 314 can be based on the reduction mode to... A bit group is defined, wherein all bits within the bit group are filled with zero bits, and zero-filler 213 and zero-filler 314 can fill all bits of the bit group with zero bits. That is, zero-filler 213 and zero-filler 314 can fill the π-th bit group with zero bits based on a reduction pattern. s (0) bit group, π-th bit group s (1) Bit group, ..., πth bit s (N pad -1) All bits in the bit group.

[0404] Thus, when N pad When N is not 0, zero-filler 213 and zero-filler 314 can determine N based on Table 8 above. pad A list of bit groups (i.e., And fill all bits in the defined bit group with zero bits.

[0405] However, when N pad When the value is 0, the aforementioned process can be omitted.

[0406] Meanwhile, since the number of all padded zero bits is K ldpc -N outer And fill into N pad The number of zero bits in each bit group is 360 × N pad Therefore, zero-filler 213 and zero-filler 314 can additionally fill zero bits into K. ldpc -N outer -360×N pad One LDPC information bit.

[0407] In this case, zero-filler 213 and zero-filler 314 can determine the bit group to which zero bits are additionally filled based on the reduction mode, and can additionally fill zero bits from the head of the determined bit group.

[0408] Specifically, zero-filler 213 and zero-filler 314 can be based on the reduction mode to... The bit group that is identified as having zero bits additionally padded, and the zero bits are additionally padded to the position located at... K of the head ldpc -N outer -360×N pad K bits. Therefore, K ldpc -N outer -360×N pad The zero bits can be obtained from the πth bit. s (N pad The first bit of the bit group is filled in.

[0409] As a result, targeting Zero bits can be additionally padded to the bits located at... K of the head ldpc -N bch -360×N pad 1 bit.

[0410] Meanwhile, the aforementioned example describes K ldpc -N outer -360×N pad zero bits from The first bit is padded, this is just an example. Therefore, the zero bit is... The position of the filler can be changed. For example, K ldpc -N outer -360×N pad One zero bit can be filled into The middle or last part can also be filled into Any location.

[0411] Next, zero-filler 213 and zero-filler 314 can map the BCH-encoded bits to positions where zero bits are not filled to construct LDPC information bits.

[0412] Therefore, N outer The bits encoded by BCH are sequentially mapped to K. ldpc LDPC information bits The positions of the bits where zero bits are not filled, therefore, K ldpc Each LDPC information bit can be generated by N outer The BCH-encoded bits and K ldpc -Nouter It is formed by one information bit.

[0413] The padded zero bits are not sent to receiver 200. Thus, the process of padded zero bits or padded zero bits and then not sending the padded zero bits to receiver 200 can be called reduction.

[0414] LDPC encoder 214 and LDPC encoder 315 perform LDPC encoding on L1-basic signaling and L1-detail signaling, respectively.

[0415] Specifically, LDPC encoder 214 and LDPC encoder 315 can perform LDPC encoding on the LDPC information bits output from zero filler 213 and zero filler 314 to generate LDPC parity bits, and send the LDPC codeword including the LDPC information bits and LDPC parity bits to parity permuter 215 and parity permuter 316 respectively.

[0416] In other words, K output from zero-filler 213 ldpc Each bit can include K sig L1-basic signaling bits, M outer (=N outer -K sig ) BCH parity bits, and K ldpc -N outer K filled zero bits, where K sig L1-basic signaling bits, M outer (=N outer -K sig ) BCH parity bits, and K ldpc -N outer The filled zero bits can form K for the LDPC encoder 214. ldpc LDPC information bits .

[0417] Additionally, K output from zero-filler 314 ldpc Each bit can include K sig L1-detail signaling bits, M outer (=N outer -K sig ) BCH parity bits, and (K ldpc -N outer ) padding zero bits, where K sig L1-detail signaling bits, M outer (=N outer -K sig ) BCH parity bits, and (K ldpc -N outer) padding zero bits can form K for the LDPC encoder 315 ldpc LDPC information bits .

[0418] In this case, LDPC encoder 214 and LDPC encoder 315 can systematically control K. ldpc Each LDPC information bit is LDPC encoded to produce a result consisting of N bits. inner LDPC codeword formed by bits .

[0419] In L1-basic mode and L1-details modes 1 and 2, LDPC encoder 214 and LDPC encoder 315 can encode L1-basic signaling and L1-details signaling at a code rate of 3 / 15 to produce 16200 LDPC codeword bits. In this case, LDPC encoder 214 and LDPC encoder 315 can perform LDPC encoding based on Table 1 above.

[0420] Additionally, in L1-detail modes 3, 4, 5, 6, and 7, the LDPC encoder 315 can encode L1-detail signaling at a code rate of 6 / 15 to produce 16,200 LDPC codeword bits. In this case, the LDPC encoder 315 can perform LDPC encoding based on Table 3 above.

[0421] The code rates and code lengths for L1-basic signaling and L1-detail signaling are shown in Table 4 above, and the number of LDPC information bits is shown in Table 7 above.

[0422] Parity permuter 215 and parity permuter 316 perform parity permutation. That is, parity permuter 215 and parity permuter 316 can perform permutation only on the LDPC parity bit among the LDPC information bits and the LDPC parity bits.

[0423] Specifically, parity permuters 215 and 316 perform parity permutation on the LDPC codewords output from LDPC encoders 214 and 315, respectively, and output the parity-permutated LDPC codewords to repeaters 216 and 317. Parity permuter 316 can output the parity-permutated LDPC codewords to an additional parity generator 319. In this case, the additional parity generator 319 can use the parity-permutated LDPC codewords output from parity permuter 316 to generate additional parity bits.

[0424] For this purpose, parity permuter 215 and parity permuter 316 may include a parity interleaver (not shown) and a group interleaver (not shown).

[0425] First, the parity interleaver can interleave only the LDPC parity bits among the LDPC information bits and LDPC parity bits that constitute the LDPC codeword. However, the parity interleaver can only perform parity interleaving in L1-detail modes 3, 4, 5, 6, and 7. That is, since L1-basic mode and L1-detail modes 1 and 2 include parity interleaving as part of the LDPC encoding process, the parity interleaver may not perform parity interleaving in L1-basic mode and L1-detail modes 1 and 2.

[0426] In parity interleaving mode, the parity interleaver can interleave LDPC parity bits based on the following equation 21.

[0427] u i =c i Where, 0≤i <K ldpc (Information bits were not interleaved)

[0428] Where, 0≤s<360, 0≤t<27....(21)

[0429] Specifically, based on Equation 21 above, the parity check interleaver processes the LDPC codewords. Parity interleaving is performed, and the output of the parity interleaver can be determined by... To express.

[0430] Meanwhile, since L1-basic mode and L1-detail modes 1 and 2 do not use a parity interleaver, the output of the parity interleaver... It can be represented as Equation 22 below.

[0431] u i =c i Where, 0≤i <N inner ....(twenty two)

[0432] The group interleaver can perform group interleaving on the output of the parity interleaver.

[0433] Here, as mentioned above, the output of the parity interleaver can be an LDPC codeword that has been parity interleaved by the parity interleaver or an LDPC codeword that has not been parity interleaved by the parity interleaver.

[0434] Therefore, when parity interleaving is performed, the group interleaver can perform group interleaving on LDPC codewords that have undergone parity interleaving, and when parity interleaving is not performed, the group interleaver can perform group interleaving on LDPC codewords that have not undergone parity interleaving.

[0435] Specifically, a group interleaver can interleave the output of a parity interleaver in units of bit groups.

[0436] For this purpose, a group interleaver can divide the LDPC codeword output from the parity interleaver into multiple bit groups. As a result, the LDPC parity bits output from the parity interleaver can be divided into multiple bit groups.

[0437] Specifically, the group interleaver can take the LDPC-encoded bits output from the parity interleaver based on the following equation 23. Divide into N group (=N inner (360) bits.

[0438] X j ={u k |360×j≤k<360×(j+1),0≤k<N inner}, where 0 ≤ i < N group ...(twenty three)

[0439] In equation 23 above, X j This represents the j-th bit group.

[0440] Figure 23 An example is shown of dividing the LDPC codeword output from the parity interleaver into multiple bit groups.

[0441] Reference Figure 23 LDPC codewords are divided into N group (=N inner (360) bit groups, each bit group X j It consists of 360 bits, where 0 ≤ j < N group .

[0442] As a result, by K ldpc The LDPC information bits formed by these bits can be divided into K bits. ldpc / 360 bit groups, consisting of N inner -K ldpc The LDPC parity check bits formed by N bits can be divided into N bits. inner -K ldpc / 360 bit groups.

[0443] In addition, the group interleaver performs group interleaving on the LDPC codewords output from the parity interleaver.

[0444] In this case, the group interleaver does not perform interleaving on the LDPC information bits, and can perform interleaving only on the LDPC parity bits to change the order of the multiple bit groups that make up the LDPC parity bits.

[0445] As a result, the LDPC information bits within LDPC bits may not be interleaved by the group interleaver, but the LDPC parity bits within LDPC bits may be interleaved by the group interleaver. In this case, the LDPC parity bits can be interleaved in groups.

[0446] Specifically, the group interleaver can perform group interleaving on the LDPC codewords output from the parity interleaver based on the following Equation 24.

[0447] Y j =X j 0≤j<K ldpc / 360

[0448] Y j =X πp(j) K ldpc / 360≤j<N group ....(twenty four)

[0449] Here, X j Y represents the j-th bit group (i.e., the j-th bit group that is not interleaved) among the multiple bit groups that constitute the LDPC codeword. j This represents the j-th bit group that has undergone group interleaving. Additionally, π... p (j) indicates the permutation order of the group interleaving.

[0450] The permutation order can be defined based on Tables 9 and 10 below. Here, Table 9 shows the grouped interleaving patterns for the parity check portion under L1-basic mode and L1-details modes 1 and 2, and Table 10 shows the grouped interleaving patterns for the parity check portion under L1-details modes 3, 4, 5, 6 and 7.

[0451] In this case, the group interleaving device can determine the group interleaving mode according to the corresponding modes shown in Tables 9 and 10 below.

[0452] [Table 9]

[0453]

[0454] [Table 10]

[0455]

[0456] The operation of the group interleaver will be described below, with an example of the group interleaving mode in L1-detail mode 2.

[0457] In L1-detail mode 2, the LDPC encoder 315 performs LDPC encoding on 3240 LDPC information bits at a code rate of 3 / 15 to produce 12960 LDPC parity bits. In this case, the LDPC codeword can be formed from 16200 bits.

[0458] Each bit group consists of 360 bits, resulting in an LDPC codeword consisting of 16,200 bits that is divided into 45 bit groups.

[0459] Here, since the number of LDPC information bits is 3240 and the number of LDPC parity bits is 12960, the 0th to 8th bit groups correspond to the LDPC information bits, and the 9th to 44th bit groups correspond to the LDPC parity bits.

[0460] In this case, based on Equation 24 and Table 9 above, the group interleaver does not perform interleaving on the bit groups that constitute the LDPC information bits (i.e., bit groups 0 to 8), but it can interleave the bit groups that constitute the LPDC parity bits (i.e., bit groups 9 to 44) in group units to change the order of bit groups 9 to 44.

[0461] Specifically, under L1-detail mode 2 in Table 9 above, equation 28 above can be expressed as Y0=X0,Y1=X1,...,Y7=X7,Y8=X8,Y9=X πp(9) =X9,Y 10 =X πp(10) =X 31 ,Y 11 =X πp(11) =X 23 ,...,Y 42 =X πp(42) =X 28 ,Y 43 =X πp(43) =X 39 ,Y 44 =X πp(44) =X 42 That's how it's represented.

[0462] Therefore, the group interleaver does not change the order of the 0th to 8th bit groups, which include the LDPC information bits, but it can change the order of the 9th to 44th bit groups, which include the LDPC parity bits.

[0463] Specifically, the group interleaver can change the order of bit groups from the 9th bit group to the 44th bit group, so that the 9th bit group is at the 9th position, the 31st bit group is at the 10th position, the 23rd bit group is at the 11th position, ..., the 28th bit group is at the 42nd position, the 39th bit group is at the 43rd position, and the 42nd bit group is at the 44th position.

[0464] As described below, since pruners 217 and 318 perform pruning starting from the last parity bit, the parity bit groups can be arranged in reverse order of the pruning mode through parity permutation. That is, the first bit group to be pruned is located in the last bit group.

[0465] The foregoing example describes only the parity bits being interleaved; this is merely an example. That is, parity permuters 215 and 316 can also interleave LDPC information bits. In this case, parity permuters 215 and 316 can interleave the LDPC information bits with the identifier and output LDPC information bits in the same order as before interleaving, ensuring that the order of the LDPC information bits is not changed.

[0466] Repeaters 216 and 317 can repeat at least some bits of the LDPC codeword after the parity permutation at positions following the LDPC information bits, and output the repeated LDPC codeword (i.e., the LDPC codeword bits including the repeated bits) to truncates 217 and 318. Repeater 317 can also output the repeated LDPC codeword to an additional parity generator 319. In this case, the additional parity generator 319 can use the repeated LDPC codeword to generate additional parity bits.

[0467] Specifically, repeaters 216 and 317 can repeat a predetermined number of LDPC parity bits after the LDPC information bits. That is, repeaters 216 and 317 can add a predetermined number of repeated LDPC parity bits after the LDPC information bits. Therefore, within the LDPC codeword, the repeated LDPC parity bits are located between the LDPC information bits and the LDPC parity bits.

[0468] Therefore, since a predetermined number of bits in the LDPC codeword can be repeated after repetition and additionally sent to the receiver 200, the aforementioned operation can be referred to as repetition.

[0469] The term "addition" refers to setting a repeating bit between the LDPC information bit and the LDPC parity bit, so that the bit is repeated.

[0470] Repetition can be performed only on L1-basic mode 1 and L1-detail mode 1, and may not be performed on other modes. In this case, repeaters 216 and 317 do not perform repetition, and can output the LDPC codeword with parity permutation to truncates 217 and 318.

[0471] The methods for performing repetition will be described in more detail below.

[0472] Repeaters 216 and 317 can calculate the number N of additional bits sent for each LDPC codeword based on Equation 25 below. repeat .

[0473]

[0474] In Equation 25 above, C has a fixed value, and D can be an even number. Referring to Equation 25 above, it can be understood that the number of bits to be repeated can be determined by multiplying C by a given N. outer And add D to calculate.

[0475] The parameters C and D for repetition can be selected based on Table 11 below. That is, repeaters 216 and 317 can determine C and D based on the corresponding modes, as shown in Table 11 below.

[0476] [Table 11]

[0477]

[0478] Additionally, repeaters 216 and 317 can enable N repeat The LDPC parity bit is repeated.

[0479] Specifically, when N repeat ≤N ldpc_parity At times, such as Figure 24 As shown, repeaters 216 and 317 can extract the first N bits of the LDPC parity bits after parity permutation. repeat The Nth bit is added to the LDPC information bit. That is, repeaters 216 and 317 can add the first LDPC parity bit (after parity permutation) after the LDPC information bit as the Nth bit. repeat One LDPC parity bit.

[0480] When N repeat >N ldpc_parity At times, such as Figure 25 As shown, repeaters 216 and 317 can replace N with parity-checked N. ldpc_parityAdd N LDPC parity bits to the LDPC information bits, and add N repeat -N ldpc_parity A number of LDPC parity bits, after parity permutation, are additionally added to the N bits that were initially added. ldpc_parity LDPC parity bits. That is, repeaters 216 and 317 can add all the parity-permuted LDPC parity bits after the LDPC information bits, and pass the first LDPC parity bit among the parity-permuted LDPC parity bits to the Nth bit. repeat -N ldpc_parity An additional LDPC parity bit is added after the LDPC parity bit that was added first.

[0481] Therefore, under L1-basic mode 1 and L1-detail mode 1, the additional N repeat Each bit can be selected and sent within an LDPC codeword.

[0482] Truncation units 217 and 318 can truncate some LDPC parity bits from the LDPC codewords output from repeaters 216 and 317, and output the truncated LDPC codeword (that is, the remaining LDPC codeword bits excluding the truncated bits, also referred to as the truncated LDPC codeword) to zero removers 218 and 321. Additionally, truncation unit 318 can provide information related to the truncated LDPC parity bits (e.g., the number and position of the truncated bits) to the additional parity generator 319. In this case, the additional parity generator 319 can generate additional parity bits based on this information.

[0483] As a result, some LDPC parity bits can be truncated after parity permutation.

[0484] In this case, the truncated LDPC parity bit is not transmitted in the frame in which the L1 signaling bit is transmitted. Specifically, the truncated LDPC parity bit is not transmitted in the current frame in which the L1 signaling bit is transmitted. In some cases, the truncated LDPC parity bit may be transmitted in a frame preceding the current frame, which will be described with reference to the additional parity bit generator 319.

[0485] For this purpose, pruners 217 and 318 can determine the number of LDPC parity bits to be pruned for each LDPC codeword and the size of a coding block.

[0486] Specifically, truncation 217 and truncation 318 can calculate the temporary number N of the LDPC parity bits to be truncated based on the following equation 26. punc_temp In other words, for a given N outer The truncation operators 217 and 318 can calculate the temporary number N of the LDPC parity bits to be truncated based on the following equation 26. punc_temp .

[0487]

[0488] Referring to Equation 26 above, the temporary size of the bits to be truncated can be obtained by adding a constant integer B to the length to be reduced (i.e., K). ldpc -N outer The result of multiplying the number of bits to be truncated by a preset constant A value is used to calculate the integer. In this exemplary embodiment, it is obvious that the constant A value is set as the ratio of the number of bits to be truncated to the number of bits to be reduced, and can be set in various ways as needed by the system.

[0489] Here, the B value represents the length of the bits that will be truncated even when the reduction length is 0, and therefore, the B value represents the minimum length that the truncated bits can have. Additionally, the A and B values ​​are used to adjust the actual transmission rate. That is, to prepare for cases where the length of the information bits (i.e., the length of the L1 signaling) is short or the length of the L1 signaling is long, the A and B values ​​are used to adjust the actual transmission rate that will be reduced.

[0490] The above K ldpc A and B are listed in Table 12 below, which shows the parameters used for truncation. Therefore, truncation 217 and truncation 318 can determine the parameters used for truncation according to the corresponding modes, as shown in Table 12 below.

[0491] [Table 12]

[0492]

[0493] Deleters 217 and 318 can calculate the temporary size N of a coded block as shown in Equation 27 below. FEC_temp Here, the number N of LDPC parity bits for the corresponding pattern is used. ldpc_parity As shown in Table 12 above.

[0494] N FEC_temp =N outer +N ldpc_parity -N punc_temp ...(27)

[0495] Additionally, truncation 217 and truncation 318 can calculate the size N of a coded block as shown in Equation 28 below. FEC .

[0496]

[0497] In equation 28 above, η MOD This is the modulation order. For example, when L1-basic signaling and L1-detail signaling are modulated via QPSK, 16-QAM, 64-QAM, or 256-QAM according to the corresponding modes, as shown in Table 12 above, η MOD It can be 2, 4, 6, or 8. According to equation 28 above, N... FEC It can be an integer multiple of the modulation order.

[0498] Additionally, truncation 217 and truncation 318 can calculate the number N of LDPC parity bits to be truncated based on the following equation 29. punc .

[0499] N punc =N punc_temp -(N FEC -N FEC_temp ...(29)

[0500] Here, N punc It is either 0 or a positive integer. Additionally, N... FEC By passing through K sig N is obtained by performing BCH encoding and LDPC encoding on each information bit. outer +N ldpc_parity Subtract the N bits to be deleted punc The number of bits in an information block obtained from N bits. That is, N FEC It is the number of bits actually transmitted, excluding repeating bits, and can be referred to as the number of bits in the LDPC codeword after reduction and pruning.

[0501] Referring to the aforementioned processing, truncation units 217 and 318 can multiply A by the number of zero bits to be padded (i.e., reduce the length) and add B to the result to calculate the temporary number N of LDPC parity bits to be truncated. punc_temp .

[0502] Additionally, cutouts 217 and 318 are based on N. punc_temp To calculate the temporary number N of LDPC codeword bits after truncation and reduction. FEC_temp .

[0503] Specifically, LDPC information bits are LDPC encoded, and LDPC parity bits generated through LDPC encoding are added to the LDPC information bits to form LDPC codewords. Here, LDPC information bits include BCH-encoded bits of L1-basic signaling and L1-detail signaling, and in some cases, may also include padding zero bits.

[0504] In this case, since the padding zero bits are LDPC encoded and then not sent to receiver 200, the reduced LDPC codeword (i.e., the LDPC codeword excluding the padding zero bits) can be formed from the BCH-encoded bits and the LDPC parity bits.

[0505] Therefore, truncators 217 and 318 calculate N by subtracting the temporary number of LDPC parity bits to be truncated from the sum of the number of bits encoded by BCH and the number of LDPC parity bits. FEC_temp .

[0506] The truncated and reduced LDPC codewords (i.e., the LDPC codeword bits other than the truncated and reduced bits) are mapped to constellation symbols according to the corresponding mode through various modulation schemes (such as QPSK, 16-QAM, 64-QAM or 256-QAM), and the constellation symbols can be sent to the receiver 200 through frames.

[0507] Therefore, truncation 217 and truncation 318 are based on N FEC_temp Determine the number N bits of the LDPC codeword after truncation and reduction. FEC , where N FEC It is an integer multiple of the modulation order, and truncation units 217 and 318 determine the number of bits N to be truncated based on the reduced LDPC codeword bits. punc To obtain N FEC .

[0508] When zero bits are not padded, LDPC codewords can be formed from BCH-encoded bits and LDPC parity bits, and reduction can be omitted.

[0509] Furthermore, in L1-basic mode 1 and L1-detail mode 1, the process is repeated, and therefore, the number of LDPC codewords after reduction and pruning is equal to N. FEC +N repeat .

[0510] Cutters 217 and 318 can cut off up to a calculated number of LDPC parity bits.

[0511] In this case, pruners 217 and 318 can prune the last N in all LDPC codewords. punc Each bit is truncated. That is, truncators 217 and 318 can truncate N bits starting from the last LDPC parity bit. punc 1 bit.

[0512] Specifically, when repetition is not performed, the LDPC codeword after parity permutation only includes the LDPC parity bits generated by LDPC encoding.

[0513] In this case, truncation 217 and truncation 318 can truncate the last N of all LDPC codewords that have undergone parity-check permutation. punc Each bit is truncated. Therefore, N bits are truncated starting from the last LDPC parity bit in the LDPC parity bits generated by LDPC encoding. punc One bit can be truncated.

[0514] When repetition is performed, the LDPC codeword after parity permutation and repetition includes the repeated LDPC codeword bits and the LDPC parity bits generated by LDPC encoding.

[0515] In this case, such as Figure 26 and Figure 27 As shown, truncation 217 and truncation 318 can respectively truncate the last N bits of all LDPC codewords that have undergone parity-check permutation and repetition. punc Each bit is truncated.

[0516] Specifically, the repeated LDPC parity bits are located between the LDPC information bits and the LDPC parity bits generated by LDPC encoding, and therefore truncation units 217 and 318 can respectively truncate N bits starting from the last LDPC parity bit in the LDPC parity bits generated by LDPC encoding. punc Each bit is truncated.

[0517] Thus, truncation 217 and truncation 318 can respectively truncate N bits starting from the last LDPC parity bit. punc Each bit is truncated.

[0518] N punc It is 0 or a positive integer, and repetition can only be applied to L1-basic mode 1 and L1-detail mode 1.

[0519] The example described above, where repetition is performed followed by pruning, is merely an example. In some cases, repetition may be performed after pruning.

[0520] The additional parity generator 319 can select bits from the LDPC parity bits to generate additional parity (AP) bits.

[0521] In this case, the additional parity bits can be selected from the LDPC parity bits generated based on the L1-detail signaling sent in the current frame, and sent to the receiver 200 through the frame preceding the current frame (i.e., the previous frame).

[0522] Specifically, L1-details signaling is LDPC encoded, and the LDPC parity bits generated by LDPC encoding are added to the L1-details signaling to form LDPC codewords.

[0523] Additionally, truncation and reduction can be performed on the LDPC codewords, and the truncated and reduced LDPC codewords can be mapped to frames to be sent to receiver 200. Here, when repetition is performed according to the corresponding mode, the truncated and reduced LDPC codewords may include repeated LDPC parity bits.

[0524] In this configuration, the L1-detail signaling corresponding to each frame can be sent to the receiver 200 along with the LDPC parity bits for each frame. For example, the truncated and reduced LDPC codewords including the L1-detail signaling corresponding to the (i-1)th frame can be mapped to the (i-1)th frame for transmission to the receiver 200, and the truncated and reduced LDPC codewords including the L1-detail signaling corresponding to the i-th frame can be mapped to the i-th frame for transmission to the receiver 200.

[0525] Additional parity generator 319 can select at least some of the LDPC parity bits generated based on the L1-detail signaling transmitted in the i-th frame to generate additional parity bits.

[0526] Specifically, some LDPC parity bits generated by performing LDPC encoding on the L1-detail signaling can be truncated and not sent to the receiver 200. In this case, the additional parity generator 319 can select at least some of the truncated LDPC parity bits generated by performing LDPC encoding on the L1-detail signaling sent in the i-th frame to generate additional parity bits.

[0527] Additionally, the additional parity generator 319 may select at least some of the LDPC parity bits sent to the receiver 200 via the i-th frame to generate additional parity bits.

[0528] Specifically, the LDPC parity bits included in the truncated and reduced LDPC codeword mapped to the i-th frame can be composed of only LDPC parity bits generated by LDPC encoding, or composed of LDPC parity bits generated by LDPC encoding and repeated LDPC parity bits, depending on the corresponding mode.

[0529] In this case, the additional parity generator 319 may select at least some of the LDPC parity bits included in the truncated and reduced LDPC codeword to be mapped to the i-th frame to generate additional parity bits.

[0530] Additional parity bits can be sent to receiver 200 via frames preceding the i-th frame (i.e., the (i-1)-th frame).

[0531] In other words, the transmitter 100 can transmit not only the truncated and reduced LDPC codeword, which includes the L1-detail signaling corresponding to the (i-1)th frame, to the receiver 200, but also the additional parity bits generated based on the L1-detail signaling transmitted in the i-th frame.

[0532] In this case, the frame to which the additional parity bits are sent can be the earliest frame in time among the frames preceding the current frame.

[0533] For example, the additional parity bits have the same bootstrap major / minor version as the current frame in frames preceding the current frame, and can be sent in the earliest time frame.

[0534] In some cases, the additional parity generator 319 may not generate additional parity bits.

[0535] In this case, the transmitter 100 can use the L1-basic signaling transmitted through the current frame to send information to the receiver 200 regarding whether additional parity bits for the L1-detail signaling for the next frame were transmitted through the current frame.

[0536] For example, the use of additional parity bits for L1-detail signaling of the next frame with the same bootstrap major / minor version as the current frame can be indicated by the L1B_L1_Detail_additional_parity_mode field in the L1-basic parameters of the current frame. Specifically, when L1B_L1_Detail_additional_parity_mode in the L1-basic parameters of the current frame is set to "00", additional parity bits for L1-detail signaling of the next frame are not sent in the current frame.

[0537] Therefore, in order to further improve the robustness of L1-detail signaling, additional parity bits can be sent in the frame that sent the L1-detail signaling of the current frame before the current frame.

[0538] Figure 28 This illustrates an example where additional parity bits for L1-detail signaling for frame i are sent in the preamble of frame (i-1).

[0539] Figure 28 The L1-detail signaling transmitted via the i-th frame is divided into M blocks by segmentation, and each block in the segmented block is FEC encoded.

[0540] Therefore, M LDPC codewords (i.e., LDPC codewords including LDPC information bits L1-D(i)_1 and their parity bits for L1-D(i)_1, ..., LDPC codewords including LDPC information bits L1-D(i)_M and their parity bits for L1-D(i)_M) are mapped to the i-th frame to be sent to receiver 200.

[0541] In this case, the additional parity bits generated based on the L1-detail signaling sent in the i-th frame can be sent to the receiver 200 through the (i-1)-th frame.

[0542] Specifically, the additional parity bits (i.e., the AP for L1-D(i)_1, ..., the AP for L1-D(i)_M generated based on the L1-detail signaling transmitted in the i-th frame) can be mapped to the preamble of the (i-1)-th frame to be transmitted to the receiver 200. As a result of using the additional parity bits, diversity gain for L1 signaling can be obtained.

[0543] The method for generating additional parity bits will be described in detail below.

[0544] The additional parity bit generator 319 calculates the temporary number N of additional parity bits based on the following equation 30. AP_temp .

[0545]

[0546] In equation 30 above,

[0547] Additionally, K represents the ratio of the additional parity bits to half the total number of bits in the transmitted encoded L1-details signaling block (i.e., the bits that constitute the L1-details signaling block after duplication, pruning, and removal of zero bits (i.e., reduction)).

[0548] In this case, K corresponds to the L1B_L1_Detail_additional_parity_mode field of L1-basic signaling. Here, the value of L1B_L1_Detail_additional_parity_mode associated with the L1-detail signaling of the i-th frame (i.e., frame (#i)) can be sent in the (i-1)-th frame (i.e., frame (#i-1)).

[0549] As mentioned above, when the L1 detail mode is 2, 3, 4, 5, 6, and 7, since the repetition is not executed, N in the above equation 30 is... repeat It is 0.

[0550] In addition, the additional parity generator 319 calculates the number N of additional parity bits based on the following equation 31. AP Therefore, the number of additional parity bits N AP It can be an integer multiple of the modulation order.

[0551]

[0552] here, It is the largest integer not greater than x. Here, η MOD It is the modulation order. For example, when L1-detail signaling is modulated by QPSK, 16-QAM, 64-QAM, or 256-QAM according to the corresponding mode, η MOD It can be 2, 4, 6 or 8.

[0553] Thus, the number of additional parity bits can be determined based on the total number of bits transmitted in the current frame.

[0554] Next, the additional parity generator 319 can select up to a calculated number of bits in the LDPC parity bits to generate additional parity bits.

[0555] Specifically, when the number of truncated LDPC parity bits is equal to or greater than the number of additional parity bits, the additional parity generator 319 can select up to a calculated number of bits from the first LDPC parity bit among the truncated LDPC parity bits to generate additional parity bits.

[0556] When the number of truncated LDPC parity bits is less than the number of additional parity bits, the additional parity generator 319 may first select all the truncated LDPC parity bits, and then additionally select, starting from the first LDPC parity bit included in the LDPC codeword, the same number of bits as obtained by subtracting the number of truncated LDPC parity bits from the calculated number of additional parity bits, to generate additional parity bits.

[0557] Specifically, when repetition is not performed, the LDPC parity bits included in the repeated LDPC codeword are LDPC parity bits generated by LDPC encoding.

[0558] In this case, the additional parity generator 319 may first select all the truncated LDPC parity bits, and starting from the first LDPC parity bit among the LDPC parity bits generated by LDPC encoding, additionally select as many bits as obtained by subtracting the number of truncated LDPC parity bits from the number of calculated additional parity bits to generate additional parity bits.

[0559] Here, the LDPC parity bits generated by LDPC encoding are divided into undisturbed LDPC parity bits and truncated LDPC parity bits. As a result, when bits are selected starting from the first bit among the LDPC parity bits generated by LDPC encoding, they can be selected in the order of undisturbed LDPC parity bits and truncated LDPC parity bits.

[0560] When repetition is performed, the LDPC parity bits included in the repeated LDPC codeword are the repeated LDPC parity bits and the LDPC parity bits generated through LDPC encoding. Here, the repeated LDPC parity bits are located between the LDPC information bits and the LDPC parity bits generated through LDPC encoding.

[0561] In this case, the additional parity generator 319 may first select all the truncated LDPC parity bits, and starting from the first LDPC parity bit among the repeated LDPC parity bits, additionally select as many bits as calculated by subtracting the number of truncated LDPC parity bits from the calculated number of additional parity bits to generate additional parity bits.

[0562] Here, when bits are selected starting from the first bit in the repeated LDPC parity bits, they can be selected in the order of the repeated bits and the LDPC parity bits generated by LDPC encoding. Additionally, within the LDPC parity bits generated by LDPC encoding, bits can be selected in the order of the undisturbed LDPC parity bits and the truncated LDPC parity bits.

[0563] In the following text, reference will be made to Figures 29 to 31 A method for generating additional parity bits according to an exemplary embodiment will be described in more detail.

[0564] Figures 29 to 31 This is a diagram illustrating a method for generating additional parity bits when repeated, according to an exemplary embodiment. In this case, the repeated LDPC codeword... Can Figure 29 The diagram shown is used to represent this.

[0565] First, when N AP ≤N punc At times, such as Figure 30 As shown, the additional parity generator 319 can select N from the first LDPC parity bit among the truncated LDPC parity bits. AP Each bit is used to generate an additional parity bit.

[0566] Therefore, for the additional parity bits, the truncated LDPC parity bits It can be selected. That is, the additional parity generator 319 can select N bits starting from the first bit of the truncated LDPC parity bits. AP Each bit is used to generate an additional parity bit.

[0567] When N AP >N punc At times, such as Figure 31 As shown, the additional parity generator 319 selects all the truncated LDPC parity bits.

[0568] Therefore, for the additional parity bits, all truncated LDPC parity bits It can be selected.

[0569] Additionally, the supplementary parity generator 319 can additionally select the first N LDPC parity bits from the LDPC parity bits, including the repeated LDPC parity bits and the LDPC parity bits generated by LDPC encoding. AP -N punc 1 bit.

[0570] In other words, since the repeated LDPC parity bits and the LDPC parity bits generated by LDPC encoding are arranged sequentially, the additional parity generator 319 can additionally select N bits starting from the first LDPC parity bit among the repeated LDPC parity bits. AP -N punc One parity bit.

[0571] Therefore, for the additional parity bits, LDPC parity bits It can be selected additionally.

[0572] In this case, the additional parity generator 319 can add additionally selected bits to the previously selected bits to generate additional parity bits. That is, as... Figure 31 As shown, the additional parity generator 319 can add additionally selected LDPC parity bits to the truncated LDPC parity bits to generate additional parity bits.

[0573] As a result, regarding the additional parity bits, It can be selected.

[0574] Thus, when the number of truncated bits is equal to or greater than the number of additional parity bits, additional parity bits can be generated by selecting bits from the truncated bits based on the truncating order. On the other hand, in other cases, additional parity bits can be generated by selecting all truncated bits and N... AP -N punc It is generated by parity bits.

[0575] Because N is not executed when repetition is not performed repeat =0, therefore the method used to generate additional parity bits when repetition is not performed is the same as... Figures 29 to 31 N in repeat The case where = 0 is the same.

[0576] Additional parity bits can be bit-interleaved and mapped to a constellation. In this case, the constellation for the additional parity bits can be generated in the same way as the constellation for the L1-detail signaling bits transmitted in the current frame, where the L1-detail signaling bits are repeated, truncated, and zero bits have been removed. Additionally, as... Figure 28 As shown, after being mapped to a constellation, additional parity bits can be added after the L1-detail signaling block in the frame that sent the L1-detail signaling for the current frame before the current frame.

[0577] The additional parity generator 319 can output additional parity bits to the bit demultiplexer 323.

[0578] As described above with reference to Tables 9 and 10, the group interleaving pattern with a defined permutation order can have two modes: mode 1 and mode 2.

[0579] Specifically, since the value of B in Equation 26 above represents the minimum length of the LDPC parity bits to be truncated, a predetermined number of bits can always be truncated based on the value of B, regardless of the length of the input signaling. For example, in L1-detail mode 2, since B = 6036 and the bit group consists of 360 bits, even when the reduction length is 0, at least Each bit group is always truncated.

[0580] In this case, since truncation is performed starting from the last LDPC parity bit, a predetermined number of bit groups starting from the last bit group among the multiple bit groups that constitute the interleaved LDPC parity bits can always be truncated, regardless of length reduction.

[0581] For example, in L1-detail mode 2, the last 16 bits of the 36 bits that make up the interleaved LDPC parity bits can always be truncated.

[0582] As a result, some patterns in the group interleaving modes that restrict the permutation order represent the bit groups that are always truncated. Therefore, the group interleaving modes can be divided into two modes. Specifically, the mode that restricts the remaining bit groups other than the bit groups that are always truncated is called the first mode, and the mode that restricts the bit groups that are always truncated is called the second mode.

[0583] For example, in L1-detail mode 2, since the group interleaving mode is defined as shown in Table 9 above, it means that no group interleaving has been performed and the data is located in the 9th to 28th bit groups after group interleaving (i.e., Y9 = X). πp(9) =X9,Y 10 =X πp(10) =X 31 ,Y 11 =X πp(11) =X 23 ,...,Y 26 =X πp(26) =X 17 ,Y 27 =X πp(27) =X 35 ,Y 28 =X πp(28) =X 21The index pattern of the bit group in ) can be the first pattern, and it indicates that it has not undergone group interleaving and is located in the 29th to 44th bit groups after group interleaving (i.e., Y). 29 =X πp(29) =X 20 ,Y 30 =X πp(30) =X 24 ,Y 31 =X πp(31) =X 44 ,...,Y 42 =X πp(42) =X 28 ,Y 43 =X πp(43) =X 39 ,Y 44 =X πp(44) =X 42 The index mode of the bit group in () can be the second mode.

[0584] As described above, the second mode defines the bit groups that will always be truncated in the current frame regardless of the reduction length, and the first mode defines the bit groups that will be additionally truncated when the reduction length is long, such that the first mode can be used to determine the LDPC parity bits that will be sent in the current frame after truncation.

[0585] Specifically, depending on the number of LDPC parity bits to be truncated, more LDPC parity bits can be additionally truncated in addition to the LDPC parity bits that are always truncated.

[0586] For example, in L1-detail mode 2, when the number of LDPC parity bits to be truncated is 7200, 20 bit groups need to be truncated, and therefore, in addition to the 16 bit groups that will always be truncated, four (4) bit groups need to be additionally truncated.

[0587] In this case, the additional four (4) bit groups that are truncated correspond to the bit groups located at positions 25 to 28 after group interleaving, and since these bit groups can be determined according to the first mode (i.e., belong to the first mode), the first mode can be used to determine the truncated bit groups.

[0588] In other words, when more LDPC parity bits are truncated than the minimum number of LDPC parity bits to be truncated, the groups of bits to be additionally truncated are determined based on which groups of bits follow the groups of bits that will always be truncated. As a result, a first pattern that limits the groups of bits following the groups of bits that will always be truncated, depending on the truncating direction, can be considered as determining the groups of bits to be truncated.

[0589] That is, as in the example above, when the number of LDPC parity bits to be truncated is 7200, in addition to the 16 bit groups that are always truncated, four (4) bit groups (i.e., the bit groups located at positions 28, 27, 26, and 25 after group interleaving is performed) are additionally truncated. Here, the bit groups located at positions 25 to 28 after group interleaving are determined according to the first mode.

[0590] As a result, the first mode can be considered as a method for determining the bit groups to be truncated. Additionally, the remaining LDPC parity bits, excluding the truncated LDPC parity bits, are transmitted through the current frame; therefore, the first mode can be considered as a method for determining the bit groups transmitted in the current frame.

[0591] The second mode can be used solely to determine additional parity bits sent in previous frames.

[0592] Specifically, since the bit groups determined to always be truncated are always truncated and subsequently not transmitted in the current frame, these bit groups only need to be located at the positions where bits are always truncated after group interleaving. Therefore, the exact position of these bit groups within them is irrelevant.

[0593] For example, in L1-detail mode 2, bit groups located at positions 20, 24, 44, ..., 28, 39, and 42 before group interleaving only need to be located in bit groups 29 through 44 after group interleaving. Therefore, the position of these bit groups is not important.

[0594] Thus, the second mode, which specifies the groups of bits that will always be truncated, is only used to identify the groups of bits that will be truncated. Therefore, specifying the order of the groups of bits in the second mode is meaningless during truncation, and thus the second mode, which specifies the groups of bits that will always be truncated, can be considered not to be used for truncating.

[0595] However, in order to determine the additional parity bits, the positions of the bit groups that will always be truncated within these bit groups need to be considered.

[0596] Specifically, since the additional parity bits are generated by selecting up to a predetermined number of bits from the first bit of the truncated LDPC parity bits, bits included in at least some of the bit groups in the truncated bit groups can be selected as at least some of the additional parity bits depending on the number of truncated LDPC parity bits and the number of additional parity bits.

[0597] In other words, when the additional parity bit is selected beyond the bit group defined according to the first mode, the order of the bit groups belonging to the second mode is meaningful in terms of the selection of the additional parity bit, since the additional parity bits are selected sequentially from the beginning of the second mode. As a result, the second mode, which will always be truncated, can be considered as the method for determining the additional parity bit.

[0598] For example, in L1-detail mode 2, the total number of LDPC parity bits is 12960, and the number of bit groups that are always truncated is 16.

[0599] In this case, the second mode can be used to generate additional parity bits based on whether the value obtained by subtracting the number of LDPC parity bits to be truncated from the total number of LDPC parity bits and adding the result to the number of additional parity bits exceeds 7200. Here, 7200 is the number of LDPC parity bits included in the remaining bit groups that constitute the LDPC parity bits, excluding the bit groups that will always be truncated. That is, 7200 = (36-16) × 360.

[0600] Specifically, when the value obtained by subtracting and adding the above is equal to or less than 7200 (i.e., 12960-N), punc +N AP When the parity is ≤7200, the additional parity bits can be generated according to the first mode.

[0601] However, when the value obtained by subtracting and adding the above values ​​exceeds 7200 (i.e., 12960-N), punc +N AP When the value is greater than 7200, the additional parity bits can be generated according to the first mode and the second mode.

[0602] Specifically, when 12960-N punc +N AP When the value is greater than 7200, for the additional parity bits, the bits included in the bit group at position 28 starting from the first LDPC parity bit in the truncated LDPC parity bits can be selected, and the bits included in the bit group at predetermined positions starting from position 29 can be selected.

[0603] Here, the bit group to which the first LDPC parity bit in the truncated LDPC parity bits belongs, and the bit group at the predetermined position (i.e., the bit group to which the finally selected LDPC parity bit belongs when selected sequentially from the first LDPC parity bit in the truncated LDPC parity bits) can be determined based on the number of LDPC parity bits to be truncated and the number of additional parity bits.

[0604] In this case, the bit group at position 28, starting from the first LDPC parity bit in the truncated LDPC parity bits, is determined according to the first mode, and the bit group at predetermined positions starting from position 29 is determined according to the second mode.

[0605] As a result, the additional parity bits are determined according to the first mode and the second mode.

[0606] Thus, the first mode can be used to determine the additional parity bits and the LDPC parity bits to be truncated, but the second mode can be used to determine only the additional parity bits.

[0607] The foregoing example described grouped interleaving modes including a first mode and a second mode, merely for ease of explanation regarding truncation and additional parity. That is, grouped interleaving can be considered as a single mode without being divided into a first mode and a second mode. In this case, grouped interleaving can be viewed as performing both truncation and additional parity using a single mode.

[0608] The values ​​used in the aforementioned examples (such as the number of truncated LDPC parity bits) are merely example values.

[0609] Zero removers 218 and 321 can remove zero bits filled by zero fillers 213 and 314 from the LDPC codewords output from truncates 217 and 318, and output the remaining bits to bit demultiplexers 219 and 322.

[0610] Here, the removal operation is not only about removing the padding zero bits, but can also include the remaining bits in the LDPC codeword besides the padding zero bits.

[0611] Specifically, zero remover 218 and zero remover 321 can remove K filled by zero filler 213 and zero filler 314. ldpc -N outer One zero bit. Therefore, K ldpc -N outer The padding zero bits are removed and therefore may not be sent to receiver 200.

[0612] For example, such as Figure 32 As shown, it is assumed that all bits in the first, fourth, fifth, seventh, and eighth bit groups that constitute the LDPC codeword are filled with zero bits, and some bits in the second bit group are filled with zero bits.

[0613] In this case, zero remover 218 and zero remover 321 can remove zero bits that have been filled into the first bit group, the second bit group, the fourth bit group, the fifth bit group, the seventh bit group, and the eighth bit group.

[0614] Thus, when the zero bit is removed, as Figure 32 As shown, K can be retained sig K information bits (i.e., K) sig One L1-basic signaling bit and K sig 168 L1-detail signaling bits, 168 BCH parity bits (i.e., BCH FEC), and N inner -K ldpc -N punc or N inner -K ldpc -N punc +N repeat The LDPC codeword is formed by parity check bits.

[0615] In other words, when the process is repeated, the length of all LDPC codewords becomes N. FEC +N repeat Here, N FEC =N outer +N ldpc_parity -N punc However, in the mode where the repetition is not executed, the length of all LDPC codewords becomes N. FEC .

[0616] Bit demultiplexers 219 and 322 can interleave the bits output from zero removers 218 and 321, demultiplex the interleaved bits, and then output them to constellation mappers 221 and 324.

[0617] For this purpose, bit demultiplexer 219 and bit demultiplexer 322 may include a block interleaver (not shown) and a demultiplexer (not shown).

[0618] First, the block interleaving scheme executed in the block interleaver is... Figure 33 As shown in the image.

[0619] Specifically, N after the zero bits are removed FEC or N FEC +Nrepeat Bits of length can be written consecutively column-wise into the block interleaver. Here, the number of columns in the block interleaver is equal to the modulation order, and the number of rows is N. FEC / η MOD or (N) FEC +N repeat ) / η MOD .

[0620] Additionally, during the read operation, bits of a constellation symbol can be read sequentially along the row direction to be input into the demultiplexer. This operation can continue up to the last row of the column.

[0621] In other words, N FEC or (N) FEC +N repeat Bits can be written into multiple columns starting from the first row of the first column, and the bits written into the multiple columns are read sequentially from the first row to the last row of the multiple columns. In this case, the bits read in the same row can form a modulation symbol.

[0622] The demultiplexer can demultiplex the bits output from the block interleaver.

[0623] Specifically, before the bits are mapped to the constellation, the demultiplexer can demultiplex each bit group in the block-interleaved bit group (i.e., the bits output when they are read bit by bit within the same line of the block interleaver).

[0624] In this case, there are two mapping rules depending on the modulation order.

[0625] Specifically, when QPSK is used for modulation, since the bits within a constellation symbol have the same reliability, the demultiplexer does not perform demultiplexing operations on the bit groups. Therefore, the bit groups read and output from the block interleaver can be mapped to QPSK symbols without demultiplexing.

[0626] However, when higher-order modulation is used, the demultiplexer can perform demultiplexing on the bit groups read from and output by the block interleaver based on Equation 32 below. That is, the bit groups can be mapped to QAM symbols according to Equation 32 below. ...

[0628] S demux_in(i) ={b i (0), b i (1), b i (2), ..., b i (η MOD -1)},

[0629] S demux_out(i)={C i (0), C i (1), c i (2), ..., c i (η MOD -1)},

[0630] C i (0)=b i (i%η MOD ), C i (1) = b i ((i+1)%η MOD ), ..., C i (η MOD -1)=b i ((i+η MOD -1)%η MOD ) (32)

[0632] In Equation 32 above, % represents the modulo operation, and η MOD It is the modulation order.

[0633] Additionally, i is the bit group index corresponding to the row index of the block interleaver. That is, the bit group S of the output of each QAM symbol mapped into the QAM symbol. demux_out(i) The bit group index i can be used in S demux_in(i) The middle is cyclically shifted.

[0634] Figure 34 An example of bit demultiplexing is shown for a 16-nonuniform constellation (16-NUC) (i.e., NUC 16-QAM). The operation can continue until all bit groups in the block interleaver have been read.

[0635] Bit demultiplexer 323 can perform the same operation on the additional parity bits output from additional parity generator 319 as the operation performed by bit demultiplexer 219 and bit demultiplexer 322, and output the block-interleaved and demultiplexed bits to constellation mapper 325.

[0636] Constellation mappers 221, 324, and 325 can map the bits output from bit demultiplexers 219, 322, and 323 to constellation symbols, respectively.

[0637] In other words, each of constellation mappers 221, 324, and 325 can use constellations to map S according to the corresponding pattern. demux_out(i) Mapped to the information element. Here, S demux_out(i) It can be constructed from a number of bits that are the same as the modulation order.

[0638] Specifically, constellation mappers 221, 324, and 325 can use QPSK, 16-QAM, 64-QAM, 256-QAM, etc., to map the bits output from bit demultiplexers 219, 322, and 323 to constellation symbols according to the corresponding modes.

[0639] In this configuration, constellation mappers 221, 324, and 325 can utilize NUCs. That is, constellation mappers 221, 324, and 325 can use NUC 16-QAM, NUC 64-QAM, or NUC 256-QAM. The modulation schemes applied to L1-basic signaling and L1-detail signaling according to the corresponding modes are shown in Table 4 above.

[0640] Transmitter 100 can map constellation symbols to frames and send the mapped symbols to receiver 200.

[0641] Specifically, transmitter 100 can map each corresponding constellation symbol in the L1-basic signaling and L1-detail signaling output from constellation mapper 221 and constellation mapper 324, and map the constellation symbol corresponding to the additional parity bit output from constellation mapper 325 to the preamble symbol of the frame.

[0642] In this case, the transmitter 100 can map additional parity bits generated based on the L1-detail signaling transmitted in the current frame to the frames preceding the corresponding frame.

[0643] In other words, the transmitter 100 can map LDPC codeword bits including L1-basic signaling corresponding to the (i-1)th frame to the (i-1)th frame, map LDPC codeword bits including L1-detail signaling corresponding to the (i-1)th frame to the (i-1)th frame, and additionally map additional parity bits generated from LDPC parity bits generated based on L1-detail signaling corresponding to the i-th frame to the (i-1)th frame and can send the mapped bits to the receiver 200.

[0644] In addition to L1 signaling, transmitter 100 can also map data to data symbols of frames and send frames including L1 signaling and data to receiver 200.

[0645] In this case, since L1 signaling includes signaling information related to the data, the data-related signaling mapped to each piece of data can be mapped to the preamble of the corresponding frame. For example, transmitter 100 can map L1 signaling, which includes signaling information related to the data mapped to the i-th frame, to the i-th frame.

[0646] As a result, receiver 200 can receive data from the corresponding frame using signaling obtained from the frame for processing.

[0647] Figure 35 and Figure 36 This is a block diagram used to describe the configuration of a receiver according to an exemplary embodiment.

[0648] Specifically, such as Figure 35 As shown, receiver 200 may include constellation demapper 2510, multiplexer 2520, log-likelihood ratio (LLR) inserter 2530, LLR combiner 2540, parity depermutation unit 2550, LDPC decoder 2560, zero remover 2570, BCH decoder 2580, and descrambler 2590 for processing L1-basic signaling.

[0649] In addition, such as Figure 36 As shown, receiver 200 may include constellation demappers 2611 and 2612, multiplexers 2621 and 2622, LLR inserter 2630, LLR combiner 2640, parity de-permuter 2650, LDPC decoder 2660, zero remover 2670, BCH decoder 2680, descrambler 2690, and desegmenter 2695 for processing L1-detail signaling.

[0650] here, Figure 35 and Figure 36 The components shown perform respectively with Figure 19 and Figure 20 The functions of the components shown are merely examples. In some cases, some components may be omitted or changed, and other components may be added.

[0651] Receiver 200 can use the frame preamble to obtain frame synchronization and receive L1-basic signaling from the frame preamble using the information included in the preamble for processing L1-basic signaling.

[0652] Additionally, receiver 200 can use the information included in L1-basic signaling for processing L1-detail signaling to receive L1-detail signaling from the preamble, and use the L1-detail signaling to receive broadcast data required by the user from the data symbols of the frame.

[0653] Therefore, receiver 200 can determine the mode used at transmitter 100 for processing L1-basic signaling and L1-detail signaling, and process the signals received from transmitter 100 according to the determined mode to receive L1-basic signaling and L1-detail signaling. For this purpose, receiver 200 can pre-store information related to the parameters used at transmitter 100 to process the signaling according to the corresponding mode.

[0654] Thus, L1 basic signaling and L1 detailed signaling can be sequentially obtained from the preamble. (In the description...) Figure 35 and Figure 36 For ease of explanation, components that perform the same function will be described together.

[0655] Constellation demappers 2510, 2611, and 2612 demodulate the signals received from transmitter 100.

[0656] Specifically, constellation demappers 2510, 2611, and 2612 are components corresponding to constellation mappers 221, 324, and 325 of transmitter 100, respectively, and can demodulate the signal received from transmitter 100 and generate a value corresponding to the bits sent from receiver 100.

[0657] In other words, as described above, transmitter 100 maps LDPC codewords including L1-basic signaling and LDPC codewords including L1-detail signaling to the preamble of a frame, and sends the mapped LDPC codewords to receiver 200. Additionally, in some cases, transmitter 100 may map additional parity bits to the preamble of a frame and send the mapped bits to receiver 200.

[0658] As a result, constellation demappers 2510 and 2611 can generate values ​​corresponding to LDPC codeword bits including L1-basic signaling and LDPC codeword bits including L1-detail signaling. Additionally, constellation demapper 2612 can generate values ​​corresponding to additional parity bits.

[0659] For this purpose, receiver 200 may pre-store information related to the modulation scheme used by transmitter 100 to modulate L1-basic signaling, L1-detail signaling, and additional parity bits according to a corresponding pattern. Therefore, constellation demappers 2510, 2611, and 2612 can demodulate the signal received from transmitter 100 according to the corresponding pattern to generate values ​​corresponding to LDPC codeword bits and additional parity bits.

[0660] The value corresponding to the bit transmitted from transmitter 100 is a value calculated based on the probability that the received bit is 0 or 1; alternatively, the probability itself can also be used as the value corresponding to each bit. As another example, the value can also be the likelihood ratio (LR) or LLR value.

[0661] Specifically, the LR value can represent the ratio of the probability that the bit transmitted from the transmitter 100 is 0 to the probability that the bit is 1, and the LLR value can represent the value obtained by taking the logarithm of the probability that the bit transmitted from the transmitter 100 is 0 to the probability that the bit is 1.

[0662] The foregoing example uses LR or LLR values, which is merely an example. According to another exemplary embodiment, the received signal itself, in addition to LR or LLR values, may also be used.

[0663] Multiplexers 2520, 2621, and 2622 perform multiplexing on the LLR values ​​output from constellation demapping units 2510, 2611, and 2612.

[0664] Specifically, multiplexers 2520, 2621, and 2622 are components corresponding to bit demultiplexers 219, 322, and 323 of transmitter 100, and can respectively perform operations corresponding to the operations of bit demultiplexers 219, 322, and 323.

[0665] For this purpose, receiver 200 may pre-store information related to the parameters used by transmitter 100 to perform demultiplexing and block interleaving. Therefore, multiplexers 2520, 2621, and 2622 can perform the demultiplexing and block interleaving operations of bit demultiplexers 219, 322, and 323 in reverse order on the LLR values ​​corresponding to the cell words, so as to multiplex the LLR values ​​corresponding to the cell words bit by bit.

[0666] LLR inserter 2530 and LLR inserter 2630 can insert LLR values ​​for truncated bits and reduced bits into the LLR values ​​output from multiplexer 2520 and multiplexer 2621, respectively. In this case, LLR inserter 2530 and LLR inserter 2630 can insert predetermined LLR values ​​between the LLR values ​​output from multiplexer 2520 and multiplexer 2621, or insert them into the beginning or end of the LLR values ​​output from multiplexer 2520 and multiplexer 2621.

[0667] Specifically, LLR inserter 2530 and LLR inserter 2630 are components corresponding to zero remover 218 and 321 and truncation 217 and 318 of transmitter 100, respectively, and can perform operations corresponding to the operations of zero remover 218 and 321 and truncation 217 and 318, respectively.

[0668] First, LLR inserters 2530 and 2630 insert the LLR value corresponding to the zero bit into the position where the zero bit is filled in the LDPC codeword. In this case, the LLR value corresponding to the filled zero bit (i.e., the reduced zero bit) can be ∞ or -∞. However, ∞ or -∞ are theoretical values, but in practice, they can be the maximum or minimum LLR values ​​used in receiver 200.

[0669] For this purpose, receiver 200 may pre-store information related to the parameters and / or modes used by transmitter 100 to fill zero bits according to the corresponding mode. Therefore, LLR inserter 2530 and LLR inserter 2630 may determine the position where zero bits are filled in the LDPC codeword according to the corresponding mode, and insert the LLR value corresponding to the reduced zero bits into the corresponding position.

[0670] Additionally, LLR inserters 2530 and 2630 can insert the LLR value corresponding to the truncated bit into the position of the truncated bit in the LDPC codeword. In this case, the LLR value corresponding to the truncated bit can be 0.

[0671] For this purpose, receiver 200 may pre-store information related to the parameters and / or modes used by transmitter 100 to perform truncation according to the corresponding mode. Therefore, LLR inserter 2530 and LLR inserter 2630 may determine the length of the truncated LDPC parity bit according to the corresponding mode and insert the corresponding LLR value at the position where the LDPC parity bit is truncated.

[0672] When the additional parity bit is selected from the truncated bits, the LLR inserter 2630 can insert the LLR value corresponding to the received additional parity bit (instead of the LLR value "0" for the truncated bit) into the position of the truncated bit.

[0673] LLR combiner 2540 and LLR combiner 2640 combine (i.e., add) the LLR values ​​output from LLR inserters 2530 and 2630 with the LLR values ​​output from multiplexer 2622. However, LLR combiners 2540 and 2640 are used to update the LLR value for a specific bit to a more accurate value. However, the LLR value for a specific bit can also be decoded from the received LLR value without the need for LLR combiners 2540 and 2640; therefore, in some cases, LLR combiners 2540 and 2640 can be omitted.

[0674] Specifically, the LLR combiner 2540 is a component corresponding to the repeater 216 of the transmitter 100, and can perform operations corresponding to the operation of the repeater 216. Alternatively, the LLR combiner 2640 is a component corresponding to the repeater 317 and the additional parity generator 319 of the transmitter 100, and can perform operations corresponding to the operation of the repeater 317 and the additional parity generator 319.

[0675] First, LLR combiners 2540 and 2640 can combine the LLR value corresponding to the repeating bit with other LLR values. Here, the other LLR values ​​can be the bits that form the basis for the repeating bit generated by the transmitter 100, i.e., the LLR value of the LDPC parity bit selected as the repeating object.

[0676] In other words, as described above, the transmitter 100 selects a bit from the LDPC parity bit and repeats the selected bit between the LDPC information bit and the LDPC parity bit generated by encoding, and sends the repeated bit to the receiver 200.

[0677] As a result, the LLR value for LDPC parity bits can be formed by the LLR value for repeating LDPC parity bits and the LLR value for non-repeating LDPC parity bits (i.e., LDPC parity bits generated by LDPC encoding). Therefore, LLR combiner 2540 and LLR combiner 2640 can combine LLR values ​​for the same LDPC parity bits.

[0678] For this purpose, receiver 200 may pre-store information related to the parameters used by transmitter 100 to perform repetition according to the corresponding pattern. As a result, LLR combiner 2540 and LLR combiner 2640 may determine the length of the repeated LDPC parity bits, determine the position of the bits that form the basis of the repetition, and combine the LLR value for the repeated LDPC parity bits with the LLR value for the LDPC parity bits that form the basis of the repetition and are generated by LDPC encoding.

[0679] For example, such as Figure 37 and Figure 38 As shown, LLR combiner 2540 and LLR combiner 2640 can combine the LLR value for repeated LDPC parity bits with the LLR value for LDPC parity bits generated by LDPC encoding as the basis for repetition.

[0680] When the LDPC parity bit is repeated n times, LLR combiner 2540 and LLR combiner 2640 can combine the LLR values ​​for bits in the same position n times or less.

[0681] For example, Figure 37 This illustrates a case where some LDPC parity bits, excluding the truncated bits, are repeated once. In this case, LLR combiners 2540 and 2640 can combine the LLR value for the repeated LDPC parity bit with the LLR value for the LDPC parity bit generated by LDPC encoding, and then output the combined LLR value, or output the LLR value for the received repeated LDPC parity bit or the received LDPC parity bit generated by LDPC encoding, without combining them.

[0682] As another example, Figure 38 The following situation is shown: some LDPC parity bits in the transmitted undisturbed LDPC parity bits are repeated twice, the remaining bits are repeated once, and the truncated LDPC parity bits are repeated once.

[0683] In this case, LLR combiners 2540 and 2640 can process the remaining portion that has been repeated once and the truncated LDPC parity bits in the same way as described above. However, LLR combiners 2540 and 2640 can process the portion that has been repeated twice as described below. In this case, for ease of description, one of the two portions resulting from repeating some LDPC parity bits twice is called the first portion, and the other of the two portions is called the second portion.

[0684] Specifically, LLR combiners 2540 and 2640 can combine the LLR value for each of the first and second parts with the LLR value for the LDPC parity bit. Optionally, LLR combiners 2540 and 2640 can combine the LLR value for the first part with the LLR value for the LDPC parity bit, combine the LLR value for the second part with the LLR value for the LDPC parity bit, or combine the LLR value for the first part with the LLR value for the second part. Optionally, LLR combiners 2540 and 2640 can output the LLR value for the first part, the LLR value for the second part, and the LLR value for the remaining part and the truncated bits, without separate combination.

[0685] Additionally, the LLR combiner 2640 can combine the LLR value corresponding to the additional parity bit with other LLR values. Here, the other LLR values ​​can be LLR values ​​for the LDPC parity bit (i.e., the LDPC parity bit selected for generating the additional parity bit) that serves as the basis for generating the additional parity bit through the transmitter 100.

[0686] In other words, as described above, the transmitter 100 can map additional parity bits for L1-detail signaling transmitted in the current frame to previous frames and send the mapped bits to the receiver 200.

[0687] In this case, the additional parity bits may include truncated LDPC parity bits that were not sent in the current frame, and in some cases, may also include LDPC parity bits that were sent in the current frame.

[0688] As a result, the LLR combiner 2640 can combine the LLR value for the additional parity bit received in the current frame with the LLR value inserted into the position of the truncated LDPC parity bit in the LDPC codeword received in the next frame and the LLR value for the LDPC parity bit received in the next frame.

[0689] For this purpose, receiver 200 may pre-store information related to the parameters and / or modes used by transmitter 100 to generate additional parity bits according to the corresponding mode. As a result, LLR combiner 2640 may determine the length of the additional parity bits, determine the position of the LDPC parity bits that form the basis for generating the additional parity bits, and combine the LLR value for the additional parity bits with the LLR value for the LDPC parity bits that form the basis for generating the additional parity bits.

[0690] Parity de-permutation unit 2550 and parity de-permutation unit 2650 can de-permutate the LLR values ​​output from LLR combiner 2540 and LLR combiner 2640, respectively.

[0691] Specifically, parity de-permutation unit 2550 and parity de-permutation unit 2650 are components corresponding to parity de-permutation unit 215 and parity de-permutation unit 316 of transmitter 100, and can respectively perform operations corresponding to the operations of parity de-permutation unit 215 and parity de-permutation unit 316.

[0692] For this purpose, receiver 200 may pre-store information related to the parameters and / or modes used by transmitter 100 to perform group interleaving and parity interleaving according to the corresponding modes. Therefore, parity de-permutator 2550 and parity de-permutator 2650 may reversely perform the group interleaving and parity interleaving operations of parity de-permutator 215 and parity de-permutator 316 on the LLR values ​​corresponding to the LDPC codeword bits (i.e., perform group de-interleaving and parity de-interleaving operations) to perform parity de-permutation on the LLR values ​​corresponding to the LDPC codeword bits, respectively.

[0693] LDPC decoder 2560 and LDPC decoder 2660 can perform LDPC decoding based on the LLR values ​​output from parity de-permutation unit 2550 and parity de-permutation unit 2650, respectively.

[0694] Specifically, LDPC decoder 2560 and LDPC decoder 2660 are components corresponding to LDPC encoder 214 and LDPC encoder 315 of transmitter 100, and can respectively perform operations corresponding to the operations of LDPC encoder 214 and LDPC encoder 315.

[0695] For this purpose, receiver 200 may pre-store information relating to the parameters used by transmitter 100 to perform LDPC encoding according to the corresponding mode. Therefore, LDPC decoders 2560 and 2660 may perform LDPC decoding based on the LLR values ​​output from parity de-permutation unit 2550 and parity de-permutation unit 2650 according to the corresponding mode.

[0696] For example, LDPC decoder 2560 and LDPC decoder 2660 can perform LDPC decoding based on the sum-product algorithm by iteratively decoding based on the LLR values ​​output from parity de-permutation unit 2550 and parity de-permutation unit 2650, and output the error-corrected bits according to the LDPC decoding.

[0697] Zero remover 2570 and zero remover 2670 can remove zero bits from the bits output from LDPC decoder 2560 and LDPC decoder 2660, respectively.

[0698] Specifically, zero remover 2570 and zero remover 2670 are components corresponding to zero filler 213 and zero filler 314 of transmitter 100, and can respectively perform operations corresponding to the operations of zero filler 213 and zero filler 314.

[0699] For this purpose, receiver 200 may pre-store information related to the parameters and / or modes used by transmitter 100 to fill zero bits according to the corresponding mode. As a result, zero remover 2570 and zero remover 2670 may remove zero bits filled by zero filler 213 and zero filler 314 from the bits output from LDPC decoder 2560 and LDPC decoder 2660, respectively.

[0700] BCH decoder 2580 and BCH decoder 2680 can perform BCH decoding on the bits output from zero remover 2570 and zero remover 2670, respectively.

[0701] Specifically, BCH decoder 2580 and BCH decoder 2680 are components corresponding to BCH encoder 212 and BCH encoder 313 of transmitter 100, and can perform operations corresponding to BCH encoder 212 and BCH encoder 313.

[0702] For this purpose, receiver 200 may pre-store information related to the parameters used by transmitter 100 to perform BCH encoding. As a result, BCH decoder 2580 and BCH decoder 2680 can perform BCH decoding on the bits output by zero remover 2570 and zero remover 2670 to correct errors and output the corrected bits.

[0703] Descramblers 2590 and 2690 can descramble the bits output from BCH decoder 2580 and BCH decoder 2680, respectively.

[0704] Specifically, descramblers 2590 and 2690 are components corresponding to scramblers 211 and 312 of transmitter 100, and can perform operations corresponding to the operations of scramblers 211 and 312.

[0705] For this purpose, receiver 200 may pre-store information related to the parameters used by transmitter 100 to perform scrambling. As a result, descramblers 2590 and 2690 may descramble the bits output from BCH decoder 2580 and BCH decoder 2680, respectively, and output them.

[0706] As a result, the L1-basic signaling sent from transmitter 100 can be recovered. Additionally, the L1-detail signaling sent from transmitter 100 can also be recovered when transmitter 100 does not perform segmentation on the L1-detail signaling.

[0707] However, when the transmitter 100 performs segmentation on the L1-detail signaling, the desegmenter 2695 can perform desegmentation on the bits output from the descrambler 2690.

[0708] Specifically, the desegmenter 2695 is a component corresponding to the desegmenter 311 of the transmitter 100, and can perform operations corresponding to the operations of the desegmenter 311.

[0709] For this purpose, receiver 200 may pre-store information related to the parameters used by transmitter 100 to perform segmentation. As a result, desegmenter 2695 may combine the bits (i.e., fragments of L1-detail signaling) output from descrambler 2690 to recover the L1-detail signaling before segmentation.

[0710] Information related to the length of L1 signaling, such as Figure 39 The diagram is provided. Therefore, receiver 200 can calculate the length of the L1-detail signaling and the length of the additional parity bits.

[0711] Reference Figure 39 Since L1-basic signaling provides information related to the total L1 detail cells, receiver 200 needs to calculate the length of L1-detail signaling and the length of the additional parity bits.

[0712] Specifically, when the L1B_L1_Detail_additional_parity_mode of the L1-basic signaling is not 0, the information related to the given L1B_L1_Detail_total_cells represents the total cell length (=N). L1_detail_total)cells Therefore, receiver 200 can calculate the length N of L1-detail signaling based on equations 33 to 36 below. L1_detail_cells and the length N of the additional parity bits AP_total_cells .

[0713] N L1_FEC_cclls =(N outcr +N rcpcat +N 1dpc_parity -N punc ) / η MOD =N FEC / η MOD ...(33)

[0714] N L1_detail_cells =N L1D_FECFRAME ×N L1_FEC_cells ...(34)

[0715] N AP_total_cells =N L1_detail_total_cells -N L1_detail_cells ...(35)

[0716] In this case, based on equations 33 to 35 above, N AP_total_cellsThe value can be based on N, which can be obtained from information related to L1B_L1_Detail_total_cells of L1-basic signaling. L1_detail_total_cells N FEC N L1D_FECFRAME and modulation order η MOD To obtain it. As an example, N... Ap_total_cells It can be calculated based on the following equation 36.

[0717] N AP_total_cells =N L1_detail_total_cells -N L1D_FECFRAME ×N FEC / η MOD ...(36)

[0718] Meanwhile, the syntax and semantics of the L1-basic signaling fields are shown in Table 13 below.

[0719] [Table 13]

[0720]

[0721] As a result, receiver 200 can base its reception on the N values ​​sent to the received L1 detail cells. AP_total_cells The additional parity bits of each cell are used to perform the receiver's operation on the additional parity bits in the next frame.

[0722] Figure 40 This is a flowchart describing a method for generating additional parity checks according to an exemplary embodiment.

[0723] First, LDPC codewords including parity bits are generated by encoding the input bits (S6210).

[0724] Next, at least some bits of the LDPC codeword are repeated in the LDPC codeword (S6220), and some parity bits in the parity bits are truncated (S6230), so that at least some bits of the LDPC codeword formed by the input bits and the parity bits are repeated and transmitted in the current frame.

[0725] Next, at least some bits from the LDPC codeword, including the repeated bits, are selected to generate additional parity bits transmitted in the previous frame (S6240).

[0726] Here, in operation S6220, at least some of the parity bits can be added after the input bits.

[0727] In this case, during operation S6240, at least some bits can be selected from the repeated bits added after the input bits based on the number of additional parity bits and the number of truncated bits to generate additional parity bits.

[0728] Specifically, when the number of additional parity bits is greater than the number of truncated parity bits, all truncated parity bits are selected, and up to a number of bits, starting from the first bit of the repeated bits, obtained by subtracting the number of truncated parity bits from the number of additional parity bits, are selected to generate additional parity bits.

[0729] In operation S6240, when the repetition is not performed and when the number of additional parity bits is greater than the number of truncated parity bits, all truncated parity bits are selected, and up to a number of bits from the first bit of the parity bits obtained by subtracting the number of truncated parity bits from the number of parity bits are selected to generate additional parity bits.

[0730] However, in operation S6240, when truncation and duplication are not performed, up to a number of additional parity bits can be selected from the first bit of the parity bits to generate additional parity bits.

[0731] However, in operation S6240, when truncation is not performed, up to a number of additional parity bits can be selected, starting from the first bit among the repeated parity bits, to generate additional parity bits.

[0732] The detailed method for generating the additional parity bits is as described above, therefore, repeated descriptions are omitted.

[0733] Figure 41 This is a diagram illustrating the signal transmission and reception performance according to an exemplary embodiment, when the additional parity bit is used, compared to the case where the additional parity bit is not used.

[0734] exist Figure 41 In the diagram, the frame error rate (FER) is shown for cases where the L1-detail signaling length is 2000, 3000, and 4000, respectively, for cases where additional parity is not used (dashed line) and cases where additional parity bits are used (solid line). Here, coding gain and diversity gain (slope) are obtained when parity bits are used.

[0735] According to exemplary embodiments, a non-transitory computer-readable medium may be provided, wherein a program executing the various methods described above is stored in the non-transitory computer-readable medium. The non-transitory computer-readable medium is not a medium that temporarily stores data therein (such as registers, buffers, memories, etc.), but rather means a medium that stores data therein semi-permanently and can be read by a device. Specifically, the various applications or programs described above may be stored and provided in non-transitory computer-readable media (such as CDs, DVDs, hard disks, Blu-ray discs, Universal Serial Bus (USB), memory cards, read-only memory (ROM), etc.).

[0736] According to an exemplary embodiment, such as Figure 1 , Figure 19 , Figure 20 , Figure 35 and Figure 36 At least one of the components, elements, modules, or units shown in the diagram (represented by boxes) can be implemented as various numbers of hardware, software, and / or firmware structures to perform the functions described above. For example, at least one of these components, elements, modules, or units can use a direct circuit structure (such as a memory, processor, logic circuit, lookup table, etc.) that can perform the functions under the control of one or more microprocessors or other control devices. Additionally, at least one of these components, elements, modules, or units can be specifically implemented as a portion of a module, program, or code containing one or more executable instructions for performing a specific logical function, and can be executed by one or more microprocessors or other control devices. Furthermore, at least one of these components, elements, modules, or units may also include a processor (such as a central processing unit (CPU)), microprocessor, etc., to perform the functions, or be implemented by a processor, microprocessor, etc. Two or more of these components, elements, modules, or units can be combined into a single component, element, module, or unit that performs all the operations or functions of the combined two or more components, elements, modules, or units. Additionally, at least a portion of the function of at least one of these components, elements, modules, or units can be performed by another of these components, elements, modules, or units. Furthermore, although the bus is not shown in the block diagrams above, communication between components, elements, modules, or units can be performed via the bus. The functional aspects of the above exemplary embodiments can be implemented according to algorithms executed on one or more processors. Additionally, the components, elements, modules, or units represented by blocks or processing steps can employ any number of existing technologies for electronic configuration, signal processing and / or control, data processing, etc.

[0737] While exemplary embodiments of the inventive concept have been shown and described above, the inventive concept is not limited to the exemplary embodiments described above, but can be modified in various ways by those skilled in the art to which the inventive concept pertains without departing from the scope and spirit of the inventive concept disclosed in the claims. For example, exemplary embodiments are described with respect to BCH encoding and decoding and LDPC encoding and decoding. However, these embodiments do not limit the inventive concept to specific encoding and decoding methods; rather, the inventive concept can be applied to different types of encoding and decoding with necessary modifications. These modifications should also be understood to fall within the scope of the inventive concept.

[0738] [Industrial Applicability]

[0739] -

[0740] [Sequence List Free Text]

[0741] -

Claims

1. A method for sending data, comprising: If the number of input bits is less than the number of information bits, then the information bits are filled with the input bits and one or more zero-filling bits. Information bits are encoded using low-density parity-check (LDPC) codes to generate parity bits. In a predetermined mode among multiple modes, a duplicate parity bit is generated by adding one or more parity bits from the generated parity bit between the information bit and the generated parity bit. Remove one or more parity bits from the generated parity bits; Calculate the number of additional parity bits; and Additional parity bits are generated by selecting one or more parity bits based on the calculated number. The repeated parity bits are sent in the frame. The additional parity bits were sent in the previous frame, and If the number of additional parity bits is less than or equal to the number of parity bits pruned, generating additional parity bits involves selecting additional parity bits from the pruned parity bits, and... If the number of additional parity bits is greater than the number of parity bits to be removed, then generating additional parity bits involves selecting additional parity bits from the removed parity bits, the repeated parity bits, and the generated parity bits.

2. The sending method according to claim 1, wherein, If the number of additional parity bits is less than or equal to the number of parity bits pruned, the selection step includes selecting one or more parity bits from the pruned parity bits, starting from the first bit, in a number equal to the calculated number.

3. The sending method according to claim 1, wherein, If the number of additional parity bits is greater than the number of truncated parity bits, the selection step includes: selecting truncated parity bits, and selecting one or more parity bits from the repeated parity bits, starting from the first bit, in a number equal to the number obtained by subtracting the number of truncated parity bits from the calculated number.

4. A receiving method, comprising: Receive the first and second frames from the transmitting device; The first frame is demodulated to generate a first value, and the second frame is demodulated to generate a second value; The predetermined values ​​corresponding to the parity bits of the insertion and deletion; In a predetermined pattern among multiple patterns, the third value from the first value and the inserted value is combined with the fourth value from the first value and the inserted value, and the fifth value from the first value and the inserted value is combined with the sixth value from the second value; and Decoding the combined value and the remaining value in the first and inserted values ​​is based on low-density parity-check (LDPC) codes. The third value corresponds to the repeated parity bit that is repeated in the transmitting device. The sixth value corresponds to the additional parity bit generated in the transmitting device. The fourth value corresponds to one or more parity bits selected for repetition in the transmitting device. The fifth value corresponds to one or more parity bits selected for generating additional parity bits in the transmitting device, and If the number of additional parity bits is less than or equal to the number of parity bits to be removed, then additional parity bits are selected from the removed parity bits. If the number of additional parity bits is greater than the number of parity bits to be removed, then additional parity bits are selected from the removed parity bits, the repeated parity bits, and the generated parity bits.

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