substrate structure

Abstract

This invention discloses a substrate structure comprising a substrate, a circuit layer, and a solder resist layer. The circuit layer is disposed on the substrate and includes multiple solder pads and multiple interconnects, each interconnect extending from a solder pad. The solder resist layer is disposed on the substrate. The solder resist layer has openings that expose a portion of the solder pads and each interconnect. The solder resist layer also includes circumferential walls and multiple solder resist patterns. The circumferential walls cover another portion of each interconnect and surround the openings. The solder resist patterns are located within the openings, are discontinuously arranged along the openings, and are not connected to the circumferential walls.

Description

Technical Field

[0001] This invention relates to the field of circuit board soldering, and in particular to a substrate structure. Background Technology

[0002] Traditionally, a solder resist layer is usually placed on the circuit board, exposing only the solder pads and part of the circuit lines. This prevents the solder or the high heat of the soldering process from affecting the structure and electrical properties of other parts of the circuit board.

[0003] As the density of circuit layouts increases, laser welding is now commonly used to ensure welding precision and avoid open circuits. However, the high energy of the laser can easily cause solder, such as solder, that was originally placed on the pads to splatter.

[0004] The solder mask layer is taller than the circuit board, and sputtered particles are easily blocked by the edges of the solder mask layer, accumulating at those edges. Due to the continuous structure of the solder mask layer, the sputtered particles accumulate continuously in a linear pattern, causing electrical connections between solder pads or circuits, resulting in short circuits. Summary of the Invention

[0005] To address the problems encountered in the prior art, a substrate structure is provided herein. The substrate structure includes a substrate, a circuit layer, and a solder resist layer. The circuit layer is disposed on the substrate and includes multiple solder pads and multiple interconnects, each interconnect extending from a solder pad. The solder resist layer is disposed on the substrate. The solder resist layer has openings that expose portions of the solder pads and interconnects. The solder resist layer also includes circumferential walls and multiple solder resist patterns. The circumferential walls cover portions of each interconnect and surround the openings. The solder resist patterns are located within the openings, are discontinuously arranged along the openings, and are not connected to the circumferential walls.

[0006] In some embodiments, the solder resist pattern is located between the circumferential wall and the solder pad.

[0007] More specifically, in some embodiments, the gap between the solder resist patterns is greater than 50 μm.

[0008] More specifically, in some embodiments, the solder resist pattern is applied to the connection lines.

[0009] More specifically, in some embodiments, the solder resist pattern is respectively located between the connecting lines.

[0010] More specifically, in some embodiments, a portion of the solder resist pattern is located on one of the connecting lines, but not simultaneously on both connecting lines.

[0011] More specifically, in some embodiments, the area of ​​the solder resist pattern ranges from 2500 μm. 2 Up to 40000μm 2 between.

[0012] Furthermore, in some embodiments, the area of ​​the solder resist pattern ranges from 10,000 μm. 2 Up to 22500μm 2 between.

[0013] In some embodiments, the solder resist pattern is selected from the group consisting of rectangles, circles, trapezoids and rhombuses.

[0014] In some embodiments, the area of ​​the solder pad is 10000 μm. 2 Up to 22500μm 2 Between them, and the distance between the two connecting lines is greater than 50μm.

[0015] As shown in the aforementioned embodiments, by setting the solder resist pattern to be located in the opening, arranged discontinuously along the opening, and not connected to the circumferential wall, the continuous accumulation of splashed solder particles can be avoided, thereby preventing the problem of short circuits. Attached Figure Description

[0016] Figure 1 This is a cross-sectional view of the first embodiment of the substrate structure;

[0017] Figure 2 This is a top view of the first embodiment of the substrate structure;

[0018] Figure 3 This is a top view of the sputtering situation in the first embodiment of the substrate structure;

[0019] Figure 4 This is a top view of the second embodiment of the substrate structure;

[0020] Figure 5 This is a top view of the sputtering situation in the second embodiment of the substrate structure;

[0021] Figure 6 This is a top view of the third embodiment of the substrate structure;

[0022] Figure 7 This is a top view of the fourth embodiment of the substrate structure.

[0023] Symbol Explanation

[0024] 1: Substrate Structure

[0025] 10:Substrate

[0026] 20: Circuit Layer

[0027] 21: Solder pad

[0028] 23: Connecting cable

[0029] 30: Solder resist layer

[0030] 31: Opening

[0031] 33: Circumferential wall

[0032] 35: Weld resistance pattern

[0033] G1: First gap

[0034] G2: Second gap

[0035] P: Solder particles Detailed Implementation

[0036] Figure 1 This is a cross-sectional view of the first embodiment of the substrate structure. Figure 2 This is a top view of the first embodiment of the substrate structure. Figure 1 and Figure 2 As shown, the substrate structure 1 of the first embodiment includes a substrate 10, a circuit layer 20, and a solder resist layer 30. The circuit layer 20 is disposed on the substrate 10 and includes a plurality of solder pads 21 and a plurality of connecting lines 23, each connecting line 23 extending from a respective solder pad 21. Here, the extending direction of the connecting line 23 is vertical or horizontal, but this is only an example and not intended to limit.

[0037] A solder resist layer 30 is disposed on the substrate 10. The solder resist layer 30 has an opening 31, which exposes the solder pads 21 and a portion of each connecting line 23. The solder resist layer 30 also includes a circumferential wall 33 and a plurality of solder resist patterns 35. The circumferential wall 33 covers another portion of each connecting line 23, i.e., the dotted line in the figure, and surrounds the opening 31. The solder resist patterns 35 are located in the opening 31, are discontinuously arranged along the opening 31, and are not connected to the circumferential wall 33.

[0038] like Figure 2 As shown, the solder resist pattern 35 is located between the circumferential wall 33 and the solder pad 21. More specifically, in the first embodiment, the solder resist pattern 35 is arranged on the connecting line 23 in a one-to-one manner. Here, the positions of the solder resist patterns 35 are generally parallel and arranged horizontally in a line. However, this is only an example and not intended to limit the representation. In practice, they can also be arranged in a zigzag pattern.

[0039] Figure 3 This is a top view showing the sputtering situation in the first embodiment of the substrate structure. In this embodiment, multiple solder pads 21 can be soldered together with electronic components (not shown). Figure 3As shown, the size of the solder particles P that are sputtered during soldering is generally between 1 and 15 μm in diameter, and the first gap G1 between the solder resist patterns 35 is greater than 50 μm. Therefore, if the solder particles P that can be sputtered are not blocked by the solder resist patterns 35, they can easily pass through the first gap G1 between the solder resist patterns 35. In this way, the sputtered solder particles P are evenly distributed, with some passing through the first gap G1 without being blocked by the solder resist patterns 35, some located on the solder resist patterns 35, some located on the connecting lines 23, some located between the connecting lines 23, and some reaching the edge of the opening 31. In this way, the sputtered solder particles P are dispersed and discontinuous, preventing electrical conductivity between the connecting lines 23 or between the pads 21 due to the continuous accumulation of conductive particles, thus avoiding the problem of short circuits.

[0040] The dimensions described above are for illustrative purposes only and are not intended to be limiting. Here, the area of ​​pad 21 is 10000 μm. 2 Up to 22500μm 2 The second gap G2 between the two connecting lines 23 is greater than 50 μm, preferably greater than 80 μm. If the line width of the connecting line 23 is larger, a larger second gap G2 can be used proportionally. If the line width of the connecting line 23 is smaller, the proportional relationship between the connecting line 23 and the solder resist pattern 35 needs to be considered, and the size of the solder resist pattern 35 needs to be adjusted. In this embodiment, the area of ​​the solder resist pattern 35 is in the range of 2500 μm. 2 Up to 40000μm 2 Preferably, the area of ​​the solder resist pattern is in the range of 10000 μm. 2 Up to 22500μm 2 between.

[0041] Figure 4 This is a top view of the second embodiment of the substrate structure. Figure 4 As shown, the second embodiment differs from the first embodiment in that a portion of the solder resist pattern 35 in the second embodiment is located on one of the connecting lines 23, but not simultaneously on both connecting lines 23. That is, the solder resist pattern 35 can be arranged in an alternating manner with the connecting lines 23. Figure 5 This is a top view showing the sputtering situation in the second embodiment of the substrate structure. Figure 5 As shown, the solder resist pattern 35, through its discontinuous arrangement, can achieve dispersed and discontinuous solder particle P even if it is not simultaneously placed on the two connecting lines 23. Thus, this configuration can be used even when the connecting line 23 has a small line width.

[0042] Figure 6 This is a top view of the third embodiment of the substrate structure. Figure 6 As shown, Figure 6This is actually a combination of the first and second embodiments. Besides the solder resist patterns 35 being arranged one-to-one on the connecting line 23, they are also located at the upper left, lower left, upper right, and lower right corners of the opening 31, but are not connected to the circumferential wall 33. Similarly, the solder resist patterns 35 are also located between the circumferential wall 33 and the solder pad 21, and the first gap G1 between the solder resist patterns 35 is greater than 50 μm. Furthermore, the solder resist patterns 35 on the connecting line 23 are circular, but this is not a limitation; the solder resist patterns 35 can also be rectangular, trapezoidal, or rhomboid, etc.

[0043] Figure 7 This is a top view of the fourth embodiment of the substrate structure. (See attached image.) Figure 7 As shown, the fourth embodiment differs from the first to third embodiments in that the solder resist patterns 35 are respectively located between the connecting lines 23. However, to avoid short-circuiting, the width of the solder resist patterns 35 must be smaller than the second gap G2 between the connecting lines 23. Generally, the width of the solder resist patterns 35 is less than 75 μm, but the first gap G1 between the solder resist patterns 35 is greater than 50 μm.

[0044] In summary, by setting the solder resist pattern 35 to be located in the opening 31, discontinuously arranged along the opening 31, and not connected to the circumferential wall 33, the continuous accumulation of splashed solder particles P between the connecting lines 23 or between the pads 21 can be avoided, thereby preventing the problem of short circuits and improving the product yield.

[0045] Although the technical content of the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any modifications and refinements made by those skilled in the art without departing from the spirit of the present invention should be included within the scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A substrate structure comprising: substrate; A circuit layer, disposed on the substrate, includes multiple solder pads and multiple interconnects, each interconnect extending from a respective solder pad; and A solder resist layer is disposed on the substrate. The solder resist layer has an opening that exposes a plurality of solder pads and a portion of each of the interconnects. The solder resist layer also includes a circumferential wall and a plurality of solder resist patterns. The circumferential wall covers another portion of each interconnect and surrounds the opening. The plurality of solder resist patterns are located in the opening, are discontinuously arranged along the opening, and are not connected to the circumferential wall. The plurality of anti-weld patterns are located between the circumferential wall and the plurality of solder pads.

2. The substrate structure as claimed in claim 1, wherein the gap between the plurality of solder resist patterns is greater than 50 μm.

3. The substrate structure as claimed in claim 2, wherein the plurality of solder resist patterns are respectively located on the plurality of connecting lines.

4. The substrate structure as claimed in claim 2, wherein the plurality of solder resist patterns are respectively located between the plurality of connecting lines.

5. The substrate structure of claim 2, wherein a portion of the plurality of solder resist patterns is located on one of the plurality of connecting lines, but not simultaneously on both of the plurality of connecting lines.

6. The substrate structure of claim 2, wherein the plurality of anti- solder patterns range in area between 2500 μm 2 and 40,000 μm 2 between.

7. The substrate structure of claim 6, wherein the plurality of anti- solder patterns range in area between 10,000 μm 2 and 22,500 μm 2 between.

8. The substrate structure of claim 6, wherein the plurality of solder resist patterns are selected from the group consisting of rectangles, circles, trapezoids and rhombuses.

9. The substrate structure as claimed in claim 1, wherein the area of ​​the plurality of solder pads is 10000 μm. 2 Up to 22500μm 2 Between, and the spacing between any two of the multiple connecting lines is greater than 50 μm.

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